Double-gate BRT structure suitable for power switch and power pulse application

Abstract

The double-gate BRT structure is characterized in that an N-type field stop FS layer and a P + anode region are arranged on the back surface of an N-type silicon substrate, and an anode A is arranged on the outer surface of the P + anode region; a groove is formed in the center of a cell on the front face of the N-type silicon substrate, and the groove is filled with a gate oxide layer and a gate G1 of heavily-doped polycrystalline silicon. P base regions formed by selective doping are arranged on the two sides of the trench, and N + cathode regions are arranged in the P base regions and close to the trench; a P + + shunting area is arranged on the outer side in the cell; a polycrystalline silicon grid G2 is arranged on the surfaces of the partial N + cathode region, the P base region, the N-drift region and the partial P + + shunt region; a cathode K is arranged on the surfaces of part of the P + + shunt region and the N + cathode region; the whole device is of a multi-cell parallel structure. The invention further discloses a double-gate BRT structure with a conventional N type CS layer and a double-gate BRT structure with a buried N type CS layer. According to the invention, the voltage turn-back phenomenon of the existing single-gate BRT is eliminated, and the conduction loss of the device is obviously reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices and relates to a double-gate BRT structure. The present invention also relates to a double-gate BRT structure with a conventional N-type CS layer. The present invention further relates to a double-gate BRT structure with a buried N-type CS layer. Background Art

[0002] The base resistance controlled thyristor (BRT) is another type of MOS gate controlled thyristor developed on the basis of the existing MOS controlled thyristor (MCT), and is usually used as a power switching device or a power pulse device. Compared with MCT, although the manufacturing process of the existing single-gate BRT (SG-BRT for short) is greatly simplified, there is still a very serious voltage snapback phenomenon under low current, resulting in large conduction voltage drop and conduction loss. In addition, power pulse applications require devices to have high voltage, high current rise rate and high current peak at the same time, which contradicts the requirements for the thickness of the chip's voltage-resistant layer, making it difficult to meet the requirements for the rise rate and current peak of high-voltage devices. Summary of the invention

[0003] The purpose of the present invention is to provide a dual-gate BRT structure (DG-BRT for short), which introduces a trench gate on the basis of the existing SG-BRT structure to accelerate the device conduction process, eliminate the voltage foldback phenomenon, reduce the conduction voltage drop and loss, and meet the application requirements of power switching devices; at the same time, it achieves high voltage, high current rise rate and high current peak value to meet the application requirements of power pulse devices.

[0004] The second object of the present invention is to provide a conventional N-type CS layer double-gate BRT structure (abbreviated as DG-NCS-BRT), in which the P ++ A conventional CS layer is set outside the shunt area to further accelerate the conduction of the device, eliminate the voltage foldback phenomenon, and reduce the device conduction voltage drop and loss; at the same time, high voltage, high current rise rate and high current peak value are achieved to meet the application requirements of power pulse devices.

[0005] The third object of the present invention is to provide a double-gate BRT structure with a buried N-type CS layer (abbreviated as DG-BNCS-BRT), in which the P ++ A buried N-type CS layer is set under the shunt area to further accelerate the conduction of the device, eliminate the voltage foldback phenomenon, and significantly reduce the conduction voltage drop and loss of the device; at the same time, high voltage, high current rise rate and high current peak value are achieved to meet the application requirements of power pulse devices.

[0006] The technical solution adopted by the present invention is that the double-gate BRT structure uses an N-type silicon substrate as the N - Drift region, an N-type field stop FS layer and a P+ Anode region, in P + A multilayer metallized anode A is arranged on the outer surface of the anode region; a groove is arranged in the center of the cell on the front side of the N-type silicon substrate, and the groove is filled with a gate oxide layer and heavily doped polysilicon as the gate G1; on both sides of the groove, there is a P base region formed by selective doping, and an N + Cathode region; P is set on the outside of the cell ++ Diversion area; in part N + Cathode region, P base region, N - Drift zone and part of P ++ The outer surface of the shunt region is provided with a gate oxide layer and heavily doped polysilicon as the gate G2; ++ Diversion area and N + A metalized cathode K is commonly arranged on the outer surface of the cathode region; each unit cell is symmetrical with respect to the central groove, and the entire device is a multi-unit parallel structure.

[0007] The second technical solution adopted by the present invention is to have a conventional N-type CS layer double-gate BRT structure, with an N-type silicon substrate as N - Drift region, with N-type field stop FS layer and P + Anode region, in P + An anode A is provided on the surface of the anode region; a groove is provided in the center of the cell on the front side of the N-type silicon substrate, and the groove is filled with a gate oxide layer and a heavily doped polysilicon gate G1; on both sides of the groove, there is a P base region formed by selective doping, and an N + Cathode region: An N-type CS layer connected to the surface of the P base region is provided on the outside of the cell, and a P ++ Diversion area; in part N + Cathode region, P base region, N-type CS layer and part of P ++ The outer surface of the shunt region is provided with a gate oxide layer and a heavily doped polysilicon gate G2; ++ Diversion area and N + A cathode K is provided on the outer surface of the cathode region; each unit cell is symmetrical with respect to the central groove, and the entire device is a multi-unit parallel structure.

[0008] The third technical solution adopted by the present invention is to have a buried N-type CS layer double-gate BRT structure with an N-type silicon substrate as N - Drift region, with N-type field stop FS layer and P + Anode region, in P +An anode A is provided on the outer surface of the anode region; a groove is provided in the center of the cell on the front side of the N-type silicon substrate, and the groove is filled with a gate oxide layer and a heavily doped polysilicon gate G1; on both sides of the groove, a P base region formed by selective doping is provided, and an N + Cathode region; an N-type buried CS layer connected to the arc of the side of the P base region is provided on the outside of the cell, and a P ++ Diversion area; in part N + Cathode region, P base region, N - Drift zone and part of P ++ The outer surface of the shunt region is provided with a gate oxide layer and a heavily doped polysilicon gate G2; ++ Diversion area and N + A cathode K is provided on the outer surface of the cathode region; each unit cell is symmetrical with respect to the central groove, and the entire device is a multi-unit parallel structure.

[0009] The beneficial effect of the present invention is that, by adopting the double-gate BRT structure, when the device is turned on, four N channels can be formed on the side of the P base region along the side wall of the trench of the gate G1 and on the surface of the P base region below the gate G2. + The cathode region can be connected to N through four N channels - The electrons injected into the drift region inject more holes into the anode side to accelerate the conduction of the thyristor and eliminate the voltage foldback phenomenon, thereby reducing the conduction voltage drop and loss of the device; ++ A conventional N-type CS layer or a P-type CS layer is arranged around the shunt area. ++ A buried N-type CS layer is set under the shunt area to prevent holes from flowing from P ++ The outflow from the shunt area further reduces the on-state voltage drop and loss of the device, meeting the application requirements of power switching devices; at the same time, it achieves high voltage, high current rise rate and high current peak value, meeting the application requirements of power pulse devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the cell structure of the existing SG-BRT;

[0011] Figure 2 is a schematic diagram of the cell structure of the DG-BRT of Example 1 of the present invention;

[0012] Figure 3 is a schematic diagram of the cell structure of DG-NCS-BRT of Example 2 of the present invention;

[0013] Figure 4 is a schematic diagram of the cell structure of DG-BNCS-BRT of Example 3 of the present invention;

[0014] Figure 5This is a schematic diagram of the carrier transport trajectory in the initial stage of the opening of the existing SG-BRT;

[0015] Figure 6 It is a schematic diagram of carrier transport trajectory in the initial stage of DG-BRT opening in the present invention;

[0016] Figure 7 It is a schematic diagram of the carrier transport trajectory in the initial stage of opening of DG-NCS-BRT in the present invention;

[0017] Figure 8 It is a schematic diagram of the carrier transport trajectory in the initial stage of opening of DG-BNCS-BRT in the present invention;

[0018] Fig. 9 It is a comparison curve of blocking characteristics of DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and existing SG-BRT at room temperature;

[0019] Fig.10 It is a comparison curve of the on-state characteristics of the DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT at room temperature;

[0020] Fig.11 It is a comparison curve of the opening characteristics of the DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT at room temperature;

[0021] Fig.12 It is a comparison curve of the shut-off characteristics of the DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT at room temperature;

[0022] Fig.13 It is a comparison curve of the shutdown energy consumption density of the DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT at room temperature;

[0023] Fig.14 It is a comparison curve of the maximum turn-off current density of the DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT at room temperature;

[0024] Fig.15 It is the step-by-step control voltage signal applied to the two gates of the DG-BRT of the present invention;

[0025] Fig.16 It is a comparison curve of the switching characteristics of the DG-BRT under synchronous control and step-by-step control of two gates of the present invention;

[0026] Fig.17The DG-BRT of the present invention has different groove widths W T Lower V T With E off Relationship diagram;

[0027] Fig.18 The DG-BRT of the present invention has different groove depths D T Lower V T With E off Relationship diagram;

[0028] Fig.19 The DG-BRT of the present invention has different N + Cathode region width W N+ Lower V T With E off Relationship diagram;

[0029] Fig. 20 The DG-BRT of the present invention has different P ++ Depth of diversion area D p++ Lower V T With E off Relationship diagram;

[0030] Fig.21 It is a comparison curve of the pulse discharge characteristics of the DG-BRT, DG-NCS-BRT, DG-BNCS-BRT of the present invention and the existing SG-BRT at room temperature. DETAILED DESCRIPTION

[0031] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] Reference Figure 1 The structure of the existing single-gate BRT (hereinafter referred to as SG-BRT in the text and drawings) is that an N-type silicon substrate is used as the N - Drift region, an N-type field stop FS layer and a P + Anode region, in P + A multi-layer metal anode A is arranged on the outer surface of the anode region; a P base region formed by selective doping is arranged in the center of the front cell of the N-type silicon substrate, and an N base region formed by selective doping is arranged inside the P base region. + Cathode region: On the outside of the cell, there is a P ++ Diversion area; in part N + Cathode region, P base region, N - Drift zone and part of P ++ The surface of the shunt region is provided with a gate oxide layer and heavily doped polysilicon as the gate G; ++ Diversion area, N + The surface of the cathode region is provided with a metalized cathode K. It can be seen that in the SG-BRT structure, each cell is N+ The cathode region and the center of the P-base region are axially symmetrical, and the entire device is a multi-cell parallel structure.

[0033] Example 1

[0034] Reference Figure 2 The dual-gate base resistance controlled thyristor (DG-BRT) structure of the present invention is to use an N-type silicon substrate as N - Drift region, an N-type field stop FS layer and a P + Anode region, in P + A multilayer metallized anode A is arranged on the outer surface of the anode region; a groove is arranged in the center of the cell on the front side of the N-type silicon substrate, and the groove is filled with a gate oxide layer and heavily doped polysilicon as the gate G1; on both sides of the groove, there is a P base region formed by selective doping, and an N + Cathode region; P is set on the outside of the cell ++ Diversion area; in part N + Cathode region, P base region, N - Drift zone and part of P ++ The outer surface of the shunt region is provided with a gate oxide layer and heavily doped polysilicon as the gate G2; ++ Diversion area and N + The outer surface of the cathode region is commonly provided with a metalized cathode K. In the DG-BRT structure, each unit cell is symmetrical about the central groove, and the entire device is a multi-unit parallel structure.

[0035] The structural parameters of the device in this embodiment 1 are: the trench width W of the gate G1 T 2~5μm, the groove depth D T 5.5~7μm; N on both sides of the groove + Total width of cathode region W N+ 15~20μm; P ++ Depth of diversion area D P++ 1~2μm.

[0036] contrast Figure 1 , Figure 2 It can be seen that compared with the existing SG-BRT, the difference of the DG-BRT of the present invention is that the P base region and the N + A trench is set in the center of the emitter area to connect the P base area and the N + The emitter area is divided into two parts, left and right, symmetrical with the trench as the axis; the trench is filled with a gate oxide layer and heavily doped polysilicon as the gate G1. When the DG-BRT is turned on, two additional vertical N channels are formed along the side of the P base region on the sidewall of the trench, allowing electrons to be vertically injected into the N -Deep in the drift region, the conversion of the DG-BRT of the present invention from IGBT to thyristor can be accelerated when the device is turned on, thereby eliminating the voltage foldback phenomenon, reducing the conduction voltage drop and loss; and at the same time improving the turn-on current rise rate and current peak.

[0037] Example 2

[0038] Reference Figure 3 The second structure of the present invention, that is, the structure of the double-gate BRT with a conventional CS layer (ie, DG-NCS-BRT), is to use an N-type silicon substrate as the N - Drift region, an N-type field stop FS layer and a P + Anode region, a multi-layer metal anode A is arranged on the surface of the anode region; a groove is arranged in the center of the cell on the front side of the N-type silicon substrate, and the groove is filled with a gate oxide layer and heavily doped polysilicon as the gate G1; on both sides of the groove, there is a P base region formed by selective doping, and an N + Cathode region; an N-type CS layer connected to the surface of the P base region is arranged on the outside of the cell, and a P ++ Diversion area; in part N + Cathode region, P base region, N-type CS layer and part of P ++ The outer surface of the shunt region is provided with a gate oxide layer and heavily doped polysilicon as the gate G2; ++ Diversion area and N + The outer surface of the cathode region is commonly provided with a metalized cathode K. In the DG-NCS-BRT structure, each unit cell is symmetrical about the central groove, and the entire device is a multi-unit parallel structure.

[0039] The structural parameters of the device in the second embodiment based on the first embodiment are as follows: the doping concentration of the N-type CS layer is 5×10 15 cm -3 ~1×10 16 cm -3 , thickness is 1.1~1.5μm.

[0040] contrast Figure 2 , Figure 3 Compared with the DG-BRT of the present invention, the DG-NCS-BRT of the present invention has a different structure in that an N-type CS layer connected to the surface of the P base region is arranged on the outside of the cell, and a P ++ When the DG-NCS-BRT is turned on, the current from P + The anode region is injected into N - Holes in the drift region will accumulate below the N-type CS layer, causing the four N channels to be injected into the N -The greater number of electrons in the drift region further accelerates the transition from IGBT to thyristor when the device is turned on, thereby eliminating voltage foldback and reducing turn-on losses, but at the same time increasing the threshold voltage of the device.

[0041] Example 3

[0042] Reference Figure 4 The third structure of the present invention, namely the double-gate BRT with buried CS layer (ie DG-BNCS-BRT) structure, is to use N-type silicon substrate as N - Drift region, an N-type field stop FS layer and a P + Anode region, in P + A multilayer metallized anode A is arranged on the outer surface of the anode region; a groove is arranged in the center of the cell on the front side of the N-type silicon substrate, and the groove is filled with a gate oxide layer and heavily doped polysilicon as the gate G1; a P base region formed by selective doping is arranged on both sides of the groove, and an N + Cathode region; an N-type buried CS layer connected to the arc of the side of the P base region is arranged on the outside of the cell, and a P ++ Diversion area; in part N + Cathode region, P base region, N - Drift zone and part of P ++ The outer surface of the shunt region is provided with a gate oxide layer and heavily doped polysilicon as the gate G2; ++ Diversion area and N + The outer surface of the cathode region is commonly provided with a metalized cathode K. In the DG-BNCS-BRT structure, each unit cell is symmetrical about the central groove, and the entire device is a multi-unit parallel structure.

[0043] The structural parameters of the device in the third embodiment based on the first embodiment are as follows: the doping concentration of the N-type buried CS layer is 6×10 15 cm -3 ~9×10 15 cm -3 , thickness is 1.5~2μm, and P ++ The longitudinal spacing at the bottom of the shunt region is 1 to 2 μm, and the lateral spacing with the arc on the side of the P base region is 0 to 1.5 μm.

[0044] contrast Figure 2 , Figure 4 It can be seen that the structure of the DG-BNCS-BRT of the present invention is different from that of the DG-BRT of the present invention in that a buried N-type CS layer connected to the arc of the side of the P base region is arranged on the outer side of the unit cell, and a P base region is arranged above the buried N-type CS layer. ++ Shunt region. When the device is turned on, the current from P +The anode region is injected into N - Holes in the drift region will accumulate under the buried N-type CS layer, causing the four N channels to be injected into the N - The greater number of electrons in the drift region further accelerates the transition from IGBT to thyristor when the device is turned on, thereby eliminating voltage foldback and reducing turn-on losses, while having no effect on the threshold voltage of the device.

[0045] The comparative analysis of the above three dual-gate BRT structures of the present invention and the existing SG-BRT is as follows:

[0046] 1) The working principles of the above three dual-gate BRTs of the present invention are significantly different from those of the existing SG-BRT.

[0047] Reference Figure 5 , is a schematic diagram of the carrier transport trajectory in the initial stage of the existing SG-BRT opening. It can be seen that when V G2 >V TH 、V AK >0, at the beginning of SG-BRT conduction, an N channel will be formed on the surface of the P base region under the gate G, and N + The electrons in the cathode region enter the N channel through the N channel. - drift region, resulting in N - The potential of the drift region decreases. In order to ensure that N - The drift region is electrically neutral, so P + Anode region to N - Inject holes into the drift region; inject into N - Some of the holes in the drift region recombine with the electrons from the channel, and some of them pass through P ++ The shunt area flows into the cathode, and less enters the P base area. At this time, the SG-BRT is turned on in IGBT mode. Only when there are enough holes entering the P base area, so that the potential of the P base area increases and is greater than the turn-on voltage of the J3 junction, the J3 junction will be turned on, so N + The cathode region injects electrons into the P base region. The injected electrons diffuse in the P base region and reach the reverse biased J2 junction. They are swept into the N junction by the electric field of the space charge region of J2. - Drift zone. When N + The electrons injected from the cathode region and from P + When the hole concentration injected into the anode region is large enough, N - A strong conductivity modulation effect will occur in the drift region, so the existing SG-BRT is turned on in the mode of a thyristor with a very low conduction voltage drop.

[0048] Reference Figure 6, is a schematic diagram of the carrier transport trajectory of the DG-BRT of the present invention at the initial stage of opening. It can be seen that the current distribution of the DG-BRT of the present invention is significantly different from that of the existing SG-BRT at the initial stage of opening. In addition to the two parallel N channels formed under the gate G2, due to the existence of the gate G1, two vertical N channels are also formed on the side of the P base region of the trench sidewall. + The electrons in the cathode region enter the N - drift region, resulting in P + A large number of holes are injected into the anode region, accumulated under the trench and enter the P base region, accelerating the conversion of the DG-BRT of the present invention from the IGBT mode to the thyristor mode, thereby eliminating the voltage foldback phenomenon and making the device have a very low on-state voltage drop.

[0049] Reference Figure 7 , is a schematic diagram of the carrier transport trajectory of the DG-NCS-BRT of the present invention at the initial stage of turn-on. It can be seen that in the initial stage of turn-on, in addition to forming two parallel N channels and two vertical N channels similar to DG-BRT, due to the existence of a conventional N-type CS layer, + The anode region is injected into N - The holes in the drift region cannot be transferred from P ++ The flow out of the shunt area accumulates below the N-type CS layer, further strengthening the N - The conductivity modulation effect in the drift region accelerates the conversion of the DG-NCS-BRT of the present invention from the IGBT mode to the thyristor mode, thereby eliminating the voltage foldback phenomenon and further reducing the on-state voltage drop of the device.

[0050] Figure 8 , is a schematic diagram of the carrier transport trajectory of the DG-BNCS-BRT of the present invention at the initial stage of opening. It can be seen that due to the presence of the buried N-type CS layer, the carrier transport from P + The anode region is injected into N - The holes in the drift region are transferred from P ++ The outflow from the shunt area causes it to accumulate below the buried N-type CS layer, further strengthening the N - The conductivity modulation effect in the drift region accelerates the conversion of the DG-BNCS-BRT of the present invention from the IGBT mode to the thyristor mode, thereby eliminating the voltage foldback phenomenon and further reducing the on-state voltage drop of the device.

[0051] 2) Taking the 6.5kV withstand voltage level as an example, the relevant characteristics are compared and explained.

[0052] Reference Fig. 9 , which is the blocking characteristic comparison curve of the present invention's DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT at room temperature. It can be seen that under the same longitudinal structural parameters, -5V gate voltage and 1mA / cm 2Under leakage current, the forward blocking voltage of the existing SG-BRT is 7800V, while the forward blocking voltages of the DG-BRT, DG-NCS-BRT, and DG-BNCS-BRT of the present invention are 7580V, 7570V, and 7380V, respectively, which are 2.8%, 2.9%, and 5.4% lower than the forward blocking voltage of the existing SG-BRT, respectively. This indicates that the forward blocking voltages of the DG-BRT, DG-NCS-BRT, and DG-BNCS-BRT of the present invention and the existing SG-BRT all meet the 6.5kV withstand voltage grade requirement.

[0053] Reference Fig.10 , which is the on-state characteristic comparison curve of the DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT at room temperature. It can be seen that the existing SG-BRT has obvious voltage foldback phenomenon, the foldback voltage is about 9.3V, and the corresponding current is 8.7A / cm 2 The DG-BRT, DG-NCS-BRT and DG-BNCS-BRT of the present invention completely eliminate the voltage foldback phenomenon. 2 Under rated current density, the on-state voltage drop of the existing SG-BRT is 4.93V, while the on-state voltage drops of the DG-BRT, DG-NCS-BRT and DG-BNCS-BRT of the present invention are 4.32V, 3.42V and 3.74V, respectively, which are 12.4%, 30.6% and 24.1% lower than the on-state voltage drop of the existing SG-BRT.

[0054] Reference Fig.11 , is the comparison curve of the opening characteristics of DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT at room temperature. It can be seen that under the same opening conditions (V G1 =V G2 =+15V, V DC =3600V), the voltage of the existing SG-BRT drops slowly when it is turned on, and the voltage drop is large in the initial stage of opening; the opening current and voltage waveforms of the DG-BRT, DG-NCS-BRT and DG-BNCS-BRT of the present invention are almost the same, and the anode voltage drops quickly and the opening time is short.

[0055] Reference Fig.12 , is a comparison curve of the shutdown characteristics of the DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT at room temperature. Fig.12 It can be seen that under the same shutdown conditions (V G1 =V G2 =-15V, V DC=3600V), the current tail time of the existing SG-BRT when it is turned off is longer and the turn-off voltage spike is larger; the turn-off current tail time of the DG-BRT of the present invention is shorter and the turn-off voltage spike is smaller; the turn-off current and voltage waveforms of the DG-NCS-BRT and DG-BNCS-BRT of the present invention are almost identical, and the turn-off current tail time is the shortest and the turn-off voltage spike is smaller.

[0056] Reference Fig.13 , is the comparison curve of the shutdown energy consumption density of the DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT. It can be seen that under the same shutdown conditions, the shutdown energy consumption density of the existing SG-BRT is slightly smaller, which is 0.134mJ / cm 2 The shutdown energy consumption density of DG-BRT, DG-NCS-BRT and DG-BNCS-BRT of the present invention is slightly different, which is 0.139 mJ / cm 2 , 0.145mJ / cm 2 , 0.144mJ / cm 2 .

[0057] Reference Fig.14 , is the maximum turn-off current density comparison curve of DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and existing SG-BRT of the present invention. It can be seen that under the gate voltage of -15V, the maximum turn-off current density J of the existing SG-BRT at 26μs MTCD 107.5A / cm 2 ; J of the DG-BRT of the present invention at 80μs MTCD 386.2A / cm 2 ; J of DG-NCS-BRT of the present invention at 70μs MTCD 340.1A / cm 2 ; J of DG-BNCS-BRT of the present invention at 34μs MTCD 146.3A / cm 2 Therefore, the maximum switchable current density of the DG-BRT, DG-NCS-BRT and DG-BNCS-BRT of the present invention is increased by about 259.3%, 216.5% and 36.1% respectively compared with the existing SG-BRT; they are 9.7, 8.5 and 3.7 times of the rated current density respectively, while the maximum switchable current density of the existing SG-BRT is only 2.7 times of the rated current density.

[0058] 3) The DG-BRT of the present invention may also adopt a control method different from that of the existing SG-BRT.

[0059] The existing SG-BRT has only one gate G, and its switch can only be controlled by the gate G. The DG-BRT of the present invention has two gates, G1 and G2. In addition to the above-mentioned synchronous control, in order to reduce its turn-off energy consumption, the gates G1 and G2 can also be controlled separately, that is, the two gates use asynchronous signals to control their switches. When the DG-BRT of the present invention is turned on, in order to make the side of the P base region of the gate G1 trench sidewall and the surface of the P base region below the gate G2 simultaneously form two vertical N channels and two parallel N channels, respectively, to speed up the conduction of the thyristor, it is necessary to apply a +15V gate voltage to G1 and G2 at the same time; when the DG-BRT of the present invention is turned off, the gate voltage of G1 is first removed at △t before turning off, that is, V G1 = 0V, so the vertical channel no longer injects electrons; when turned off, a gate voltage of -5V is applied to the gate G2, that is, V G2 = -5V, N below it - Two parallel P channels are formed on the surface of the drift region, providing a path for extracting holes in the P base region, allowing the device to be quickly turned off.

[0060] Reference Fig.15 , is the step-by-step control voltage signal applied to the two gates of the DG-BRT of the present invention. The turn-on signal V G2 Advanced V G1 =△t1, so that V G1 From 0V to +15V, V G2 From -5V to +15V, ensure that the vertical channel and the parallel channel are formed at the same time, that is, use G1 and G2 to control the opening of the device at the same time; turn off the signal V G2 Delay V G1 =△t2, so that V G1 Reduce from +15V to 0V in advance, after △t2, V G2 From +15V down to -5V, that is, using G2 to control the shutdown of the device.

[0061] Reference Fig.16 , which is the comparison curve of the turn-off characteristics of the two gates in the DG-BRT of the present invention under synchronous control and step-by-step control. Here, synchronous control means that V G1 With V G2 The control signals are exactly the same; the step control is to turn off the control in two steps, that is, first remove the signal of gate G1 (V G1 =0), and then a negative voltage signal (V G2 =-5V). It can be seen that the turn-off characteristics of the step-by-step control are better than those of the synchronous control. Not only is the turn-off anode current large, but the tail current is also small.

[0062] Similarly, the DG-NCS-BRT and DG-BNCS-BRT of the present invention also have the above-mentioned characteristics.

[0063] 4) Explanation of the influence trend of key structural parameters of DG-BRT on the characteristics of the present invention.

[0064] Reference Fig.17 , is the DG-BRT of the present invention at different groove widths W T Lower V T With E off Relationship diagram. It can be seen that when W T When 5μm is used, a lower V T , E off and V T The product of is also the smallest, and the characteristics of the DG-BRT of the present invention are optimal.

[0065] Reference Fig.18 , is the DG-BRT of the present invention at different groove depths D T Lower V T With E off Relationship diagram. It can be seen that when D T When the value is 5.7 μm, the turn-off energy consumption is the minimum, E off and V T The product is also the smallest, and the characteristics of the DG-BRT of the present invention are optimal.

[0066] Reference Fig.19 , is the DG-BRT of the present invention in different N + Cathode region width W N+ Lower V T With E off Relationship diagram. It can be seen that with W N+ Increase, the on-state voltage drop V T will decrease, but the shutdown energy consumption will increase. N+ When 16.2μm is used, the turn-off energy consumption is small, E off and V T The product is also the smallest, and the characteristics of the DG-BRT of the present invention are optimal.

[0067] Reference Fig. 20 , is the DG-BRT of the present invention at different P ++ Depth of diversion area D p++ Lower V T With E off Relationship diagram. It can be seen that with D p++ Increase, the on-state voltage drop V T will increase, but the turn-off energy consumption has a larger change trend. p++ Take 1.4μm, E off and V T The product is the smallest and the characteristics of the DG-BRT of the present invention are optimal.

[0068] Similarly, the DG-NCS-BRT and DG-BNCS-BRT of the present invention both have the above-mentioned excellent characteristics, and therefore, can be used as power switches to control the on and off of current.

[0069] 5) Comparison of power pulse discharge characteristics.

[0070] Reference Fig.21 , is the pulse discharge characteristic comparison curve of the present invention DG-BRT, DG-NCS-BRT, DG-BNCS-BRT and the existing SG-BRT at room temperature. It can be seen that under the same discharge conditions (discharge circuit voltage power supply V AK The discharge characteristics of the DG-BRT and DG-NCS-BRT of the present invention are very close to those of the existing SG-BRT. The current peak value and current density rise rate of the DG-BRT of the present invention are 7179A and 19.13kA / cm 2 / μs, the current peak value and current density rise rate of the DG-NCS-BRT of the present invention are 7192A and 19.49kA / cm 2 / μs, the current peak value and current density rise rate of the DG-BNCS-BRT of the present invention are 6912A and 19.96kA / cm 2 / μs, while the current peak value and current density rise rate of the existing SG-BRT are 7187A and 19.04kA / cm 2 This shows that the DG-BRT, DG-NCS-BRT and DG-BNCS-BRT of the present invention can also be used in the field of power pulses to achieve rapid discharge of large currents.

[0071] In addition, the DG-BRT structure of the present invention can also be extended to 4H-SiC DG-BRT by adding a P-type shielding layer under the gate to improve the high electric field at the bottom of the trench, so that it can be used as a higher performance switching device and pulse discharge device.

Claims

1. Double-gate BRT structure, characterized by: N-type silicon substrate as N - Drift region, with N-type field stop FS layer and P + Anode region, in P + The outer surface of the anode area is provided with a multi-layer metallized anode A; A trench is provided in the center of the cell on the front side of the N-type silicon substrate. The trench is filled with a gate oxide layer and heavily doped polysilicon as the gate G1. On both sides of the trench, there is a P-base region formed by selective doping. N + Cathode region; P is located on the outside of the cell. ++ Diversion area; in part N + Cathode region, P base region, N - Drift zone and part of P ++ The outer surface of the shunt region is provided with a gate oxide layer and heavily doped polysilicon as the gate G2; ++ Diversion area and N + A metalized cathode K is provided on the outer surface of the cathode region; each unit cell is symmetrical with the central groove as the axis, and the entire device is a multi-unit parallel structure.

2. The dual-gate BRT structure according to claim 1, characterized in that: The trench width W of the gate G1 is T 2~5μm, the groove depth D T 5.5~7μm; Both sides of the groove N + Total width of cathode region W N+ 15~20μm; P ++ Depth of diversion area D P++ 1~2μm.

3. It has a conventional N-type CS layer double-gate BRT structure, characterized by: N-type silicon substrate as N - Drift region, the back of the N-type silicon substrate is provided with an N-type field stop FS layer and a P + Anode region, in P + The outer surface of the anode region is provided with an anode A; a groove is provided in the center of the front cell of the N-type silicon substrate, and the groove is filled with a gate oxide layer and a gate G1 of heavily doped polysilicon; on both sides of the groove, there is a P base region formed by selective doping, and the part of the P base region near the groove is provided with an N + Cathode region: An N-type CS layer is provided on the outside of the cell, which is connected to the surface of the P base region, and a P ++ Diversion area; part N + Cathode region, P base region, N-type CS layer and part of P ++ The outer surface of the shunt region is provided with a gate oxide layer and a heavily doped polysilicon gate G2; part P ++ Diversion area and N + A cathode K is provided on the outer surface of the cathode region; each unit cell is symmetrical with respect to the central groove, and the entire device is a multi-unit parallel structure.

4. The double-gate BRT structure with conventional N-type CS layer according to claim 3, characterized in that: The doping concentration of the N-type CS layer is 5×10 15 cm -3 ~1×10 16 cm -3 , thickness is 1.1~1.5μm.

5. It has a buried N-type CS layer double-gate BRT structure, characterized by: N-type silicon substrate as N - Drift region, the back of the N-type silicon substrate is provided with an N-type field stop FS layer and a P + Anode region, P + An anode A is provided on the outer surface of the anode region; a groove is provided in the center of the front cell of the N-type silicon substrate, and the groove is filled with a gate oxide layer and a gate G1 of heavily doped polysilicon; a P base region formed by selective doping is provided on both sides of the groove, and an N + Cathode region; an N-type buried CS layer connected to the arc of the side of the P base region is provided on the outside of the cell, and a P ++ Diversion area; part N + Cathode region, P base region, N - Drift zone and part of P ++ The outer surface of the shunt region is provided with a gate oxide layer and a heavily doped polysilicon gate G2; part P ++ Diversion area and N + A cathode K is provided on the surface of the cathode region; each unit cell is symmetrical about the central groove, and the entire device is a multi-unit parallel structure.

6. The double-gate BRT structure with buried N-type CS layer according to claim 5, characterized in that: The doping concentration of the N-type buried CS layer is 6×10 15 cm -3 ~9×10 15 cm -3 , thickness is 1.5~2μm, and P ++ The longitudinal spacing at the bottom of the shunt region is 1 to 2 μm, and the lateral spacing with the arc on the side of the P base region is 0 to 1.5 μm.

Images