Light emitting diode with tunneling layer and preparation method thereof
A tunneling layer with P-type and N-type InGaN layers in LEDs addresses the high driving voltage and low efficiency issues by enhancing hole tunneling and reducing resistance, leading to improved luminous efficiency and brightness.
Patent Information
- Application Number
- CN202411032667.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-30
- Publication Date
- 2024-12-27
AI Technical Summary
The low doping efficiency and activation efficiency of the P-type semiconductor layer in LEDs result in high driving voltage, large resistance, and reduced luminous efficiency due to low hole concentration and injection efficiency.
Incorporating a tunneling layer with a P-type heavily doped InGaN layer, an insertion layer, and an N-type heavily doped InGaN layer stacked in sequence, forming a tunneling junction that enhances hole tunneling probability and reduces contact resistance through a strong built-in electric field and polarization effects.
The solution effectively reduces the driving voltage and improves luminous efficiency by increasing hole injection and radiation recombination efficiency, resulting in higher brightness and lower voltage operation.
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Figure CN119208478A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a light emitting diode with a tunneling layer and a preparation method thereof. Background Art
[0002] Light Emitting Diode (LED) has been widely used in various light source fields such as backlight, lighting, and landscaping due to its small size, long service life, rich colors, and low energy consumption.
[0003] In the related art, an LED includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked in sequence.
[0004] However, due to the low doping efficiency and activation efficiency of the P-type doping element in the P-type semiconductor layer, the concentration of the activated P-type doping element in the P-type semiconductor layer is low, and the resistance of the P-type semiconductor layer is large, resulting in a high driving voltage of the LED. In addition, the low doping efficiency and activation efficiency of the P-type doping element will also affect the concentration and injection efficiency of holes in the P-type semiconductor layer, thereby reducing the radiation recombination efficiency of holes and electrons and affecting the luminous efficiency of the LED. Summary of the invention
[0005] The embodiment of the present disclosure provides a light emitting diode with a tunneling layer and a preparation method thereof, which can reduce the driving voltage of the LED and improve the light emitting efficiency of the LED. The technical solution is as follows:
[0006] On the one hand, a light-emitting diode is provided, comprising an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer and a tunneling layer stacked in sequence, wherein the tunneling layer comprises a P-type heavily doped InGaN layer, an insertion layer and an N-type heavily doped InGaN layer stacked in sequence in a direction away from the P-type semiconductor layer, and the insertion layer is an InSb layer or an InN layer.
[0007] Optionally, the In component content of the P-type heavily doped InGaN layer is lower than the In component content of the N-type heavily doped InGaN layer.
[0008] Optionally, the light-emitting layer includes multiple pairs of quantum well layers and quantum barrier layers that are alternately stacked, the quantum well layer includes In element, and the ratio of the In component content of the P-type heavily doped InGaN layer to the In component content of the quantum well layer is 0.9 to 1.1.
[0009] Optionally, the In component content of the P-type heavily doped InGaN layer is 0.1 to 0.3.
[0010] Optionally, the In component content of the N-type heavily doped InGaN layer is 0.2 to 0.6.
[0011] Optionally, the doping concentration of the P-type heavily doped InGaN layer is 1*10 20 / cm 3 Up to 5*10 21 / cm 3 The doping concentration of the N-type heavily doped InGaN layer is 1*10 20 / cm 3 Up to 5*10 21 / cm 3 .
[0012] Optionally, the thickness of the P-type heavily doped InGaN layer is 10 nm to 50 nm.
[0013] Optionally, the thickness of the N-type heavily doped InGaN layer is 5 nm to 20 nm.
[0014] Optionally, the insertion layer has a thickness of 1 nm to 5 nm.
[0015] On the other hand, a method for preparing a light-emitting diode is provided, comprising: forming a light-emitting layer on an N-type semiconductor layer; forming a P-type semiconductor layer on the light-emitting layer; forming a tunneling layer on the P-type semiconductor layer, the tunneling layer comprising a P-type heavily doped InGaN layer, an insertion layer and an N-type heavily doped InGaN layer stacked in sequence in a direction away from the P-type semiconductor layer, the insertion layer being an InSb layer or an InN layer.
[0016] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0017] In the disclosed embodiment, a tunneling layer is provided on the P-type semiconductor layer, and the tunneling layer includes a P-type heavily doped InGaN layer, an insertion layer, and an N-type heavily doped InGaN layer stacked in sequence in a direction away from the P-type semiconductor layer. The P-type heavily doped InGaN layer and the N-type heavily doped InGaN layer can form a tunneling junction. The bandgap width of the InGaN material is small, and the tunneling junction can form a strong built-in electric field. The probability of hole tunneling can be increased through the built-in electric field, that is, more holes can pass through the semiconductor material without any external energy, thereby improving the current expansion effect. In addition, the ohmic contact performance of the InGaN material is good, and the resistance of the N-type heavily doped InGaN layer is very small, thereby effectively reducing the contact resistance and reducing the driving voltage of the LED. In addition, the insertion layer is an InSb layer or an InN layer, and both the InSb layer and the InN layer can produce polarization effects with the P-type heavily doped InGaN layer and the N-type heavily doped InGaN layer. The electric field direction of the polarization electric field formed by the polarization effect is the same as the electric field direction of the built-in electric field of the tunnel junction, and the bandgap width of the InSb material and the InN material is very small, which can further greatly increase the intensity of the built-in electric field of the tunnel junction and increase the probability of hole tunneling, thereby improving the hole injection efficiency and the radiation recombination efficiency of holes and electrons, so as to effectively improve the luminous efficiency of the LED. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0019] Figure 1 is a schematic diagram of the structure of an LED provided by an embodiment of the present disclosure;
[0020] Figure 2 is a flow chart of a method for preparing an LED provided by an embodiment of the present disclosure;
[0021] Figure 3 It is a flow chart of another method for preparing LED provided in an embodiment of the present disclosure.
[0022] Reference numerals:
[0023] 10: N-type semiconductor layer; 20: light-emitting layer; 21: quantum well layer; 22: quantum barrier layer; 30: P-type semiconductor layer; 40: tunneling layer; 41: P-type heavily doped InGaN layer; 42: insertion layer; 43: N-type heavily doped InGaN layer; 50: substrate; 60: buffer layer; 61: first buffer layer; 62: second buffer layer; 70: electron blocking layer. DETAILED DESCRIPTION
[0024] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0025] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantitative limitation, but indicate the existence of at least one. Words such as "include" and similar words mean that the elements or objects appearing before "include" include the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0026] Figure 1 Schematic diagram of the structure of an LED provided by an embodiment of the present disclosure. Figure 1 As shown, the LED includes an N-type semiconductor layer 10, a light emitting layer 20, a P-type semiconductor layer 30 and a tunneling layer 40 which are stacked in sequence.
[0027] The tunneling layer 40 includes a P-type heavily doped InGaN layer 41, an insertion layer 42, and an N-type heavily doped InGaN layer 43 stacked in sequence in a direction away from the P-type semiconductor layer 30, and the insertion layer is an InSb layer or an InN layer. Here, heavily doped means that the amount of impurities doped into the semiconductor material is relatively large, and the doping concentration of the semiconductor material is relatively high. For example, the doping concentration of the semiconductor material is 1*10 18 / cm 3 above.
[0028] In the disclosed embodiment, a tunneling layer 40 is provided on the P-type semiconductor layer 30, and the tunneling layer 40 includes a P-type heavily doped InGaN layer 41, an insertion layer 42, and an N-type heavily doped InGaN layer 43 stacked in sequence in a direction away from the P-type semiconductor layer 30. The P-type heavily doped InGaN layer 41 and the N-type heavily doped InGaN layer 43 can form a tunneling junction. Compared with materials such as GaN, the bandgap width of the InGaN material is smaller, and the tunneling junction can form a strong built-in electric field. The probability of hole tunneling can be increased through the built-in electric field, that is, more holes can pass through the semiconductor material without any external energy, thereby improving the current expansion effect. In addition, the ohmic contact performance of the InGaN material is good, and the resistance of the N-type heavily doped InGaN layer 43 is very small, so that the contact resistance can be effectively reduced, and the driving voltage of the LED can be reduced. In addition, the insertion layer 42 is an InSb layer or an InN layer, and both the InSb layer and the InN layer can generate polarization effects with the P-type heavily doped InGaN layer 41 and the N-type heavily doped InGaN layer 43. The electric field direction of the polarization electric field formed by the polarization effect is the same as the electric field direction of the built-in electric field of the tunnel junction, and the bandgap width of the InSb material and the InN material is very small, which can further greatly improve the strength of the built-in electric field of the tunnel junction and increase the probability of hole tunneling, thereby improving the hole injection efficiency and the radiation recombination efficiency of holes and electrons, so as to effectively improve the luminous efficiency of the LED.
[0029] Optionally, the In component content of the P-type heavily doped InGaN layer 41 is lower than the In component content of the N-type heavily doped InGaN layer 43. In this way, the P-type heavily doped InGaN layer 41 closer to the light-emitting layer 20 has a lower In component content, which can reduce the influence of polarization on the light-emitting layer 20, ensure that the radiation recombination efficiency of holes and electrons in the light-emitting layer 20 is high, and the luminous efficiency of the LED is high. The N-type heavily doped InGaN layer 43 closer to the electrode of the LED has a higher In component content, which is conducive to the N-type heavily doped InGaN layer 43 forming an ohmic contact with the electrode, thereby reducing the contact resistance and reducing the driving voltage of the LED.
[0030] Optionally, the light emitting layer 20 is a multi-quantum well layer, including multiple pairs of quantum well layers 21 and quantum barrier layers 22 that are alternately stacked.
[0031] Optionally, the quantum well layer 21 includes an In element, and the ratio of the In component content of the P-type heavily doped InGaN layer 41 to the In component content of the quantum well layer 21 is 0.9 to 1.1. In this way, the In component content of the P-type heavily doped InGaN layer 41 is close to the In component content of the quantum well layer 21, which can effectively reduce the influence of polarization on the light-emitting layer 20, and ensure that the radiation recombination efficiency of holes and electrons in the light-emitting layer 20 is high.
[0032] For example, the ratio of the In component content of the P-type heavily doped InGaN layer 41 to the In component content of the quantum well layer 21 may be 0.9, 1, 1.1, or the like.
[0033] Exemplarily, the In component content of the P-type heavily doped InGaN layer 41 is 0.1 to 0.3. For example, the In component content of the P-type heavily doped InGaN layer 41 may be 0.1, 0.2, or 0.3.
[0034] If the In component content of the P-type heavily doped InGaN layer 41 is too high, the polarization effect may affect the radiation recombination efficiency of holes and electrons in the light-emitting layer 20; if the In component content of the P-type heavily doped InGaN layer 41 is too low, the strength of the built-in electric field of the tunnel junction will be affected. When the In component content of the P-type heavily doped InGaN layer 41 is within this range, the influence of the polarization effect on the light-emitting layer 20 can be reduced while ensuring that the strength of the built-in electric field of the tunnel junction is relatively high and the probability of hole tunneling is relatively high.
[0035] Exemplarily, the In component content of the N-type heavily doped InGaN layer 43 is 0.2 to 0.6. For example, the In component content of the N-type heavily doped InGaN layer 43 may be 0.2, 0.4 or 0.6, etc. The In component content of the N-type heavily doped InGaN layer 43 is within the above range, and the activation energy of the P-type doping element can be effectively reduced by In, which is beneficial to increase the concentration of the activated P-type doping element, increase the concentration and injection efficiency of holes, and is beneficial to form a good ohmic contact with the electrode, thereby effectively reducing the contact resistance.
[0036] It should be noted that the In component content ranges of the P-type heavily doped InGaN layer 41 and the N-type heavily doped InGaN layer 43 overlap, and it is sufficient to ensure that the In component content of the P-type heavily doped InGaN layer 41 is lower than the In component content of the N-type heavily doped InGaN layer 43 .
[0037] Exemplarily, the P-type heavily doped InGaN layer 41 is an InGaN layer heavily doped with Mg, and the N-type heavily doped InGaN layer 43 is an InGaN layer heavily doped with Si. In the disclosed embodiment, the P-type doped impurity element includes but is not limited to Mg, and the N-type doped impurity element includes but is not limited to Si.
[0038] Optionally, the doping concentration of the P-type heavily doped InGaN layer 41 is 1*10 20 / cm 3 Up to 5*10 21 / cm 3If the doping concentration of the P-type heavily doped InGaN layer 41 is too low, it may result in a low hole concentration and injection efficiency; if the doping concentration of the P-type heavily doped InGaN layer 41 is too high, it may affect the crystal quality of the P-type heavily doped InGaN layer 41. The doping concentration of the P-type heavily doped InGaN layer 41 within this range can ensure that the crystal quality of the P-type heavily doped InGaN layer 41 is good, and is conducive to improving the hole concentration and injection efficiency.
[0039] For example, the doping concentration of the P-type heavily doped InGaN layer 41 is 6*10 20 / cm 3 Up to 1*10 21 / cm 3 For example, the doping concentration of the P-type heavily doped InGaN layer 41 may be 6*10 20 / cm 3 ,8*10 20 / cm 3 or 1*10 21 / cm 3 wait.
[0040] Optionally, the doping concentration of the N-type heavily doped InGaN layer 43 is 1*10 20 / cm 3 Up to 5*10 21 / cm 3 If the doping concentration of the N-type heavily doped InGaN layer 43 is too low, the strength of the built-in electric field of the tunneling junction may be too small, affecting the probability of hole tunneling; if the doping concentration of the N-type heavily doped InGaN layer 43 is too high, the crystal quality of the N-type heavily doped InGaN layer 43 may be affected. The doping concentration of the N-type heavily doped InGaN layer 43 within this range can ensure that the quality of the N-type heavily doped InGaN layer 43 is good, and is conducive to improving the probability of hole tunneling and the radiation recombination efficiency of holes and electrons, so as to improve the luminous efficiency of the LED.
[0041] For example, the doping concentration of the N-type heavily doped InGaN layer 43 is 6*10 20 / cm 3 Up to 1*10 21 / cm 3 For example, the doping concentration of the N-type heavily doped InGaN layer 43 may be 6*10 20 / cm 3 ,8*10 20 / cm 3 or 1*10 21 / cm 3 wait.
[0042] Optionally, the thickness of the P-type heavily doped InGaN layer 41 is 10 nm to 50 nm.
[0043] By way of example, the thickness of the P-type heavily doped InGaN layer 41 may be 10 nm, 30 nm, or 50 nm.
[0044] Optionally, the thickness of the N-type heavily doped InGaN layer 43 is 5 nm to 20 nm.
[0045] By way of example, the thickness of the N-type heavily doped InGaN layer 43 may be 5 nm, 10 nm, or 15 nm.
[0046] For the P-type heavily doped InGaN layer 41 and the N-type heavily doped InGaN layer 43, if the thickness is too small, it may affect the strength of the built-in electric field of the tunnel junction, resulting in a low concentration and injection efficiency of holes; if the thickness is too large, it may cause the resistance of the P-type heavily doped InGaN layer 41 and the N-type heavily doped InGaN layer 43 to be high, and the driving voltage of the LED to increase. The thickness of the P-type heavily doped InGaN layer 41 and the N-type heavily doped InGaN layer 43 within this range is conducive to improving the luminous efficiency of the LED and reducing the driving voltage of the LED.
[0047] Optionally, the thickness of the insertion layer 42 is 1 nm to 5 nm. If the thickness of the insertion layer 42 is too small, the strength of the built-in electric field of the tunnel junction may be small; if the thickness of the insertion layer 42 is too large, the effect of improving the strength of the built-in electric field of the tunnel junction is limited, which may cause a waste of production costs. When the thickness of the insertion layer 42 is within this range, the strength of the built-in electric field of the tunnel junction can be effectively improved, and the probability of hole tunneling can be increased.
[0048] By way of example, the thickness of the insertion layer 42 may be 1 nm, 3 nm, 5 nm, or the like.
[0049] like Figure 1 As shown, the LED further includes a substrate 50 , which is located on a side of the N-type semiconductor layer 10 away from the light emitting layer 20 .
[0050] Optionally, the substrate 50 may be a sapphire substrate, a silicon substrate or a silicon carbide substrate.
[0051] Optionally, the LED further includes a buffer layer 60, which is located on the surface of the N-type semiconductor layer 10 away from the light-emitting layer 20, that is, between the substrate 50 and the N-type semiconductor layer 10. The buffer layer 60 is conducive to reducing the lattice mismatch and thermal mismatch between the substrate 50 and the semiconductor material, thereby ensuring good quality of the LED.
[0052] like Figure 1 As shown, the buffer layer 60 includes a first buffer layer 61 and a second buffer layer 62 sequentially stacked in a direction away from the substrate 50 .
[0053] Optionally, the first buffer layer 61 may be an AlN buffer layer. The AlN buffer layer may reduce the lattice mismatch between the substrate 50 and the semiconductor material, which is beneficial to reducing the lattice defects of the LED. Since the AlN buffer layer grows at a relatively low temperature, the first buffer layer 61 may also be referred to as a low-temperature buffer layer.
[0054] Exemplarily, the thickness of the first buffer layer 61 is 15 nm to 30 nm.
[0055] Optionally, the second buffer layer 62 may be an undoped GaN buffer layer. The undoped GaN buffer layer may reduce the thermal mismatch stress between the substrate 50 and the semiconductor material, thereby ensuring better quality of the LED. Since the undoped GaN buffer layer is grown at a relatively high temperature, the second buffer layer 62 may also be referred to as a high-temperature buffer layer.
[0056] Exemplarily, the thickness of the second buffer layer 62 is 1 μm to 3 μm.
[0057] Optionally, the N-type semiconductor layer 10 may be an N-type GaN layer, and the P-type semiconductor layer 30 may be a P-type GaN layer.
[0058] Exemplarily, the N-type semiconductor layer 10 is a Si-doped GaN layer.
[0059] For example, the Si doping concentration of the N-type semiconductor layer 10 is 1*10 19 cm -3 Up to 1*10 21 cm -3 .
[0060] Exemplarily, the thickness of the N-type semiconductor layer 10 is 1 μm to 3 μm.
[0061] Exemplarily, the P-type semiconductor layer 30 is a Mg-doped GaN layer.
[0062] For example, the Mg doping concentration of the P-type semiconductor layer 30 is 1*10 19 cm -3 Up to 1*10 21 cm -3 .
[0063] Exemplarily, the thickness of the P-type semiconductor layer 30 is 30 nm to 100 nm.
[0064] Optionally, different materials may be selected for the quantum well layer 21 and the quantum barrier layer 22 in the light-emitting layer 20 according to the different light-emitting wavelength ranges of the LED. For example, the light-emitting layer 20 of the blue-green LED may adopt multiple pairs of alternately stacked InGaN layers and GaN layers, and the light-emitting layer 20 of the red LED may adopt multiple pairs of alternately stacked InGaAs layers and GaAs layers.
[0065] Exemplarily, the light emitting layer 20 includes 6 to 12 pairs of alternately stacked InGaN layers and GaN layers, for example, 9 pairs of alternately stacked InGaN layers and GaN layers, and other pairs, which are not limited in the present disclosure.
[0066] Exemplarily, the quantum well layer 21 in the light emitting layer 20 is an InGaN layer, and the In component content of the InGaN layer is 0.1 to 0.3.
[0067] Exemplarily, the thickness of the quantum well layer 21 in the light emitting layer 20 is 2 nm to 4 nm.
[0068] Exemplarily, the thickness of the quantum barrier layer 22 in the light emitting layer 20 is 8 nm to 20 nm.
[0069] like Figure 1 As shown, the LED further includes an electron blocking layer 70, which is located between the light-emitting layer 20 and the P-type semiconductor layer 30. The electron blocking layer 70 can block electrons and reduce the probability of electrons escaping from the light-emitting layer 20 to the P-type semiconductor layer 30, thereby improving the radiation recombination efficiency of holes and electrons and improving the luminous efficiency of the LED.
[0070] Optionally, the electron blocking layer 70 may be an AlGaN layer. Exemplarily, the Al component content of the electron blocking layer 70 is 0.1 to 0.5.
[0071] Optionally, the thickness of the electron blocking layer 70 is 20 nm to 100 nm.
[0072] It should be noted that Figure 1 The film layer structure of the LED shown and the material of the above film layer are only used as an example. In other embodiments, the LED may also include more or fewer film layer structures, and the materials of each film layer can be selected according to actual needs, etc., and there is no limitation on this publicly.
[0073] Figure 2 FIG. 1 is a flow chart of a method for preparing an LED provided by an embodiment of the present disclosure. Figure 2 As shown, the preparation method comprises:
[0074] In step S101 , a light emitting layer is formed on an N-type semiconductor layer.
[0075] In step S102 , a P-type semiconductor layer is formed on the light emitting layer.
[0076] In step S103 , a tunneling layer is formed on the P-type semiconductor layer.
[0077] The tunneling layer includes a P-type heavily doped InGaN layer, an insertion layer and an N-type heavily doped InGaN layer which are sequentially stacked in a direction away from the P-type semiconductor layer, and the insertion layer is an InSb layer or an InN layer.
[0078] In the disclosed embodiment, a tunneling layer is provided on the P-type semiconductor layer, and the tunneling layer includes a P-type heavily doped InGaN layer, an insertion layer, and an N-type heavily doped InGaN layer stacked in sequence in a direction away from the P-type semiconductor layer. The P-type heavily doped InGaN layer and the N-type heavily doped InGaN layer can form a tunneling junction. The bandgap width of the InGaN material is small, and the tunneling junction can form a strong built-in electric field. The probability of hole tunneling can be increased through the built-in electric field, that is, more holes can pass through the semiconductor material without any external energy, thereby improving the current expansion effect. In addition, the ohmic contact performance of the InGaN material is good, and the resistance of the N-type heavily doped InGaN layer is very small, thereby effectively reducing the contact resistance and reducing the driving voltage of the LED. In addition, the insertion layer is an InSb layer or an InN layer, and both the InSb layer and the InN layer can produce polarization effects with the P-type heavily doped InGaN layer and the N-type heavily doped InGaN layer. The electric field direction of the polarization electric field formed by the polarization effect is the same as the electric field direction of the built-in electric field of the tunnel junction, and the bandgap width of the InSb material and the InN material is very small, which can further greatly increase the intensity of the built-in electric field of the tunnel junction and increase the probability of hole tunneling, thereby improving the hole injection efficiency and the radiation recombination efficiency of holes and electrons, so as to effectively improve the luminous efficiency of the LED.
[0079] Figure 3 FIG. 1 is a flow chart of another method for preparing an LED provided by an embodiment of the present disclosure. Figure 3 As shown, the preparation method comprises:
[0080] In step S201 , a first buffer layer is formed on a substrate.
[0081] Optionally, the substrate may be a sapphire substrate.
[0082] For example, the substrate can be placed in a physical vapor deposition (PVD) device, the temperature can be controlled to be 500° C. to 650° C., the pressure can be controlled to be 1 torr to 10 torr, NH 3 and TMAl can be introduced, and an AlN buffer layer can be formed on the substrate to obtain a first buffer layer.
[0083] Exemplarily, the sputtering power of the PVD equipment is 2500W to 4000W.
[0084] Optionally, before performing step S201, the preparation method may further include: decomposing oxides on the surface of the substrate using hydrogen under high temperature conditions to remove the oxides on the surface of the substrate to obtain a clean substrate.
[0085] Optionally, after completing step S201, the preparation method may further include: placing the product having the first buffer layer formed on the substrate into a metal-organic chemical vapor deposition (MOCVD) reaction chamber, controlling the temperature of the reaction chamber to 1000°C to 1200°C and the pressure to 150 torr to 500 torr, and performing annealing treatment in a hydrogen atmosphere for 5 min to 10 min.
[0086] In step S202 , a second buffer layer is formed on the first buffer layer.
[0087] Optionally, in step S202, the temperature of the reaction chamber can be controlled to be 1050° C. to 1200° C., the pressure can be 100 torr to 300 torr, NH3 and TMGa can be introduced to form an undoped GaN buffer layer on the first buffer layer to obtain a second buffer layer.
[0088] In step S203 , an N-type semiconductor layer is formed on the second buffer layer.
[0089] Optionally, in step S203, the temperature of the reaction chamber can be controlled to be 1100° C. to 1200° C., the pressure can be 100 torr to 300 torr, NH 3 , TMGa and SiH 4 can be introduced to form a Si-doped GaN layer on the second buffer layer to obtain an N-type semiconductor layer.
[0090] In step S204 , a light emitting layer is formed on the N-type semiconductor layer.
[0091] Optionally, NH3, TEGa and TMIn may be introduced in step S204 to form a plurality of pairs of alternately stacked InGaN quantum well layers and GaN quantum barrier layers on the N-type semiconductor layer to obtain a light-emitting layer.
[0092] Optionally, the growth temperature of the InGaN layer is 800° C. to 900° C., and the growth pressure is 100 torr to 200 torr.
[0093] Optionally, the growth temperature of the GaN layer is 900° C. to 1000° C., and the growth pressure is 100 torr to 200 torr.
[0094] In step S205 , an electron blocking layer is formed on the light emitting layer.
[0095] Optionally, in step S205, the temperature of the reaction chamber can be controlled to be 1000° C. to 1100° C., the pressure can be 50 torr to 100 torr, NH3, TEGa and TMAl can be introduced to form an AlGaN layer on the light-emitting layer to obtain an electron blocking layer.
[0096] In step S206 , a P-type semiconductor layer is formed on the electron blocking layer.
[0097] Optionally, in step S206, the temperature of the reaction chamber can be controlled to be 950° C. to 1050° C., the pressure can be 100 torr to 600 torr, NH3, TEGa and Cp2Mg can be introduced to form a Mg-doped GaN layer on the electron blocking layer to obtain a P-type semiconductor layer.
[0098] In step S207 , a P-type heavily doped InGaN layer is formed on the P-type semiconductor layer.
[0099] Optionally, in step S207, NH3, TEGa, TMIn and Cp2Mg may be introduced into the reaction chamber to form an InGaN layer heavily doped with Mg on the P-type semiconductor layer to obtain a P-type heavily doped InGaN layer.
[0100] Optionally, the growth temperature of the P-type heavily doped InGaN layer is 800°C to 900°C.
[0101] For example, the growth temperature of the P-type heavily doped InGaN layer may be 800° C., 850° C., or 900° C., etc.
[0102] Optionally, the growth pressure of the P-type heavily doped InGaN layer is 100 torr to 200 torr.
[0103] For example, the growth pressure of the P-type heavily doped InGaN layer may be 100 torr, 150 torr, or 200 torr.
[0104] In step S208 , an insertion layer is formed on the P-type heavily doped InGaN layer.
[0105] Optionally, in step S208, TMIn and SbH3 may be introduced into the reaction chamber to form an InSb layer on the P-type heavily doped InGaN layer to obtain an insertion layer.
[0106] Optionally, the growth temperature of the insertion layer is 400°C to 600°C.
[0107] For example, the growth temperature of the insertion layer may be 400° C., 500° C., 600° C., or the like.
[0108] Optionally, the insertion layer is grown at a pressure of 100 torr to 200 torr.
[0109] For example, the growth pressure of the insertion layer may be 100 torr, 150 torr, or 200 torr, etc.
[0110] In step S209 , an N-type heavily doped InGaN layer is formed on the insertion layer.
[0111] Optionally, in step S209, NH3, TEGa, TMIn and SiH4 may be introduced into the reaction chamber to form a Si-heavy doped InGaN layer on the insertion layer to obtain an N-type heavily doped InGaN layer.
[0112] Optionally, the growth temperature of the N-type heavily doped InGaN layer is 800° C. to 900° C.
[0113] For example, the growth temperature of the N-type heavily doped InGaN layer may be 800° C., 850° C., or 900° C., etc.
[0114] Optionally, the growth pressure of the N-type heavily doped InGaN layer is 100 torr to 200 torr.
[0115] For example, the growth pressure of the N-type heavily doped InGaN layer may be 100 torr, 150 torr, or 200 torr.
[0116] Through the above steps S207 to S209 , a tunneling layer can be formed on the P-type semiconductor layer.
[0117] Optionally, after completing step S209, the preparation method may include: controlling the temperature of the reaction chamber to be 650° C. to 850° C., and performing annealing treatment on the LED in a nitrogen atmosphere for a duration of 5 min to 15 min.
[0118] Optionally, the material, doping concentration, thickness, component content and number of cycles of each layer can be found in Figure 1 The detailed description of the related embodiments is omitted here.
[0119] The brightness and driving voltage of the LED provided in the embodiment of the present disclosure are exemplarily described below. Figure 1 The LED in the related embodiment adopts Figure 3 The control group LED refers to the LED in the related art, and the difference between the control group LED and the experimental group LED is that the control group LED does not have a tunneling layer set on the P-type semiconductor.
[0120] The brightness and driving voltage of the experimental group LED and the control group LED were tested under the condition of 120mA current. Table 1 shows the brightness and driving voltage test results of the experimental group LED and the control group LED.
[0121] Table 1 Brightness and driving voltage test results
[0122] Brightness(mW) Driving voltage(V) Experimental group LED 127.7 2.76 Control group LED 123.3 2.84
[0123] After testing, it was found that the brightness of the experimental group LED was 127.7mW, the driving voltage was 2.76V, and the brightness of the control group LED was 123.3mW, the driving voltage was 2.84V. That is, the brightness of the experimental group LED was higher than that of the control group LED, and the driving voltage of the experimental group LED was lower than that of the control group LED. Therefore, the LED provided by the embodiment of the present disclosure improves the luminous efficiency of the LED and reduces the driving voltage of the LED.
[0124] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.
Claims
1. A light emitting diode, characterized in that: It comprises an N-type semiconductor layer (10), a light-emitting layer (20), a P-type semiconductor layer (30) and a tunneling layer (40) which are stacked in sequence. The tunneling layer (40) comprises a P-type heavily doped InGaN layer (41), an insertion layer (42) and an N-type heavily doped InGaN layer (43) which are sequentially stacked in a direction away from the P-type semiconductor layer (30); the insertion layer (42) is an InSb layer or an InN layer.
2. The light emitting diode according to claim 1, characterized in that: The In component content of the P-type heavily doped InGaN layer (41) is lower than the In component content of the N-type heavily doped InGaN layer (43).
3. The light emitting diode according to claim 2, characterized in that: The light-emitting layer (20) comprises a plurality of pairs of quantum well layers (21) and quantum barrier layers (22) that are alternately stacked, the quantum well layer (21) comprises an In element, and the ratio of the In component content of the P-type heavily doped InGaN layer (41) to the In component content of the quantum well layer (21) is 0.9 to 1.
1.
4. The light emitting diode according to claim 2, characterized in that: The In component content of the P-type heavily doped InGaN layer (41) is 0.1 to 0.
3.
5. The light emitting diode according to claim 2, characterized in that: The In component content of the N-type heavily doped InGaN layer (43) is 0.2 to 0.
6.
6. The light emitting diode according to any one of claims 1 to 5, characterized in that: The doping concentration of the P-type heavily doped InGaN layer (41) is 1*10 20 / cm 3 Up to 5*10 21 / cm 3 The doping concentration of the N-type heavily doped InGaN layer (43) is 1*10 20 / cm 3 Up to 5*10 21 / cm 3 .
7. The light emitting diode according to any one of claims 1 to 5, characterized in that: The thickness of the P-type heavily doped InGaN layer (41) is 10 nm to 50 nm.
8. The light emitting diode according to any one of claims 1 to 5, characterized in that: The thickness of the N-type heavily doped InGaN layer (43) is 5 nm to 20 nm.
9. The light emitting diode according to any one of claims 1 to 5, characterized in that: The thickness of the insertion layer (42) is 1 nm to 5 nm.
10. A method for preparing a light emitting diode, characterized in that: include: forming a light emitting layer (20) on the N-type semiconductor layer (10); forming a P-type semiconductor layer (30) on the light-emitting layer (20); A tunneling layer (40) is formed on the P-type semiconductor layer (30), the tunneling layer (40) comprising a P-type heavily doped InGaN layer (41), an insertion layer (42) and an N-type heavily doped InGaN layer (43) which are sequentially stacked in a direction away from the P-type semiconductor layer (30), and the insertion layer (42) is an InSb layer or an InN layer.