Light-emitting diode chip with current expansion layer and preparation method of light-emitting diode chip

Abstract

The invention provides a light emitting diode chip with a current expansion layer and a preparation method thereof, and belongs to the technical field of semiconductors. The light-emitting diode chip comprises a first current expansion layer, an epitaxial layer and a second current expansion layer, the first current expansion layer and the second current expansion layer are respectively positioned on two opposite sides of the epitaxial layer; the first current expansion layer comprises well layers and barrier layers which are periodically and alternately stacked, the well layers are (Al < x > 1 < Ga < 1-x >) < 0.5 > In < 0.5 > P layers, x < 1 > is larger than or equal to 0.1 and smaller than or equal to 0.2, the barrier layers are (Al < x > 2 < Ga < 1-x > 2) < 0.5 > In < 0.5 > P layers, x < 2 > is larger than or equal to 0.3 and smaller than or equal to 0.4, and the thickness of the well layers is larger than that of the barrier layers. The problem of light absorption can be effectively solved.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductor technology, and in particular relates to a light emitting diode chip with a current spreading layer and a preparation method thereof. Background Art

[0002] A light emitting diode (LED) is a semiconductor diode that can convert electrical energy into light energy.

[0003] In the related art, the light-emitting diode chip is the main component of the light-emitting diode, which mainly includes an epitaxial layer and a current spreading layer for improving the current spreading capability. There is a light-emitting diode for plant lighting, which requires lower voltage and higher brightness than conventional light-emitting diodes. In order to meet the above requirements, the thickness of the current spreading layer needs to be designed to be larger and the Al component needs to be designed to be lower.

[0004] However, the design of the current spreading layer will lead to a serious light absorption problem, thereby reducing the light emitting efficiency of the light emitting diode. Summary of the invention

[0005] The embodiment of the present disclosure provides a light-emitting diode chip with a current spreading layer and a preparation method thereof, which can effectively solve the problem of light absorption. The technical solution is as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a light-emitting diode chip, comprising a first current spreading layer, an epitaxial layer, and a second current spreading layer;

[0007] The first current spreading layer and the second current spreading layer are respectively located on opposite sides of the epitaxial layer;

[0008] The first current spreading layer includes a well layer and a barrier layer that are periodically and alternately stacked. The well layer is (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer, 0.1≤x1≤0.2, the barrier layer is (Al x2 Ga 1-x2 ) 0.5 In 0.5 P layer, 0.3≤x2≤0.4, the thickness of the well layer is greater than the thickness of the barrier layer.

[0009] In one implementation of the present disclosure, the thickness of the well layer is 30 nm to 50 nm;

[0010] The thickness of the barrier layer is 4nm-6nm.

[0011] In another implementation of the present disclosure, the carrier concentration of the well layer is 0.5e18 to 1e18;

[0012] The carrier concentration of the barrier layer is 1e18-2e18.

[0013] In yet another implementation of the present disclosure, the number of stacking periods of the well layer and the barrier layer is 30-50.

[0014] In yet another implementation of the present disclosure, the second current spreading layer is a GaP layer, the thickness of the second current spreading layer is 0.5-1.5 μm, and the carrier concentration of the second current spreading layer is 2e18-4e18.

[0015] In yet another implementation of the present disclosure, the epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence;

[0016] The first semiconductor layer is N-type Al 0.5 In 0.5 P layer, the active layer is a multi-quantum well layer, and the second semiconductor layer is a P-type Al 0.5 In 0.5 P layer;

[0017] The first current spreading layer is located on a side of the first semiconductor layer facing away from the active layer, and the second current spreading layer is located on a side of the second semiconductor layer facing away from the active layer.

[0018] In another implementation of the present disclosure, the light-emitting diode chip further includes a first ohmic contact layer, an electrode fixing layer, and a roughening layer stacked in sequence;

[0019] The first ohmic contact layer is an N-type GaAs layer, and the electrode fixing layer is an N-type Ga 0.5 In 0.5 P layer, the roughened layer is N-type (Al x Ga 1-x ) 0.5 In 0.5 P layer, 0.4≤x≤1;

[0020] The first current spreading layer is located on a side of the roughening layer facing away from the electrode fixing layer.

[0021] In yet another implementation of the present disclosure, the light-emitting diode chip further includes a stress transition layer and a second ohmic contact layer;

[0022] The stress transition layer is P type (Al x Ga 1-x ) 0.5 In 0.5P layer, 0.4≤x≤1, the second ohmic contact layer is a P-type GaP layer;

[0023] The stress transition layer is located between the epitaxial layer and the second current spreading layer, and the second ohmic contact layer is located on a side of the second current spreading layer facing away from the stress transition layer.

[0024] On the other hand, an embodiment of the present disclosure provides a method for preparing a light emitting diode chip, the method comprising:

[0025] The well layer and the barrier layer are periodically prepared in sequence to prepare a first current spreading layer, wherein the well layer is (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer, 0.1≤x1≤0.2, the barrier layer is (Al x2 Ga 1-x2 ) 0.5 In 0.5 P layer, 0.3≤x2≤0.4, the thickness of the well layer is greater than the thickness of the barrier layer;

[0026] preparing an epitaxial layer;

[0027] A second current spreading layer is prepared.

[0028] In one implementation of the present disclosure, the well layer and the barrier layer are periodically prepared in sequence, including:

[0029] The growth temperature is set to 660°C to 690°C, the growth rate is set to 0.2nm / s to 0.4nm / s, the dopant is set to Si2H6, and the number of cycles is set to 30 to 50;

[0030] Growing the well layer with a thickness of 30nm to 50nm and a carrier concentration of 0.5e18 to 1e18;

[0031] The barrier layer is grown with a thickness of 4nm to 6nm and a carrier concentration of 1e18 to 2e18.

[0032] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0033] Since the first current spreading layer and the second current spreading layer are respectively arranged on both sides of the epitaxial layer, when the light-emitting diode chip is working, the current spreading on both sides of the epitaxial layer can be realized through the first current spreading layer and the second current spreading layer. In addition, the first current spreading layer includes a well layer and a barrier layer that are periodically and alternately stacked, wherein, compared with the barrier layer, the well layer has a large thickness and a low Al component, which is conducive to current spreading, and a low doping concentration, which is conducive to reducing light absorption, while the barrier layer has a high doping concentration, which is conducive to current spreading, and a small thickness, a high Al component, and a large band gap, which is conducive to reducing light absorption. The first current spreading layer of the superlattice formed in this way not only ensures the longitudinal current spreading, but also increases the lateral current spreading.

[0034] That is to say, by designing the first current spreading layer of the superlattice with alternating well layers and barrier layers of different thicknesses and different doping concentrations, and by reasonably adjusting the thickness, Al composition, and doping concentration of the well layers and barrier layers, the well layers and barrier layers can both ensure the overall current spreading capability of the first current spreading layer and reduce the overall light absorption of the first current spreading layer. In this way, the light-emitting diode chip not only improves the voltage, but also improves the luminous efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 is a structural schematic diagram of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0037] Figure 2 is a schematic structural diagram of another light-emitting diode chip provided by an embodiment of the present disclosure;

[0038] Figure 3 is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0039] Figure 4 It is a flow chart of another method for preparing a light emitting diode chip provided in an embodiment of the present disclosure.

[0040] The symbols in the figure mean the following:

[0041] 1. The first current spreading layer;

[0042] 11. well layer; 12. barrier layer;

[0043] 2. Epitaxial layer;

[0044] 21, first semiconductor layer; 22, active layer; 221, quantum well layer; 222, quantum barrier layer; 23, second semiconductor layer;

[0045] 3. Second current spreading layer;

[0046] 4. First ohmic contact layer;

[0047] 5. Electrode firming layer;

[0048] 6. Roughening layer;

[0049] 7. Stress transition layer;

[0050] 8. Second ohmic contact layer;

[0051] 9. Substrate;

[0052] 10. Buffer layer;

[0053] 101. Erosion cutoff layer.

[0054] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0056] The embodiment of the present disclosure provides a light emitting diode chip, Figure 1 is a schematic diagram of the structure of the light emitting diode chip, see Figure 1 In this embodiment, the light emitting diode chip includes a first current spreading layer 1 , an epitaxial layer 2 and a second current spreading layer 3 .

[0057] The first current spreading layer 1 and the second current spreading layer 3 are respectively located on opposite sides of the epitaxial layer 2. The first current spreading layer 1 includes a well layer 11 and a barrier layer 12 which are periodically and alternately stacked. The well layer 11 is (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer, 0.1≤x1≤0.2, barrier layer 12 is (Al x2 Ga 1-x2 ) 0.5 In 0.5 P layer, 0.3≤x2≤0.4, the thickness of the well layer 11 is greater than the thickness of the barrier layer 12 .

[0058] Since the first current spreading layer 1 and the second current spreading layer 3 are respectively arranged on both sides of the epitaxial layer 2, when the light-emitting diode chip is working, the current spreading on both sides of the epitaxial layer 2 can be realized through the first current spreading layer 1 and the second current spreading layer 3. In addition, the first current spreading layer 1 includes a well layer 11 and a barrier layer 12 that are periodically and alternately stacked, wherein, compared with the barrier layer 12, the well layer 11 has a large thickness and a low Al component, which is conducive to current spreading, and a low doping concentration, which is conducive to reducing light absorption, while the barrier layer 12 has a high doping concentration, which is conducive to current spreading, and a small thickness, a high Al component, and a large band gap, which is conducive to reducing light absorption. The first current spreading layer 1 of the superlattice formed in this way not only ensures longitudinal current spreading, but also increases lateral current spreading.

[0059] That is to say, by designing the first current spreading layer 1 of the superlattice of alternating well layers 11 and barrier layers 12 of different thicknesses and different doping concentrations, and by reasonably adjusting the thickness, Al composition, and doping concentration of the well layers 11 and barrier layers 12, the well layers 11 and barrier layers 12 can ensure the overall current spreading capability of the first current spreading layer 1 and reduce the overall light absorption of the first current spreading layer 1. In this way, the light-emitting diode chip not only improves the voltage, but also improves the luminous efficiency.

[0060] In this embodiment, the thickness of the well layer 11 is 30 nm to 50 nm, and the thickness of the barrier layer 12 is 4 nm to 6 nm.

[0061] In the above implementation, the thickness of the well layer 11 is greater than the thickness of the barrier layer 12. Furthermore, designing the thickness of the well layer 11 and the barrier layer 12 within the above numerical range not only helps to improve the voltage of the LED chip, but also can improve the luminous efficiency of the LED chip.

[0062] Exemplarily, the thickness of the well layer 11 is 40 nm, and the thickness of the barrier layer 12 is 5 nm. Of course, in other embodiments, the thickness of the well layer 11 and the barrier layer 12 can be designed to be other values ​​within the above range according to actual needs, and the present disclosure does not limit this.

[0063] In this embodiment, V / III of the first current spreading layer 1 is 30-40.

[0064] In this embodiment, the carrier concentration of the well layer 11 is 0.5e18-1e18, and the carrier concentration of the barrier layer 12 is 1e18-2e18.

[0065] In the above implementation, the carrier concentration of the well layer 11 is less than the carrier concentration of the barrier layer 12, and the doping concentration of the well layer 11 is also less than the doping concentration of the barrier layer 12. In this way, the well layer 11 and the barrier layer 12 are alternately stacked, which is not only conducive to improving the voltage of the light-emitting diode chip, but also can improve the luminous efficiency of the light-emitting diode chip.

[0066] In this embodiment, the number of stacking cycles of the well layer 11 and the barrier layer 12 is 30-50.

[0067] In the above implementation, the well layer 11 and the barrier layer 12 are stacked once, which is a stacking period. Designing the stacking period of the well layer 11 and the barrier layer 12 to the above value can not only ensure the functionality of the first current spreading layer 1, but also avoid affecting the preparation efficiency of the first current spreading layer 1 due to too large a number of cycles of the well layer 11 and the barrier layer 12.

[0068] In this embodiment, the second current spreading layer 3 is a GaP layer, the thickness of the second current spreading layer 3 is 0.5-1.5 μm, and the carrier concentration of the second current spreading layer 3 is 2e18-4e18.

[0069] In the above implementation, the thickness and carrier concentration of the second current spreading layer 3 are designed to the above values, which not only ensures the longitudinal current spreading, but also increases the lateral current spreading. In addition, it is beneficial to improve the voltage of the LED chip and improve the luminous efficiency of the LED chip.

[0070] In this embodiment, the epitaxial layer 2 includes a first semiconductor layer 21 , an active layer 22 , and a second semiconductor layer 23 which are stacked in sequence.

[0071] The first semiconductor layer 21 is N-type Al 0.5 In 0.5 P layer, the active layer 22 is a multi-quantum well layer, and the second semiconductor layer 23 is a P-type Al 0.5 In 0.5 The first current spreading layer 1 is located on a side of the first semiconductor layer 21 facing away from the active layer 22 , and the second current spreading layer 3 is located on a side of the second semiconductor layer 23 facing away from the active layer 22 .

[0072] In the above implementation, the first semiconductor layer 21 is an N-type layer, the second semiconductor layer 23 is a P-type layer, and energy transition occurs between the first semiconductor layer 21 and the second semiconductor layer 23, so that light can be emitted at the active layer 22. In the first current spreading layer 1, the well layer 11 is an N-type (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer, 0.1≤x1≤0.2, barrier layer 12 is N-type (Al x2 Ga1-x2 ) 0.5 In 0.5 P layer, 0.3≤x2≤0.4. The second current spreading layer 3 is a P-type GaP layer.

[0073] In addition, since the first semiconductor layer 21 is N-type Al 0.5 In 0.5 P layer, the second semiconductor layer 23 is P-type Al 0.5 In 0.5 P layer, so the light-emitting diode chip is a red light chip.

[0074] Exemplarily, the first semiconductor layer 21 has a thickness of 250 nm to 800 nm, a V / III ratio of 30 to 40, and a carrier concentration of 1e18 to 2e18.

[0075] Exemplarily, the second semiconductor layer 23 has a thickness of 100 nm to 1000 nm, a V / III ratio of 30 to 40, and a carrier concentration of 0.5e18 to 1e18.

[0076] Exemplarily, the multi-quantum well layer includes periodically alternately stacked quantum well layers 221 and quantum barrier layers 222. The thickness of the quantum well layer 221 is 2nm to 5nm, the thickness of the quantum barrier layer 222 is 5nm to 10nm, the stacking period number is 6 to 20, and V / III is 30 to 40.

[0077] Figure 2 A schematic diagram of the structure of another light emitting diode chip provided in an embodiment of the present disclosure, Figure 2 and Figure 1 The difference is that the first current spreading layer 1 and the epitaxial layer 2 are simplified, and more other sublayers are shown.

[0078] Combination Figure 2 In this embodiment, the light emitting diode chip further includes a substrate 9 , and the substrate 9 is a GaAs substrate 9 .

[0079] In the above implementation, the substrate 9 can provide a supporting foundation for the epitaxial layer 2 .

[0080] In this embodiment, the light-emitting diode chip further includes a buffer layer 10, which is located on one side of the substrate 9. The buffer layer 10 is an N-type GaAs layer, has a thickness of 300nm to 600nm, V / III of 30 to 40, and a carrier concentration of 1e18 to 2e18.

[0081] In the above implementation, by providing the buffer layer 10, a good foundation can be provided for the preparation of other sub-layers, which is helpful to solve the problem of lattice mismatch. In addition, by designing the thickness of the buffer layer 10 to be within the above range, on the one hand, it can avoid reducing the quality of the subsequently grown crystals due to being too thin, and on the other hand, it can avoid increasing the absorption of light by the buffer layer 10 due to being too thick, thereby reducing the luminous efficiency of the light-emitting diode chip.

[0082] In this embodiment, the light emitting diode further includes an etching stop layer 101, which is located on the side of the buffer layer 10 facing away from the substrate 9. The etching stop layer 101 is an N-type Ga 0.5 In 0.5 The thickness of the P layer and the etching stop layer 101 is 100 nm to 200 nm, V / III is 30 to 40, and the carrier concentration is 1e18 to 3e18.

[0083] In this embodiment, the light emitting diode chip further includes a first ohmic contact layer 4, an electrode fixing layer 5, and a roughening layer 6 which are stacked in sequence. The first ohmic contact layer 4 is an N-type GaAs layer, and the electrode fixing layer 5 is an N-type GaAs layer. 0.5 In 0.5 P layer, the rough layer 6 is N type (Al x Ga 1-x ) 0.5 In 0.5 P layer, 0.4≤x≤1. The first current spreading layer 1 is located on the side of the roughening layer 6 facing away from the electrode fixing layer 5 .

[0084] In the above implementation, the first ohmic contact layer 4, the electrode fixing layer 5, and the roughening layer 6 are sequentially stacked on the corrosion stop layer 101. Among them, the first ohmic contact layer 4 is an N-type ohmic contact layer for realizing ohmic contact, the electrode fixing layer 5 is used to improve the adhesion firmness of the electrode, and the roughening layer 6 is used to reduce the total reflection of light on one side of the first semiconductor, thereby effectively improving the luminous efficiency.

[0085] Exemplarily, the first ohmic contact layer 4 has a thickness of 30 nm to 90 nm, a V / III ratio of 30 to 40, and a carrier concentration of 4e18 to 6e18.

[0086] Exemplarily, the electrode securing layer 5 has a thickness of 10 nm to 20 nm, a V / III ratio of 30 to 40, and a carrier concentration of 1e18 to 2e18.

[0087] Exemplarily, the thickness of the roughened layer 6 is 1-2 μm, V / III is 30-40, and the carrier concentration is 1e18-2e18.

[0088] In this embodiment, the light emitting diode chip further includes a stress transition layer 7 and a second ohmic contact layer 8 .

[0089] The stress transition layer 7 is P-type (Al x Ga 1-x ) 0.5 In 0.5 P layer, 0.4≤x≤1, the second ohmic contact layer 8 is a P-type GaP layer. The stress transition layer 7 is located between the epitaxial layer 2 and the second current spreading layer 3 , and the second ohmic contact layer 8 is located on the side of the second current spreading layer 3 facing away from the stress transition layer 7 .

[0090] In the above implementation, the second ohmic contact layer 8 is a P-type ohmic contact layer for achieving ohmic contact, and the stress transition layer 7 is used to reduce stress, thereby improving the growth quality.

[0091] Exemplarily, the stress transition layer 7 has a thickness of 20 nm to 50 nm, a V / III ratio of 30 to 40, and a carrier concentration of 4e18 to 6e18.

[0092] Exemplarily, the second ohmic contact layer 8 has a thickness of 50 nm to 200 nm and a carrier concentration of 0.5e20 to 1e20.

[0093] Figure 3 A method for preparing a light emitting diode chip provided in an embodiment of the present disclosure, combined with Figure 3 In this embodiment, the preparation method comprises:

[0094] Step 301: Periodically prepare a well layer 11 and a barrier layer 12 in sequence to prepare a first current spreading layer 1, wherein the well layer 11 is (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer, 0.1≤x1≤0.2, barrier layer 12 is (Al x2 Ga 1-x2 ) 0.5 In 0.5 P layer, 0.3≤x2≤0.4, the thickness of the well layer 11 is greater than the thickness of the barrier layer 12 .

[0095] Step 302: Prepare an epitaxial layer 2.

[0096] Step 303: preparing a second current spreading layer 3.

[0097] Since the first current spreading layer 1 and the second current spreading layer 3 are respectively arranged on both sides of the epitaxial layer 2, the light-emitting diode chip prepared by the preparation method provided by the embodiment of the present disclosure can realize the current spreading on both sides of the epitaxial layer 2 through the first current spreading layer 1 and the second current spreading layer 3 when working. In addition, the first current spreading layer 1 includes a well layer 11 and a barrier layer 12 that are periodically and alternately stacked, wherein, compared with the barrier layer 12, the well layer 11 has a large thickness and a low Al component on the one hand, which is conducive to the realization of current spreading, and a low doping concentration on the other hand, which is conducive to reducing light absorption, while the barrier layer 12 has a high doping concentration on the one hand, which is conducive to current spreading, and a small thickness, a high Al component, and a large band gap on the other hand, which is conducive to reducing light absorption. The first current spreading layer 1 of the superlattice formed in this way not only ensures the longitudinal current spreading, but also increases the lateral current spreading.

[0098] That is to say, by designing the first current spreading layer 1 of the superlattice of alternating well layers 11 and barrier layers 12 of different thicknesses and different doping concentrations, and by reasonably adjusting the thickness, Al composition, and doping concentration of the well layers 11 and barrier layers 12, the well layers 11 and barrier layers 12 can ensure the overall current spreading capability of the first current spreading layer 1 and reduce the overall light absorption of the first current spreading layer 1. In this way, the light-emitting diode chip not only improves the voltage, but also improves the luminous efficiency.

[0099] Figure 4 Another method for preparing a light emitting diode chip provided in an embodiment of the present disclosure is combined with Figure 4 In this embodiment, the preparation method comprises:

[0100] Step 401: Provide a substrate 9.

[0101] Exemplarily, the substrate 9 is a GaAs substrate 9

[0102] Step 402 : preparing a buffer layer 10 .

[0103] Exemplarily, the buffer layer 10 is an N-type GaAs layer, the growth temperature is set to 660° C. to 690° C., the growth thickness is set to 300 nm to 600 nm, the growth rate is set to 0.4 nm / s to 0.5 nm / s, and the dopant is set to Si2H6.

[0104] Step 403: Prepare the corrosion stop layer 101.

[0105] Exemplarily, the corrosion stop layer 101 is N-type Ga 0.5 In 0.5 For the P layer, the growth temperature is set to 660° C. to 690° C., the growth thickness is set to 100 nm to 200 nm, the growth rate is set to 0.4 nm / s to 0.5 nm / s, and the dopant is set to Si2H6.

[0106] Step 404: preparing a first ohmic contact layer 4.

[0107] Exemplarily, the first ohmic contact layer 4 is an N-type GaAs layer, the growth temperature is set to 660° C. to 690° C., the growth thickness is set to 30 nm to 90 nm, the growth rate is set to 0.8 nm / s to 1.2 nm / s, and the dopant is set to Si2H6.

[0108] Step 405: Prepare the electrode fixing layer 5.

[0109] Exemplarily, the electrode fixing layer 5 is N-type Ga 0.5 In 0.5 For the P layer, the growth temperature is set to 660° C. to 690° C., the growth thickness is set to 10 nm to 20 nm, the growth rate is set to 0.4 nm / s to 0.5 nm / s, and the dopant is set to Si2H6.

[0110] Step 406: Prepare a roughened layer 6.

[0111] For example, the roughening layer 6 is N-type (Al x Ga 1-x ) 0.5 In 0.5 P layer, 0.4≤x≤1, the growth temperature is set to 690℃~720℃, the growth thickness is set to 1~2μm, the growth rate is set to 0.2nm / s~0.4nm / s, and the dopant is set to Si2H6.

[0112] Step 407: preparing a first current spreading layer 1.

[0113] Exemplarily, the growth temperature is set to 660°C to 690°C, the growth rate is set to 0.2nm / s to 0.4nm / s, the dopant is set to Si2H6, the number of periods is set to 30 to 50, and the well layer 11 and the barrier layer 12 are grown periodically in sequence. The growth thickness of the well layer 11 is 30nm to 50nm, and the growth thickness of the barrier layer 12 is 4nm to 6nm.

[0114] Step 408: Prepare epitaxial layer 2.

[0115] In this embodiment, step 407 includes the following steps:

[0116] Step 4081 : preparing a first semiconductor layer 21 .

[0117] For example, the first semiconductor layer 21 is an N-type Al 0.5 In 0.5For the P layer, the growth temperature is set to 700° C. to 720° C., the growth thickness is set to 250 nm to 800 nm, and the growth rate is set to 0.6 nm / s to 0.8 nm / s.

[0118] Step 4082 : Prepare the active layer 22 .

[0119] Exemplarily, the active layer 22 is a multi-quantum well layer, and the quantum well layer 221 and the quantum barrier layer 222 are periodically and alternately grown. The growth temperature is set to 670°C to 700°C, the growth rate is set to 0.3nm / s to 0.4nm / s, the number of stacking periods is 6 to 20, the growth thickness of the quantum well layer 221 is set to 2nm to 5nm, and the growth thickness of the quantum barrier layer 222 is set to 5nm to 10nm.

[0120] Step 4083 : Prepare the second semiconductor layer 23 .

[0121] For example, the second semiconductor layer 23 is a P-type Al 0.5 In 0.5 For the P layer, the growth temperature is set to 700° C. to 720° C., the growth thickness is set to 100 nm to 1000 nm, the growth rate is set to 0.3 nm / s to 0.4 nm / s, and the dopant is set to Cp2Mg.

[0122] Step 409: preparing a stress transition layer 7.

[0123] For example, the stress transition layer 7 is of P type (Al x Ga 1-x ) 0.5 In 0.5 P layer, 0.4≤x≤1, the growth temperature is set to 700°C~720°C, the growth thickness is set to 20nm~50nm, the growth rate is set to 0.2nm / s~0.3nm / s, and the dopant is set to Cp2Mg.

[0124] Step 410: preparing a second current spreading layer 3.

[0125] Exemplarily, the second current spreading layer 3 is a P-type GaP layer, the growth temperature is set to 800° C. to 850° C., the growth thickness is set to 0.5 to 1.5 μm, the growth rate is set to 2 nm / s to 4 nm / s, and the dopant is set to Cp2Mg.

[0126] Step 411: preparing a second ohmic contact layer 8.

[0127] Exemplarily, the second ohmic contact layer 8 is a P-type GaP layer, the growth temperature is set to 640° C. to 660° C., the growth thickness is set to 50 nm to 200 nm, the growth rate is set to 1 nm / s to 2 nm / s, and the dopant is set to CCL4.

[0128] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0129] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode chip, characterized in that: It comprises a first current spreading layer (1), an epitaxial layer (2) and a second current spreading layer (3); The first current spreading layer (1) and the second current spreading layer (3) are respectively located on opposite sides of the epitaxial layer (2); The first current spreading layer (1) comprises a well layer (11) and a barrier layer (12) which are periodically and alternately stacked, wherein the well layer (11) is (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer, 0.1≤x1≤0.2, the barrier layer (12) is (Al x2 Ga 1-x2 ) 0.5 In 0.5 P layer, 0.3≤x2≤0.4, the thickness of the well layer (11) is greater than the thickness of the barrier layer (12).

2. The light emitting diode chip according to claim 1, characterized in that: The thickness of the well layer (11) is 30nm to 50nm; The thickness of the barrier layer (12) is 4 nm to 6 nm.

3. The light emitting diode chip according to claim 1, characterized in that: The carrier concentration of the well layer (11) is 0.5e18 to 1e18; The carrier concentration of the barrier layer (12) is 1e18-2e18.

4. The light emitting diode chip according to claim 1, characterized in that: The number of stacking cycles of the well layer (11) and the barrier layer (12) is 30 to 50.

5. The light emitting diode chip according to claim 1, characterized in that: The second current spreading layer (3) is a GaP layer, the thickness of the second current spreading layer (3) is 0.5-1.5 μm, and the carrier concentration of the second current spreading layer (3) is 2e18-4e18.

6. The light emitting diode chip according to claim 1, characterized in that: The epitaxial layer (2) comprises a first semiconductor layer (21), an active layer (22) and a second semiconductor layer (23) which are stacked in sequence; The first semiconductor layer (21) is N-type Al 0.5 In 0.5 P layer, the active layer (22) is a multi-quantum well layer (11), and the second semiconductor layer (23) is a P-type Al 0.5 In 0.5 P layer; The first current spreading layer (1) is located on a side of the first semiconductor layer (21) facing away from the active layer (22), and the second current spreading layer (3) is located on a side of the second semiconductor layer (23) facing away from the active layer (22).

7. The light emitting diode chip according to claim 1, characterized in that: It also includes a first ohmic contact layer (4), an electrode fixing layer (5), and a roughening layer (6) which are stacked in sequence; The first ohmic contact layer (4) is an N-type GaAs layer, and the electrode fixing layer (5) is an N-type Ga 0.5 In 0.5 P layer, the roughened layer (6) is N-type (Al x Ga 1-x ) 0.5 In 0.5 P layer, 0.4≤x≤1; The first current spreading layer (1) is located on a side of the roughening layer (6) facing away from the electrode fixing layer (5).

8. The light emitting diode chip according to claim 1, characterized in that: It also includes a stress transition layer (7) and a second ohmic contact layer (8); The stress transition layer (7) is of P type (Al x Ga 1-x ) 0.5 In 0.5 P layer, 0.4≤x≤1, the second ohmic contact layer (8) is a P-type GaP layer; The stress transition layer (7) is located between the epitaxial layer (2) and the second current spreading layer (3), and the second ohmic contact layer (8) is located on a side of the second current spreading layer (3) facing away from the stress transition layer (7).

9. A method for preparing a light emitting diode chip, characterized in that: For preparing the light emitting diode chip according to claim 1, the preparation method comprises: The well layer (11) and the barrier layer (12) are periodically prepared in sequence to prepare a first current spreading layer (1), wherein the well layer (11) is (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer, 0.1≤x1≤0.2, the barrier layer (12) is (Al x2 Ga 1-x2 ) 0.5 In 0.5 P layer, 0.3≤x2≤0.4, the thickness of the well layer (11) is greater than the thickness of the barrier layer (12); preparing an epitaxial layer (2); A second current spreading layer (3) is prepared.

10. The preparation method according to claim 9, characterized in that: The well layer (11) and the barrier layer (12) are periodically prepared in sequence, comprising: The growth temperature is set to 660°C to 690°C, the growth rate is set to 0.2nm / s to 0.4nm / s, the dopant is set to Si2H6, and the number of cycles is set to 30 to 50; Growing the well layer (11) with a thickness of 30 nm to 50 nm and a carrier concentration of 0.5e18 to 1e18; The barrier layer (12) is grown with a thickness of 4nm to 6nm and a carrier concentration of 1e18 to 2e18.

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