Driving circuit, full-bridge driving circuit, wireless charging circuit and chip

Abstract

The invention relates to the field of driving circuits, and discloses a driving circuit, a full-bridge driving circuit, a wireless charging circuit and a chip, and the driving circuit is characterized in that the input end of a high-side voltage detection module is connected with the output end of a high-side driving module, and the high-side voltage detection module samples a high-side driving voltage output by the high-side driving module; under the condition that the high-side driving voltage is reduced to a first threshold voltage, a high-side detection signal is output, and the high-side detection signal triggers the low-side driving module to be conducted; the input end of the low-side voltage detection module is connected with the output end of the low-side driving module, the low-side voltage detection module samples the low-side driving voltage output by the low-side driving module and outputs a low-side detection signal when the low-side driving voltage is reduced to a second threshold voltage, and the low-side detection signal triggers the high-side driving module to be conducted. According to the embodiment of the invention, the dead time can be adaptively adjusted.

Description

Technical Field

[0001] The present application relates to the field of drive circuits, and in particular to a drive circuit, a full-bridge drive circuit, a wireless charging circuit and a chip. Background Art

[0002] The existing SOC (System on Chip) full-bridge drive circuit integrates the main control chip and the driver chip together, and places the power tube outside the chip to improve heat dissipation. However, in order to avoid the power tubes from being turned on at the same time, the SOC solution usually adopts a fixed dead time to avoid the upper and lower power tubes from being turned on at the same time. However, since the dead time is fixed and cannot be dynamically adjusted according to actual working conditions, this leads to large reverse conduction losses in the power tubes in the SOC solution, affecting the power transmission efficiency.

[0003] In summary, it is necessary to provide a driving circuit, a full-bridge driving circuit, a wireless charging circuit and a chip that can adaptively adjust the dead time. Summary of the invention

[0004] The present application proposes a driving circuit, a full-bridge driving circuit, a wireless charging circuit and a chip, which can adaptively adjust the dead time.

[0005] In a first aspect, the present application proposes a driving circuit, comprising: a high-side voltage detection module, a low-side voltage detection module, a high-side driving module and a low-side driving module;

[0006] The input end of the high-side voltage detection module is connected to the output end of the high-side driving module, the high-side voltage detection module samples the high-side driving voltage output by the high-side driving module, and outputs a high-side detection signal when the high-side driving voltage drops to a first threshold voltage, and the high-side detection signal triggers the low-side driving module to turn on;

[0007] The input end of the low-side voltage detection module is connected to the output end of the low-side driving module. The low-side voltage detection module samples the low-side driving voltage output by the low-side driving module, and outputs a low-side detection signal when the low-side driving voltage drops to a second threshold voltage. The low-side detection signal triggers the high-side driving module to turn on.

[0008] Optionally, the high-side voltage detection module includes a level shift unit and a first potential conversion unit;

[0009] The input end of the level shift unit is connected to the output end of the high-side driving module, and the output end is connected to the first potential conversion unit; the level shift unit clamps the value of the high-side driving voltage and shapes the waveform of the high-side driving voltage;

[0010] The output end of the first potential conversion unit is connected to the high-side driving module; the first potential conversion unit converts the shaped high-side driving voltage from the high voltage domain to the low voltage domain, and generates a first detection voltage according to the high-side driving voltage in the low voltage domain, and the first detection voltage is used as a high-side detection signal.

[0011] Optionally, the level shift unit includes a clamping subunit and a first shifting subunit;

[0012] The input end of the clamping subunit is connected to the output end of the high-side driving module, and the output end is connected to the input end of the first shifting subunit;

[0013] An output terminal of the first shift subunit is connected to the first potential conversion unit.

[0014] Optionally, the high-side voltage detection module further includes a voltage protection unit, and the voltage protection unit is arranged between the level shifting unit and the first potential conversion unit.

[0015] Optionally, the low-side voltage detection module includes a switch unit and a second potential conversion unit;

[0016] The input end of the switch unit is connected to the output end of the low-side driving module, and the output end is connected to the second potential conversion unit; the switch unit is turned on or off according to the potential of the low-side driving voltage in the high voltage domain to generate a turn-on voltage or a turn-off voltage;

[0017] The output end of the second potential conversion unit is connected to the low-side driving module; the second potential conversion unit generates a second detection voltage in the low voltage domain according to the on-voltage or the off-voltage, and the second detection voltage is used as a low-side detection signal.

[0018] Optionally, the high-side driver module includes a high-side voltage bias unit and a high-side driver unit;

[0019] The high-side driving unit generates the high-side driving voltage according to the driving signal and the high-side potential;

[0020] The output end of the high-side voltage bias unit is connected to the high-side driving unit. The high-side voltage bias unit generates the high-side potential according to the bootstrap voltage and the switch node voltage. The high-side potential is the operating voltage of the high-side driving unit.

[0021] Optionally, the high-side voltage bias unit includes a first high-side potential subunit and a second high-side potential subunit;

[0022] The first high-side potential subunit generates a first high-side operating voltage according to the bootstrap voltage when being turned on;

[0023] When the second high-side potential subunit is turned on, it generates a second high-side operating voltage according to the switch node voltage.

[0024] Optionally, the first high-side potential subunit includes a first Zener transistor, a first NMOS transistor and a first PMOS transistor;

[0025] The bootstrap voltage is input to the cathode of the first Zener tube, and the anode is respectively connected to the drain of the first NMOS tube and the gate of the first PMOS tube;

[0026] The switch node voltage is input to the source of the first NMOS tube and the drain of the first PMOS tube;

[0027] The source of the first PMOS tube outputs the first high-side operating voltage.

[0028] Optionally, the second high-side potential subunit includes a second Zener transistor and a second NMOS transistor;

[0029] The positive electrode of the second Zener tube inputs the switch node voltage, and the negative electrode is connected to the source of the second NMOS tube;

[0030] The drain of the second NMOS tube inputs the bootstrap voltage, and the source outputs the second high-side operating voltage.

[0031] Optionally, the high-side driving unit includes a low-to-high level shifting subunit, a high-to-low level shifting subunit and a high-side output switch subunit;

[0032] The output end of the low-to-high level shift subunit is connected to the high-to-low level shift subunit, and the low-to-high level shift subunit also inputs the driving signal and the bootstrap voltage; the low-to-high level shift subunit converts the low voltage domain from the working voltage to the ground terminal voltage into a high voltage domain output voltage from the bootstrap voltage to the high-side potential according to the driving signal and the bootstrap voltage;

[0033] The high-to-low level shift subunit converts the input high-side potential to the high voltage domain of the bootstrap voltage into a low voltage domain output voltage from the switch node voltage to the high-side potential;

[0034] The high-side output switch subunit is connected to the output end of the low-to-high level shift subunit and the output end of the high-to-low level shift subunit; the high-side output switch subunit outputs the high-side drive voltage according to the high voltage domain output voltage and the low voltage domain output voltage.

[0035] Optionally, the high-side driving unit further includes a first delay matching subunit, a second delay matching subunit, a first driving buffer subunit and a second driving buffer subunit;

[0036] The first delay matching subunit is arranged between the low-to-high level shifting subunit and the high-side output switch subunit; the first delay matching subunit delays and outputs the high voltage domain output voltage;

[0037] The first driving buffer subunit is arranged between the first delay matching subunit and the high-side output switch subunit;

[0038] The second delay matching subunit is connected to the high-to-low level shifting subunit and the second driving buffer subunit respectively;

[0039] The second driving buffer subunit is also connected to the high-side output switch subunit; the second delay matching subunit delays the output of the low voltage domain output voltage.

[0040] Optionally, the low-side driving module includes: a low-side voltage bias unit and a low-side driving unit;

[0041] The low-side driving unit generates the low-side driving voltage according to the driving signal and the low-side potential;

[0042] An output end of the low-side voltage bias unit is connected to the low-side driving unit, and the low-side voltage bias unit generates the low-side potential according to a first voltage domain.

[0043] Optionally, the low-side driving unit comprises: a second shifting subunit, a third delay matching subunit and a low-side output switch subunit;

[0044] The second shift subunit and the third delay matching subunit are both connected to the low-side output switch subunit; the second shift subunit and the third delay matching subunit are both input with the driving signal;

[0045] The second shift subunit converts the driving signal in the low voltage domain into a first high voltage in the first voltage domain of the high voltage domain or a voltage of the low side potential according to the low side potential;

[0046] The third delay matching subunit delays and outputs the driving signal;

[0047] The low-side output switch subunit outputs the low-side drive voltage according to the first high-level voltage or the low-side potential voltage and the delayed output drive signal.

[0048] Optionally, it also includes a high-side logic module and a low-side logic module;

[0049] The high-side logic module is arranged between the high-side driving module and the low-side voltage detection module; the high-side logic module adjusts the driving signal input to the high-side driving module according to the enable signal;

[0050] The low-side logic module is arranged between the low-side driving module and the high-side voltage detection module; the low-side logic module adjusts the driving signal input to the low-side driving module according to the enable signal.

[0051] In a second aspect, the present application provides a full-bridge drive circuit, comprising: a first power MOS tube, a second power MOS tube, a third power MOS tube, a fourth power MOS tube and two drive circuits, wherein the drive circuit is the drive circuit described in any one of the first aspect;

[0052] The output end of the high-side driving module and the input end of the high-side voltage detection module of one of the two driving circuits are both connected to the gate of the first power MOS tube, and the output end of the low-side driving module and the input end of the low-side voltage detection module are both connected to the gate of the second power MOS tube;

[0053] The output end of the high-side driving module and the input end of the high-side voltage detection module of the other driving circuit of the two driving circuits are both connected to the gate of the third power MOS tube, and the output end of the low-side driving module and the input end of the low-side voltage detection module are both connected to the gate of the fourth power MOS tube.

[0054] In a third aspect, the present application proposes a wireless charging circuit, comprising the full-bridge drive circuit described in the second aspect.

[0055] In a fourth aspect, the present application proposes a chip on which the driving circuit described in any one of the first aspect, or the bridge driving circuit described in the second aspect, or the wireless charging circuit described in the third aspect is integrated.

[0056] The advantages of the present application are: the low-side driving voltage and the high-side driving voltage are sampled respectively by the high-side voltage detection module and the low-side voltage detection module, and a high-side detection signal or a low-side detection signal is output according to the sampling result, and the low-side driving module or the high-side driving module is driven to be turned on, so that the low-side driving module and the high-side driving module can be turned on or off respectively according to the actual situation, so that the driving circuit can adaptively adjust the dead time. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0058] Figure 1 is a schematic diagram of a driving circuit provided by the present application;

[0059] Figure 2 is a schematic diagram of another driving circuit provided by the present application;

[0060] Figure 3 It is a schematic diagram of the connection between a driving circuit and a power tube provided by the present application;

[0061] Figure 4 It is a schematic diagram of a high-side voltage detection module of a driving circuit provided by the present application;

[0062] Figure 5 It is a schematic diagram of a high-side voltage detection module of another driving circuit provided by the present application;

[0063] Figure 6 It is a schematic diagram of a low-side voltage detection module of a driving circuit provided by the present application;

[0064] Figure 7 is a schematic diagram of a low-side voltage detection module of another driving circuit provided by the present application;

[0065] Figure 8 is a schematic diagram of a high-side driver module of a driver circuit provided by the present application;

[0066] Fig. 9 is a schematic diagram of a high-side voltage bias unit of another driving circuit provided by the present application;

[0067] Fig.10 is a schematic diagram of a high-side drive unit of a drive circuit provided by the present application;

[0068] Fig.11 is a schematic diagram of a high-side driving unit of another driving circuit provided by the present application;

[0069] Fig.12 It is a schematic diagram of a low-to-high level shift subunit of a driving circuit provided by the present application;

[0070] Fig.13 It is a schematic diagram of a high-to-low level shift subunit of a driving circuit provided by the present application;

[0071] Fig.14is a schematic diagram of a first delay matching subunit of a driving circuit provided by the present application;

[0072] Fig.15 is a schematic diagram of a second delay matching subunit of a driving circuit provided by the present application;

[0073] Fig.16 It is a schematic diagram of another driving circuit provided by the present application connected to a power tube;

[0074] Fig.17 is a schematic diagram of a low-side driver module of a driver circuit provided by the present application;

[0075] Fig.18 is a schematic diagram of a low-side voltage bias unit of a driving circuit provided by the present application;

[0076] Fig.19 is a schematic diagram of a low-side driving unit of a driving circuit provided by the present application;

[0077] Fig. 20 is a schematic diagram of a full-bridge drive circuit provided by the present application;

[0078] Fig.21 It is a schematic diagram of a wireless charging circuit provided by the present application. DETAILED DESCRIPTION

[0079] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should be the common meanings understood by those skilled in the art to which this application belongs.

[0080] At present, full-bridge drive circuits are generally divided into two types. One is the Powerstage chip integration solution, which integrates the driver chip and the power tube. This solution has a high degree of integration, but in order to minimize the on-resistance of the power tube, a larger power tube area is required, thereby increasing the area of ​​the chip. In addition, since the Powerstage solution integrates the power tube inside the chip, the heat dissipation performance is poor. The other is the SOC solution, which integrates the main control chip and the driver chip together, but places the power tube outside the chip to achieve better heat dissipation performance. However, in order to avoid the power tube from being turned on at the same time, the SOC solution will use a fixed dead time to avoid the upper and lower power tubes from being turned on at the same time. However, since the dead time is fixed, it cannot be dynamically adjusted according to the actual working conditions, which will cause the power tube in the SOC solution to have a large reverse conduction loss, affecting the power transmission efficiency.

[0081] In addition, in the SOC solution, since the power tube is external to the chip, a MOS tube with a larger gate-source withstand voltage can be used to minimize the on-resistance. However, when the bootstrap voltage exceeds 5V, the circuit inside the chip needs to be properly designed so that the gate-source voltage of the MOS tube in the circuit does not exceed 5V, thereby avoiding damage to the circuit.

[0082] To solve the above problems, the embodiments of the present application propose a drive circuit, a full-bridge drive circuit, a wireless charging circuit and a chip.

[0083] Embodiment 1

[0084] This embodiment provides a driving circuit such as Figure 1 As shown, it includes: a high-side voltage detection module 100, a low-side voltage detection module 200, a high-side driving module 300 and a low-side driving module 400;

[0085] The input end of the high-side voltage detection module is connected to the output end of the high-side driving module 300. The high-side voltage detection module samples the high-side driving voltage HS_GD (high-side power tube HM driving voltage) output by the high-side driving module 300, and outputs a high-side detection signal HS_GD_Z when the high-side driving voltage HS_GD drops to a first threshold voltage. The high-side detection signal HS_GD_Z triggers the low-side driving module 400 to turn on.

[0086] The input end of the low-side voltage detection module 200 is connected to the output end of the low-side driving module 400. The low-side voltage detection module 200 samples the low-side driving voltage LS_GD (low-side power tube LM driving voltage) output by the low-side driving module 400, and outputs a low-side detection signal LS_GD_Z when the low-side driving voltage LS_GD drops to a second threshold voltage. The low-side detection signal LS_GD_Z triggers the high-side driving module 300 to turn on.

[0087] Wherein, the high side detection signal HS_GD_Z and the low side detection signal LS_GD_Z both include a high potential signal and a low potential signal. By outputting different potential signals, the high side detection signal HS_GD_Z can trigger the conduction or disconnection of the low side driver module 400, and the low side detection signal LS_GD_Z can trigger the conduction and disconnection of the high side driver module 300. The output end of the high side driver module 300 is connected to the gate of a power MOS tube, and the output high side drive voltage HS_GD is used to drive the conduction or disconnection (disconnection) of the power MOS tube connected thereto; the output end of the low side driver module 400 is connected to the gate of another power MOS tube, and the output low side drive voltage LS_GD is used to drive the conduction or disconnection of the power MOS tube connected thereto. The first threshold voltage is the switch node voltage SW, or the same voltage as the switch node voltage SW, and the second threshold voltage is the ground terminal voltage GND, or the same voltage as the ground terminal voltage GND.

[0088] The high-side driving voltage HS_GD and the low-side driving voltage LS_GD are sampled respectively by the high-side voltage detection module 100 and the low-side voltage detection module 200. According to the sampling results, i.e., whether the high-side driving voltage HS_GD is reduced to the first threshold voltage, and whether the low-side driving voltage LS_GD is reduced to the second threshold voltage, a high-side detection signal HS_GD_Z or a low-side detection signal LS_GD_Z is outputted correspondingly to drive the low-side driving module 400 or the high-side driving module 300 to be turned on, so that the low-side driving module 400 and the high-side driving module 300 are respectively turned on or off according to the actual situation, so that the driving circuit can adaptively adjust the dead time.

[0089] In the present application embodiment, Figure 2 As shown, it also includes a high-side logic module 500 and a low-side logic module 600. The high-side logic module 500 is arranged between the high-side driver module 300 and the low-side voltage detection module 200; the high-side logic module 500 adjusts the driving signal input to the high-side driver module 300 according to the enable signal. The low-side logic module 600 is arranged between the low-side driver module 400 and the high-side voltage detection module 100; the low-side logic module 600 adjusts the driving signal input to the low-side driver module 400 according to the enable signal.

[0090] The high-side logic module 500 is used to invert the signal LS_GD_Z output by the low-side voltage detection module 200 and perform an AND operation on the high-side drive signal HS_DRIVER_IN to obtain the high-side drive signal H_DRIVER_IN after the logic operation, and output it to the high-side driver module 300. The low-side logic module 600 is used to invert the signal HS_GD_Z output by the high-side voltage detection module 100 and perform an AND operation on the low-side drive signal LS_DRIVER_IN to obtain the low-side drive signal L_DRIVER_IN after the logic operation, and output it to the low-side driver module 400.

[0091] The implementation method of this application is used for a full-bridge drive circuit. Since the left and right sides of the full-bridge drive circuit are complementary, the implementation method of the application only introduces the specific principles of the left half circuit applied in the full-bridge drive circuit. Figure 3 As shown, the adaptive dead time adjustment of the embodiment of the present application is realized by the high-side voltage detection module 100 and the low-side voltage detection module 200 respectively collecting the gate potential of the high-side power tube HM and the gate potential of the low-side power tube LM, and respectively feeding back the high-side detection signal HS_GD_Z and the low-side detection signal LS_GD_Z. Figure 3 As shown, when the output signal H_DRIVER_IN of the high-side logic module 500 is at a high potential and the output signal LS_DRIVER_IN of the low-side logic module 600 is at a low potential, the gate input voltage (high-side drive voltage) HS_GD of the high-side power tube HM is at a high potential, and the gate input voltage (low-side drive voltage) LS_GD of the low-side power tube LM is at a low potential, the high-side power tube HM is turned on, and the low-side power tube LM is turned off. When the high-side driving signal HS_DRIVER_IN input to the high-side logic module 500 jumps to a low potential, the low-side driving signal LS_DRIVER_IN input to the low-side logic module 600 jumps to a high potential, and the gate input voltage HS_GD of the high-side power tube HM jumps to a low potential. When the high-side voltage detection module 100 detects that the gate input voltage HS_GD of the high-side power tube HM jumps to a low potential, the high-side power tube HM is disconnected at this time, and the high-side voltage detection module 100 outputs a high-side detection signal HS_GD_Z. The low-side logic module 600 inverts the high-side detection signal HS_GD_Z output by the high-side voltage detection module 100 and performs an AND operation with the low-side driving signal LS_DRIVER_IN, and outputs a high potential. After the low-side driving module 400 increases the driving capability, the output end (the twenty-sixth PMOS tube MP26) of the low-side driving module 400 is turned on, the gate input voltage LS_GD of the low-side power tube LM becomes a high potential, and the low-side driving tube is turned on. In this way, the low-side power tube LM is turned on again after the high-side power tube HM is turned off.

[0092] like Figure 4As shown, the high-side voltage detection module 100 in the embodiment of the present application includes a level shift unit 101 and a first potential conversion unit 102. The input end of the level shift unit 101 is connected to the output end of the high-side driving module 300, and the output end is connected to the first potential conversion unit 102; the level shift unit 101 clamps the value of the high-side driving voltage HS_GD and shapes the waveform of the high-side driving voltage HS_GD. The output end of the first potential conversion unit 102 is connected to the high-side driving module 300; the first potential conversion unit 102 converts the shaped high-side driving voltage HS_GD from the high voltage domain to the low voltage domain, and generates a first detection voltage according to the high-side driving voltage HS_GD in the low voltage domain, and the first detection voltage is used as the high-side detection signal HS_GD_Z.

[0093] The level shift unit 101 can output a stable high-side drive voltage HS_GD to the first potential conversion unit 102 through clamping and rectification functions. Wherein, the high voltage domain includes a voltage range from the bootstrap voltage BST (BST voltage) to the switch node voltage SW (SW voltage), and the high-side drive voltage HS_GD and the low-side drive voltage LS_GD also belong to the high voltage domain. In the implementation method of the application itself, the bootstrap voltage BST and the switch node voltage of the high voltage domain are input to the high-side drive module 300 and the low-side drive module 400, wherein the potential difference between the bootstrap voltage BST and the switch node voltage SW is 10V, and the maximum can reach 20V, so that the power consumption of the driving power MOS tube can be reduced. However, this potential difference can damage many components in the high-drive circuit, so the high-side drive voltage HS_GD is converted from the high voltage domain to the low voltage domain by the first potential conversion unit 102, thereby realizing the protection of the components in the drive circuit and improving the safety of the drive circuit.

[0094] like Figure 5 As shown, in the embodiment of the present application, the level shift unit 101 includes a clamping subunit 111 and a first shifting subunit 112. The input end of the clamping subunit 111 is connected to the output end of the high-side driver module 300, and the output end is connected to the input end of the first shifting subunit 112; the output end of the first shifting subunit 112 is connected to the first potential conversion unit 102.

[0095] Among them, Figure 5As shown, the clamp subunit 111 includes: a third NMOS tube MN3 and a first Schmitt buffer (Schmitt Buffer) S1. The drain of the third NMOS tube MN3 is connected to the output end of the high-side driver module 300, and the high-side drive voltage HS_GD is input, the source is connected to the input end of the first Schmitt buffer S1, and the gate inputs the third high-side working voltage HVD1. The output end of the first Schmitt buffer S1 is connected to the first shift subunit 112, and the working voltage domain is HVD3 to the switch node voltage SW. The first Schmitt buffer S1 includes a Schmitt inverter (Schmitt trigger) and an inverter.

[0096] By shaping the input high-side driving voltage HS_GD through the first Schmitt buffer S1 , the stability and quality of the high-side driving voltage HS_GD output to the first shift subunit 112 can be improved.

[0097] like Figure 5 As shown, the first shift subunit 112 includes: a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a first PMOS transistor MP1, a second PMOS transistor MP2, a first resistor R1 and a second resistor R2. The gate of the fourth NMOS transistor MN4 is connected to the output end of the first Schmitt buffer S1, the source inputs the switch node voltage SW, and the drain is connected to the source of the fifth NMOS transistor MN5 and one end of the first resistor R1. The drain and gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 are all connected to the drain of the fifth NMOS transistor MN5. The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are both input with the bootstrap voltage BST. The gate of the fifth NMOS transistor MN5 inputs the third high-side working voltage HVD1. The drain of the second PMOS transistor MP2 is connected to the drain of the sixth NMOS transistor MN6. The source of the sixth NMOS transistor MN6 is connected to one end of the second resistor R2, and the gate inputs the HVD2 voltage. The other end of the second resistor R2 is connected to the ground end GND.

[0098] like Figure 5 As shown, the first shift subunit 112 also includes a third Zener transistor Z3 and a first capacitor C1. The cathode of the third Zener transistor Z3 is connected to the source of the fifth NMOS transistor MN5, the anode is connected to the source of the fourth NMOS transistor MN4, and the switch node voltage SW is input. One end of the first capacitor C1 inputs the bootstrap voltage BST, and the other end is connected to the gate of the first PMOS transistor MP1.

[0099] The first shift subunit is used for level shifting, and performs level shifting on the voltage output by the clamp subunit 111 to prevent the voltage from causing damage to the first potential conversion unit 102 .

[0100] like Figure 5 As shown, the first potential conversion unit 102 includes: a seventh NMOS tube MN7, a third PMOS tube MP3, a second Schmitt buffer S2 and a first inverter INV1. The gate of the seventh NMOS tube MN7 is connected to the source of the sixth NMOS tube MN6 of the first shift sub-unit 112, the source is connected to the ground terminal GND, and the drain is connected to the drain of the third PMOS tube MP3 and the input end of the second Schmitt buffer S2. The source of the third PMOS tube MP3 inputs the first power supply voltage VDDH, and the gate inputs the fourth high-side working voltage HVD4. The output end of the second Schmitt buffer S2 is connected to the input end of the first inverter INV1. The working voltage domains of the second Schmitt buffer S2 and the first inverter INV1 are both the first power supply voltage VDDH to the ground terminal GND voltage.

[0101] like Figure 5 As shown, in the embodiment of the present application, the high-side voltage detection module 100 further includes a voltage protection unit 103 , and the voltage protection unit 103 is disposed between the level shift unit 101 and the first potential conversion unit 102 .

[0102] The voltage protection unit 103 is used to protect the gate and source (gate-source) of the seventh NMOS transistor MN7 of the first potential conversion unit 102 to prevent it from being broken down.

[0103] like Figure 5 As shown, the voltage protection unit 103 includes: a fourth Zener tube Z4, a second capacitor C2, a first diode D1 and a second diode D2. The cathode of the fourth Zener tube Z4 is connected to the anode of the first diode D1, one end of the second capacitor C2 and the gate of the seventh NMOS tube MN7 of the first potential conversion unit 102; the cathode of the first diode D1 is connected to the anode of the second diode D2; the anode of the fourth Zener tube Z4, the cathode of the second diode D2 and the other end of the second capacitor C2 are all connected to the ground terminal GND.

[0104] When the high-side voltage detection module 100 detects that the potential of the high-side driving voltage HS_GD input to the gate of the high-side power tube HM (power MOS tube) drops to a low potential (first threshold voltage), the high-side power tube HM is turned off (disconnected) at this time, and the high-side voltage detection module 100 needs to output a high-side detection signal HS_GD_Z to trigger the low-side driving module 400 to turn on, so as to achieve the low-side power tube LM to be turned on when the gate potential of the high-side power tube HM drops to a low potential and is turned off (disconnected). In the high-side voltage detection module 100, the third NMOS tube MN3 is a high-voltage clamping tube, which plays an isolation role. The operating voltage domain of the high-side driving voltage HS_GD is a high voltage domain from the switch node voltage SW to the bootstrap voltage BST (SW-BST), and the operating voltage domain of the next-level Schmitt buffer (first Schmitt buffer S1) is SW-HVD3 (switch node voltage SW to the second high-side operating voltage HVD3). The fourth NMOS tube MN4, the fifth NMOS tube MN5, the sixth NMOS tube MN6, the seventh NMOS tube MN7, the first PMOS tube MP1, the second PMOS tube MP2, the first resistor R1 and the second resistor R2 constitute a level shift circuit. The third Zener tube Z3 is used to protect the drain-source voltage of the fourth NMOS tube MN4 from not exceeding the normal working voltage of the fourth NMOS tube MN4, thereby protecting the drain-source of the fourth NMOS tube MN4 from breakdown; the fourth Zener tube Z4, the first diode D1 and the second diode D2 are used to protect the gate-source voltage of the seventh NMOS tube MN7 from not exceeding the normal working voltage of the seventh NMOS tube MN7, thereby protecting the gate-source of the seventh NMOS tube MN7 from breakdown. The first capacitor C1 is used to couple the gate noise to the power supply, thereby stabilizing the gate-source voltage of the first PMOS tube MP1 and the second PMOS tube MP2; the second capacitor C2 is used to couple the gate noise to the ground, thereby maintaining the stability of the gate-source voltage of the seventh NMOS tube MN7. The low potential, the first threshold voltage and the second threshold voltage all include: 0 potential and / or the ground terminal potential GND (ground terminal voltage GND).

[0105] The working principle of the high-side voltage detection module 100 is that when the input high-side drive voltage HS_GD is a high potential, that is, the potential of the bootstrap voltage BST, the fourth NMOS tube MN4 is turned on, so that the source output of the sixth NMOS tube MN6 is a high potential, thereby turning on the seventh NMOS tube MN7. When the seventh NMOS tube MN7 is turned on, the potential of point F is a low potential, that is, the ground terminal potential GND. The low potential of point F is shaped by the second Schmidt buffer S2 and reversed by the first inverter INV1, and a high potential VDDH is output as the high-side detection signal HS_GD_Z. Among them, the first power supply voltage VDDH is a 5V power supply voltage, and the high potential VDDH indicates that its potential is equal to the first power supply voltage VDDH. Similarly, when the input high-side drive voltage HS_GD is at a low potential, that is, the switch node voltage SW, the fourth NMOS tube MN4 is disconnected, and the source of the sixth NMOS tube MN6 is pulled down to a low potential (ground terminal potential GND) by the second resistor R2. At this time, the seventh NMOS tube MN7 is disconnected, so that the potential of point F is pulled up to a high potential VDDH by the third PMOS tube MP3. After the high potential of point F is shaped by the second Schmidt buffer S2 and reversed by the first inverter INV1, a low potential GND is output as the high-side detection signal HS_GD_Z. The low potential GND indicates that its potential is equal to the potential of the ground terminal GND.

[0106] The high-side voltage detection module 100 can convert the high-side driving voltage HS_GD from the high voltage domain (SW-BST) to the low voltage domain (GND-VDDH), so that it can adaptively and quickly output the high-side detection signal HS_GD_Z to trigger the conduction or shutdown of the low-side driving module 400 while protecting the safety of the driving circuit.

[0107] like Figure 6 As shown, in the embodiment of the present application, the low-side voltage detection module 200 includes a switch unit 201 and a second potential conversion unit 202. The input end of the switch unit 201 is connected to the output end of the low-side driving module 400, and the output end is connected to the second potential conversion unit 202; the switch unit 201 is turned on or off (disconnected) according to the potential of the low-side driving voltage LS_GD in the high voltage domain, and generates a turn-on voltage or a turn-off voltage; the output end of the second potential conversion unit 202 is connected to the low-side driving module 400; the second potential conversion unit 202 generates a second detection voltage in the low voltage domain according to the turn-on voltage or the turn-off voltage, and the second detection voltage is used as the low-side detection signal LS_GD_Z.

[0108] The switch unit 201 outputs the corresponding on-voltage or off-voltage to the second potential conversion unit 202 according to the potential change of the low-side drive voltage LS_GD, and can output a stable voltage to the second potential conversion unit 202. The high voltage domain also includes a first voltage domain, that is, a voltage range from the ground terminal voltage GND to the first high voltage VDDR (GND-VDDR), and the low-side drive voltage LS_GD also belongs to the high voltage domain. Among them, the first high voltage VDDR includes an external input voltage or a voltage generated inside the chip, about 10V. In the implementation method of the application itself, the switch unit 201 can generate a turn-on voltage or a turn-off voltage of the low voltage domain according to the low-side drive voltage LS_GD of the high voltage domain. The second potential conversion unit 202 outputs a low-side detection signal LS_GD_Z of the low voltage domain according to the turn-on voltage or the turn-off voltage, thereby converting the low-side drive voltage LS_GD from the high voltage domain to the low voltage domain, realizing the protection of the components in the drive circuit and improving the safety of the drive circuit.

[0109] like Figure 7 As shown, the switch unit 201 includes: an eighth NMOS tube MN8, a ninth NMOS tube MN9, a fourth PMOS tube MP4, a third capacitor C3 and a third resistor R3. The drain of the eighth NMOS tube MN8 is connected to the output end of the low-side driving module 400, and the low-side driving voltage LS_GD is input, the gate is connected to one end of the third resistor R3 and one end of the third capacitor C3, and the source is connected to the gate of the ninth NMOS tube MN9. The drain of the ninth NMOS tube MN9 is connected to the drain of the fourth PMOS tube MP4 and the second potential conversion unit 202, and the source of the ninth NMOS tube MN9 and the other end of the third capacitor C3 are both connected to the ground terminal GND. The other end of the third resistor R3 and the source of the fourth PMOS tube MP4 are both input with the first power supply voltage VDDH. The gate of the fourth PMOS tube MP4 inputs the second low-side working voltage VD2.

[0110] When the low-side driving voltage LS_GD input by the eighth NMOS tube MN8 is at a low potential (reaching the second threshold voltage), that is, the ground terminal voltage GND, the ninth NMOS tube MN9 is turned off, and the drain voltage of the ninth NMOS tube MN9 is used as the turn-off voltage. When the low-side driving voltage LS_GD input by the eighth NMOS tube MN8 is at a high potential, that is, the first power supply voltage VDDH, the ninth NMOS tube MN9 is turned on, and the drain voltage of the ninth NMOS tube MN9 is used as the turn-on voltage.

[0111] like Figure 7As shown, the second potential conversion unit 202 includes: a first Schmitt trigger SMIT1, a second inverter INV2 and a third inverter INV3. The input end of the first Schmitt trigger SMIT1 is connected to the drain of the ninth NMOS tube MN9 of the switch unit 201, and the output end is connected to the input end of the second inverter INV2. The output end of the second inverter INV2 is connected to the input end of the third inverter INV3. The output end of the third inverter INV3 outputs a low-side detection signal LS_GD_Z. The operating voltage domains of the first Schmitt trigger SMIT1, the second inverter INV2 and the third inverter INV3 are all from the first power supply voltage VDDH to the ground terminal voltage GND.

[0112] The eighth NMOS transistor MN8 in the low-side voltage detection module 200 is a high-voltage clamping tube. When the low-side driving voltage LS_GD input to the eighth NMOS transistor MN8 is the first high voltage VDDR (high potential), the low-side power tube LM is turned on, and the low-side voltage detection module 200 needs to output the low-side detection signal LS_GD_Z to trigger the high-side driving module 300 to disconnect. When the low-side drive voltage LS_GD input to the eighth NMOS tube MN8 is the first high voltage VDDR (high potential), the source potential of the eighth NMOS tube MN8 is VVDDH-VGSN, wherein VVDDH is the voltage value of VDDH, and VGSN is the gate-source voltage of the eighth NMOS tube MN8. The eighth NMOS tube MN8 is turned on, so that the ninth NMOS tube MN9 is turned on, and the voltage at the input end of the first Schmitt trigger SMIT1 (at the drain of the ninth NMOS tube MN9) is pulled down to a low potential voltage close to the ground terminal voltage GND, so that the output low-side detection signal LS_GD_Z is a high potential (VDDH). When LS_GD drops to a low potential (ground terminal voltage GND), the low-side power tube LM is disconnected, the low-side drive voltage LS_GD input to the eighth NMOS tube MN8 is the ground terminal voltage GND (low potential), and the source of the eighth NMOS tube MN8 is a low potential (GND), so that the ninth NMOS tube MN9 is disconnected. The fourth PMOS transistor MP4 pulls up the voltage at the input end of the first Schmitt trigger SMIT1 to a high voltage approximately equal to VDDH-VDSMP4 (VDSMP4 is the drain-source voltage of the fourth PMOS transistor MP4), so that the low-side detection signal LS_GD_Z output by the low-side voltage detection module 200 is output as a low potential, triggering the high-side driving module 300 to turn on.

[0113] The low-side voltage detection module 200 can convert the input low-side drive voltage LS_GD from the high voltage domain (GND-VDDR) to the low voltage domain (GND-VDDH), so that it can adaptively and quickly output the low-side detection signal LS_GD_Z to trigger the conduction or disconnection of the high-side drive module 300 while protecting the safety of the drive circuit.

[0114] like Figure 8 As shown, in the embodiment of the present application, the high-side driver module 300 includes a high-side voltage bias unit 301 and a high-side driver unit 302. The high-side driver unit 302 generates a high-side driver voltage HS_GD according to a driving signal (H_DRIVER_IN) and a high-side potential; the output end of the high-side voltage bias unit 301 is connected to the high-side driver unit 302, and the high-side voltage bias unit 301 generates a high-side potential according to a bootstrap voltage BST and a switch node voltage SW, and the high-side potential is the operating voltage of the high-side driver unit 302.

[0115] Wherein, the driving signal is a PWM signal, including: a high-side driving signal HS_DRIVER_IN, a low-side driving signal LS_DRIVER_IN, a high-side driving signal H_DRIVER_IN after a logic operation, and a low-side driving signal L_DRIVER_IN after a logic operation, and the high-side potential includes the potential of the first high-side working voltage HVD2 and the potential of the second high-side working voltage HVD3. When the high-side logic module 500 receives the low-side detection signal LS_GD_Z, it will output the high-side driving signal H_DRIVER_IN after a logic operation, and the high-side driving unit 302 generates the low-side driving voltage HS_GD according to the driving signal H_DRIVER_IN and the high-side potential.

[0116] Although increasing the driving voltage of the gate of the power MOS tube can reduce power consumption, excessive driving voltage can also damage other components in the driving circuit, thereby reducing the safety and practicality of the circuit. The high-side driving module 300 of the embodiment of the present application can generate multiple high-side potentials according to the input bootstrap voltage BST and the switch node voltage SW, and the high-side potentials are multiple working voltages for the high-side driving unit 302 and the high-side voltage detection module 100, so that the embodiment of the present application is not only suitable for high-voltage and wide-range driving circuits, but also can reduce power consumption while enabling the driving circuit to obtain the voltage required for normal operation.

[0117] like Fig. 9As shown, in the embodiment of the present application, the high-side voltage bias unit 301 includes a first high-side potential subunit 311 and a second high-side potential subunit 312. The first high-side potential subunit 311 generates a first high-side operating voltage HVD2 according to the bootstrap voltage BST when it is turned on; the second high-side potential subunit 312 generates a second high-side operating voltage HVD3 according to the switch node voltage SW when it is turned on.

[0118] The first high-side potential subunit 311 and the second high-side potential subunit 312 can generate a first high-side operating voltage HVD2 and a second high-side operating voltage HVD3 according to the input bootstrap voltage BST and the switch node voltage SW, providing a stable and appropriate operating voltage for the high-side driving unit 302 and the high-side voltage detection module 100 .

[0119] like Fig. 9 As shown, the first high-side potential subunit 311 includes a first Zener transistor Z1, a first NMOS transistor MN1 and a first PMOS transistor MP1. The negative electrode of the first Zener transistor Z1 inputs the bootstrap voltage BST, and the positive electrode is respectively connected to the drain of the first NMOS transistor MN1 and the gate of the first PMOS transistor MP1; the source of the first NMOS transistor MN1 and the drain of the first PMOS transistor MP1 are both input with the switch node voltage SW; the source of the first PMOS transistor MP1 outputs the first high-side working voltage HVD2.

[0120] The first high-side potential subunit 311 also includes a fifth Zener tube Z5, a sixth Zener tube Z6, a seventh Zener tube Z7, a third capacitor C3 and a fourth resistor R4. The source of the first PMOS tube MP1 is also connected to one end of the fourth resistor R4 and the positive electrode of the fifth Zener tube Z5, and the substrate end is connected to the other end of the fourth resistor R4 and the positive electrode of the sixth Zener tube Z6; the negative electrode of the fifth Zener tube Z5 and the negative electrode of the sixth Zener tube Z6 are both input with the bootstrap voltage BST. The positive electrode of the seventh Zener tube Z7 is connected to the source of the first NMOS tube MN1, and the negative electrode is connected to the gate of the first NMOS tube MN1. One end of the third capacitor C3 is connected to the positive electrode of the first Zener tube Z1, and the other end is connected to the negative electrode of the first Zener tube Z1.

[0121] The source and substrate end of the first PMOS tube MP1 are connected respectively through two Zener tubes (fifth Zener tube Z5 and sixth Zener tube Z6), and a fourth resistor R4 is added between the fifth Zener tube Z5 and the sixth Zener tube Z6 for isolation, which mainly prevents a large current from flowing through the substrate end of the first PMOS tube MP1, causing the parasitic diode of the first PMOS tube MP1 to be turned on. The seventh Zener tube Z7 is used to keep the gate-source voltage of the first NMOS tube MN1 constant. The third capacitor C3 is used to keep the voltage across the first Zener tube Z1 stable.

[0122] like Fig. 9 As shown, the second high-side potential subunit 312 includes a second Zener transistor Z2 and a second NMOS transistor MN2. The positive electrode of the second Zener transistor Z2 inputs the switch node voltage SW, and the negative electrode is connected to the source of the second NMOS transistor MN2; the drain of the second NMOS transistor MN2 inputs the bootstrap voltage BST, and the source outputs the second high-side working voltage HVD3.

[0123] The second high-side potential subunit 312 further includes a fourth capacitor C4. One end of the fourth capacitor C4 is connected to the positive electrode of the second Zener diode Z2, and the other end is connected to the negative electrode of the second Zener diode Z2.

[0124] The fourth capacitor C4 is used to keep the voltage across the second Zener diode Z2 stable.

[0125] like Fig. 9 As shown, the high side voltage bias unit 301 further includes: a third high side potential subunit 313, a fourth high side potential subunit 314 and a current mirror unit 315. The current mirror unit is connected to the first high side potential subunit 311, the third high side potential subunit and the fourth high side potential subunit respectively.

[0126] The third high-side potential sub-unit is used to generate a third high-side operating voltage HVD3 according to the bootstrap voltage BST and the switch node voltage SW; the fourth high-side potential sub-unit is used to generate a fourth high-side operating voltage HVD4 according to the first power supply voltage VDDH and the ground terminal voltage GND; the current mirror unit is used to provide a suitable bias current to the first high-side potential sub-unit 311, the third high-side potential sub-unit and the fourth high-side potential sub-unit.

[0127] The first high-side operating voltage HVD2, the second high-side operating voltage HVD3, the third high-side operating voltage HVD1 and the fourth high-side operating voltage HVD4 are all voltages generated for driving the MOS transistors in the high-side voltage detection module 100, the low-side voltage detection module 200, the high-side driving module 300 and the low-side driving module 400. Fig. 9 As shown, the third high-side potential subunit 313 includes: a fifth PMOS tube MP5, a fifth capacitor C5, an eighth Zener tube Z8 and a ninth Zener tube Z9. The drain of the fifth PMOS tube MP5 is connected to the cathode of the eighth Zener tube Z8, one end of the fifth capacitor C5 and the gate of the second NMOS tube MN2 of the second high-side potential subunit 312, the gate is connected to the anode of the ninth Zener tube Z9 and the current mirror unit, and the source and the cathode of the ninth Zener tube Z9 are both input with the bootstrap voltage BST. The drain of the fifth PMOS tube MP5 outputs the third high-side working voltage HVD1. The anode of the ninth Zener tube Z9 also inputs the switch node voltage SW.

[0128] like Fig. 9As shown, the fourth high-side potential subunit 314 includes: a sixth capacitor C6 and a tenth NMOS transistor MN10. The drain and gate of the tenth NMOS transistor MN10 are both connected to one end of the sixth capacitor C6, and the source and the other end of the sixth capacitor C6 are both connected to the ground terminal GND. The drain of the tenth NMOS transistor MN10 outputs the fourth high-side operating voltage HVD4.

[0129] like Fig. 9 As shown, the current mirror unit 315 includes: a first current source I1, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a seventh capacitor C7, an eighth capacitor C8 and a tenth Zener transistor Z10. The input end of the first current source I1 is connected to the first power supply voltage VDDH, and the output end is connected to the drain and gate of the eleventh NMOS transistor MN11 and the gate of the twelfth NMOS transistor MN12. The source of the eleventh NMOS transistor MN11, the source of the twelfth NMOS transistor MN12, the source of the fifteenth NMOS transistor MN15 and the source of the seventeenth NMOS transistor MN17 are all connected to the ground terminal GND. The drain of the twelfth NMOS tube MN12 is connected to the source of the thirteenth NMOS tube MN13, and the gate is also connected to the gate of the fifteenth NMOS tube MN15 and the gate of the seventeenth NMOS tube MN17. The drain of the thirteenth NMOS tube MN13 is connected to the drain and gate of the tenth PMOS tube MP10, the gate of the seventh PMOS tube MP7, the positive electrode of the tenth Zener tube Z10 and one end of the seventh capacitor C7, and the gate inputs the first power supply voltage VDDH. The source of the tenth PMOS tube MP10, the other end of the seventh capacitor C7, the negative electrode of the tenth Zener tube Z10 and the source of the seventh PMOS tube MP7 are all input with the bootstrap voltage BST. The drain of the seventh PMOS tube MP7 is connected to the drain and gate of the fourteenth NMOS tube MN14. The drain of the seventh PMOS tube MP7 is also connected to the negative electrode of the seventh Zener tube Z7 of the first high-side potential sub-unit 311. The source of the fourteenth NMOS tube MN14 inputs the switch node voltage SW.

[0130] The drain of the fifteenth NMOS tube MN15 is connected to the source of the sixteenth NMOS tube MN16. The drain of the sixteenth NMOS tube MN16 is connected to the drain and gate of the sixth PMOS tube MP6, and the gate inputs the first power supply voltage VDDH. The source of the sixth PMOS tube MP6 inputs the bootstrap voltage BST, and the gate is also connected to the positive electrode of the ninth Zener tube Z9 of the third high-side potential sub-unit. The drain of the seventeenth NMOS tube MN17 is connected to the drain and gate of the eighth PMOS tube MP8, the gate of the ninth PMOS tube MP9, and one end of the eighth capacitor C8. The drain of the ninth PMOS tube MP9 is connected to the drain of the tenth NMOS tube MN10 of the fourth high-side potential sub-unit. The source of the eighth PMOS tube MP8, the source of the ninth PMOS tube MP9, and the other end of the eighth capacitor C8 are all input with the first power supply voltage VDDH.

[0131] like Fig. 9 As shown, the bootstrap voltage BST of the embodiment of the present application is usually 10V, and this bootstrap voltage BST can also exceed 10V, and can reach up to 20V, which is used to reduce the on-resistance of the power tube. When the bootstrap voltage BST is 10V, the potential difference between the bootstrap voltage BST and the switch node voltage SW is 10V. However, due to process reasons, the gate and source withstand voltage values ​​of the general MOS tube are generally 5V, so it is necessary to design a suitable high-side voltage bias unit 301 (bias circuit) to ensure that the high-side drive module 300 operates within the voltage domain range of 5V. In order to ensure that the gate-source voltage of the MOS tube does not exceed 5V, when the bootstrap voltage BST is used as the high potential of the inverter, VBST-5V is required to be the low potential of the inverter. When the switch node voltage SW is used as the low potential of the inverter, VSW+5V is required to be the high potential of the inverter. Among them, VBST is the voltage of the bootstrap voltage BST, and VSW is the voltage of the switch node voltage SW.

[0132] The thirteenth NMOS transistor MN13 in the high-side voltage bias unit 301 of the embodiment of the present application is a high-voltage clamping transistor, which is used to protect the twelfth NMOS transistor MN12. The eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the fourteenth NMOS transistor MN14, the first NMOS transistor MN1, the fifteenth NMOS transistor MN15, the seventeenth NMOS transistor MN17, the tenth NMOS transistor MN10, and the tenth PMOS transistor MP10, the seventh PMOS transistor MP7, the sixth PMOS transistor MP6, the fifth PMOS transistor MP5, the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are all current mirror transistors, which are used to provide a stable bias current to the high-side voltage bias unit 301. Among them, the twelfth NMOS transistor MN12 is used to provide a stable bias current to the branch where the twelfth NMOS transistor MN12 is located, and the branch where the twelfth NMOS transistor MN12 is located includes the tenth PMOS transistor MP10, the thirteenth NMOS transistor MN13 and the twelfth NMOS transistor MN12. The fourteenth NMOS transistor MN14 is used to provide a stable bias current to the branch where the fourteenth NMOS transistor MN14 is located. The branch where the fourteenth NMOS transistor MN14 is located includes the seventh PMOS transistor MP7 and the fourteenth NMOS transistor MN14.

[0133] The tenth Zener transistor Z10, the ninth Zener transistor Z9 and the seventh Zener transistor Z7 are used to protect the tenth PMOS transistor MP10, the seventh PMOS transistor MP7, the sixth PMOS transistor MP6, the fifth PMOS transistor MP5, the fourteenth NMOS transistor MN14 and the first NMOS transistor MN1 and other MOS transistors to prevent the gate-source voltage of the MOS transistors from breaking down. The seventh capacitor C7, the eighth capacitor C8 and the sixth capacitor C6 are used to keep the gate-source voltage of the MOS transistors such as the tenth PMOS transistor MP10, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9 and the tenth NMOS transistor MN10 constant, and at the same time couple the gate potential noise of these MOS transistors to the power supply and / or the ground terminal GND. The third capacitor C3, the fifth capacitor C5 and the fourth capacitor C4 are used to keep the voltage at both ends of the Zener transistors such as the first Zener transistor Z1, the eighth Zener transistor Z8 and the second Zener transistor Z2 stable.

[0134] In the embodiment of the present application, when working normally, the first NMOS tube MN1 is constantly turned on, and the potential difference between the switch node voltage SW and the bootstrap voltage BST is 10V, so the first Zener tube Z1 is reversely turned on, and the gate potential of the first PMOS tube MP1 is stabilized at VBST-Vzener, and the source voltage of the first PMOS tube MP1 is the first high-side operating voltage HVD2, which is equal to VBST-Vzener+VGSP. Similarly, because the fifth PMOS tube MP5 is constantly turned on, the eighth Zener tube Z8 is turned on, so that the gate potential HVD1 (the third high-side operating voltage HVD1) of the second NMOS tube MN2 is equal to VSW+Vzener, and the source voltage of the second NMOS tube MN2 is the second high-side operating voltage HVD3, which is equal to VSW+Vzener-VGSN. Since the Zener breakdown voltage of a general Zener tube is 5.7V and the gate-source voltage of a MOS tube is 0.7, the third high-side operating voltage HVD1 is VSW+5.7V, the HVD2 voltage is VBST-5V, and the HVD3 voltage is VSW+5V, thus realizing the voltage domain of BST dropping 5V and SW increasing 5V. Among them, VBST is the voltage of the bootstrap voltage BST, VSW is the voltage of the switch node voltage SW, VGSP is the gate-source voltage of the first PMOS tube MP1, and Vzener is the Zener breakdown voltage of the Zener tube.

[0135] like Fig.10 As shown, in the embodiment of the present application, the high-side driving unit 302 includes a low-to-high level shift subunit 321, a high-to-low level shift subunit 322 and a high-side output switch subunit 323. The output end of the low-to-high level shift subunit 321 is connected to the high-to-low level shift subunit 322, and the low-to-high level shift subunit 321 also inputs a driving signal H_DRIVER_IN and a bootstrap voltage BST; the low-to-high level shift subunit 321 converts the low voltage domain of the first power supply voltage VDDH to the ground terminal voltage GND into a high voltage domain output voltage of the bootstrap voltage BST to the first high-side working voltage HVD2 according to the driving signal H_DRIVER_IN and the bootstrap voltage BST, that is, converts the low voltage domain VDDH-GND into the high voltage domain BST- HVD2; the high-to-low level shift subunit 322 converts the input first high-side operating voltage HVD2 to the high voltage domain (HVD2-BST) of the bootstrap voltage BST into the switch node voltage SW to the low voltage domain (SW-HVD3) output voltage of the second high-side operating voltage HVD3; the high-side output switch subunit 323 is connected to both the output end of the low-to-high level shift subunit 321 and the output end of the high-to-low level shift subunit 322; the high-side output switch subunit 323 outputs the high-side drive voltage HS_GD according to the high voltage domain output voltage and the low voltage domain output voltage.

[0136] Since the voltage domain of the driving signal H_DRIVER_IN input to the high-side driving unit 302 is 0-5V, and the driving voltage of the high-side power tube HM needs to be in the voltage domain HVD2-BST and / or the voltage domain SW-HVD3, a low-to-high level shift subunit 321 is required to perform low-voltage to high-voltage level shift. Since the bootstrap voltage BST of the external high-side power tube HM is 10V, the SW-BST voltage domain needs to be divided into two voltage domains: the HVD2-BST voltage domain and the SW-HVD3 voltage domain. The voltage domain can be converted from the GND-VDDH voltage domain to the HVD2-BST voltage domain through the low-to-high level shift subunit 321, and then the HVD2-BST voltage domain is converted to the SW-HVD3 voltage domain through the high-to-low level shift subunit 322.

[0137] The low-to-high level shift subunit 321 is used for level shifting from low voltage to high voltage, and can generate a corresponding high voltage domain output voltage according to the input low voltage domain drive signal. The low-to-high level shift subunit 321 is used for level shifting from high voltage to low voltage, and can generate a corresponding low voltage domain output voltage according to the high voltage domain drive signal, thereby preventing circuit damage. The high-side output switch subunit 323 can generate a suitable high-side drive voltage HS_GD according to the high voltage domain output voltage and the low voltage domain output voltage, and accurately drive the high-side power tube HM to be turned on or off.

[0138] like Fig.11 As shown, in the embodiment of the present application, the high-side driving unit 302 further includes a first delay matching subunit 324, a second delay matching subunit 325, a first driving buffer subunit 326 and a second driving buffer subunit 327. The first delay matching subunit 324 is arranged between the low-to-high level shifting subunit 321 and the high-side output switch subunit 323; the first delay matching subunit 324 delays the output voltage of the high voltage domain; the first driving buffer subunit 326 is arranged between the first delay matching subunit 324 and the high-side output switch subunit 323; the second delay matching subunit 325 is respectively connected to the high-to-low level shifting subunit 322 and the second driving buffer subunit 327; the second driving buffer subunit 327 is also connected to the high-side output switch subunit 323; the second delay matching subunit 325 delays the output voltage of the low voltage domain.

[0139] The first delay matching subunit 324 and the second delay matching subunit 325 are used to delay the high voltage domain output voltage and the low voltage domain output voltage, so that the high side output switch subunit 323 can accurately turn on or off, so that the high side output switch subunit 323 can accurately drive the high side power tube HM to turn on or off. The first drive buffer subunit 326 and the second drive buffer subunit 327 are used to increase the driving force so that the high side power tube HM can be turned on as soon as possible.

[0140] like Fig.11 As shown, in the embodiment of the present application, the high-side driving unit 302 also includes a thirteenth capacitor C13, a sixth resistor R6, a third Schmitt buffer S3, a fourth inverter INV4 and a fifth inverter INV5. One end of the sixth resistor R6 is connected to the output end of the low-to-high level shift subunit 321, and the other end is connected to one end of the thirteenth capacitor C13 and the input end of the third Schmitt buffer S3. The other end of the thirteenth capacitor C13 inputs the bootstrap voltage BST. The output end of the third Schmitt buffer S3 is connected to the input end of the fifth inverter INV5 and the input end of the first delay matching subunit 324. The output end of the fifth inverter INV5 is connected to the input end of the low-to-high level shift subunit 321. The input end of the fourth inverter INV4 is connected to the output end of the first delay matching subunit 324, and the output end is connected to the input end of the first drive buffer subunit 326. The operating voltage range of the fourth inverter INV4 is from the bootstrap voltage BST to the first high-side operating voltage HVD2.

[0141] like Fig.12 As shown, the low-to-high level shift subunit 321 includes: a third AND gate AND3, a twenty-third NMOS tube MN23, a twenty-fourth NMOS tube MN24, a twenty-fifth NMOS tube MN25, a seventh resistor R7, a fourteenth Zener tube Z14 and a sixth inverter INV6. The output end of the third AND gate AND3 is connected to the gate of the twenty-third NMOS tube MN23, one input end is connected to the output end of the high-side logic module 500, and the other input end inputs the enable signal EN. The source of the twenty-third NMOS tube MN23 is connected to the ground terminal GND, and the drain is connected to the source of the twenty-fourth NMOS tube MN24. The gate of the twenty-fourth NMOS tube MN24 inputs the fourth high-side working voltage HVD4, and the drain is connected to the source of the twenty-fifth NMOS tube MN25. The gate of the twenty-fifth NMOS tube MN25 inputs the first power supply voltage VDDH, and the drain is connected to one end of the seventh resistor R7, the positive electrode of the fourteenth Zener tube Z14 and the input end of the sixth inverter INV6. The output end of the sixth inverter INV6 is connected to one end of the sixth resistor R6. The other end of the seventh resistor R7 and the cathode of the fourteenth Zener transistor Z14 are both input with the bootstrap voltage BST.

[0142] The low-to-high level shift subunit 321 is used for level shifting from low voltage to high voltage. When the output signal H_DRIVER_IN at the output end of the high-side logic module 500 is at a low potential, it is input to the low-to-high level shift subunit 321, so that the twenty-third NMOS tube MN23 is disconnected, so that the drain of the twenty-fifth NMOS tube MN25 is pulled up to a high potential (bootstrap voltage BST) by the seventh resistor R7. When the output signal H_DRIVER_IN at the output end of the high-side logic module 500 is at a high potential, it turns on the twenty-third NMOS tube MN23, and at this time, the fourteenth Zener tube Z14 is turned on, so that the drain voltage of the twenty-fifth NMOS tube MN25 is stabilized at VBST-VZENER, and finally outputted through the sixth inverter INV6, realizing the conversion of the low voltage domain GND-VDDH to the high voltage domain HVD2-BST voltage domain. The twenty-fifth NMOS tube MN25 is a high-voltage clamping tube, which is used to protect the drain-source voltage of the twenty-third NMOS tube MN23 and the twenty-fourth NMOS tube MN24MN24 from exceeding the normal working voltage. VBST is the bootstrap voltage BST, and VZENER is the Zener breakdown voltage of the Zener tube.

[0143] like Fig.13As shown, the high-to-low level shift subunit 322 includes: a fourteenth PMOS tube MP14, a fifteenth PMOS tube MP15, a twenty-sixth NMOS tube MN26, a twenty-seventh NMOS tube MN27, a twenty-eighth NMOS tube MN28, a twenty-ninth NMOS tube MN29, a seventh inverter INV7, and an eighth inverter INV8. The input end of the seventh inverter INV7 is connected to the output end of the fifth inverter INV5 and the gate of the fifteenth PMOS tube MP15, and the output end is connected to the gate of the fourteenth PMOS tube MP14. The source of the fourteenth PMOS tube MP14 and the source of the fifteenth PMOS tube MP15 are both input with the HVD3 voltage. The drain of the fourteenth PMOS tube MP14 is connected to the drain of the twenty-sixth NMOS tube MN26. The drain of the fifteenth PMOS tube MP15 is connected to the drain of the twenty-seventh NMOS tube MN27. The gate of the twenty-sixth NMOS tube MN26 is connected to the gate of the twenty-seventh NMOS tube MN27, and the third high-side working voltage HVD1 is input, and the source is connected to the drain of the twenty-eighth NMOS tube MN28 and the gate of the twenty-ninth NMOS tube MN29. The source of the twenty-seventh NMOS tube MN27 is connected to the gate of the twenty-eighth NMOS tube MN28, the drain of the twenty-ninth NMOS tube MN29 and the input end of the eighth inverter INV8. The source of the twenty-eighth NMOS tube MN28 and the source of the twenty-ninth NMOS tube MN29 are both input with the switch node voltage SW. The output end of the eighth inverter INV8 is connected to the second delay matching subunit 325. The working voltage domain of the seventh inverter INV7 is HVD3 to the switch node voltage SW, and the working voltage domain of the eighth inverter INV8 is HVD3 to the switch node voltage SW.

[0144] The high-to-low level shift subunit 322 is used for level shifting from high voltage to low voltage, and converts the input voltage domain from the high voltage domain of HVD2-BST to the low voltage domain of SW-HVD3 for output. When the input terminal C of the high-to-low level shift subunit 322 is at a high potential (bootstrap voltage BST), the fourteenth PMOS tube MP14 is turned on, and the drain potential of the twenty-eighth NMOS tube MN28 is pulled up, so that the twenty-ninth NMOS tube MN29 is turned on, and the drain of the twenty-ninth NMOS tube MN29 outputs a low potential, which is reversely outputted through the eighth inverter INV8, so that the potential of point D is a high potential (the second high-side working voltage HVD3); when point C is at a low potential (the first high-side working voltage HVD2), the fifteenth PMOS tube MP15 is turned on, so that the drain of the twenty-ninth NMOS tube MN29 outputs a high potential, and after being reversely outputted through the eighth inverter INV8, the potential of point D is a low potential (the switch node voltage SW). The twenty-sixth NMOS tube MN26 and the twenty-seventh NMOS tube MN27 are high-voltage clamping tubes for protecting the twenty-eighth NMOS tube MN28 and the twenty-ninth NMOS tube MN29 from breakdown.

[0145] like Fig.14As shown, the first delay matching subunit 324 includes: a sixteenth PMOS tube MP16, a seventeenth PMOS tube MP17, a thirtieth NMOS tube MN30, a thirty-first NMOS tube MN31, an eighth resistor R8, a ninth resistor R9, a fourteenth capacitor C14, a fifteenth capacitor C15, a first buffer BU1 and a first AND gate AND1. The gate of the sixteenth PMOS tube MP16, the gate of the thirtieth NMOS tube MN30 and an input end of the first AND gate AND1 are all connected to the output end of the third Schmidt buffer S3. The drain of the sixteenth PMOS tube MP16 is connected to one end of the eighth resistor R8, one end of the fourteenth capacitor C14 and the input end of the first buffer BU1. The other end of the eighth resistor R8 is connected to the drain of the thirtieth NMOS tube MN30. The gate of the seventeenth PMOS tube MP17 is connected to the gate of the thirty-first NMOS tube MN31 and the output end of the first buffer BU1. The drain of the seventeenth PMOS tube MP17 is connected to one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the drain of the thirty-first NMOS tube MN31, one end of the fifteenth capacitor C15 and the other input end of the first AND gate AND1. The source of the thirtieth NMOS tube MN30, the other end of the fourteenth capacitor C14, the source of the thirty-first NMOS tube MN31 and the other end of the fifteenth capacitor C15 are all input with the first high-side operating voltage HVD2. The output end of the first AND gate AND1 is connected to the input end of the fourth inverter INV4. The sources of the sixteenth PMOS tube MP16 and the seventeenth PMOS tube MP17 are all input with the bootstrap voltage BST. The operating voltage domain of the first AND gate AND1 is from the bootstrap voltage BST to the first high-side operating voltage HVD2. Among them, the first buffer BU1 includes two inverters connected in series.

[0146] The sixteenth PMOS transistor MP16, the thirtieth NMOS transistor MN30, the eighth resistor R8 and the fourteenth capacitor C14 in the first delay matching subunit 324 form a falling edge delay circuit, and the seventeenth PMOS transistor MP17, the thirty-first NMOS transistor MN31, the ninth resistor R9 and the fifteenth capacitor C15 form a rising edge delay circuit. The falling edge delay circuit, the rising edge delay circuit and the first AND gate AND1 form a point A rising edge delay circuit, so that the first delay matching subunit 324 can achieve the rising edge delay of the point A signal.

[0147] like Fig.15 As shown, the second delay matching subunit 325 includes: an eighteenth PMOS tube MP18, a nineteenth PMOS tube MP19, a thirty-second NMOS tube MN32, a thirty-third NMOS tube MN33, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth capacitor C16, a seventeenth capacitor C17, a second buffer BU2 and a second AND gate AND2.

[0148] The gate of the eighteenth PMOS tube MP18, the gate of the thirty-second NMOS tube MN32, and one input end of the second AND gate AND2 are all connected to the output end of the eighth inverter INV8 of the high-to-low level shift sub-unit 322. The drain of the eighteenth PMOS tube MP18 is connected to one end of the fourteenth resistor R14, one end of the sixteenth capacitor C16, and the input end of the second buffer BU2. The other end of the fourteenth resistor R14 is connected to the drain of the thirty-second NMOS tube MN32. The gate of the nineteenth PMOS tube MP19 is connected to the gate of the thirty-third NMOS tube MN33 and the output end of the second buffer BU2. The drain of the nineteenth PMOS tube MP19 is connected to one end of the fifteenth resistor R15. The other end of the fifteenth resistor R15 is connected to the drain of the thirty-third NMOS tube MN33, one end of the seventeenth capacitor C17, and the other input end of the second AND gate AND2. The source of the thirty-second NMOS transistor MN32, the other end of the sixteenth capacitor C16, the source of the thirty-third NMOS transistor MN33, and the other end of the seventeenth capacitor C17 are all input with the switch node voltage SW. The output end of the second AND gate AND2 is connected to the input end of the second driving buffer subunit 327. The sources of the eighteenth PMOS transistor MP18 and the nineteenth PMOS transistor MP19 are all input with the second high-side operating voltage HVD3. The operating voltage domain of the second AND gate AND2 is from the second high-side operating voltage HVD3 to the switch node voltage SW. Among them, the second buffer BU2 includes two inverters connected in series.

[0149] The eighteenth PMOS transistor MP18, the thirty-second NMOS transistor MN32, the fourteenth resistor R14 and the sixteenth capacitor C16 of the second delay matching subunit 325 form a falling edge delay circuit, and the nineteenth PMOS transistor MP19, the thirty-third NMOS transistor MN33, the fifteenth resistor R15 and the seventeenth capacitor C17 form a rising edge delay circuit. The falling edge delay circuit, the rising edge delay circuit and the second AND gate AND2 form a D point rising edge delay circuit, so that the second delay matching subunit 325 can achieve the rising edge delay of the D point signal.

[0150] The first drive buffer subunit 326 and the second drive buffer subunit 327 both include an existing drive buffer circuit, such as a drive buffer circuit composed of inverters with gradually increasing width-to-length ratios connected in series. The input end of the first drive buffer subunit 326 is connected to the output end of the fourth inverter INV4, and the output end is connected to an input end of the low-side output switch subunit. The first drive buffer subunit 326 outputs the H_Z0 signal to the first drive buffer subunit 326. The input end of the second drive buffer subunit 327 is connected to the output end of the second AND gate AND2 of the second delay matching subunit 325, and the output end is connected to another input end of the low-side output switch subunit. The second drive buffer subunit 327 outputs the H_Z1 signal to the first drive buffer subunit 326.

[0151] like Fig.16 As shown, the high-side output switch subunit 323 includes a twenty-fifth PMOS tube MP25 and a forty-first NMOS tube MN41. The gate of the twenty-fifth PMOS tube MP25 is connected to the output end of the first drive buffer subunit 326, and the drain is connected to the drain of the forty-first NMOS tube MN41, the gate of the high-side power tube HM, and the drain of the third NMOS tube MN3 of the high-side voltage detection module 100. The source of the twenty-fifth PMOS tube MP25 is connected to the first high-bit voltage VDDR through the fifth diode D5. The source of the twenty-fifth PMOS tube MP25 is also connected to one end of the twentieth capacitor. The gate of the forty-first NMOS tube MN41 is connected to the output end of the second drive buffer subunit 327, and the source is connected to the other end of the twentieth capacitor and the source of the high-side power tube HM.

[0152] like Fig.11 and Fig.16As shown, the source input voltage VIN of the high-side power tube HM, the first delay matching subunit 324 and the second delay matching subunit 325 jointly prevent the 25th PMOS tube MP25 and the 41st NMOS tube MN41 of the last stage inverter of the high-side output switch subunit 323 from being turned on at the same time. When the output signal H_DRIVER_IN of the output end of the high-side logic module 500 is at a high potential, the potential of point A of the high-side drive unit 302 is at a high potential. At this time, the output signal H_Z0 of the first drive buffer subunit 326 and the output signal H_Z1 of the second drive buffer subunit 327 are both at a low potential. At this time, the 25th PMOS tube MP25 of the last stage inverter of the high-side output switch subunit 323 (full-bridge drive high side) is turned on, and the high-side drive voltage HS_GD output is at a high potential. When the output signal H_DRIVER_IN of the output terminal of the high-side logic module 500 is converted from a high potential to a low potential, the potential of the point A of the high-side driving unit 302 is converted from a high potential to a low potential, and the point D is converted from a low potential to a high potential. Therefore, at this time, only the rising edge delay circuit corresponding to the point D and the second delay matching subunit 325 work, and at this time, the output signal H_Z0 of the first driving buffer subunit 326 can quickly become a high potential, so that the last stage inverter 25 PMOS tube MP25 of the high-side output switch subunit 323 (full-bridge drive high side) is disconnected, and the output signal H_Z1 of the second driving buffer subunit 327 becomes a high potential again, so that the last stage inverter 41 NMOS tube MN41 of the high-side output switch subunit 323 (full-bridge drive high side) is turned on, so that the high-side driving voltage HS_GD is output as a low potential. In this way, it is possible to avoid the upper and lower MOS tubes of the last stage inverter of the high-side output switch subunit 323 of the high-side driving module 300 being turned on at the same time. This enables precise control of the on and off of the high-side power tube HM.

[0153] like Fig.17 As shown, in the embodiment of the present application, the low-side driving module 400 includes: a low-side voltage bias unit 401 and a low-side driving unit 402. The low-side driving unit 402 generates a low-side driving voltage LS_GD according to the driving signal and the low-side potential; the output end of the low-side voltage bias unit 401 is connected to the low-side driving unit 402, and the low-side voltage bias unit 401 generates a low-side potential according to the first voltage domain. Wherein, the first voltage domain is a high potential VDDR to a ground terminal GND potential, and the voltage difference between the high potential VDDR and the ground terminal GND is 10V. The high potential VDDR indicates that its potential is equal to the potential of the first high voltage VDDR.

[0154] When receiving the high-side detection signal HS_GD_Z, the low-side logic module 600 outputs a low-side driving signal L_DRIVER_IN after logic operation, and the low-side driving unit 402 generates a low-side driving voltage LS_GD according to the driving signal L_DRIVER_IN and the low-side potential.

[0155] The low-side driver module 400 can generate a plurality of low-side potentials according to the input first voltage domain, thereby realizing dividing the input first voltage domain into a plurality of low-side potentials. The low-side potentials include a plurality of operating voltages for the low-side driver unit 402 and the low-side voltage detection module 200. Thus, the driver circuit can obtain the voltage required for normal operation while reducing power consumption.

[0156] like Fig.18 As shown, the low-side voltage bias unit 401 includes a first low-side potential subunit 411 and a second low-side potential subunit 412. The first low-side potential subunit 411 generates a first low-side operating voltage VD1 according to a first voltage domain when it is turned on. The second low-side potential subunit 412 generates a second low-side operating voltage VD2 according to a low voltage domain from a high potential VDDH to a low potential GND when it is turned on.

[0157] The first low-side operating voltage VD1 and the second low-side operating voltage VD2 are both voltages generated for driving MOS transistors in the high-side voltage detection module 100 , the low-side voltage detection module 200 , the high-side driving module 300 and the low-side driving module 400 .

[0158] The first low-side potential subunit 411 and the second low-side potential subunit 412 can generate a first low-side potential and a second low-side potential according to the input first voltage domain and low voltage domain, and provide a stable and appropriate operating voltage for the low-side driving module 400 and the low-side voltage detection module 200.

[0159] like Fig.18 As shown, the first low-side potential subunit 411 includes: an eleventh Zener tube Z11, a twelfth Zener tube Z12, a thirteenth Zener tube Z13, a fifth resistor R5, a ninth capacitor C9 and an eleventh PMOS tube MP11. The cathode of the eleventh Zener tube Z11, the cathode of the twelfth Zener tube Z12, the cathode of the thirteenth Zener tube Z13 and one end of the ninth capacitor C9 are all input with the first high voltage VDDR. The anode of the eleventh Zener tube Z11 is connected to the other end of the ninth capacitor C9 and the gate of the eleventh PMOS tube MP11. The source of the eleventh PMOS tube MP11 is connected to the positive electrode of the twelfth Zener tube Z12 and one end of the fifth resistor R5, the substrate end is connected to the positive electrode of the thirteenth Zener tube Z13 and the other end of the fifth resistor R5, and the drain is connected to the ground end GND. The source of the eleventh PMOS tube MP11 outputs the first low-side working voltage VD1.

[0160] The first low-side potential subunit 411 also includes: a twentieth NMOS transistor MN20, a twenty-first NMOS transistor MN21, a twenty-second NMOS transistor MN22, a twelfth capacitor C12, and a second current source I2. The input end of the second current source I2 is connected to the first power supply voltage VDDH, and the output end is connected to the drain of the twentieth NMOS transistor MN20. The source of the twentieth NMOS transistor MN20, one end of the twelfth capacitor C12, and the source of the twenty-first NMOS transistor MN21 are all connected to the ground terminal GND. The gate of the twentieth NMOS transistor MN20 is connected to the gate of the twenty-first NMOS transistor MN21 and the other end of the twelfth capacitor C12. The gate of the twenty-first NMOS transistor MN21 is also connected to the second low-side potential subunit 412, and the drain is connected to the source of the twenty-second NMOS transistor MN22. The drain of the twenty-second NMOS transistor MN22 is connected to the gate of the eleventh PMOS transistor MP11, and the gate inputs the first power supply voltage VDDH.

[0161] like Fig.18 As shown, the second low-side potential subunit 412 includes: a tenth capacitor C10, an eleventh capacitor C11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, an eighteenth NMOS transistor MN18 and a nineteenth NMOS transistor MN19. The source of the twelfth PMOS transistor MP12, one end of the eleventh capacitor C11 and the source of the thirteenth PMOS transistor MP13 are all input with the first power supply voltage VDDH. The gate of the twelfth PMOS transistor MP12 is connected to the gate of the thirteenth PMOS transistor MP13 and the other end of the eleventh capacitor C11. The drain of the twelfth PMOS transistor MP12 is connected to the drain of the nineteenth NMOS transistor MN19. The drain of the thirteenth PMOS transistor MP13 is connected to one end of the tenth capacitor C10, the drain and the gate of the eighteenth NMOS transistor MN18. The source of the eighteenth NMOS transistor MN18, the other end of the tenth capacitor C10 and the source of the nineteenth NMOS transistor MN19 are all connected to the ground terminal GND. The gate of the nineteenth NMOS transistor MN19 is connected to the gate of the twenty-first NMOS transistor MN21 of the first low-side potential sub-unit 411 .

[0162] like Fig.18As shown, the twenty-second NMOS tube MN22 is a high-voltage clamping tube, which is used to protect the drain-source voltage of the twenty-first NMOS tube MN21 from breakdown. The twelfth capacitor C12 is used to keep the gate-source voltage of the twenty-first NMOS tube MN21 constant, and the ninth capacitor C9 is used to keep the gate-source voltage of the eleventh PMOS tube MP11 constant. When the driving circuit of the embodiment of the present application works normally, the twenty-first NMOS tube MN21 and the twenty-second NMOS tube MN22 are always kept in the on (open) state, and the voltage difference between the first high voltage VDDR and the ground terminal GND is 10V. Therefore, the eleventh Zener tube Z11 is broken down, the gate voltage of the eleventh PMOS tube MP11 is VVDDR-VZENER, and the source voltage of the eleventh PMOS tube MP11, that is, the first low-side operating voltage VD1 is VVDDR-VZENER+VGSP, where VGSP is the gate-source voltage of the eleventh PMOS tube MP11. Since the breakdown voltage of the Zener tube is generally 5.7V and the gate-source voltage of the MOS tube is 0.7V, the source voltage of the eleventh PMOS tube MP11, that is, the first low-side operating voltage VD1 can be approximately considered to be VVDDR-5V. The source of the eleventh PMOS tube MP11 is connected to the positive electrode of the twelfth Zener tube Z12, and the substrate end is connected to the positive electrode of the thirteenth Zener tube Z13. At the same time, a fifth resistor R5 is added between the positive electrode of the twelfth Zener tube Z12 and the positive electrode of the thirteenth Zener tube Z13 for isolation. The main function of the eleventh Zener tube Z11, the twelfth Zener tube Z12 and the fifth resistor R5 is to prevent a large current from flowing through the substrate end of the eleventh PMOS tube MP11, causing the parasitic diode of the eleventh PMOS tube MP11 to be turned on. The nineteenth NMOS tube MN19, the eighteenth NMOS tube MN18, the twelfth PMOS tube MP12 and the thirteenth PMOS tube MP13 are mainly used for current mirror bias and provide a bias voltage VD2 (the second low-side operating voltage VD2); the eleventh capacitor C11 and the tenth capacitor C10 are mainly used to ensure the stability of the gate-source voltage of the current mirror tubes twelfth PMOS tube MP12, thirteenth PMOS tube MP13 and eighteenth NMOS tube MN18 and to couple the gate noise to the power supply or the ground terminal GND.

[0163] like Fig.16As shown, in the embodiment of the present application, the low-side drive unit 402 includes: a second shift subunit 421, a third delay matching subunit 422 and a low-side output switch subunit 423. The second shift subunit 421 and the third delay matching subunit 422 are both connected to the low-side output switch subunit 423; the second shift subunit 421 and the third delay matching subunit 422 are both input with a drive signal. The second shift subunit 421 converts the drive signal of the low voltage domain into the first high voltage VDDR or the first low-side operating voltage VD1 in the first voltage domain of the high voltage domain according to the low-side potential. The third delay matching subunit 422 delays the output of the drive signal. The low-side output switch subunit 423 outputs the low-side drive voltage LS_GD according to the voltage of the first high voltage or the low-side potential and the delayed output drive signal.

[0164] The second shift subunit 421 converts the low voltage drive signal into the first high voltage VDDR in the high voltage domain, which is used to drive the low-side power tube LM, thereby reducing power consumption. The third delay matching subunit 422 is used to delay the output of the drive signal so that the low-side output switch subunit 423 is accurately turned on or off, so that the low-side output switch subunit 423 can accurately drive the low-side power tube LM to be turned on or off.

[0165] like Fig.19 As shown, in the embodiment of the present application, the low-side drive unit 402 further includes: a third drive buffer subunit 424 and a fourth drive buffer subunit 425. The third drive buffer subunit 424 is arranged between the second shift subunit and the low-side output switch subunit 423. The input end of the third drive buffer subunit 424 is connected to the output end of the second shift subunit, and the output end is connected to an input end of the low-side output switch subunit 423. The fourth drive buffer subunit 425 is arranged between the third delay matching subunit 422 and the low-side output switch subunit 423. The input end of the fourth drive buffer subunit 425 is connected to the output end of the third delay matching subunit 422, and the output end is connected to another input end of the low-side output switch subunit 423.

[0166] The third driving buffer subunit 424 and the fourth driving buffer subunit 425 are used to increase the driving force so that the low-side power tube LM can be turned on as quickly as possible.

[0167] like Fig.19As shown, the second shift subunit 421 includes: a fourth AND gate AND4, a thirty-fourth NMOS tube MN34, a thirty-fifth NMOS tube MN35, a thirty-sixth NMOS tube MN36, a twentieth PMOS tube MP20, a tenth resistor R10, an eleventh resistor R11, a third diode D3 and a fourth diode D4. The output end of the fourth AND gate AND4 is connected to the gate of the thirty-fourth NMOS tube MN34, one input end is connected to the output end of the low-side logic module 600, and the other input end inputs the enable signal EN. The source of the thirty-fourth NMOS tube MN34 is connected to the ground terminal GND, and the drain is connected to the source of the thirty-fifth NMOS tube MN35. The drain of the thirty-fifth NMOS tube MN35 is connected to the source of the thirty-sixth NMOS tube MN36, and the gate inputs the second low-side working voltage VD2. The drain of the thirty-sixth NMOS tube MN36 is connected to one end of the tenth resistor R10, the gate of the twentieth PMOS tube MP20 and the cathode of the fourth diode D4, and the gate inputs the first power supply voltage VDDH. The other end of the tenth resistor R10, the anode of the third diode D3 and the source of the twentieth PMOS tube MP20 are all input with the first high voltage VDDR. The cathode of the third diode D3 is connected with the anode of the fourth diode D4. The drain of the twentieth PMOS tube MP20 is connected to one end of the eleventh resistor R11 and the third delay matching subunit 422. The other end of the eleventh resistor R11 is input with the first low-side working voltage VD1.

[0168] like Fig.19As shown, the third delay matching subunit 422 includes: a ninth inverter INV9, a second AND gate AND2, a twenty-second PMOS tube MP22, a twenty-third PMOS tube MP23, a thirty-eighth NMOS tube MN38, a thirty-ninth NMOS tube MN39, a twelfth resistor R12, a thirteenth resistor R13, an eighteenth capacitor C18, a nineteenth capacitor C19 and a third buffer BU3. The input end of the ninth inverter INV9 is connected to the gate of the thirty-fourth NMOS tube MN34 of the second shift subunit 421, and the output end is connected to the gate of the twenty-second PMOS tube MP22, the gate of the thirty-eighth NMOS tube MN38 and an input end of the second AND gate AND2. The source of the twenty-second PMOS tube MP22 inputs the first power supply voltage VDDH, and the drain is connected to one end of the twelfth resistor R12, one end of the eighteenth capacitor C18 and the input end of the third buffer BU3. The drain of the thirty-eighth NMOS tube MN38 is connected to the other end of the twelfth resistor R12. The source of the thirty-eighth NMOS transistor MN38, the other end of the eighteenth capacitor C18, the source of the thirty-ninth NMOS transistor MN39, and one end of the nineteenth capacitor C19 are all connected to the ground terminal GND. The source of the twenty-third PMOS transistor MP23 inputs the first power supply voltage VDDH, the gate is connected to the input end of the third buffer BU3 and the gate of the thirty-ninth NMOS transistor MN39, and the drain is connected to one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to the other end of the nineteenth capacitor C19, the drain of the thirty-ninth NMOS transistor MN39, and the other input end of the second AND gate AND2. The output end of the second AND gate AND2 is connected to the fourth driving buffer subunit 425. The operating voltage domain of the second AND gate AND2 is from VDDH to the ground terminal voltage GND.

[0169] like Fig.19As shown, the third driving buffer subunit 424 includes: a second Schmitt trigger SMIT2, a first inverter chain INVC1, a twenty-first PMOS tube MP21 and a thirty-seventh NMOS tube MN37. The input end of the second Schmitt trigger SMIT2 is connected to the gate of the twentieth PMOS tube MP20 of the second shift subunit 421, and the output end is connected to the input end of the first inverter chain INVC1. The output end of the first inverter chain INVC1 is connected to the gate of the twenty-first PMOS tube MP21 and the gate of the thirty-seventh NMOS tube MN37. The drain of the twenty-first PMOS tube MP21 is connected to the drain of the thirty-seventh NMOS tube MN37. The drain of the twenty-first PMOS tube MP21 is also connected to an input end of the low-side output switch subunit 423, and the signal L_Z0 is output to the low-side output switch subunit 423. The source of the twenty-first PMOS transistor MP21 also inputs the first high voltage VDDR, and the source of the thirty-seventh NMOS transistor MN37 also inputs the first low-side operating voltage VD1. The operating voltage domains of the second Schmitt trigger SMIT2 and the first inverter chain INVC1 are both from the first high voltage VDDR to the first low-side operating voltage VD1.

[0170] like Fig.19 As shown, the fourth driving buffer subunit 425 includes: a second inverter chain INVC2, a twenty-fourth PMOS tube MP24 and a fortieth NMOS tube MN40. The input end of the second inverter chain INVC2 is connected to the output end of the second AND gate AND2 of the third delay matching subunit 422, and the output end is connected to the gate of the twenty-fourth PMOS tube MP24 and the gate of the fortieth NMOS tube MN40. The source of the twenty-fourth PMOS tube MP24 inputs the first power supply voltage VDDH, and the source of the fortieth NMOS tube MN40 is connected to the ground terminal GND. The drain of the twenty-fourth PMOS tube MP24 is connected to the drain of the fortieth NMOS tube MN40. The drain of the twenty-fourth PMOS tube MP24 is also connected to another input end of the low-side output switch subunit 423, and the signal L_Z1 is output to the low-side output switch subunit 423. The operating voltage domain of the second inverter chain INVC2 is VDDH to the ground terminal voltage GND.

[0171] The first inverter chain INVC1 and the second inverter chain INVC2 are two groups of inverter chains with gradually increasing width-to-length ratios, so as to improve the driving capability and minimize the Miller conduction time of the low-side power tube LM.

[0172] like Fig.16As shown, the low-side output switch subunit 423 includes: a twenty-sixth PMOS tube MP26 and a forty-second NMOS tube MN42. The gate of the twenty-sixth PMOS tube MP26 is connected to the gate of the twenty-first PMOS tube MP21 of the third drive buffer subunit 424, the source inputs the first high voltage VDDR, and the drain is connected to the drain of the forty-second NMOS tube MN42, the gate of the low-side power tube LM, and the drain of the eighth NMOS tube MN8 of the low-side voltage detection module 200. The gate of the forty-second NMOS tube MN42 is connected to the drain of the twenty-fourth PMOS tube MP24 of the fourth drive buffer subunit 425, and the source is connected to the ground terminal GND.

[0173] The thirty-fourth NMOS transistor MN34, the thirty-fifth NMOS transistor MN35, the thirty-sixth NMOS transistor MN36, the twentieth PMOS transistor MP20, the tenth resistor R10, the eleventh resistor R11, the third diode D3 and the fourth diode D4 constitute a high-voltage level shift circuit in the second shift subunit 421. When the output signal L_DRIVER_IN at the output end of the low-side logic module 600 is at a high potential, the high-potential L_DRIVER_IN signal pulls down the gate potential of the twentieth PMOS transistor MP20, the twentieth PMOS transistor MP20 is turned on, and the G point is at a high potential (the first high voltage VDDR). When the output signal L_DRIVER_IN at the output end of the low-side logic module 600 is at a low potential, the thirty-fourth NMOS transistor MN34 is turned off, the gate of the twentieth PMOS transistor MP20 is pulled up to a high potential (the first high voltage VDDR) by the tenth resistor R10, and the twentieth PMOS transistor MP20 is turned off. Therefore, the G point is pulled down to a low potential (the first low-side working voltage VD1) by the eleventh resistor R11, thereby realizing the voltage domain conversion of the output signal L_DRIVER_IN at the output end of the low-side logic module 600 from the low voltage domain (0-VDD) to the high voltage domain (VD1-VDDR). The thirty-sixth NMOS transistor MN36 is a high-voltage clamping transistor, which is used to protect the drain-source voltage of the thirty-fourth NMOS transistor MN34 and the thirty-fifth NMOS transistor MN35 from being broken down.

[0174] The 22nd PMOS tube MP22, the 23rd PMOS tube MP23, the 38th NMOS tube MN38, the 39th NMOS tube MN39, the 12th resistor R12, the 13th resistor R13, the 18th capacitor C18, and the 19th capacitor C19 in the third delay matching subunit 422 constitute a delay matching circuit, and the second Schmitt trigger SMIT2 is the delay matching circuit of the third driving buffer subunit 424. Both parts of the delay matching are used to prevent the 26th PMOS tube MP26 and the 42nd NMOS tube MN42 of the last stage inverter of the low-side output switch subunit 423 from being turned on at the same time. The specific principle of the delay matching circuit is: when the output signal L_DRIVER_IN at the output end of the low-side logic module 600 is at a high potential, the output signal L_Z0 of the third drive buffer sub-unit 424 and the output signal L_Z1 of the fourth drive buffer sub-unit 425 are both at a low potential. At this time, the twenty-sixth PMOS tube MP26 of the last-stage inverter of the low-side output switch sub-unit 423 is turned on, so that the output of the low-side drive voltage LS_GD is at a high potential. When the output signal L_DRIVER_IN of the low-side logic module 600 jumps from a high potential to a low potential, the potential of the point H of the third delay matching subunit 422 jumps from a low potential to a high potential, and the rising edge delay circuit composed of the twenty-second PMOS tube MP22, the twenty-third PMOS tube MP23, the thirty-eighth NMOS tube MN38, the thirty-ninth NMOS tube MN39, the twelfth resistor R12, the thirteenth resistor R13, the eighteenth capacitor C18, the nineteenth capacitor C19 and the second AND gate AND2 will delay the rising edge of the signal at the point H, so the output signal L_Z0 of the third driving buffer subunit 424 jumps to a high potential first, ensuring that after the twenty-sixth PMOS tube MP26 of the last stage inverter of the low-side output switch subunit 423 is disconnected, the output signal L_Z1 of the fourth driving buffer subunit 425 jumps to a high potential again, thereby avoiding the upper and lower MOS tubes of the last stage inverter of the low-side output switch subunit 423 of the low-side driver module 400 from being turned on at the same time.

[0175] The high-side logic module 500 is connected to the output end of the second potential conversion unit 202. Fig.16As shown, the high-side logic module 500 includes: the tenth inverter INV10, the fifth AND gate AND5 and the first OR gate OR1. The input end of the tenth inverter INV10 is connected to the output end of the third inverter INV3 of the low-side voltage detection module 200, and receives the LS_GD_Z signal (low-side detection signal) output by the low-side voltage detection module 200. The output end of the tenth inverter INV10 is connected to an input end of the first OR gate OR1. One input end of the fifth AND gate AND5 inputs the high-side drive signal HS_DRIVER_IN, the other input end is connected to the output end of the first OR gate OR1, and the output end is connected to the high-side driver unit 302. The other input end of the first OR gate OR1 inputs the enable signal EN. Specifically, the output end of the fifth AND gate AND5 is connected to the third AND gate AND3 of the low-to-high level shift subunit 321 of the high-side driver unit 302.

[0176] The low-side logic module 600 is connected to the output end of the first potential conversion unit 102. Fig.16 As shown, the low side logic module 600 comprises: the 11th inverter INV11, the 6th AND gate AND6 and the second OR gate OR2. The input end of the 11th inverter INV11 is connected with the output end of the first inverter INV1 of the high side voltage detection module 100, and receives the HS_GD_Z signal (high side detection signal) output by the high side voltage detection module 100. The output end of the 11th inverter INV11 is connected with an input end of the second OR gate OR2. An input end of the 6th AND gate AND6 inputs a low side drive signal LS_DRIVER_IN, and another input end is connected with the output end of the second OR gate OR2, and the output end is connected with the low side drive unit 402. Another input end of the second OR gate OR2 inputs an enable signal EN. Specifically, the output end of the 6th AND gate AND6 is connected with the 4th AND gate AND4 of the second shift subunit 421 of the low side drive unit 402.

[0177] The high-side voltage detection module 100 , the low-side voltage detection module 200 , the high-side driving module 300 , the low-side driving module 400 , the high-side logic module 500 and the low-side logic module 600 are all integrated in the chip.

[0178] In the embodiment of the present application, the high-side voltage detection module 100 and the low-side voltage detection module 200 collect the potential changes of the high-side driving voltage HS_GD and the low-side driving voltage LS_GD of the output signals of the high-side driving module 300 and the low-side driving module 400 in real time, and generate control signals (high-side detection signal HS_GD_Z and low-side detection signal LS_GD_Z). The low-side driving module 400 and the high-side driving module 300 respectively delay the high-side driving signal H_DRIVER_IN after the logic operation and the low-side driving signal L_DRIVER_IN after the logic operation according to the low-side detection signal LS_GD_Z and the high-side detection signal HS_GD_Z, so as to control the conduction or closing of the low-side power tube LM and the high-side power tube HM. That is, only when the gate potential of the high-side power tube HM (high-side drive voltage HS_GD) becomes a low potential (first threshold voltage) and the high-side power tube HM is disconnected, the low-side power tube LM is turned on; similarly, only when the gate potential of the low-side power tube LM (low-side drive voltage LS_GD) becomes a low potential (second threshold voltage) and the low-side power tube LM is disconnected, the high-side power tube HM is turned on. Thus, adaptive control of the dead time is achieved. The implementation method of the present application can adaptively adjust the dead time with different loads, which has higher flexibility than the traditional inherent dead time.

[0179] The embodiment of the present application proposes a driving circuit of an anti-cross conduction structure based on an external power tube. The driving circuit can realize adaptive changes of the dead time according to the load, thereby avoiding the disadvantage of large reverse conduction loss of the power tube due to inaccurate dead time when using traditional RC delay as dead zone. The high-side voltage detection module 100 and the low-side voltage detection module 200 of the embodiment of the present application have good protection functions and can be generally applied to high-voltage drive circuits. The high-side drive module 300 and the low-side drive module 400 of the embodiment of the present application can make the gate-source drive voltage of the power tube reach 10V and above 10V, thereby greatly reducing the conduction impedance of the power tube. At the same time, in the high-side drive module 300 and the low-side drive module 400, the Zener clamping method is also adopted, which can be compatible with the 5V CMOS tube of the existing ordinary BCD process, and can be generally applied to the CMOS tube of the general BCD process.

[0180] Embodiment 2

[0181] This embodiment also provides a full-bridge drive circuit, such as Fig. 20 and Fig.16 As shown, it includes: a first power MOS tube HM1, a second power MOS tube LM1, a third power MOS tube HM2, a fourth power MOS tube LM2 and two driving circuits, and the driving circuit is the driving circuit described in any one of the first aspects;

[0182] The output end of the high-side driving module 300 and the input end of the high-side voltage detection module 100 of one of the two driving circuits 10 are both connected to the gate of the first power MOS transistor HM1, and the output end of the low-side driving module 400 and the input end of the low-side voltage detection module 200 are both connected to the gate of the second power MOS transistor LM1;

[0183] The output end of the high-side driving module 300 and the input end of the high-side voltage detection module 100 of the other driving circuit 20 of the two driving circuits are both connected to the gate of the third power MOS tube HM2, and the output end of the low-side driving module 400 and the input end of the low-side voltage detection module 200 are both connected to the gate of the fourth power MOS tube LM2.

[0184] The source of the first power MOS transistor HM1 and the drain of the second power MOS transistor LM1 are both connected to one end of the load, and the source of the third power MOS transistor HM2 and the drain of the fourth power MOS transistor LM2 are both connected to the other end of the load.

[0185] The full-bridge driving circuit provided in this embodiment is also based on the same concept as the above driving circuit, so it can at least achieve the beneficial effects that the above driving circuit can achieve, which will not be described in detail here.

[0186] Embodiment 3

[0187] This embodiment also provides a wireless charging circuit, including the full-bridge driving circuit described in the second aspect.

[0188] The full-bridge driving circuit described in the second aspect can be applied to a wireless charging circuit, such as Fig.21 As shown, the four switches HM1, HM2, LM1, and LM2 are controlled by the full-bridge drive circuit, so that a set of complementary square waves are generated at the SW node and the SW1 node, thereby causing the inductor and capacitor CL in the wireless charging circuit to resonate. As a result, the inductor current changes sinusoidally, realizing energy transmission.

[0189] The driving circuit described in the first aspect and the full-bridge driving circuit described in the second aspect can both be applied to motors.

[0190] The wireless charging circuit provided in this embodiment is also based on the same concept as the above-mentioned full-bridge driving circuit, so it can at least achieve the beneficial effects that can be achieved by the above-mentioned full-bridge driving circuit, which will not be described in detail here.

[0191] Embodiment 4

[0192] This embodiment further provides a chip, on which the driving circuit described in any one of the first aspect, or the bridge driving circuit described in the second aspect, or the wireless charging circuit described in the third aspect is integrated.

[0193] The chip provided in this embodiment is also based on the same concept as the above-mentioned driving circuit, so it can at least achieve the beneficial effects that can be achieved by the above-mentioned driving circuit, which will not be described in detail here.

[0194] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not deviate from the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way.

[0195] In the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of means or steps not listed in the claims. The word "a" or "an" preceding a means does not exclude the presence of a plurality of such means. The present application may be implemented by means of hardware comprising several different means and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0196] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A driving circuit, characterized in that: include: A high-side voltage detection module, a low-side voltage detection module, a high-side driver module and a low-side driver module; The input end of the high-side voltage detection module is connected to the output end of the high-side driving module, the high-side voltage detection module samples the high-side driving voltage output by the high-side driving module, and outputs a high-side detection signal when the high-side driving voltage drops to a first threshold voltage, and the high-side detection signal triggers the low-side driving module to turn on; The input end of the low-side voltage detection module is connected to the output end of the low-side driving module. The low-side voltage detection module samples the low-side driving voltage output by the low-side driving module, and outputs a low-side detection signal when the low-side driving voltage drops to a second threshold voltage. The low-side detection signal triggers the high-side driving module to turn on.

2. The driving circuit according to claim 1, characterized in that: The high-side voltage detection module includes a level shift unit and a first potential conversion unit; The input end of the level shift unit is connected to the output end of the high-side driving module, and the output end is connected to the first potential conversion unit; the level shift unit clamps the value of the high-side driving voltage and shapes the waveform of the high-side driving voltage; The output end of the first potential conversion unit is connected to the high-side driving module; The first potential conversion unit converts the shaped high-side driving voltage from the high voltage domain to the low voltage domain, and generates a first detection voltage according to the high-side driving voltage in the low voltage domain, and the first detection voltage is used as a high-side detection signal.

3. The driving circuit according to claim 2, characterized in that: The level shift unit comprises a clamping subunit and a first shifting subunit; The input end of the clamping subunit is connected to the output end of the high-side driving module, and the output end is connected to the input end of the first shifting subunit; An output terminal of the first shift subunit is connected to the first potential conversion unit.

4. The driving circuit according to claim 2, characterized in that: The high-side voltage detection module further includes a voltage protection unit, and the voltage protection unit is arranged between the level shift unit and the first potential conversion unit.

5. The driving circuit according to claim 1, characterized in that: The low-side voltage detection module includes a switch unit and a second potential conversion unit; The input end of the switch unit is connected to the output end of the low-side driving module, and the output end is connected to the second potential conversion unit; the switch unit is turned on or off according to the potential of the low-side driving voltage in the high voltage domain to generate a turn-on voltage or a turn-off voltage; The output end of the second potential conversion unit is connected to the low-side driving module; The second potential conversion unit generates a second detection voltage in a low voltage domain according to the on-voltage or the off-voltage, and the second detection voltage is used as a low-side detection signal.

6. The driving circuit according to claim 1, characterized in that: The high-side driving module includes a high-side voltage bias unit and a high-side driving unit; The high-side driving unit generates the high-side driving voltage according to the driving signal and the high-side potential; The output end of the high-side voltage bias unit is connected to the high-side driving unit. The high-side voltage bias unit generates the high-side potential according to the bootstrap voltage and the switch node voltage. The high-side potential is the operating voltage of the high-side driving unit.

7. The driving circuit according to claim 6, characterized in that: The high-side voltage bias unit includes a first high-side potential subunit and a second high-side potential subunit; The first high-side potential subunit generates a first high-side operating voltage according to the bootstrap voltage when being turned on; When the second high-side potential subunit is turned on, it generates a second high-side operating voltage according to the switch node voltage.

8. The driving circuit according to claim 7, characterized in that: The first high-side potential subunit includes a first Zener tube, a first NMOS tube and a first PMOS tube; The bootstrap voltage is input to the cathode of the first Zener tube, and the anode is respectively connected to the drain of the first NMOS tube and the gate of the first PMOS tube; The switch node voltage is input to the source of the first NMOS tube and the drain of the first PMOS tube; The source of the first PMOS tube outputs the first high-side operating voltage.

9. The driving circuit according to claim 6, characterized in that: The second high-side potential subunit includes a second Zener tube and a second NMOS tube; The positive electrode of the second Zener tube inputs the switch node voltage, and the negative electrode is connected to the source of the second NMOS tube; The drain of the second NMOS tube inputs the bootstrap voltage, and the source outputs the second high-side operating voltage.

10. The driving circuit according to claim 6, characterized in that: The high-side driving unit includes a low-to-high level shifting subunit, a high-to-low level shifting subunit and a high-side output switch subunit; The output end of the low-to-high level shift subunit is connected to the high-to-low level shift subunit, and the low-to-high level shift subunit also inputs the driving signal and the bootstrap voltage; the low-to-high level shift subunit converts the low voltage domain from the working voltage to the ground terminal voltage into a high voltage domain output voltage from the bootstrap voltage to the high-side potential according to the driving signal and the bootstrap voltage; The high-to-low level shift subunit converts the input high-side potential to the high voltage domain of the bootstrap voltage into a low voltage domain output voltage from the switch node voltage to the high-side potential; The high-side output switch subunit is connected to the output end of the low-to-high level shift subunit and the output end of the high-to-low level shift subunit; the high-side output switch subunit outputs the high-side drive voltage according to the high voltage domain output voltage and the low voltage domain output voltage.

11. The driving circuit according to claim 10, characterized in that: The high-side driving unit further includes a first delay matching subunit, a second delay matching subunit, a first driving buffer subunit and a second driving buffer subunit; The first delay matching subunit is arranged between the low-to-high level shifting subunit and the high-side output switch subunit; the first delay matching subunit delays and outputs the high voltage domain output voltage; The first driving buffer subunit is arranged between the first delay matching subunit and the high-side output switch subunit; The second delay matching subunit is connected to the high-to-low level shifting subunit and the second driving buffer subunit respectively; The second driving buffer subunit is also connected to the high-side output switch subunit; the second delay matching subunit delays the output of the low voltage domain output voltage.

12. The driving circuit according to claim 1, characterized in that: The low-side driving module comprises: a low-side voltage bias unit and a low-side driving unit; The low-side driving unit generates the low-side driving voltage according to the driving signal and the low-side potential; An output end of the low-side voltage bias unit is connected to the low-side driving unit, and the low-side voltage bias unit generates the low-side potential according to a first voltage domain.

13. The driving circuit according to claim 12, characterized in that: The low-side driving unit comprises: a second shift sub-unit, a third delay matching sub-unit and a low-side output switch sub-unit; The second shift subunit and the third delay matching subunit are both connected to the low-side output switch subunit; the second shift subunit and the third delay matching subunit are both input with the driving signal; The second shift subunit converts the driving signal in the low voltage domain into a first high voltage in the first voltage domain of the high voltage domain or a voltage of the low side potential according to the low side potential; The third delay matching subunit delays and outputs the driving signal; The low-side output switch subunit outputs the low-side drive voltage according to the first high-level voltage or the low-side potential voltage and the delayed output drive signal.

14. The driving circuit according to claim 1, characterized in that: Also included are high-side logic modules and low-side logic modules; The high-side logic module is arranged between the high-side driving module and the low-side voltage detection module; the high-side logic module adjusts the driving signal input to the high-side driving module according to the enable signal; The low-side logic module is arranged between the low-side driving module and the high-side voltage detection module; the low-side logic module adjusts the driving signal input to the low-side driving module according to the enable signal.

15. A full-bridge drive circuit, characterized in that: include: A first power MOS tube, a second power MOS tube, a third power MOS tube, a fourth power MOS tube and two driving circuits, wherein the driving circuit is the driving circuit according to any one of claims 1 to 14; The output end of the high-side driving module and the input end of the high-side voltage detection module of one of the two driving circuits are both connected to the gate of the first power MOS tube, and the output end of the low-side driving module and the input end of the low-side voltage detection module are both connected to the gate of the second power MOS tube; The output end of the high-side driving module and the input end of the high-side voltage detection module of the other driving circuit of the two driving circuits are both connected to the gate of the third power MOS tube, and the output end of the low-side driving module and the input end of the low-side voltage detection module are both connected to the gate of the fourth power MOS tube.

16. A wireless charging circuit, characterized in that: Includes the full-bridge drive circuit as claimed in claim 15.

17. A chip, characterized in that: The driving circuit according to any one of claims 1 to 14 is integrated thereon, or the bridge driving circuit according to claim 15 is integrated thereon, or the wireless charging circuit according to claim 16 is integrated thereon.

Images