Chip, single-gate logic chip and manufacturing method
By introducing multiple fuse arrays and logic gate circuit modules into the chip, flexible adjustment of chip functions is achieved, and the problem of mismatch between single-gate logic chip production and market demand is solved, the production efficiency and product delivery speed are improved, and users are reduced cost.
Patent Information
- Application Number
- CN202411350768.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2024-12-27
AI Technical Summary
Single-door logic chip products have single functions and diverse and unbalanced market demand, which leads to difficult matching of production and market demand, resulting in lag in production and untimely product delivery, increasing user costs.
Design a chip that includes multiple fuse arrays and multiple logic gate circuits, input modules and output modules. By selectively fuse fuses, adjust the chip's functions, and realize the specified single-gate logic functions and input and output levels, and adapt to the Different market demands.
It realizes flexible adjustment and customized production of chips, improves production efficiency and product delivery speed, reduces user usage costs, and maintains high production efficiency and product consistency.
Smart Images
Figure CN119210431A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuits, and in particular to a chip, a single-gate logic chip, and a manufacturing method thereof. Background Art
[0002] A single-gate logic (chip) product is an integrated circuit (IC) that features a single basic logic gate. In digital electronics, logic gates perform fundamental logic operations such as AND, OR, NOT, NAND, NOR, and XOR. These gates are the building blocks of more complex digital circuits and systems.
[0003] Single-gate logic products are of various types and widely used in the market. With the development of semiconductor microelectronics process technology, the design and processing are carried out using processes below 0.18μm, and the wafer area occupied by the product can be less than 0.1mm 2 , so its single wafer output is very high.
[0004] However, due to the single function of its individual products, the market demands a wide variety of functions, the uneven demand for different types, and the large difference in annual usage, it is difficult to match the production of single-gate logic products with market demand. In other words, it is difficult to effectively adjust the production rhythm according to market demand, resulting in production delays and untimely product delivery, thereby increasing users' usage costs. Summary of the Invention
[0005] In order to solve or improve the above-mentioned problems existing in the prior art, the present disclosure provides a chip in a first aspect, which includes one or more input stages, an intermediate stage, an output stage and a plurality of fuse arrays;
[0006] The fuse array includes a plurality of fuses capable of being selectively blown;
[0007] The input stage includes the chip input terminal and multiple different input modules;
[0008] The middle stage includes a number of different logic gate circuits;
[0009] The output stage includes the chip output terminal and multiple different output modules;
[0010] Multiple fuse arrays including:
[0011] One or more first fuse arrays, corresponding one to one with one of the one or more input stages, wherein the plurality of fuses are respectively connected to the plurality of input modules in the corresponding input stage;
[0012] One or more second fuse arrays are connected to the one or more first fuse arrays in a one-to-one correspondence, wherein the plurality of fuses are respectively connected to some or all of the input terminals of the plurality of logic gate circuits;
[0013] a third fuse array, wherein the plurality of fuses are connected to the output terminals of the plurality of logic gate circuits in a one-to-one correspondence;
[0014] The fourth fuse array is connected to the third fuse array, wherein the plurality of fuses are connected to the plurality of output modules in a one-to-one correspondence.
[0015] The aforementioned chip is pre-set with multiple logic gate circuits, multiple input modules and multiple output modules, and is also provided with fuse arrays connected between the input stage and the intermediate stage, and between the intermediate stage and the output stage.
[0016] According to actual needs, the fuses in each fuse array are selectively blown, and the logic gate circuit, input module and output module in the aforementioned chip are selected to obtain a single-gate logic product with a specified single-gate logic function, specified input level and specified output level that meets actual needs.
[0017] Optionally, the chip includes a first input stage and a second input stage;
[0018] The middle stage includes a plurality of single-ended logic gate circuits and a plurality of double-ended logic gate circuits;
[0019] In a second fuse array corresponding to the first input stage:
[0020] The plurality of fuses are respectively connected to the input ends of the plurality of single-ended logic gate circuits and the first input ends of the plurality of double-ended logic gate circuits;
[0021] In a second fuse array corresponding to a second input stage:
[0022] The plurality of fuses are respectively connected to the second input terminals of the plurality of two-terminal logic gate circuits.
[0023] In the above scheme, the chip can be adjusted into a single-ended logic gate circuit or a dual-ended logic gate circuit in subsequent manufacturing steps. Specifically, the two second fuse arrays corresponding to the two input terminals are respectively responsible for connecting the first input terminal of each logic gate circuit (including the only input terminal of the single-ended logic gate circuit) and the second input terminal of the dual-ended logic gate circuit.
[0024] This structure is easy to adjust during the subsequent production and trimming process, and is particularly suitable for situations where semi-finished chips are pre-set with single-ended and double-ended logic gate circuits at the same time.
[0025] Optionally, the multiple input modules in the input stage include CMOS input modules, TTL-compatible input modules, Schmitt input modules, bus holding modules and anti-power-flooding input modules, so that the chip can optionally adapt to the input modes corresponding to the above multiple input modules.
[0026] Optionally, the multiple output modules in the output stage include multiple types of CMOS output modules, three-state output modules, open-drain output modules and anti-flooding output modules, so that the chip can optionally adapt to the output modes corresponding to the above multiple output modules.
[0027] Optionally, the multiple logic gate circuits in the intermediate level include single-ended inputs, such as positive phase circuits and negative phase circuits, and also include dual-ended inputs, such as OR gate circuits, AND gate circuits, NAND gate circuits, NOR gate circuits, XNOR gate circuits and XOR gate circuits.
[0028] In combination with one or more of the aforementioned input stages, the chip in the present disclosure can be set as a single-ended input product such as a positive-phase or negative-phase logic product, or a dual-ended input product such as an OR gate, an AND gate, a NAND gate, a NOR gate, an XNOR gate, and the like.
[0029] Optionally, multiple fuses in the first fuse array and the fourth fuse array are arranged at equal intervals, and multiple fuses in the second fuse array and the third fuse array are arranged at equal intervals, and each fuse is also connected to a fuse and grounded through an external lead, that is, a grounding fuse. The reason for setting the grounding fuse is that, considering that the input end cannot be left floating, it is necessary to ensure the safety and reliability of the product. Therefore, a grounding fuse is pre-connected on each fuse corresponding to the input and output ends of the logic gate circuit. During the trimming process, the above-mentioned fuses that are blown retain the grounding fuse to prevent them from being left floating, and for the retained fuses, their corresponding grounding fuses are blown to prevent the input signal from being grounded.
[0030] Optionally, one or more input stages, intermediate stages, and output stages are formed on the same wafer substrate.
[0031] In the aforementioned scheme or its optional scheme, multiple input stages, intermediate stages and output stages with different functions are formed on the same wafer. Therefore, in terms of production, only one set of photolithography plates needs to be made and the same version of wafers needs to be mass-produced, thereby reducing the complexity and storage pressure of small-batch production of multiple varieties. After determining the actual product functional requirements, the required functional products can be obtained through adjustments.
[0032] Alternatively, based on the above, users can be provided with "semi-finished products" of wafers or bare chips of the same model and stored centrally. When used, they can be adjusted and packaged into products with the required specific functions according to actual usage.
[0033] In the aforementioned embodiment, a fuse array is used as the structure for selecting the functional module. Since the fuse size is very small and the area occupied is also small, multiple fuse arrays do not affect the overall size of the product, and the output of a single wafer is still high.
[0034] A second aspect of the present disclosure provides a method for manufacturing a chip product. Specifically, a method for manufacturing a chip provided by the aforementioned technical solution or any optional solution thereof, further manufacturing the chip into a chip implementing single-gate logic, the method comprising:
[0035] Providing a chip as provided in the aforementioned technical solution or any of its optional solutions, and performing the following steps on the chip to obtain a single-gate logic chip product that meets the requirements;
[0036] Select an input module to be used in the input stage, retain the fuse connected to the selected input module in the first fuse array corresponding to the input stage, and blow all other fuses;
[0037] Selecting a logic gate circuit to be used in the middle stage, retaining the fuse connected to the input end of the selected logic gate circuit in the second fuse array and blowing all other fuses; retaining the fuse connected to the output end of the selected logic gate circuit in the third fuse array and blowing all other fuses;
[0038] An output module required for use in the output stage is selected, and in the fourth fuse array, the fuse connected to the selected output module is retained, and all other fuses are blown.
[0039] Optionally, a chip with a ground fuse as described above is provided, and the following steps are further performed on the chip based on the above steps:
[0040] In the second fuse array and the third fuse array, the ground fuses corresponding to the retained fuses are blown, and correspondingly, the ground fuses connected to the blown fuses are retained, thereby preventing the unused input terminals from being left floating.
[0041] Optionally, the manufacturing method includes: packaging the chip after blowing some fuses in each fuse array as required.
[0042] In the above method, by adjusting and blowing the fuse that does not meet the user's required function, the semi-finished chip made from the same wafer or the same photoresist can be converted into a single-gate logic product with the required function, which can increase the production speed and product delivery speed, and ultimately reduce the user's end cost.
[0043] A third aspect of the present disclosure provides a chip implementing single-gate logic. This chip implementing single-gate logic is based on the chip described in the first aspect and is further manufactured using the manufacturing method described in the second aspect and any of its optional solutions. Due to its manufacturing method of achieving the desired functionality through fuse trimming and the use of a general-purpose chip semi-finished product, this chip implementing single-gate logic also has high production efficiency, a high customized product delivery rate, and easy cost control.
[0044] In summary, the chip, manufacturing method, and single-gate logic chip product provided in the embodiments of the present disclosure all have high customization flexibility, high production efficiency, good product consistency, and low cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the background technology, the drawings required for use in the embodiments of the present disclosure or the background technology will be described below.
[0046] Figure 1 1 is a schematic diagram of the layout structure of an embodiment of a chip provided by the present disclosure. In this embodiment, all fuse arrays are in an unblown state;
[0047] Figure 2 This is a schematic diagram of the layout structure of an embodiment of a chip implementing single-gate logic provided by the present disclosure. This embodiment implements customized single-gate logic functions and input and output characteristics by adjusting the fuse array. DETAILED DESCRIPTION
[0048] In this specification, it will also be understood that when an element is referred to as being relative to other elements, such as being "connected to" other elements, the one element may be directly connected to or directly coupled to the one element, or there may also be a third element in between; in addition, in the embodiments of the present disclosure, "connection" is specifically mainly electrical connection, more specifically digital electrical signal connection.
[0049] The present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided herein to make the present disclosure more detailed and complete and to fully convey the scope of the present disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals represent the same objects.
[0050] In addition, it should be understood that the “correspondence” referred to in this disclosure may be a correspondence relationship formed by a direct corresponding connection, or a correspondence relationship formed by an indirect connection, for example Figure 1 The input 1 , the input stage, the first fuse array R1 , and the second fuse array R2 in the upper middle row all have corresponding relationships as described in the present disclosure.
[0051] Taking into account the current situation in the prior art where there are many types of single-gate logic products, uneven demand for different types, and large differences in annual usage, as well as the problems of slow product type switching and production delays caused by the aforementioned situation, the inventors of the present disclosure further realized that the packaging forms of different types of single-gate logic products are often similar (mostly using ultra-small packages), and the number and type of pins are also relatively similar (generally including power pins, ground pins, input pins, output pins, and control pins). In view of this, the inventors of the present disclosure hope to develop a chip prefabricated product (or semi-finished product) that pre-integrates multiple logic functions and multiple input and output functions to facilitate universal production and can be converted into a product with the required functions through simple adjustments after the needs are determined.
[0052] More specifically, the embodiments of the present disclosure provide a design method for a product that can realize multiple single-gate logic functions through adjustment. The design method aims to use fuses to select different combinations of modules in the input stage, intermediate stage, and output stage of the chip based on the aforementioned chip prefabricated product to obtain the desired single-gate logic product.
[0053] Single-gate logic products have similar structures, all consisting of an input stage, an intermediate stage, and an output stage. Depending on the input level, the input stage can be categorized as CMOS, TTL-compatible, or Schmitt input. The intermediate stage includes various logic gates, such as AND, OR, NOT, NAND, NOR, XNOR, and XOR. The output stage includes open-drain, CMOS, and tri-state outputs. Each single-gate logic product is a combination of different input, intermediate, and output stages. The design method in the embodiments adjusts fuses to select the connection between the input, intermediate, and output stages, enabling product customization by combining different input types, output types, and logic functions.
[0054] The present disclosure provides an embodiment of a chip, which is designed based on the aforementioned design method and is suitable for large-scale production as a universal prefabricated part or semi-finished product. It adopts a unified package and external pins, has high product consistency, and is easy to adjust and customize to form a single-gate logic product with specific functions.
[0055] In a typical embodiment, Figure 1 As shown, this chip includes one or more input stages, an intermediate stage, an output stage and multiple fuse arrays; typically, there are two input stages, which are respectively connected to a first input terminal and a second input terminal. This is because common logic gate circuits require one or two input terminals, for example, positive phase and negative phase require one input terminal, while AND gate, OR gate, NAND gate, NOR gate, XNOR gate, XOR gate, etc. require two input terminals.
[0056] Each of the aforementioned multiple fuse arrays includes a plurality of fuses.
[0057] The input stage includes a chip input terminal and a plurality of different input modules; the intermediate stage includes a plurality of different logic gate circuits; the output stage includes a chip output terminal and a plurality of different output modules; illustratively, the optional input modules, logic gate circuits or output modules are as follows: Figure 1 shown.
[0058] The multiple fuse arrays specifically include the following:
[0059] One or more first fuse arrays R1 correspond to one or more input stages, wherein the fuses are respectively connected to the input modules in the corresponding input stages and are all connected to the second fuse array R2. The first fuse array R1 is used to determine the input structure of the connected input stage.
[0060] One or more second fuse arrays R2 correspond to the aforementioned first fuse arrays R1 and input stages. The second fuse arrays R2 are at least used to determine the input form of the single-gate logic product. Figure 1 As shown, each group of fuses in the second fuse array R2 for input 1 is arranged at equal intervals. In the figure, the upper fuse in each group of fuses is respectively connected to the input terminals of multiple logic gate circuits, and the lower fuse is a ground fuse that is grounded via an external lead, and the two fuses are connected. In the second fuse array R2 for input 2, each group of fuses is arranged at equal intervals. The upper fuse in each group of fuses is respectively connected to the other input terminal of the dual-input logic gate circuit, and the lower fuse is a ground fuse that is grounded via an external lead, and the two fuses are connected.
[0061] The third fuse array R3 has fuses arranged at equal intervals in each group, as shown in the figure. The top fuse in each group is connected to the output terminals of multiple logic gate circuits, and the bottom fuse is a ground fuse, which is grounded through an external lead. The two fuses are connected and both connected to the fourth fuse array R4. The third fuse array R3 is used to determine the logical function of the product.
[0062] A plurality of fuses in the fourth fuse array R4 are respectively connected to a plurality of output modules. The fourth fuse array R4 is used to determine the output structure of the product.
[0063] In an embodiment, the two fuse arrays connected to each other specifically refer to all fuses in the two fuse arrays being indirectly electrically connected via a specific fuse.
[0064] In a typical embodiment, two input stages are included, and a first fuse array R1 is respectively connected to the two input stages.
[0065] In a typical embodiment, the number of fuses in the second fuse array R2 of input 1 is the same as the number of logic gate circuits in the middle stage, and one end input of the single-end input logic gate circuit and the dual-end input logic gate circuit can be selected. The number of fuses in the second fuse array R2 of input 2 is the same as the number of dual-end input logic gate circuits in the middle stage, and the other end input of the dual-end input logic gate circuit can be selected.
[0066] It should be understood that the specific structures of the aforementioned fuse arrays, the material properties and structural features of the fuses therein, etc., are all in accordance with the prior art. They can be applied to the embodiments of the present disclosure as long as they meet the connection relationship in the embodiments of the present disclosure and can be selectively blown as required. Therefore, the specific features of the fuse arrays are not described in detail in this disclosure.
[0067] The aforementioned chip is pre-set with multiple logic gate circuits, multiple input modules and multiple output modules, and is also provided with fuse arrays connected between the input stage and the intermediate stage, and between the intermediate stage and the output stage.
[0068] According to actual needs, the fuses in each fuse array are selectively blown, and the logic gate circuit, input module and output module in the aforementioned chip are selected to obtain a single-gate logic product with a specified single-gate logic function, specified input level and specified output level that meets actual needs.
[0069] In an optional embodiment, the multiple input modules in the input stage include multiple types of CMOS input modules, TTL-compatible input modules, Schmitt input modules, bus-hold modules, and anti-sinking input modules. This allows the chip to selectively adapt to the input modes corresponding to these multiple input modules. The multiple output modules in the output stage include multiple types of CMOS output modules, tri-state output modules, open-drain output modules, and anti-sinking output modules. This allows the chip to selectively adapt to the output modes corresponding to these multiple output modules.
[0070] In an optional embodiment, the plurality of logic gate circuits in the intermediate stage include a plurality of positive phase circuits, negative phase circuits, OR gate circuits, AND gate circuits, NAND gate circuits, NOR gate circuits, XNOR gate circuits and XOR gate circuits.
[0071] It should be understood that in the aforementioned embodiments, the specific circuit structures of the logic gate circuit, input module, and output module are the same as those in the prior art. Those skilled in the art may select them as appropriate according to actual product requirements. Due to space limitations, this disclosure will not describe them in detail.
[0072] In a typical embodiment, based on the configuration in the aforementioned optional embodiment, illustratively, when a CMOS input / output inverting logic product is required, the chip may be adjusted as follows:
[0073] Among the two first fuse arrays R1, the first fuse array R1 corresponding to input 1 is selected, and the input level corresponding to input 1 is used as the effective input level. Input 1 is the actual (effective) input terminal of the product.
[0074] In the first fuse array R1, a fuse connected to the CMOS input module is selected and retained, and all other fuses (in the fuse array) are blown;
[0075] In the second fuse array R2 corresponding to input 1, the fuse connected to the input terminal of the inverter circuit in the middle stage is retained, the part of the fuse connected to the ground fuse is blown, and the remaining fuses connected to the input terminals of other logic gate circuits in the middle stage are blown.
[0076] Since the inverter circuit is a single-ended logic circuit and requires only one input terminal, all fuses in the second fuse array R2 in the chip, that is, the second fuse array R2 corresponding to input 2, can be blown (but the ground fuse must be retained to prevent the input terminal from being left floating).
[0077] In the third fuse array R3, a fuse connected to the output terminal of the inverter circuit in the middle stage is selected and retained, the portion of the fuse connected to the ground fuse is blown, and the remaining fuses connected to the output terminals of other logic gate circuits in the middle stage are blown;
[0078] In the fourth fuse array R4 , a fuse connected to the CMOS output module in the output stage is selected and retained, and all other fuses (in the fuse array) are blown.
[0079] In the aforementioned embodiments, in combination with one or more of the aforementioned input stages, the chip in the present disclosure can be set as a single-ended input product such as a positive-phase or negative-phase logic product, or a dual-ended input product such as an AND gate, an OR gate, a NAND gate, a NOR gate, an XNOR gate, an XOR gate, etc.
[0080] Optionally, the fuse array includes a plurality of fuses arranged at equal intervals;
[0081] Multiple fuses in a fuse array can be selectively blown, resulting in:
[0082] One of the plurality of input stages is connected to the intermediate stage;
[0083] and / or
[0084] One of the plurality of input modules in the input stage is connected to an input terminal of one of the plurality of logic gate circuits in the intermediate stage, and an output terminal of the logic gate circuit is connected to one of the plurality of output modules in the output stage.
[0085] Optionally, one or more input stages, intermediate stages, and output stages are formed on the same wafer substrate.
[0086] In the embodiment, since multiple input stages, intermediate stages and output stages with different functions are formed on the same wafer, in terms of production, only one set of photoresist plates needs to be made and the same version of wafers needs to be mass-produced, thereby reducing the complexity and storage pressure of small-batch production of multiple varieties. After determining the actual product functional requirements, the required functional products can be obtained through adjustments.
[0087] Alternatively, based on the above, users can be provided with "semi-finished products" of wafers or bare chips of the same model and stored in a centralized manner. When actually used, they can be adjusted and packaged into products with the required specific functions according to actual usage.
[0088] In the aforementioned embodiment, a fuse array is used as the structure for selecting the functional module. Since the fuse size is very small and the area occupied is also small, multiple fuse arrays do not affect the overall size of the product, and the output of a single wafer is still high.
[0089] The present disclosure further provides an embodiment of a method for manufacturing a chip product. Specifically, the present disclosure provides a method for manufacturing a chip provided by the aforementioned technical solution or any of its optional solutions, further manufacturing the chip to a chip implementing single-gate logic. The manufacturing method includes:
[0090] Providing a chip as provided in the aforementioned technical solution or any of its optional solutions;
[0091] Select an input module to be used in the input stage, retain the fuse connected to the selected input module in the first fuse array corresponding to the input stage, and blow all other fuses;
[0092] Selecting a logic gate circuit to be used in the middle stage, retaining the fuse connected to the input end of the selected logic gate circuit in the second fuse array and blowing all other fuses; retaining the fuse connected to the output end of the selected logic gate circuit in the third fuse array and blowing all other fuses;
[0093] An output module required for use in the output stage is selected, and in the fourth fuse array, the fuse connected to the selected output module is retained, and all other fuses are blown.
[0094] In the embodiment of the manufacturing method, the selection logic for blowing fuses in each fuse array has been specifically described in the aforementioned chip embodiment, and thus will not be repeated here.
[0095] In a typical embodiment, in order to obtain a double-terminal TTL input, CMOS output NAND gate logic product, the fuses in each fuse array are processed as follows: Figure 2 Selective fusing shown.
[0096] Optionally, the manufacturing method includes: packaging the chip.
[0097] In a typical embodiment, if a NAND gate product with CMOS output and TTL-compatible input is required, the following manufacturing method is performed:
[0098] Provide the chip described in the above embodiment. In the initial state, the two input stages of the chip are fully connected to the corresponding first fuse arrays R1 (two), the middle stage is fully connected to the second fuse array R2 and the third fuse array R3, and the output stage is fully connected to the fourth fuse array R4.
[0099] Make sure the product input stage is compatible with the TTL level structure: retain the fuses connected to the compatible TTL input modules in the two first fuse arrays R1, and blow all fuses connected to the remaining input modules;
[0100] Determine that the product function is a NAND gate: retain the fuse connected to the NAND gate circuit in the second fuse array R2, and blow the remaining fuses. The portion of the fuse connected to the NAND gate circuit that is connected to the ground fuse is also blown. Retain the fuse connected to the NAND gate in the third fuse array R3, and blow the remaining fuses. The portion of the fuse connected to the NAND gate circuit that is connected to the ground fuse is also blown.
[0101] Specifically, the embodiment includes two second fuse arrays R2 , and two fuses connected to two input terminals of the NAND gate circuit in the two second fuse arrays R2 are retained respectively, while the other fuses in the two second fuse arrays R2 are blown.
[0102] The output stage is determined to be a CMOS output structure: the fuses connected to the CMOS output module in the fourth fuse array R4 are retained, and the fuses connected to the remaining output modules are all blown.
[0103] At this point, a NAND gate product with CMOS output and TTL-level compatible input that meets user needs is obtained.
[0104] In the above method, by adjusting and blowing the fuse that does not meet the user's required function, the semi-finished chip made from the same wafer or the same set of photolithography plates can be converted into a single-gate logic product with the required function, which can improve the production speed and product delivery speed, and ultimately reduce the user's end cost.
[0105] The present disclosure provides an embodiment of a chip implementing single-gate logic, fabricated using the methods described in the aforementioned embodiments and any of their preferred and optional embodiments. Due to the fabrication method of achieving desired functionality through fuse trimming and the use of a general-purpose semi-finished chip, this chip implementing single-gate logic also boasts high production efficiency, a high rate of customized product delivery, and ease of cost control.
[0106] In summary, the chips, further fabrication methods based on the chips, and the resulting single-gate logic products described in the aforementioned embodiments are based on the same technical concept and have the following advantages:
[0107] 1. Improve production speed. Only one set of photomasks needs to be prepared to mass-produce the same version of wafers, which can reduce the complexity and storage pressure of small-batch production of multiple varieties.
[0108] 2. Improve user flexibility. Users can customize the product to meet their needs. After providing wafers or bare chips to users, they can store the same wafers or bare chips and package them into the corresponding product based on actual usage.
[0109] 3. The connection relationship between the input stage, intermediate stage, and output stage can be flexibly adjusted through adjustment. The adjustment method is precise and controllable, which can avoid wrong selection or omission and ensure the correctness and reliability of product functions.
[0110] The above descriptions are only some specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the embodiments of the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.
Claims
1. A chip, characterized in that: including one or more input stages, an intermediate stage, an output stage and a plurality of fuse arrays; The fuse array includes a plurality of fuses that can be selectively blown; The input stage includes a chip input terminal and a plurality of different input modules; The intermediate stage includes a plurality of different logic gate circuits; The output stage includes a chip output terminal and a plurality of different output modules; The plurality of fuse arrays include: One or more first fuse arrays, corresponding one to one with the one or more input stages, wherein a plurality of fuses are respectively connected to a plurality of input modules in the corresponding input stage; One or more second fuse arrays are connected to the one or more first fuse arrays in a one-to-one correspondence, wherein a plurality of fuses are respectively connected to some or all of the input terminals of the plurality of different logic gate circuits; A third fuse array, wherein the plurality of fuses are connected to the output ends of the plurality of different logic gate circuits in a one-to-one correspondence; The fourth fuse array is connected to the third fuse array, wherein a plurality of fuses are respectively connected to the plurality of different output modules in a one-to-one correspondence.
2. The chip according to claim 1, characterized in that: The chip includes a first input stage and a second input stage; The intermediate stage includes a plurality of single-ended logic gate circuits and a plurality of double-ended logic gate circuits; In a second fuse array corresponding to the first input stage: A plurality of fuses are respectively connected to the input ends of the plurality of single-ended logic gate circuits and the first input ends of the plurality of double-ended logic gate circuits; In a second fuse array corresponding to the second input stage: A plurality of fuses are respectively connected to the second input terminals of the plurality of two-terminal logic gate circuits.
3. The chip according to claim 2, characterized in that: The plurality of single-ended logic gate circuits include a positive phase circuit and an inverting phase circuit; The plurality of two-terminal logic gate circuits include multiple types of OR gate circuits, AND gate circuits, NAND gate circuits, NOR gate circuits, XNOR gate circuits and XOR gate circuits.
4. The chip according to any one of claims 1 to 3, characterized in that: The multiple input modules in the input stage include multiple types of CMOS input modules, TTL compatible input modules, Schmitt input modules, bus holding modules and anti-power input modules; The multiple output modules in the output stage include multiple types of CMOS output modules, three-state output modules, open-drain output modules and anti-power-flooding output modules.
5. The chip according to any one of claims 1 to 3, characterized in that: The one or more input stages, the intermediate stage and the output stage are formed on a same wafer substrate.
6. The chip according to any one of claims 1 to 3, characterized in that: The second fuse array and the third fuse array further include: A plurality of ground fuses are connected to the other fuses in the second fuse array and the third fuse array in a one-to-one correspondence.
7. A method for manufacturing a single-gate logic chip, characterized in that: The production method comprises: A chip as claimed in any one of claims 1 to 6 is provided, and the following steps are performed on the chip to obtain a desired single-gate logic chip: Select an input module required for use in the input stage, retain the fuse connected to the selected input module in the first fuse array corresponding to the input stage, and blow all other fuses; Selecting a logic gate circuit required for use in the intermediate stage, retaining the fuse connected to the input end of the selected logic gate circuit in the second fuse array and blowing all other fuses; retaining the fuse connected to the output end of the selected logic gate circuit in the third fuse array and blowing all other fuses; An output module required for use in the output stage is selected, and in the fourth fuse array, the fuse connected to the selected output module is retained, and the remaining fuses are all blown.
8. The method according to claim 7, characterized in that: The providing of the chip according to any one of claims 1 to 6 specifically comprises providing the chip according to claim 6; The production method further comprises the following steps: In the second fuse array and the third fuse array, the ground fuses corresponding to the reserved fuses are blown.
9. The manufacturing method according to claim 7, characterized in that: The production method further comprises: After the fuse is blown, the chip is packaged.
10. A single-gate logic chip, characterized in that: The single-gate logic chip is manufactured by the manufacturing method according to any one of claims 7 to 9.