A synchronous circuit for multiple phase-locked loop clock chips

Abstract

The invention discloses a multi-chip phase-locked loop clock chip synchronization circuit, belonging to the field of integrated circuits, comprising: D flip-flops DFF0-DFF17, inverters INV1-INV5, and an AND gate AND1; the invention controls the reset signals of an input frequency divider, a feedback frequency divider, and a frequency and phase detector of the phase-locked loop respectively through a received off-chip synchronization signal, and releases them in sequence, so that the phases of the multi-chip phase-locked loops are re-aligned to REF_CLK without causing the phase-locked loops to lose lock, thereby realizing the synchronization of the multi-chip clocks.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a multi-chip phase-locked loop clock chip synchronization circuit. Background Art

[0002] With the development of smart devices, the improvement of data accuracy and the surge in data volume, many protocols (JESD204B) have begun to support the transmission of multiple serial links while transmitting data on high-speed serial links. When multiple serial links are working at the same time, it is sometimes necessary to synchronize the data sent and received by the multiple links. At this time, it is necessary to synchronize multiple phase-locked loop clock chips that provide clock solutions for the links. Summary of the invention

[0003] The object of the present invention is to provide a multi-chip phase-locked loop clock chip synchronization circuit to solve the problems in the background technology.

[0004] In order to solve the above technical problems, the present invention provides a multi-chip phase-locked loop clock chip synchronization circuit, which controls the reset signal of the input frequency divider, feedback frequency divider, and frequency and phase detector in the phase-locked loop. The multi-chip phase-locked loop clock chip synchronization circuit includes: D flip-flops DFF0~DFF17, inverters INV1~INV5, and AND gate AND1;

[0005] The synchronization signal CHIP_SYNC is input to the clock terminal of the D flip-flop DFF0, the Q terminal of the D flip-flop DFF0 is connected to the D terminal of the D flip-flop DFF1, the Q terminal of the D flip-flop DFF1 is connected to the D terminal of the D flip-flop DFF2, the Q terminal of the D flip-flop DFF2 is connected to the D terminal of the D flip-flop DFF3, the Q terminal of the D flip-flop DFF3 is connected to the D terminal of the D flip-flop DFF4, the Q terminal of the D flip-flop DFF4 is connected to the D terminal of the D flip-flop DFF5, and the Q terminal of the D flip-flop DFF5 is connected to the D terminal of the D flip-flop DFF6;

[0006] The clock terminals of D flip-flops DFF1, D flip-flops DFF2, D flip-flops DFF3, D flip-flops DFF5 and D flip-flops DFF10 are connected to the reference clock REF_CLK, and the reference clock REF_CLK is connected to the clock terminals of D flip-flops DFF4 and D flip-flops DFF6 through inverter INV1; the Q terminal of D flip-flop DFF2 is connected to the clock terminals of D flip-flops DFF7, D flip-flops DFF8 and D flip-flops DFF9 respectively; the Q terminal of D flip-flop DFF4 is connected to the reset RN terminal of D flip-flop DFF7 through inverter INV3, the Q terminal of D flip-flop DFF5 is connected to the reset RN terminal of D flip-flop DFF8 through inverter INV4, and the Q terminal of D flip-flop DFF6 is connected to the reset RN terminal of D flip-flop DFF9 through inverter INV5;

[0007] The Q end of the D flip-flop DFF0 outputs a synchronous reset signal RESET_SYNC to the reset RN end of the D flip-flops DFF10 to DFF17, the clock end of the D flip-flop DFF11 is connected to the reference clock REF_CLK, the D end of the D flip-flop DFF11 is connected to its own non-Q end and the clock end of the D flip-flop DFF12, the D end of the D flip-flop DFF12 is connected to its own non-Q end and the clock end of the D flip-flop DFF13, the D end of the D flip-flop DFF13 is connected to its own non-Q end and the clock end of the D flip-flop DFF14, and the D end of the D flip-flop DFF14 is connected to the clock end of the D flip-flop DFF14. Connect its own non-Q end and the clock end of the D flip-flop DFF15, the D end of the D flip-flop DFF15 is connected to its own non-Q end and the clock end of the D flip-flop DFF16, the D end of the D flip-flop DFF16 is connected to its own non-Q end and the clock end of the D flip-flop DFF17, the Q end of the D flip-flop DFF16 and the Q end of the D flip-flop DFF17 are respectively connected to the two input ends of the AND gate AND1, the output end of the AND gate AND1 is connected to the D end of the D flip-flop DFF10, and the Q end of the D flip-flop DFF10 is connected to the reset RN end of the D flip-flop DFF0 through the inverter INV2;

[0008] The D ends of D flip-flop DFF0, D flip-flop DFF7, D flip-flop DFF8, and D flip-flop DFF9 are all connected to the high-level signal 1; the Q end of D flip-flop DFF7 outputs the reset signal RESET_RDIV of the input divider, the Q end of D flip-flop DFF8 outputs the reset signal RESET_NDIV of the feedback divider, and the Q end of D flip-flop DFF9 outputs the reset signal RESET_PFD of the frequency detector and phase detector.

[0009] In one implementation, when the synchronization signal CHIP_SYNC changes from 0 to 1, the output synchronization reset signal RESET_SYNC of the D flip-flop DFF0 changes from 0 to 1, and the D flip-flops DFF1, D flip-flops DFF2, D flip-flops DFF3, D flip-flops DFF4, D flip-flops DFF5, and D flip-flops DFF6 operate at the reference clock REF_CLK frequency and perform delay processing on the received synchronization reset signal RESET_SYNC in turn, wherein the D flip-flops DFF1, D flip-flops DFF2, D flip-flops DFF3, and D flip-flops DFF5 are delayed by one cycle respectively, and the D flip-flops DFF4 and D flip-flops DFF6 are delayed by half a cycle respectively;

[0010] D flip-flops DFF7, D flip-flops DFF8, and D flip-flops DFF9 receive the output signal RST_D2 of the D flip-flop DFF2. When RST_D2 changes from 0 to 1, the reset signal RESET_RDIV of the input frequency divider of the phase-locked loop is controlled to change from 0 to 1, the reset signal RESET_NDIV of the feedback frequency divider of the phase-locked loop is controlled to change from 0 to 1, and the reset signal RESET_PFD of the phase frequency detector of the phase-locked loop is controlled to change from 0 to 1;

[0011] When the output signal RST_D4 of the D flip-flop DFF4 changes from 0 to 1, RESET_RDIV changes from 1 to 0, releasing the reset signal of the input divider, and starting frequency division at the rising edge of the next reference clock REF_CLK; when the output signal RST_D5 of the D flip-flop DFF5 changes from 0 to 1, RESET_NDIV changes from 1 to 0, releasing the reset signal of the feedback divider, and starting frequency division at the rising edge of the next VCO clock; when the output signal RST_D6 of the D flip-flop DFF6 changes from 0 to 1, RESET_PFD changes from 1 to 0, releasing the reset signal of the frequency detector and phase detector, and the frequency detector and phase detector generates a phase difference signal based on the divided reference clock RCLK and the feedback clock NCLK.

[0012] In one embodiment, the D flip-flop DFF10, D flip-flop DFF11, D flip-flop DFF12, D flip-flop DFF13, D flip-flop DFF14, D flip-flop DFF15, D flip-flop DFF16, D flip-flop DFF17, and AND gate AND1 constitute a counter, which counts the input reference clock REF_CLK, generates a CLEAR_RESET signal when the counting cycle is reached, clears the synchronous reset signal RESET_SYNC, and waits for the next CHIP_SYNC signal.

[0013] The invention provides a multi-chip phase-locked loop clock chip synchronization circuit, which controls the reset signals of the input frequency divider, feedback frequency divider and phase frequency detector of the phase-locked loop respectively through the received off-chip synchronization signal, and releases them in sequence, so that the phases of the multi-chip phase-locked loops are re-aligned to REF_CLK without losing the lock, and the phase-locked loops will not lose the lock, so as to realize the synchronization of the multi-chip clock chips and ensure the correct operation of the multi-channel serial links. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the connection relationship between the synchronization circuit of multiple phase-locked loop clock chips and various modules of the phase-locked loop provided by the present invention.

[0015] Figure 2 The present invention provides a schematic diagram of a synchronous circuit structure of multiple phase-locked loop clock chips.

[0016] Figure 3The present invention provides a timing diagram of a synchronous circuit of multiple phase-locked loop clock chips. DETAILED DESCRIPTION

[0017] The following is a further detailed description of a multi-chip phase-locked loop clock chip synchronization circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0018] The present invention provides a multi-chip phase-locked loop clock chip synchronization circuit, which controls the reset signal RESET_RDIV of the input divider, the reset signal RESET_NDIV of the feedback divider, and the reset signal RESET_PFD of the phase frequency detector in the phase-locked loop. Figure 1 As shown, they are released in sequence, so that the phases of multiple phase-locked loops can be realigned to REF_CLK without losing lock, thereby achieving synchronization of multiple clock chips and ensuring the correct operation of multiple serial links.

[0019] The architecture of the multi-chip phase-locked loop clock chip synchronization circuit is as follows Figure 2 As shown, it includes D flip-flops DFF0~DFF17, inverters INV1~INV5, and an AND gate AND1; a synchronization signal CHIP_SYNC is input to the clock end of the D flip-flop DFF0, the Q end of the D flip-flop DFF0 is connected to the D end of the D flip-flop DFF1, the Q end of the D flip-flop DFF1 is connected to the D end of the D flip-flop DFF2, the Q end of the D flip-flop DFF2 is connected to the D end of the D flip-flop DFF3, the Q end of the D flip-flop DFF3 is connected to the D end of the D flip-flop DFF4, the Q end of the D flip-flop DFF4 is connected to the D end of the D flip-flop DFF5, and the Q end of the D flip-flop DFF5 is connected to the D end of the D flip-flop DFF6;

[0020] The clock terminals of D flip-flops DFF1, D flip-flops DFF2, D flip-flops DFF3, D flip-flops DFF5 and D flip-flops DFF10 are connected to the reference clock REF_CLK, and the reference clock REF_CLK is connected to the clock terminals of D flip-flops DFF4 and D flip-flops DFF6 through inverter INV1; the Q terminal of D flip-flop DFF2 is connected to the clock terminals of D flip-flops DFF7, D flip-flops DFF8 and D flip-flops DFF9 respectively; the Q terminal of D flip-flop DFF4 is connected to the reset RN terminal of D flip-flop DFF7 through inverter INV3, the Q terminal of D flip-flop DFF5 is connected to the reset RN terminal of D flip-flop DFF8 through inverter INV4, and the Q terminal of D flip-flop DFF6 is connected to the reset RN terminal of D flip-flop DFF9 through inverter INV5;

[0021] The Q end of the D flip-flop DFF0 outputs a synchronous reset signal RESET_SYNC to the reset RN end of the D flip-flops DFF10~DFF17, the clock end of the D flip-flop DFF11 is connected to the reference clock REF_CLK, the D end of the D flip-flop DFF11 is connected to its own non-Q end and the clock end of the D flip-flop DFF12, the D end of the D flip-flop DFF12 is connected to its own non-Q end and the clock end of the D flip-flop DFF13, the D end of the D flip-flop DFF13 is connected to its own non-Q end and the clock end of the D flip-flop DFF14, and the D end of the D flip-flop DFF14 is connected to its own non-Q end. And the clock end of the D flip-flop DFF15, the D end of the D flip-flop DFF15 is connected to its own non-Q end and the clock end of the D flip-flop DFF16, the D end of the D flip-flop DFF16 is connected to its own non-Q end and the clock end of the D flip-flop DFF17, the Q end of the D flip-flop DFF16 and the Q end of the D flip-flop DFF17 are respectively connected to the two input ends of the AND gate AND1, the output end of the AND gate AND1 is connected to the D end of the D flip-flop DFF10, and the Q end of the D flip-flop DFF10 is connected to the reset RN end of the D flip-flop DFF0 through the inverter INV2; the above reset RN end is valid at 0.

[0022] The D ends of D flip-flop DFF0, D flip-flop DFF7, D flip-flop DFF8, and D flip-flop DFF9 are all connected to the high-level signal 1; the Q end of D flip-flop DFF7 outputs a reset signal RESET_RDIV, the Q end of D flip-flop DFF8 outputs a reset signal RESET_NDIV, and the Q end of D flip-flop DFF9 outputs a reset signal RESET_PFD.

[0023] DFF0 receives the synchronization signal CHIP_SYNC from outside the chip. When the synchronization signal CHIP_SYNC changes from 0 to 1, the output synchronization reset signal RESET_SYNC of DFF0 will change from 0 to 1. DFF1, DFF2, DFF3, DFF4, DFF5, and DFF6 work at the frequency of the chip's input reference clock REF_CLK, and delay the received synchronization reset signal RESET_SYNC in turn. DFF1, DFF2, DFF3, and DFF5 are delayed by one cycle respectively, and DFF4 and DFF6 are delayed by half a cycle respectively. DFF7, DFF8, and DFF9 receive the output signal RST_D2 of DFF2. When RST_D2 changes from 0 to 1, the reset signal RESET_RDIV of the input divider of the phase-locked loop is controlled to change from 0 to 1, the reset signal RESET_NDIV of the feedback divider of the phase-locked loop is controlled to change from 0 to 1, and the reset signal RESET_PFD of the phase-locked loop frequency detector is controlled to change from 0 to 1. When the output signal RST_D4 of DFF4 changes from 0 to 1, RESET_RDIV changes from 1 to 0, the reset signal of the input divider is released, and the frequency division starts at the rising edge of the next reference clock REF_CLK. When the output signal RST_D5 of DFF5 changes from 0 to 1, RESET_NDIV changes from 1 to 0, the reset signal of the feedback divider is released, and the frequency division starts at the rising edge of the next VCO clock. When the output signal RST_D6 of DFF6 changes from 0 to 1, RESET_PFD changes from 1 to 0, the reset signal of the frequency detector is released, and the frequency detector generates a phase difference signal based on the reference clock RCLK and the feedback clock NCLK after the frequency division. The connection relationship diagram of each module is as follows: Figure 1 As shown, the timing diagram of the synchronous circuit is as follows Figure 3 DFF10, DFF11, DFF12, DFF13, DFF14, DFF15, DFF16, DFF17, and AND1 form a counter to count the input reference clock REF_CLK. When the counting cycle (96 cycles in this example) is reached, a CLEAR_RESET signal (0 to 1) is generated to clear RESET_SYNC and wait for the next CHIP_SYNC signal.

[0024] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A multi-chip phase-locked loop clock chip synchronization circuit, characterized in that: Control the reset signal of the input frequency divider, feedback frequency divider and frequency and phase detector in the phase-locked loop, and the multi-chip phase-locked loop clock chip synchronization circuit includes: D flip-flops DFF0~DFF17, inverters INV1~INV5, and AND gate AND1; The synchronization signal CHIP_SYNC is input to the clock terminal of the D flip-flop DFF0, the Q terminal of the D flip-flop DFF0 is connected to the D terminal of the D flip-flop DFF1, the Q terminal of the D flip-flop DFF1 is connected to the D terminal of the D flip-flop DFF2, the Q terminal of the D flip-flop DFF2 is connected to the D terminal of the D flip-flop DFF3, the Q terminal of the D flip-flop DFF3 is connected to the D terminal of the D flip-flop DFF4, the Q terminal of the D flip-flop DFF4 is connected to the D terminal of the D flip-flop DFF5, and the Q terminal of the D flip-flop DFF5 is connected to the D terminal of the D flip-flop DFF6; The clock terminals of D flip-flops DFF1, D flip-flops DFF2, D flip-flops DFF3, D flip-flops DFF5 and D flip-flops DFF10 are connected to the reference clock REF_CLK, and the reference clock REF_CLK is connected to the clock terminals of D flip-flops DFF4 and D flip-flops DFF6 through inverter INV1; the Q terminal of D flip-flop DFF2 is connected to the clock terminals of D flip-flops DFF7, D flip-flops DFF8 and D flip-flops DFF9 respectively; the Q terminal of D flip-flop DFF4 is connected to the reset RN terminal of D flip-flop DFF7 through inverter INV3, the Q terminal of D flip-flop DFF5 is connected to the reset RN terminal of D flip-flop DFF8 through inverter INV4, and the Q terminal of D flip-flop DFF6 is connected to the reset RN terminal of D flip-flop DFF9 through inverter INV5; The Q end of the D flip-flop DFF0 outputs a synchronous reset signal RESET_SYNC to the reset RN end of the D flip-flops DFF10 to DFF17, the clock end of the D flip-flop DFF11 is connected to the reference clock REF_CLK, the D end of the D flip-flop DFF11 is connected to its own non-Q end and the clock end of the D flip-flop DFF12, the D end of the D flip-flop DFF12 is connected to its own non-Q end and the clock end of the D flip-flop DFF13, the D end of the D flip-flop DFF13 is connected to its own non-Q end and the clock end of the D flip-flop DFF14, and the D end of the D flip-flop DFF14 is connected to the clock end of the D flip-flop DFF14. Connect its own non-Q end and the clock end of the D flip-flop DFF15, the D end of the D flip-flop DFF15 is connected to its own non-Q end and the clock end of the D flip-flop DFF16, the D end of the D flip-flop DFF16 is connected to its own non-Q end and the clock end of the D flip-flop DFF17, the Q end of the D flip-flop DFF16 and the Q end of the D flip-flop DFF17 are respectively connected to the two input ends of the AND gate AND1, the output end of the AND gate AND1 is connected to the D end of the D flip-flop DFF10, and the Q end of the D flip-flop DFF10 is connected to the reset RN end of the D flip-flop DFF0 through the inverter INV2; The D ends of D flip-flop DFF0, D flip-flop DFF7, D flip-flop DFF8, and D flip-flop DFF9 are all connected to the high-level signal 1; the Q end of D flip-flop DFF7 outputs the reset signal RESET_RDIV of the input divider, the Q end of D flip-flop DFF8 outputs the reset signal RESET_NDIV of the feedback divider, and the Q end of D flip-flop DFF9 outputs the reset signal RESET_PFD of the frequency detector and phase detector.

2. The multi-chip phase-locked loop clock chip synchronization circuit as claimed in claim 1, characterized in that: When the synchronization signal CHIP_SYNC changes from 0 to 1, the output synchronization reset signal RESET_SYNC of the D flip-flop DFF0 changes from 0 to 1, and the D flip-flops DFF1, D flip-flops DFF2, D flip-flops DFF3, D flip-flops DFF4, D flip-flops DFF5 and D flip-flops DFF6 work at the reference clock REF_CLK frequency and perform delay processing on the received synchronization reset signal RESET_SYNC in turn, wherein the D flip-flops DFF1, D flip-flops DFF2, D flip-flops DFF3 and D flip-flops DFF5 are delayed by one cycle respectively, and the D flip-flops DFF4 and D flip-flops DFF6 are delayed by half a cycle respectively; D flip-flops DFF7, D flip-flops DFF8, and D flip-flops DFF9 receive the output signal RST_D2 of the D flip-flop DFF2. When RST_D2 changes from 0 to 1, the reset signal RESET_RDIV of the input frequency divider of the phase-locked loop is controlled to change from 0 to 1, the reset signal RESET_NDIV of the feedback frequency divider of the phase-locked loop is controlled to change from 0 to 1, and the reset signal RESET_PFD of the phase frequency detector of the phase-locked loop is controlled to change from 0 to 1; When the output signal RST_D4 of the D flip-flop DFF4 changes from 0 to 1, RESET_RDIV changes from 1 to 0, releasing the reset signal of the input divider, and starting frequency division at the rising edge of the next reference clock REF_CLK; when the output signal RST_D5 of the D flip-flop DFF5 changes from 0 to 1, RESET_NDIV changes from 1 to 0, releasing the reset signal of the feedback divider, and starting frequency division at the rising edge of the next VCO clock; when the output signal RST_D6 of the D flip-flop DFF6 changes from 0 to 1, RESET_PFD changes from 1 to 0, releasing the reset signal of the frequency detector and phase detector, and the frequency detector and phase detector generates a phase difference signal based on the divided reference clock RCLK and the feedback clock NCLK.

3. The multi-chip phase-locked loop clock chip synchronization circuit as claimed in claim 2, characterized in that: The D flip-flop DFF10, D flip-flop DFF11, D flip-flop DFF12, D flip-flop DFF13, D flip-flop DFF14, D flip-flop DFF15, D flip-flop DFF16, D flip-flop DFF17 and AND gate AND1 constitute a counter, which counts the input reference clock REF_CLK, generates a CLEAR_RESET signal when the counting cycle is reached, clears the synchronous reset signal RESET_SYNC, and waits for the next CHIP_SYNC signal.

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