Continuous-time residual error amplifier analog-to-digital converter

Abstract

The application discloses a continuous-time residual amplification analog-digital converter, which is applied to the field of analog-digital converters and aims at the traditional residual amplification ADC. After the first-stage quantization is completed, a certain extra time is needed for the amplification of a residual signal and the second-stage sampling. In order to ensure the accuracy of the ADC, the establishment error of the residual amplifier must be attenuated to a low enough level in the time, which requires a long enough establishment time and a high enough amplifier bandwidth. The former will reduce the working speed of the ADC, and the latter will significantly increase the power consumption of the amplifier. The application provides a continuous-time residual amplification ADC without the need of the latter-stage sampling. Compared with the traditional residual amplification ADC, the latter stage of the application simultaneously performs the residual amplification and the latter-stage ADC quantization without sampling, so that the speed of the multi-stage ADC is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and in particular relates to an analog-to-digital converter. Background Art

[0002] Analog-to-Digital Converter (ADC) realizes the conversion of analog signals to digital signals. It is a key component of the interface between analog and digital systems and plays an important role in applications such as consumer electronics and industrial electronics.

[0003] The Successive Approximation Register (SAR) ADC has the characteristics of simple structure, low power consumption, and easy integration with other structures. The SAR ADC consists of only three parts: capacitor array, quantizer, and digital logic. Its working model is as follows: Figure 1 Ideally, the output of the SAR ADC is equal to the input signal, that is, D out =V in However, in practical applications, the performance of SAR ADC is affected by various non-ideal factors, such as noise, offset voltage, quantization error, etc. Considering these non-ideal factors, the formula is expressed as:

[0004] D out =V in +V os +V n +Q

[0005] Among them D out is the digital output signal, V in is the analog input signal, V os is the offset voltage, V n is the noise, and Q is the quantization error.

[0006] With the advancement of modern electronics, single-stage SAR ADCs are no longer able to meet the demands of modern high-speed, high-precision applications. Multistage ADC architectures retain the advantages of single-stage ADCs while achieving higher speed and precision. The interstage residual amplifier is the most crucial component of a multistage ADC. The multistage ADC's workflow is as follows: First, the input signal is quantized by the pre-stage ADC to produce a residual voltage; second, the interstage residual amplifier amplifies the residual voltage; then, the amplified signal is quantized by the post-stage ADC; finally, the quantization results from each ADC stage are aligned and recombined to produce the final quantization result.

[0007] "J.-C.Wang and T.-H.Kuo,"A 72-dB SNDR 130-MS / s 0.8-mW Pipelined-SARADC Using aDistributed Averaging Correlated Level Shifting Ring Amplifier,"inIEEE Journal of Solid-State Circuits, vol.57, no.12, pp.3794-3803, Dec.2022, doi:10.1109 / JSSC.2022.3196743.", "Y.Lim and MPFlynn, "A 1mW71.5dB SNDR 50MS / s13bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC,"inIEEE Journal of Solid-State Circuits, vol.50, no.12, pp.2901-2911, Dec.2015, doi:10.1109 / JSSC.2015.2463094.” The traditional residual amplification structure is used, and its working model is as follows. Figure 2 As shown, Figure 3 The workflow of the model is shown in Figure 2. The above two prior arts both use two-stage ADCs. Figure 2 Vres is the residual voltage obtained after quantization of Vin by ADC1 and amplification by the residual amplifier. ADC2 collects the amplified signal from the residual amplifier via switched capacitors and performs the next quantization step. Aligning and recombining the two quantization results yields the final quantization result.

[0008] For traditional residual amplifier ADCs, after the first stage of quantization is completed, additional time is required for the amplification of the residual signal and the second stage of sampling. To ensure the accuracy of the ADC, the residual amplifier's settling error must be attenuated to a sufficiently low level during this period. This requires a sufficiently long settling time and a sufficiently high amplifier bandwidth; the former reduces the ADC's operating speed, while the latter significantly increases the amplifier's power consumption. The residual amplifier settling error formula is:

[0009]

[0010] Where A is the gain of the residual amplifier, t is the amplification time, and τ is the time constant of the residual amplifier. This formula shows that when τ is constant (assuming t = 5τ), the settling error is reduced by 50%, but the settling time needs to increase by 14%. When t is constant (assuming t = 5τ), the settling error is reduced by 50%, but the time constant needs to be reduced by 12%, which means that the power consumption of the residual amplifier needs to increase by 14%. Summary of the Invention

[0011] This invention addresses traditional residual amplification ADCs and proposes a continuous-time residual amplification ADC that does not require post-stage sampling. Compared to traditional residual amplification ADCs, this invention performs residual amplification and post-stage ADC quantization simultaneously without post-stage sampling, significantly improving the speed of multi-stage ADCs.

[0012] One of the technical solutions adopted by the present invention is: a continuous-time residual amplification analog-to-digital converter, including: a first ADC, a second ADC, a first residual amplifier, and an alignment and recombination module; the input of the first ADC is Vin, the output of the first ADC serves as one of the inputs of the first residual amplifier, the other input of the first residual amplifier is a DC common-mode voltage, and the output of the residual amplifier serves as the input of the second ADC; the output of the first ADC and the output of the second ADC are input together into the alignment and recombination module to obtain the output of the analog-to-digital converter.

[0013] The first ADC includes: a first DAC (Digital to Analog Converter) unit, a first comparator, and a first digital logic unit. The input of the first DAC is the output of the first digital logic unit. The difference between Vin and the output of the first DAC serves as one input of the first comparator and the first residual amplifier. The other input of the first comparator and the first residual amplifier is a DC common-mode voltage. The output of the first comparator serves as the input of the first digital logic unit, and the output of the first digital logic unit also serves as an input of the alignment and reassembly unit.

[0014] The second ADC includes: a second DAC unit, a second comparator, and a second digital logic unit. The input of the second DAC is the output of the second digital logic unit. The result obtained by subtracting the output of the second DAC from the output of the residue amplifier serves as one input of the second comparator. The other input of the second comparator is a DC common-mode voltage. The output of the second comparator serves as the input of the second digital logic unit, and the output of the second digital logic unit also serves as another input of the alignment and reassembly unit.

[0015] The second technical solution adopted by the present invention is: a continuous-time residual amplification analog-to-digital converter, including: a third ADC, a fourth ADC, a second residual amplifier, and a second alignment and reorganization module; the first ADC includes two inputs, respectively denoted as Vin and Vip, the two outputs of the first ADC are respectively used as the two inputs of the second residual amplifier, and the two outputs of the second residual amplifier are respectively used as the two inputs of the second ADC; the output of the first ADC and the output of the second ADC are input together into the second alignment and reorganization module to obtain the output of the analog-to-digital converter.

[0016] The third ADC includes: a first DACn, a first DACp, a third comparator, and a third digital logic module; the input of the first DACn is the output of the third digital logic module, and the difference between Vin and the output of the first DACn serves as one input of the third comparator and the second residual amplifier; the input of the first DACp is the output of the third digital logic module, and the difference between Vip and the output of the first DACp serves as the other input of the third comparator and the second residual amplifier; the output of the third comparator serves as the input of the third digital logic module, and the output of the third digital logic module also serves as an input of the second alignment and reassembly module.

[0017] The fourth ADC includes: a second DACn, a second DACp, a fourth comparator, and a fourth digital logic module; the input of the second DACn is the output of the fourth digital logic module, and the difference between the output of the second DACn and the output of the second residue amplifier serves as one input of the fourth comparator; the input of the second DACp is the output of the fourth digital logic module, and the difference between the output of the second DACp and the output of the second residue amplifier serves as another input of the fourth comparator; the output of the fourth comparator serves as the input of the fourth digital logic module, and the output of the fourth digital logic module also serves as another input of the second alignment and reassembly module.

[0018] The present invention proposes a continuous-time residual amplification ADC (ADC). This architecture eliminates post-sampling and simultaneously performs residual signal amplification and post-quantization, addressing the limited operating speed and high amplifier power consumption of conventional residual amplification ADCs. Compared to conventional residual amplification structures, this technology inherently possesses greater potential for high-speed ADCs.

[0019] The present invention also provides specific examples of applying the continuous-time residual amplification ADC, namely, a continuous-time residual amplification ADC using a resistor network and a continuous-time residual amplification ADC using a capacitor network, both of which lack sampling switch capacitors. Both examples can be used with open-loop and closed-loop amplifiers. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is the schematic diagram of SAR ADC;

[0021] Figure 2 It is a two-stage traditional residual amplifier ADC (single-ended);

[0022] Figure 3 It is a two-stage traditional residual amplification ADC workflow;

[0023] Figure 4 The continuous time residual amplification ADC architecture proposed by the present invention;

[0024] Among them, (a) is a single-ended structure; (b) is a differential structure, and (c) is the workflow;

[0025] Figure 5 It is the ADC residual amplification and quantization process;

[0026] Figure 6 A continuous time residual amplification ADC using a resistor array;

[0027] Figure 7 A continuous time residual amplification ADC using a capacitor array;

[0028] Figure 8 The open-loop and closed-loop structures of the residual amplifier;

[0029] Among them, (a) is a closed-loop residual amplifier; (b) is an open-loop residual amplifier;

[0030] Figure 9 A comparison diagram of the workflow of the continuous-time residual amplification ADC proposed in the present invention and the traditional residual amplification ADC;

[0031] Among them, (a) is the traditional residual amplification ADC workflow; (b) is the continuous-time residual amplification ADC workflow. DETAILED DESCRIPTION

[0032] To facilitate those skilled in the art to understand the technical content of the present invention, the present invention is described in detail below with reference to the accompanying drawings:

[0033] This invention addresses traditional residual amplification ADCs and proposes a continuous-time residual amplification ADC (continuous-time modified residual amplification) that does not require post-stage sampling. Compared to traditional residual amplification ADCs, this invention performs residual amplification and post-stage ADC quantization simultaneously without post-stage sampling, significantly improving the speed of multi-stage ADCs.

[0034] The continuous time residual amplification ADC architecture proposed by the present invention is as follows Figure 4 As shown in the figure, the single-ended structure and the differential structure work on the same principle. Figure 4In the single-ended configuration shown in (a), the amplifier and comparator each have one input connected to the DC common-mode voltage; in the differential configuration, the amplifier and comparator inputs are connected to the positive and negative half-branch circuits, respectively. Figure 4 As shown in (b), the subscript n represents the DAC of the negative half branch, and the subscript p represents the DAC of the positive half branch. The specific workflow is as follows Figure 4 As shown in (c), in the present invention, Vres is the residual signal obtained after coarse quantization by the first stage ADC 1. The residual signal is amplified by the inter-stage residual amplifier, and the second stage ADC 2 quantizes the amplified signal.

[0035] The ADC residual amplification and quantization process is as follows Figure 5 As shown, conventional residual amplification requires the amplifier output signal to be fully established before the subsequent stage performs quantization; however, the present invention performs quantization simultaneously with the subsequent ADC when the residual amplification output signal is not fully established. Therefore, the present invention can save the time t3-t2.

[0036] While the operating time of each component of the present invention and a conventional residual amplification ADC is the same, the present invention requires no sampling time and the second-stage ADC quantization and residual amplification are performed simultaneously, resulting in a shorter time to complete a complete quantization. During the second-stage quantization process, quantization errors may occur due to the limited settling speed of the amplifier. Therefore, redundant bits are added in the second stage to increase the low-bit conversion range and correct quantization errors.

[0037] The present invention also proposes a specific implementation case of applying the continuous time residual amplification technology, such as Figure 6 Case 1 shown uses a continuous time error amplifier ADC with a resistor network as RDAC. Figure 7 Case 2 shown uses a continuous-time error amplifier ADC with a capacitor network as the CDAC.

[0038] like Figure 6 The continuous time difference amplifier ADC using a resistor network is shown as Figure 7 The continuous time residual amplifier ADC using a capacitor network is shown in the figure. In the specific implementation, the two are generally differential structures. The principles of single-ended and differential structures are the same. The implementation method of the differential structure is the same as Figure 4 (b) Similar. Figure 6 When the output signal of the amplifier changes, due to the existence of the series resistor, the input end of the comparator will show the same trend of change. At this time, after the comparison of the comparator, the code word is fed back to the DAC to offset the influence of the amplifier output signal on the input end of the comparator, thereby achieving quantization. Figure 7 In the embodiment, the capacitor network is used to realize quantization. Figure 8 open-loop and closed-loop amplifier structures. Figure 6 、 Figure 7 The DAC1 in the DAC can be arranged according to the specific design, IDAC\RDAC\CDAC are all acceptable.

[0039] Figure 2 、 Figure 4 、 Figure 6 、 Figure 7 The XOR symbol in the figure indicates the summation, and the negative sign of the DAC output means the difference between the input Vin or Vip and the DAC output.

[0040] The continuous time residual amplification ADC proposed in this invention has a comparative working process with the traditional residual amplification ADC. Figure 9 As shown. It can be seen that if the first-stage sampling time and the second-stage quantization time are the same, the present invention performs residual amplification and second-stage quantization simultaneously, eliminating the need for sampling time and significantly improving the ADC's operating speed. If the conversion time required to complete a full quantization is the same, the present invention extends the quantization time, i.e., the amplification time, significantly alleviating the challenge to the amplifier's bandwidth and thus significantly reducing the amplifier's power consumption. This invention only demonstrates a two-stage ADC using this structure, but the invention is equally applicable to multi-stage ADCs containing residual amplifiers.

[0041] Those skilled in the art will appreciate that the embodiments described herein are intended to aid the reader in understanding the principles of the present invention, and it should be understood that the scope of the present invention is not limited to such specific descriptions and embodiments. Various modifications and variations are readily apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are intended to be included within the scope of the claims.

Claims

1. A continuous-time residual amplification analog-to-digital converter, characterized in that: include: A first ADC, a second ADC, a first residual amplifier, and an alignment and recombination module; the first ADC input is Vin, the first ADC output serves as one input of the first residual amplifier, the other input of the first residual amplifier is a DC common-mode voltage, and the output of the residual amplifier serves as the input of the second ADC; the output of the first ADC and the output of the second ADC are input together into the alignment and recombination module to obtain the output of the analog-to-digital converter; The first ADC includes: a first DAC unit, a first comparator, and a first digital logic unit. The input of the first DAC is the output of the first digital logic unit. The difference between Vin and the output of the first DAC serves as one input of each of the first comparator and the first residual amplifier. The other input of each of the first comparator and the first residual amplifier is a DC common-mode voltage. The output of the first comparator serves as the input of the first digital logic unit, and the output of the first digital logic unit also serves as an input of the alignment and reassembly unit. The second ADC includes: a second DAC unit, a second comparator, and a second digital logic unit. The input of the second DAC is the output of the second digital logic unit. The result obtained by subtracting the output of the residual amplifier from the output of the second DAC serves as one input of the second comparator. The other input of the second comparator is a DC common-mode voltage. The output of the second comparator serves as the input of the second digital logic unit, and the output of the second digital logic unit also serves as another input of the alignment and reassembly unit.

2. The continuous-time residual amplification analog-to-digital converter according to claim 1, wherein: The second DAC unit adopts a resistor array and further includes a resistor connected in series between the first residual amplifier and the second DAC unit adopting the resistor array.

3. The continuous-time residual amplification analog-to-digital converter according to claim 1, wherein: The second DAC unit adopts a capacitor array and further includes a capacitor connected in series between the first residual amplifier and the second DAC unit adopting the capacitor array.

4. A continuous-time residual amplification analog-to-digital converter, characterized in that: include: A third ADC, a fourth ADC, a second residual amplifier, and a second alignment and reassembly module; the first ADC includes two inputs, denoted as Vin and Vip, the two outputs of the first ADC serve as the two inputs of the second residual amplifier, and the two outputs of the second residual amplifier serve as the two inputs of the second ADC; The output of the first ADC and the output of the second ADC are input into the second alignment and reassembly module to obtain the output of the analog-to-digital converter; The third ADC includes: a first DACn, a first DACp, a third comparator, and a third digital logic module; the input of the first DACn is the output of the third digital logic module, and the difference between Vin and the output of the first DACn serves as one input to each of the third comparator and the second residual amplifier; the input of the first DACp is the output of the third digital logic module, and the difference between Vip and the output of the first DACp serves as the other input to each of the third comparator and the second residual amplifier; the output of the third comparator serves as the input to the third digital logic module, and the output of the third digital logic module also serves as an input to the second alignment and reassembly module; The fourth ADC includes: a second DACn, a second DACp, a fourth comparator, and a fourth digital logic module; the input of the second DACn is the output of the fourth digital logic module, and the difference between the output of the second DACn and the output of the second residue amplifier serves as one input of the fourth comparator; the input of the second DACp is the output of the fourth digital logic module, and the difference between the output of the second DACp and the output of the second residue amplifier serves as another input of the fourth comparator; the output of the fourth comparator serves as the input of the fourth digital logic module, and the output of the fourth digital logic module also serves as another input of the second alignment and reassembly module.

5. The continuous-time residual amplification analog-to-digital converter according to claim 4, wherein: The second DACn and the second DACp use a resistor array and further include a resistor connected in series between the first residual amplifier and the second DACn using the resistor array, and a resistor connected in series between the first residual amplifier and the second DACp using the resistor array.

6. The continuous-time residual amplification analog-to-digital converter according to claim 4, characterized in that: The second DACn and the second DACp use a capacitor array and further include a capacitor connected in series between the first residual amplifier and the second DACn using the capacitor array, and a capacitor connected in series between the first residual amplifier and the second DACp using the capacitor array.

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