Message processing method and device for switch chip

Abstract

The invention provides a message processing method and device for a switch chip, and the method comprises the steps: dividing each module in the switch chip into a plurality of partitions, setting an independent survival time timer for each partition, and enabling the plurality of survival time timers to respond to the same enable signal for synchronous timing; when the ingress port of the switch chip receives a message, recording the ingress time of the message by using the survival time timer of the partition where the ingress port is located, and when the message enters other partitions, obtaining a current timestamp by using the survival time timer of the corresponding partition; determining message survival time according to the current timestamp and the entry time; and if the message survival time exceeds a preset threshold value, discarding the message in a timeout manner. According to the technical scheme, the stability and efficiency of the switching chip and the accuracy of data processing are improved.

Description

Technical Field

[0001] The present application belongs to the field of network transmission, and in particular, relates to a message processing method and device for a switching chip. Background Art

[0002] The timestamp function of data packets is widely used in chips. The timestamp function in network switching chips is used for traffic monitoring, delay measurement, fault diagnosis, QoS management, intrusion detection, event correlation and audit tracking to help identify abnormal behavior and attack patterns. Network interface controllers also have built-in timestamp functions to support precise time protocols or improve the performance monitoring capabilities of applications. In high-performance computing interconnect chips, timestamp functions are used for time synchronization and packet delay measurement, which is essential for maintaining efficient data transmission and task scheduling. Application-specific integrated circuits ASICs designed for network monitoring and data analysis use timestamps to accurately record the arrival and departure times of data packets for deep packet inspection, traffic analysis and compliance checks.

[0003] To implement the timestamp function in the chip, first of all, a unified and unbiased clock source is required to ensure that the clock information seen by each module of the entire chip is unified; secondly, a timing function module is required in each data processing module to calculate the time information of the packet entering and leaving the module; finally, the timestamp can be calculated through hardware solutions, where the time information is transmitted with the packet, and the actual time from the data packet entering the chip to leaving the chip can be calculated through hardware implementation or software methods.

[0004] Taking the InfiniBand IB network switch chip as an example, the performance of the network switch chip is mainly measured by its transmission bandwidth and transmission delay. Transmission bandwidth refers to the amount of data that the switch chip can process per second, usually expressed in bits per second (bps) or gigabits per second (Gbps). Transmission delay refers to the time it takes for a data packet to enter the switch chip and leave the switch chip, usually in microseconds or nanoseconds. High transmission bandwidth ensures that the switch chip can handle a large amount of data flow, while low transmission delay means that the data packet can pass through the switch chip quickly, thereby reducing network latency.

[0005] In network communications, congestion control is used to prevent network overload and maintain network stability. In a switch chip, if some data packets are delayed due to network congestion or a long transmission time in the switch chip, these data packets may be discarded. This mechanism prevents network resources from being occupied by outdated or invalid data packets, thereby ensuring subsequent bandwidth usage. For example, the IB protocol relies on the "Switch life time" mechanism to handle data packets that have been transmitted for too long in the switch chip. If the survival time of a data packet in the switch chip exceeds a certain threshold, the data packet will be discarded. Summary of the invention

[0006] The purpose of the present application is to provide a message processing method and device for a switching chip, aiming to realize a simple message survival time calculation and timeout discarding scheme.

[0007] According to a first aspect of the present application, a message processing method of a switching chip is provided, comprising:

[0008] Divide each module inside the switching chip into multiple partitions, set an independent survival time timer for each partition, and synchronize the multiple survival time timers in response to the same enable signal;

[0009] When the ingress port of the switching chip receives a message, the survival time timer of the partition where the ingress port is located is used to record the entry time of the message, and when the message enters other partitions, the survival time timer of the corresponding partition is used to obtain the current timestamp, and the survival time of the message is determined according to the current timestamp and the entry time;

[0010] If the message survival time exceeds a preset threshold, the message is discarded due to timeout.

[0011] In an optional implementation, the plurality of survival time timers are synchronized in response to the same enable signal, further comprising:

[0012] An enable signal is sent to multiple survival time timers simultaneously through a 1-bit enable bit in the chip center module, so that the multiple survival time timers are enabled at the same time, thereby achieving global precise synchronous timing.

[0013] In an optional implementation manner, after obtaining the current timestamp, the method further includes:

[0014] During the message transmission process, the timestamp information is stored in an unused field or a reserved field of the message, so that the timestamp information is transmitted synchronously with the message.

[0015] In an optional implementation manner, discarding the message due to timeout further includes:

[0016] For a message whose survival time exceeds a preset threshold, the message is discarded from both the read and write sides of the FIFO buffer.

[0017] In an optional implementation manner, discarding the message due to timeout further includes:

[0018] For a message whose survival time exceeds a preset threshold, first release the descriptor corresponding to the message, remove the descriptor from the linked list, then release the cache space occupied by the message, and return the cache space to the free list.

[0019] According to a second aspect of the present application, a message processing device of a switching chip is provided, including:

[0020] A synchronous timing unit, used to divide each module inside the switching chip into multiple partitions, set an independent survival time timer for each partition, and multiple survival time timers perform synchronous timing in response to the same enable signal;

[0021] A message tracking unit, configured to record the entry time of the message using the survival time timer of the partition where the entry port is located when the entry port of the switching chip receives the message, and to obtain the current timestamp using the survival time timer of the corresponding partition when the message enters other partitions, and determine the survival time of the message according to the current timestamp and the entry time;

[0022] The timeout discarding unit is used to discard the message when the survival time of the message exceeds a preset threshold.

[0023] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0024] The partition-synchronized Life Timer design reduces the risk of central routing and congestion in the switching chip while providing a simple and efficient global synchronization timing mechanism. This design not only optimizes physical implementation and resource utilization, but also improves the timing accuracy and reliability of the system, and meets the needs of high-performance network switching chips. While the implementation is simple and does not require each path module to accumulate and calculate the survival time, the useless VCRC field is used to transmit the timestamp along the path without adding additional routing and hardware overhead. In addition, the solution can easily implement delay statistics for each module and the entire chip, thereby providing strong support for system performance optimization and significantly improving the design efficiency, performance and maintainability of the switching chip. Through a simple and efficient discard implementation solution based on FIFO and linked list structures, the system can efficiently manage and discard messages that cannot be sent for a long time, ensuring the effective use of buffer resources. At the same time, it ensures that the system reduces the implementation cost and complexity while maintaining high performance, and enhances the stability and efficiency of the switching chip, ensuring the smooth transmission of subsequent messages.

[0025] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 It is a schematic diagram of a switching chip timing mechanism according to the related art.

[0028] Figure 2 It is a flowchart of a message processing method of a switching chip according to an exemplary embodiment of the present application.

[0029] Figure 3 is a schematic diagram of a timing mechanism according to an exemplary embodiment of the present application.

[0030] Figure 4 It is a schematic diagram of a partition synchronization timing structure according to an exemplary embodiment of the present application.

[0031] Figure 5 is a partition synchronization timing flow chart according to an exemplary embodiment of the present application.

[0032] Figure 6 It is a flow chart of calculating the message survival time according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] like Figure 1 As shown in the figure, the data packet enters the switching chip from port-m. Before the data enters the FIFO processing, a timestamp is added, and the timestamp information will be sent to the downstream switching scheduling module with the packet. The switching scheduling module also has its own timing module. When the data packet is scheduled to port-n, the latest timestamp will be added. After entering port-n and before the data packet is sent out from the chip, the total transmission time of the data packet in the chip is obtained according to the timestamp calculation module. This information can be used to solve network congestion or optimize network topology.

[0035] Therefore, the hardware implementation of the traditional solution faces significant challenges in terms of timing the survival time in the switching chip and timeout discarding for the entire transmission path of the message. With the increasing changes in the area, transmission bandwidth and chip frequency of the switching chip, the routing of the clock routing and timestamp information signal of the entire chip brought by the traditional solution poses great challenges to the implementation of the physical backend of the chip. In order to realize the survival time timing of the entire transmission path of the message, it is necessary to accumulate time in each switching chip and path module through which the message passes. This means that the message needs to record the time it has consumed at each switching node and continue to accumulate when it reaches the next node. This full-path time tracking mechanism is extremely complex because the message may pass through multiple switching chips and different modules, and each node needs to accurately record and update the time. On the other hand, in order to realize the above-mentioned full-path timing, it is necessary to maintain an independent timer for each message. In a high-performance network, millions of messages may be transmitted in the network at the same time. It is not feasible to assign a timer to each message in hardware because this will consume a lot of hardware resources (such as timer registers and logic units) and will significantly increase the complexity and cost of the switching chip. In hardware implementation, dynamically allocating and managing timers for each message is extremely challenging. The hardware logic needs to process high-speed data streams and complete the timer update and accumulation operations in a very short time. This not only increases the complexity of hardware design, but may also lead to performance bottlenecks and affect the overall performance of the switch chip.

[0036] In addition, cut-through switching is a high-performance message forwarding mode that allows the switch chip to start forwarding immediately after receiving the first few bytes of the message without waiting for the entire message to be received. Although this mode can significantly reduce transmission delays, it also brings many difficulties when designing a message discard mechanism:

[0037] 1) Challenges of early forwarding: In cut-through mode, the message is forwarded before it is fully received. Therefore, if it is found that the message needs to be discarded (for example, due to congestion or error) before the message is fully received, the switch chip must take action immediately. However, at this time, the message may have been partially forwarded to the next node, making the discard operation complicated.

[0038] 2) Error detection delay: Since the cut-through mode starts forwarding before the message is fully received, error detection (such as checksum error, format error, etc.) may be delayed until the second half of the message is received. In this case, the partially forwarded message needs to be recycled or notified to the next node to be discarded, which increases the complexity of the discard mechanism.

[0039] 3) Resource management: In cut-through mode, the switch chip needs to effectively manage its buffer resources. If a message is determined to be discarded after being partially received, the chip must ensure that the allocated buffer resources can be recovered in time and will not affect other messages being processed. This resource management requires sophisticated control logic and fast response capabilities.

[0040] 4) Flow control and congestion handling: The cut-through mode requires the switch chip to make forwarding decisions in a very short time and handle flow control and congestion. If congestion occurs in the network, the switch chip needs to respond quickly and discard some messages. However, since the message may have been partially forwarded, how to effectively perform the discard operation and notify the relevant nodes is a complex problem.

[0041] In summary, both timing the survival time of the entire message transmission path and designing a message discard mechanism in cut-through mode face significant technical challenges.

[0042] Based on the above analysis, the present application proposes a message processing method and device for a switching chip, which systematically solves the difficulties in timing the survival time of the entire transmission path of the message and the complex design of the message discard mechanism in the Cut-through mode through partition implementation, a global synchronous timing survival timer (Life Timer) and a timestamp-based survival time calculation and survival timeout message discarding function, thereby improving the stability, efficiency and data processing accuracy of the switching chip.

[0043] In order to solve the timing problem of the survival time in the switching chip of the entire transmission path of the message, a Life Timer mechanism with partition implementation and global synchronous timing is adopted. In the partition implementation, the switching chip divides the network into multiple independent areas, and the timer in each area runs independently, avoiding the hardware implementation difficulty of maintaining a timer for each message separately. At the same time, through the global synchronous timing mechanism, the timing between the partitions remains consistent, ensuring that the survival time of the message on the entire transmission path can be accurately calculated. In this way, the system can effectively determine whether the message has timed out, thereby achieving the discard of the message timeout. Partitioning is based on the distance of the internal modules of the chip in physical distribution. The partitioning scheme can reduce the internal direction of the chip and the consumption of hardware resources. The global synchronous timing ensures that the clock module of each partition will not have a large error due to the different physical routing and physical implementation positions of the chip.

[0044] In view of the difficulty in designing a message discarding mechanism in the cut-through mode, this application proposes a survival time calculation and survival timeout message discarding mechanism based on timestamp. When the message enters the switching chip, the system embeds a timestamp for each message to record its generation time. By reading and comparing the timestamp, the survival time of the message on the transmission path is calculated in real time. When the survival time of the message exceeds the preset threshold, the automatic discarding mechanism is triggered to discard the timeout message, ensuring the timeliness of message processing and the effective use of system resources.

[0045] See also Figure 2 , illustratively, the message processing method of the switching chip provided in the present application includes:

[0046] Step 201: Divide each module inside the switching chip into multiple partitions, set an independent survival time timer for each partition, and synchronize timing of multiple survival time timers in response to the same enable signal.

[0047] In order to achieve more accurate timing, the delay of each path must be consistent, which requires complex path beats to adjust. This path difference and adjustment requirements increase the complexity of system design and implementation, and restrict the improvement of overall performance and accuracy. Figure 3 As shown, the present application sets a Life Timer independently in each partition. The configuration parameters (such as time accuracy, etc.) of each Life Timer can be configured independently, but by placing a 1-bit enable bit in the chip center module, it can be ensured that each partition starts synchronous timing at the same time, thereby achieving global precise synchronous timing. Specifically, the chip center module can be a chip top_crg module to reduce the line delay deviation of the global_ctrl control signal sent to each partition.

[0048] Since each partition has its own Life Timer, the problem of different path lengths from the central timer to each port is eliminated, and complex path beat adjustments are no longer required, thus simplifying system design and improving timing accuracy and reliability. Figure 4 .

[0049] The partition division method mainly depends on the chip backend implementation. For example, physically adjacent ports are used as a partition to reduce routing and path delays, ensure the timer synchronization of the partition, and reduce errors.

[0050] For example, the Life Timer configuration process is as follows: Figure 5 First, configure the Life Timer parameters of each partition, and then enable multiple Life Timers at the same time to start synchronous timing at the same time.

[0051] Step 202: When the ingress port of the switching chip receives a message, the survival time timer of the partition where the ingress port is located is used to record the entry time of the message, and when the message enters other partitions, the survival time timer of the corresponding partition is used to obtain the current timestamp, and the message survival time is determined based on the current timestamp and the entry time.

[0052] When a message enters the system, it needs to be timestamped, which is recorded as T_stamp_in. Specifically, multiple marking methods can be used.

[0053] In a preferred embodiment, a signal may be added during the message transmission process to carry the timestamp information, which ensures that the timestamp can be transmitted synchronously with the message, making it easier for subsequent processing modules to read and use it.

[0054] In another preferred embodiment, the timestamp information may be stored in an unused field or a reserved field of the message. The unused field may be, for example, a variable cyclic redundancy check (VCRC) field that is useless when transmitting across switching chips. This method utilizes the redundant space in the message, does not increase the additional transmission burden, and ensures that the timestamp information can be transmitted along with the message.

[0055] The packet survival time is calculated as the difference between the current timestamp and the ingress time:

[0056] switch_life_time=T_stamp_cur-T_stamp_in

[0057] For example, the packet survival time calculation diagram is as follows: Figure 6 Based on the timestamp, the performance evaluation of each module transmission delay, chip transmission delay, and message survival time can be accurately completed, and the statistics of mean, maximum, and minimum delay can be completed.

[0058] Step 203: If the message survival time exceeds a preset threshold, the message is discarded due to timeout.

[0059] There are two ways to implement packet discard:

[0060] 1) For timed messages, they are discarded from both the read and write sides of the FIFO Buffer. This means that the message will no longer be read for subsequent processing and will not occupy write space. In this way, the buffer space can be rolled back and reused.

[0061] 2) For timed messages, first release the corresponding descriptor and remove it from the linked list. Then release the buffer space occupied by the message and return it to the idle list. This method ensures efficient recovery and reuse of memory resources.

[0062] The internal data flow modes of the network chip are divided into two types: cut-through and store_forward:

[0063] Cut-through data transmission mode: The internal module of the chip can send data packets to the downstream module without receiving the complete data packet, and the data transmission delay within the chip is small;

[0064] store_forward data transmission mode: a complete data packet must be received before sending the data packet downstream;

[0065] In cut-through mode, it is recommended to put the timestamp of the message in the packet header. When the entry detection times out, it can be discarded at the ingress as quickly as possible to avoid the complex scenario where part of the packet has been sent to the downstream module.

[0066] In store-forward mode, the timestamp of the message can be placed anywhere in the data. When a timeout is detected, the data packet is still completely stored in the buffer, so the entire packet can be easily discarded.

[0067] It can be seen that the message processing method of the switching chip proposed in this application has at least the following advantages compared with the related art: the Life Timer design of partition synchronization is adopted to reduce the risk of central wiring and congestion of the switching chip while providing a simple and efficient global synchronization timing mechanism. This design not only optimizes the physical implementation and resource utilization, but also improves the timing accuracy and reliability of the system, and adapts to the needs of high-performance network switching chips. While the implementation is simple and there is no need for each path module to accumulate and calculate the survival time, the useless VCRC field is used to transmit the timestamp along the path without adding additional wiring and hardware overhead. In addition, the scheme can conveniently implement the delay statistics of each module and the whole chip, thereby providing strong support for system performance optimization and significantly improving the design efficiency, performance and maintainability of the switching chip. Through a simple and efficient discarding implementation scheme based on FIFO and linked list structure, the system can efficiently manage and discard messages that cannot be sent for a long time, ensuring the effective use of Buffer resources. At the same time, it ensures that the system reduces the implementation cost and complexity while maintaining high performance, and enhances the stability and efficiency of the switching chip, ensuring the smooth transmission of subsequent messages.

[0068] Accordingly, illustratively, the present application provides a message processing device of a switching chip in a second aspect, including:

[0069] A synchronous timing unit, used to divide each module inside the switching chip into multiple partitions, set an independent survival time timer for each partition, and multiple survival time timers perform synchronous timing in response to the same enable signal;

[0070] A message tracking unit, configured to record the entry time of the message using the survival time timer of the partition where the entry port is located when the entry port of the switching chip receives the message, and to obtain the current timestamp using the survival time timer of the corresponding partition when the message enters other partitions, and determine the survival time of the message according to the current timestamp and the entry time;

[0071] The timeout discarding unit is used to discard the message when the survival time of the message exceeds a preset threshold.

[0072] The above-mentioned device can be implemented by the message processing method of the switching chip provided by the embodiment of the first aspect above. The specific implementation method can refer to the description in the embodiment of the first aspect, which will not be repeated here.

[0073] It is understood that the structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily think of combinations and adjustments to the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present application to the specific details of the above examples.

[0074] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A message processing method for a switching chip, characterized in that: include: Divide each module inside the switching chip into multiple partitions, set an independent survival time timer for each partition, and synchronize the multiple survival time timers in response to the same enable signal; When the ingress port of the switching chip receives a message, the survival time timer of the partition where the ingress port is located is used to record the entry time of the message, and when the message enters other partitions, the survival time timer of the corresponding partition is used to obtain the current timestamp, and the survival time of the message is determined according to the current timestamp and the entry time; If the message survival time exceeds a preset threshold, the message is discarded due to timeout.

2. The message processing method of the switching chip according to claim 1, characterized in that: The multiple survival time timers are synchronized in response to the same enable signal, further comprising: An enable signal is sent to multiple survival time timers simultaneously through a 1-bit enable bit in the chip center module, so that the multiple survival time timers are enabled at the same time, thereby achieving global precise synchronous timing.

3. The message processing method of the switching chip according to claim 1, characterized in that: After obtaining the current timestamp, the method further includes: During the message transmission process, the timestamp information is stored in an unused field or a reserved field of the message, so that the timestamp information is transmitted synchronously with the message.

4. The message processing method of the switching chip according to claim 1, characterized in that: The step of discarding the message due to timeout further comprises: For a message whose survival time exceeds a preset threshold, the message is discarded from both the read and write sides of the FIFO buffer.

5. The message processing method of the switching chip according to claim 1, characterized in that: The step of discarding the message due to timeout further comprises: For a message whose survival time exceeds a preset threshold, first release the descriptor corresponding to the message, remove the descriptor from the linked list, then release the cache space occupied by the message, and return the cache space to the free list.

6. A message processing device for a switching chip, characterized in that: include: A synchronous timing unit, used to divide each module inside the switching chip into multiple partitions, set an independent survival time timer for each partition, and multiple survival time timers perform synchronous timing in response to the same enable signal; A message tracking unit, configured to record the entry time of the message using the survival time timer of the partition where the entry port is located when the entry port of the switching chip receives the message, and to obtain the current timestamp using the survival time timer of the corresponding partition when the message enters other partitions, and determine the survival time of the message according to the current timestamp and the entry time; The timeout discarding unit is used to discard the message when the survival time of the message exceeds a preset threshold.

7. The message processing device of the switching chip according to claim 6, characterized in that: The synchronous timing unit is further used for: An enable signal is sent to multiple survival time timers simultaneously through a 1-bit enable bit in the chip center module, so that the multiple survival time timers are enabled at the same time, thereby achieving global precise synchronous timing.

8. The message processing device of the switching chip according to claim 6, characterized in that: The message tracking unit is further used to: after obtaining the current timestamp, store the timestamp information in an unused field or a reserved field of the message during the message transmission process, so as to transmit the timestamp information synchronously with the message.

9. The message processing device of the switching chip according to claim 6, characterized in that: The timeout discarding unit is further used for: For a message whose survival time exceeds a preset threshold, the message is discarded from both the read and write sides of the FIFO buffer.

10. The message processing device of the switching chip according to claim 6, characterized in that: The timeout discarding unit is further used for: For a message whose survival time exceeds a preset threshold, first release the descriptor corresponding to the message, remove the descriptor from the linked list, then release the cache space occupied by the message, and return the cache space to the free list.

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