Video coding and decoding performance analysis device, method, equipment and medium

Abstract

The invention discloses a video coding and decoding performance analysis device, method and equipment and a medium, belongs to the field of data processing, provides a real-time performance evaluation function, can analyze video coding and decoding performance in real time and report real-time performance analysis to a central processing unit, and the central processing unit performs optimization adjustment according to real-time data so as to realize real-time performance evaluation. Therefore, high-quality performance is kept in different video coding and decoding scenes; the performance analysis device is an independent module and optimizes a video coding and decoding algorithm on the hardware level. Through targeted hardware design and implementation, the video coding and decoding efficiency and speed can be improved, and better performance can be obtained. The method can adapt to continuously evolved video coding and decoding standards and application requirements, and provides support for future technical development.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of data processing, and specifically to a video encoding and decoding performance analysis device, method, equipment and medium. Background Art

[0002] Nowadays, video coding and decoding technology has made significant progress. From traditional standard-based compression algorithms (such as H.264, H.265, etc.) to modern efficient coding and decoding technologies (such as AV1, VP9, ​​etc.), video coding and decoding standards are constantly updated and iterated to provide better compression rates and visual quality.

[0003] At the same time, integrated circuit technology plays a vital role in the field of information processing. The continuous development of integrated circuits makes it possible to integrate more computing and processing capabilities on chips, which provides new opportunities for improving video codec performance. Innovations in integrated circuit design can optimize video codec algorithms at the hardware level, improve processing speed and energy efficiency, and adapt to different application scenarios and needs.

[0004] However, with the improvement of video resolution, the diversification of multimedia applications and the changes in network transmission, video coding and decoding technology faces new challenges and requires more in-depth performance analysis and optimization.

[0005] However, there are still some limitations in the current video codec performance analysis methods: the current performance analysis tools are in seconds (s), which can only analyze performance over a long period of time and cannot accurately know the real-time video processing performance. In addition, different performance analysis modules need to be developed for different video codec formats, which is inconvenient to use. As a result, the existing performance analysis tools cannot comprehensively and accurately evaluate the performance of different video codec algorithms on different hardware platforms. Summary of the invention

[0006] The object of the present invention is to provide a video coding performance analysis device, method, equipment and medium, so as to at least partially solve the above-mentioned problems.

[0007] According to one aspect of the present invention, a video encoding and decoding performance analysis device is provided, comprising: A video codec working status monitoring unit is used to monitor the video codec working status in real time; The video codec performance monitoring unit is used to count the number of times the video codec request signal and response signal are initiated at each rising edge of the video codec working clock, and to obtain the delay information between each request and response; A delay information sending unit, used for sending the delay information to a central processing unit; The performance analysis device is coupled to the central processing unit and the video encoding and decoding module respectively.

[0008] In some embodiments, the device further includes: the real-time monitoring of the video codec working state is specifically to monitor in real time each rising edge of the working clock to collect the working state signal value; The working status includes idle, working or waiting.

[0009] In some embodiments, the device further comprises a time configuration unit, coupled to the central processor and the analysis device respectively, The time configuration unit and the analysis device are respectively configured with a first variable and a second variable, and the value ranges of the first variable and the second variable are natural numbers. The working state signal value is collected at each rising edge of the working clock, and when the working state signal value indicates that the working state is in progress, the second variable value is set to 0; When the working status signal value indicates an idle state or a waiting state, the second variable value is increased by 1 and compared with the first variable value. If the second variable value is less than or equal to the first variable value, the working status continues to be monitored; if the second variable value is greater than the first variable value, the performance analysis device uploads the information to the central processing unit, and the central processing unit controls the reduction of the working frequency of the video codec.

[0010] In some embodiments, the device also includes the central processing unit configuring the value of the first variable, the performance analysis device counting the number of times each request signal and response signal of the working clock rising edge is initiated, and at the same time, when the value of the first variable is reduced by 1 until it reaches 0, the performance analysis device calculates the average bandwidth and average delay information of the video encoding and decoding during this period of time, and reports it to the central processing unit.

[0011] According to another aspect of the present invention, a video encoding and decoding performance analysis method is provided, comprising: The method is implemented based on the above device. Start the performance analysis device to monitor the working status of video encoding and decoding. At each rising edge of the video codec working clock, the number of times the video codec request signal and response signal are initiated is counted, and the delay information between each request and response is obtained. And send the delay information to the central processing unit.

[0012] In some embodiments, the real-time monitoring of the video codec working state is specifically to monitor in real time each rising edge of the working clock to collect the working state signal value; The working status includes idle, working or waiting.

[0013] In some embodiments, the working state signal value is collected at each rising edge of the working clock, and when the working state signal value indicates that the working state is in progress, the second variable value is set to 0; When the working status signal value indicates an idle state or a waiting state, the second variable value is increased by 1 and compared with the first variable value. If the second variable value is less than or equal to the first variable value, the working status continues to be monitored; if the second variable value is greater than the first variable value, the performance analysis device uploads the information to the central processing unit, and the central processing unit controls the reduction of the working frequency of the video codec.

[0014] In some embodiments, the central processing unit configures the value of the first variable, and the performance analysis device counts the number of times each request signal and response signal of the working clock rising edge is initiated. At the same time, when the value of the first variable is reduced by 1 until it reaches 0, the performance analysis device calculates the average bandwidth and average delay information of the video encoding and decoding during this period of time, and reports it to the central processing unit.

[0015] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the steps in the method of any of the above embodiments by calling the computer program stored in the memory.

[0016] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program executes the steps in any of the above method embodiments when executed by a processor.

[0017] The present invention realizes a video codec performance analysis device, provides a real-time performance evaluation function, can analyze the video codec performance in real time, and report the real-time performance analysis to the central processing unit, and the central processing unit optimizes and adjusts according to the real-time data, so as to maintain high-quality performance in different video codec scenarios; the performance analysis device is an independent module, which optimizes the video codec algorithm at the hardware level. Through targeted hardware design and implementation, the efficiency and speed of video codec can be improved, so as to obtain better performance. It can adapt to the evolving video codec standards and application requirements, and provide support for future technological development.

[0018] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A schematic diagram of a video encoding and decoding performance analysis device provided in an embodiment of the present application.

[0020] Figure 2 A schematic diagram of a video encoding and decoding performance analysis method provided in an embodiment of the present application.

[0021] Figure 3 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The specific embodiments of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] It should be noted that, in the description of the present invention, the directions or positional relationships indicated by the terms "up", "down", "left", "right", "front", "back", etc. are descriptions of the structure of the present invention based on the accompanying drawings, and are only for the convenience of describing the present invention, and do not indicate or imply that the referred system or element must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0024] The "first" and "second" in this technical solution are only used to distinguish the names of the same or similar structures, or corresponding structures with similar functions, and are not an arrangement of the importance of these structures, nor do they have a ranking, comparison of size, or other meanings.

[0025] In addition, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be a connection between the two structures. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood based on the overall idea of ​​the present invention and the specific context of the present solution.

[0026] The first aspect of the present invention discloses a video encoding and decoding performance analysis device, such as Figure 1 FIG. 1 is a schematic diagram of a video coding performance analysis device according to an embodiment of the present invention. Figure 1 As shown, the analysis device comprises: A video codec working status monitoring unit is used to monitor the video codec working status in real time; The video codec performance monitoring unit is used to count the number of times the video codec request signal and response signal are initiated at each rising edge of the video codec working clock, and to obtain the delay information between each request and response; A delay information sending unit, used for sending the delay information to a central processing unit; The analysis device is coupled to the central processing unit and the video encoding and decoding unit respectively.

[0027] In some embodiments, the performance analysis unit corresponds to signal A connected to the working state signal in the video codec module, and there are three working states: idle, working, and waiting; The performance analysis unit corresponds to signal B connected to the video codec working clock, and the clock frequency can reach more than 1GHz, that is, nanosecond (ns) level; The performance analysis unit corresponds to the signal C connected to the request signal in the video encoding and decoding module; The performance analysis unit corresponds to the signal D connected to the response signal in the video encoding and decoding module; The performance analysis unit is connected to a central processing unit (CPU) corresponding to the signal E to receive the signal.

[0028] In some embodiments, when monitoring the working status of the video codec, the performance analysis device monitors each clock rising edge (B signal) in real time, collects the A signal value and records it, and reports the working status of the video codec module to the central processor through the performance analysis module (signal E), and the central processor can grasp the working status of the video codec module. The central processor is the brain of the chip. It executes instructions, processes data and controls the operation of the chip. It is a vital component of the chip. The video codec module is an important component in the chip, which is responsible for encoding (compressing) and decoding (decompressing) video data, so as to effectively process the video stream when storing, transmitting and playing videos, so that video data can be efficiently transmitted, stored and played on different platforms and applications while maintaining appropriate quality.

[0029] In some embodiments, when monitoring real-time video codec performance, the performance analysis device starts working, counting the number of times the video codec request signal (signal C) and response signal (signal D) are initiated at each rising edge of the video codec working clock (signal B), and counting the delay between each request and response.

[0030] The embodiment of the present invention can analyze the performance of different codec formats. According to experimental tests, the JPEG format codec performance read bandwidth reaches 5.5Gbps, the average delay is 5.5ns, the HEVC format encoding performance read bandwidth reaches 12.4Gbps, the average delay is 45ns, and the H264 format encoding performance read bandwidth reaches 11.8Gbps, the average delay is 2.5ns.

[0031] The test reports real-time data to the central processing unit through the performance analysis module (signal E), and the central processing unit can grasp the performance of the video codec module in real-time processing of data.

[0032] In some embodiments, the performance analysis device can also cooperate with a time configuration module to reduce CPU power consumption. The time configuration unit is coupled to the central processor and the analysis device respectively. The time configuration module receives information from the central processor and configures time variables, and cooperates with the performance analysis device to jointly complete the monitoring and analysis of the video codec module.

[0033] The time configuration unit and the analysis device are respectively configured with a first variable and a second variable, and the value ranges of the first variable and the second variable are natural numbers. The working state signal value is collected at each rising edge of the working clock. When the working state signal value indicates that the device is in working state, the value of the second variable is set to 0. When the working state signal value indicates an idle state or a waiting state, the second variable value is increased by 1 and compared with the first variable value. If the second variable value is less than or equal to the first variable value, the working state continues to be monitored; if the second variable value is greater than the first variable value, the performance analysis device uploads the information to the central processor, and the central processor controls to reduce the working frequency of the video codec, thereby reducing power consumption. In some embodiments, the performance analysis device can also cooperate with the time configuration module to analyze the average performance of video encoding and decoding over a period of time. The central processing unit configures the value of the first variable, and the performance analysis device counts the number of times each of the rising edge request signals and response signals of the working clock is initiated. At the same time, when the value of the first variable is reduced by 1 until it reaches 0, the performance analysis device calculates the average bandwidth and average delay information of the video encoding and decoding during this period of time, and reports it to the central processing unit. The time configuration unit corresponds to the signal F connected to the central processing unit time configuration register, such as configuring the monitoring video codec module to enter the frequency reduction time, configuring the time statistics video codec average performance, so as to achieve less power consumption during the video codec idle or waiting period, and analyze the average performance of the video codec within a period of time, thereby improving the accuracy of performance analysis.

[0034] The second aspect of the present invention discloses a method for analyzing video encoding and decoding performance. Figure 2 As shown, the method includes: Step S1, start the performance analysis device to monitor the video codec working status, Step S2: Count the number of times the video codec request signal and response signal are initiated at each rising edge of the video codec working clock, and obtain the delay information between each request and response. Step S3, and sending the delay information to the central processing unit.

[0035] The method of the present invention is described in detail below with reference to specific examples.

[0036] Example 1: The central processing unit assigns the video codec module to encode a frame of data. The steps are as follows: The CPU issues instructions, configures the corresponding registers and starts the video codec module. The video codec module parses the instructions, then reads data from the corresponding memory to start encoding processing. At the same time, the performance analysis module is started to monitor the video codec module. The video codec module will jump between working states. In the idle phase, it will receive the CPU configuration register instruction, and then change from the idle state to the working state to start data encoding processing. When a frame of data encoding processing is completed, it will jump from the working state to the waiting state. The performance analysis module monitors the working state of the video codec and reports it to the CPU, so that the CPU can grasp the real-time working state of the video codec module.

[0037] In some embodiments, the central processor can grasp the working performance of the video codec within a period of time. When the video codec module is working, the central processor issues instructions, configures the time variables in the time configuration module, and cooperates with the performance analysis device to count the number of times the request signal and the response signal are initiated at each clock rising edge within a period of time, and count the delay between each request and response. The performance analysis module calculates the average bandwidth and average delay within a period of time and reports the information to the central processor.

[0038] The CPU can grasp the real-time working performance of the video codec. When the video codec module is working, the CPU sends instructions to configure the performance analysis module, counts the number of request signals and response signals at each rising edge of the clock, and reports the information to the CPU after analysis. The CPU knows that the video codec module has processed a frame of data, and sends instructions to configure the corresponding registers to tell the video codec module that there is no new data to process, and the video codec module changes from waiting to idle state.

[0039] Example 2: The central processing unit assigns the video codec module to encode two frames of data. The steps are as follows: The CPU issues instructions to start the video codec module to encode the first frame of data, and at the same time starts the performance analysis module to monitor the working status of the video codec module. The video codec module completes the encoding of the first frame of data and jumps from the working state to the waiting state. The performance analysis module monitors the working state of the video codec at each rising edge of the clock, and reports to the central processor when it detects that the video codec enters the waiting state. The central processor knows that the video codec module has completed the encoding of one frame of data, and sends a new instruction configuration register to let the video codec module enter the second frame of data encoding.

[0040] The video codec module parses the instruction, changes from the waiting state to the working state, reads data from the corresponding memory according to the instruction requirements, and performs encoding processing on the second frame of data. The performance analysis module continues to monitor the video codec module.

[0041] After the second frame of data is encoded and processed, the video codec changes from working state to waiting state. The performance analysis module monitors the working state of the video codec module at each rising edge of the clock, and reports to the central processor when it detects that the working state changes to waiting. The central processor knows that the video codec module has processed the second frame of data, and sends instructions to configure the corresponding registers, notifying the video codec module that there is no new data to process, and the video codec module changes from waiting to idle state.

[0042] Example 3: The CPU controls the video codec module to enter a frequency reduction state to reduce power consumption. The steps are as follows: The central processing unit writes initial values ​​to the time variables in the time configuration module and issues instructions to start the video encoding and decoding module to start working.

[0043] The video codec module parses the instruction and starts to read data from the memory for encoding. At the same time, the working state changes from the idle state to the working state. At the same time, the performance analysis module monitors the working state of the video codec module at each rising edge of the clock. At this time, the video codec module is in the working state. When the performance analysis module detects that the video codec is in the working state at each rising edge of the clock, the time variable value in the performance analysis device is written to 0. At this time, the time variable value in the performance analysis device is <= the time variable value in the time configuration module, and monitoring continues.

[0044] After the video codec module completes encoding of a frame of data, it changes from working state to waiting state. When the central processor does not issue instructions, the video codec will remain in the waiting state. At this time, the performance analysis device detects the waiting state at each rising edge of the clock, and the time variable value in the performance analysis device is increased by 1 and compared with the time variable value in the time configuration module. If the time variable value in the performance analysis device is < the time variable value in the time configuration module, continue monitoring; if the time variable value in the performance analysis device is > the time variable value in the time configuration module, it means that the video codec has not worked for a sufficiently long time, and the performance analysis device uploads the information to the central processor. The central processor issues a command to reduce the clock frequency of the video codec module to reduce power consumption.

[0045] When the CPU has new data that needs to be processed by the video codec module, it issues a command to restore the video codec module clock frequency, and then issues instructions to the video codec module to continue encoding. After parsing the instructions, the video codec module changes from the waiting state to the working state and encodes a new frame of data. This saves the step of restarting the video codec module, and at the same time, reduces power consumption by reducing the frequency when the video codec module is not needed.

[0046] The third aspect of the present invention discloses an electronic device, which may be a terminal or a server. Figure 3 As shown, Figure 3 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0047] The electronic device 300 includes a processor 301 having one or more processing cores, a memory 302 having one or more computer-readable storage media, and a computer program stored in the memory 302 and executable on the processor. The processor 301 is electrically connected to the memory 302. Those skilled in the art will appreciate that the electronic device structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0048] The processor 301 is the control center of the electronic device 300. It uses various interfaces and lines to connect various parts of the entire electronic device 300, and executes various functions of the electronic device 300 and processes data by running or loading software programs (computer programs) and / or units stored in the memory 302, and calling data stored in the memory 302, thereby monitoring the electronic device 300 as a whole.

[0049] In the embodiment of the present application, the processor 301 in the electronic device 300 will load instructions corresponding to the processes of one or more application programs into the memory 302 according to the following steps, and the processor 301 will run the application programs stored in the memory 302 to implement various functions: Start the performance analysis device to monitor the working status of video encoding and decoding. At each rising edge of the video codec working clock, the number of times the video codec request signal and response signal are initiated is counted, and the delay information between each request and response is obtained. And send the delay information to the central processing unit.

[0050] Optional, such as Figure 3As shown, the electronic device 300 further includes: a performance analysis device 303, a communication module 304, an input unit 305 and a power supply 306. The processor 301 is electrically connected to the performance analysis device 303, the communication module 304, the input unit 305 and the power supply 306 respectively. Those skilled in the art can understand that Figure 3 The electronic device structure shown in the figure does not constitute a limitation of the electronic device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0051] The performance analysis device 303 may be used to implement performance analysis of video encoding and decoding.

[0052] The communication module 304 can be used to communicate with other devices.

[0053] The input unit 305 may be used to receive input numbers, character information or user feature information (such as fingerprint, iris, facial information, etc.), and generate keyboard, mouse, joystick, optical or trackball signal input related to user settings and function control.

[0054] The power supply 306 is used to supply power to various components of the electronic device 300. Optionally, the power supply 306 can be logically connected to the processor 301 through a power management system, so that the power management system can manage charging, discharging, and power consumption. The power supply 306 can also include one or more DC or AC power supplies, recharging systems, power failure detection circuits, power converters or inverters, power status indicators, and other arbitrary components.

[0055] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0056] The fourth aspect of the present invention discloses a computer-readable storage medium. A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0057] To this end, an embodiment of the present application provides a computer-readable storage medium, in which multiple computer programs are stored, and the computer program can be loaded by a processor to execute the steps of a video encoding and decoding performance analysis method provided in an embodiment of the present application. For example, the computer program can execute the following steps: Start the performance analysis device to monitor the working status of video encoding and decoding. At each rising edge of the video codec working clock, the number of times the video codec request signal and response signal are initiated is counted, and the delay information between each request and response is obtained. And send the delay information to the central processing unit.

[0058] The specific implementation of the above operations can be found in the above embodiments, which will not be described in detail here.

[0059] The computer-readable storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0060] Since the computer program stored in the storage medium can execute the steps in any one of the video codec performance analysis methods provided in the embodiments of the present application, the beneficial effects that can be achieved by any one of the video codec performance analysis methods provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0061] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (apparatus), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A system that specifies the functions of a box or multiple boxes.

[0062] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction system, which is implemented in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0063] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0064] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions and variations of these embodiments are made without departing from the principles and spirit of the present invention, and still fall within the scope of protection of the present invention.

Claims

1. A video encoding and decoding performance analysis device, characterized in that: The device comprises: A video codec working status monitoring unit, used for real-time monitoring of the video codec working status; The video codec performance monitoring unit is used to count the number of times the video codec request signal and response signal are initiated at each rising edge of the video codec working clock, and to obtain the delay information between each request and response; A delay information sending unit, used for sending the delay information to a central processing unit; The performance analysis device is coupled to the central processing unit and the video encoding and decoding module respectively.

2. The device according to claim 1, characterized in that: The real-time monitoring of the video codec working state is specifically to monitor each rising edge of the working clock in real time and collect the working state signal value; The working status includes idle, working or waiting.

3. The device according to claim 2, characterized in that Also includes: a time configuration unit, coupled to the central processor and the analysis device respectively, The time configuration unit and the analysis device are respectively configured with a first variable and a second variable, and the value ranges of the first variable and the second variable are natural numbers. The working state signal value is collected at each rising edge of the working clock, and when the working state signal value indicates that the working state is in progress, the second variable value is set to 0; When the working status signal value indicates an idle state or a waiting state, the second variable value is increased by 1 and compared with the first variable value. If the second variable value is less than or equal to the first variable value, the working status continues to be monitored; if the second variable value is greater than the first variable value, the performance analysis device uploads the information to the central processing unit, and the central processing unit controls the reduction of the working frequency of the video codec.

4. The device according to claim 3, characterized in that: The central processing unit configures the value of the first variable, and the performance analysis device counts the number of times each request signal and response signal of the working clock rising edge is initiated. At the same time, when the value of the first variable is reduced by 1 until it reaches 0, the performance analysis device calculates the average bandwidth and average delay information of the video encoding and decoding during this period of time, and reports it to the central processing unit.

5. A video encoding and decoding performance analysis method, characterized in that: The method is implemented based on a video encoding and decoding performance analysis device according to any one of claims 1 to 4, and the method specifically comprises: Start the performance analysis device to monitor the working status of video encoding and decoding. At each rising edge of the video codec working clock, the number of times the video codec request signal and response signal are initiated is counted, and the delay information between each request and response is obtained. And send the delay information to the central processing unit.

6. The method according to claim 5, characterized in that: The real-time monitoring of the video codec working state is specifically to monitor each rising edge of the working clock in real time and collect the working state signal value; The working status includes idle, working or waiting.

7. The method according to claim 6, characterized in that: The working state signal value is collected at each rising edge of the working clock, and when the working state signal value indicates that the working state is in progress, the second variable value is set to 0; When the working status signal value indicates an idle state or a waiting state, the second variable value is increased by 1 and compared with the first variable value. If the second variable value is less than or equal to the first variable value, the working status continues to be monitored; if the second variable value is greater than the first variable value, the performance analysis device uploads the information to the central processing unit, and the central processing unit controls the reduction of the working frequency of the video codec.

8. The method according to claim 7, characterized in that The central processing unit configures the value of the first variable, and the performance analysis device counts the number of times each request signal and response signal of the working clock rising edge is initiated. At the same time, when the value of the first variable is reduced by 1 until it reaches 0, the performance analysis device calculates the average bandwidth and average delay information of the video encoding and decoding during this period of time, and reports it to the central processing unit.

9. An electronic device, characterized in that: It comprises a memory storing executable program code and a processor coupled to the memory; wherein the processor calls the executable program code stored in the memory to execute the method according to any one of claims 5-8.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 5 to 8 is performed.

Images