Memory and manufacturing method thereof, and electronic device

Abstract

Embodiments of the present application provide a memory device, a manufacturing method thereof, and an electronic device. In the manufacturing method of the memory device provided in the embodiment of the present application, before etching the first conductive layer, the first dielectric layer, and the semiconductor layer, a sacrificial layer covering the first conductive layer is first formed, and then the sacrificial layer is etched to form a sacrificial structure located in the first via hole. Thus, during the etching process of the first conductive layer, the first dielectric layer, and the semiconductor layer, the sacrificial structure can protect the first conductive layer, the first dielectric layer, and the semiconductor layer located in the first via hole, which is beneficial for ensuring the progress of subsequent processes and reducing the difficulty of manufacturing transistors in the memory device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a memory device and a method for manufacturing the same, as well as an electronic device. Background Art

[0002] With the development of semiconductor technology, the number of integrated components in semiconductor devices represented by memories is increasing. Currently, in the manufacturing process of three-dimensional stacked memories, more and more vias need to be formed to form field-effect transistors, word lines, etc.

[0003] For example, in the manufacturing process of a three-dimensional stacked memory, to form a field-effect transistor, it is necessary to sequentially form a semiconductor material layer, a dielectric material layer, and a conductive material layer covering the sidewalls of the via, and then form the field-effect transistor by etching the semiconductor material layer, the dielectric material layer, and the conductive material layer.

[0004] However, the current process of forming multiple mutually isolated field effect transistors in a via hole is relatively difficult. Summary of the Invention

[0005] In view of the shortcomings of the existing methods, this application proposes a memory and a manufacturing method thereof, and an electronic device, at least to improve the deficiencies in the background technology.

[0006] In a first aspect, an embodiment of the present application provides a method for manufacturing a memory, comprising:

[0007] forming a composite film layer comprising a plurality of first via holes on one side of the substrate; the composite film layer comprises a plurality of first dielectric film layers and first conductive film layers alternately stacked, and a protective layer is provided on a side of the composite film layer away from the substrate;

[0008] forming a semiconductor layer, a first dielectric layer, a first conductive layer, and a sacrificial layer in sequence to cover the protective layer and the inner wall of the first via hole, wherein the sacrificial layer completely fills the first via hole;

[0009] Etching and removing the sacrificial layer on the protective layer, and retaining the sacrificial layer in the first via hole, where the sacrificial layer in the first via hole is a sacrificial structure;

[0010] The sacrificial structure and the protective layer are used as etching barriers to remove the first conductive layer, the first dielectric layer and the semiconductor layer on the protective layer, while retaining the first conductive structure, the first dielectric structure and the first semiconductor structure in the first via hole.

[0011] In a second aspect, an embodiment of the present application provides a memory comprising: a plurality of word lines, a plurality of bit lines, and a multi-layer stacked memory cell;

[0012] The memory cell includes a field effect transistor and a capacitor distributed and connected along a first direction parallel to the substrate;

[0013] The bit line extends along a second direction parallel to the substrate, and is located in the memory cells of the same layer, and the bit line is connected to the semiconductor structures of the field effect transistors of a column of memory cells arranged along the second direction;

[0014] The word line extends along a third direction perpendicular to the substrate, and is connected to gates of field effect transistors of a group of memory cells stacked along the third direction.

[0015] In a third aspect, an embodiment of the present application provides an electronic device, comprising: at least one memory as provided in the second aspect.

[0016] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0017] In the manufacturing method of the memory provided in the embodiment of the present application, before etching the first conductive layer, the first dielectric layer and the semiconductor layer, a sacrificial layer covering the first conductive layer is first formed, and then the sacrificial layer is etched to form a sacrificial structure located in the first via hole. Therefore, during the etching process of the first conductive layer, the first dielectric layer and the semiconductor layer, the sacrificial structure can protect the first conductive layer, the first dielectric layer and the semiconductor layer located in the first via hole, which is beneficial to reducing the difficulty of manufacturing transistors in the memory.

[0018] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0020] Figure 1 A schematic flow chart of a method for manufacturing a memory provided in an embodiment of the present application;

[0021] Figure 2 A schematic top view of a film structure after a combined film layer is formed in a memory manufacturing method provided in an embodiment of the present application;

[0022] Figure 3 、 Figure 4 for Figure 2 Schematic diagram of the cross-section of the membrane layer at aa and bb in the membrane layer structure shown;

[0023] Figure 5 A schematic top view of a film structure after forming a first via hole and a first groove in a memory manufacturing method provided by an embodiment of the present application;

[0024] Figure 6 、 Figure 7 for Figure 5 Schematic diagram of the cross-section of the membrane layer at aa and bb in the membrane layer structure shown;

[0025] Figure 8 This is a schematic diagram of a cross-sectional film layer at point aa after forming a first conductive layer in a memory manufacturing method provided by an embodiment of the present application;

[0026] Figure 9 This is a schematic diagram of a cross-sectional film layer at point bb after forming a first conductive layer in a memory manufacturing method provided by an embodiment of the present application;

[0027] Figure 10 This is a schematic diagram of a cross-sectional film layer at point aa after forming a sacrificial layer in a memory manufacturing method provided by an embodiment of the present application;

[0028] Figure 11 This is a schematic diagram of a cross-sectional film layer at point bb after forming a sacrificial layer in a memory manufacturing method provided by an embodiment of the present application;

[0029] Figure 12 This is a schematic diagram of a cross-sectional film layer at point aa after forming a sacrificial structure in a memory manufacturing method provided by an embodiment of the present application;

[0030] Figure 13 This is a schematic diagram of a cross-sectional film layer at point bb after forming a sacrificial structure in a memory manufacturing method provided by an embodiment of the present application;

[0031] Figure 14 This is a schematic diagram of a cross-sectional film layer at point aa after forming a first conductive structure, a first dielectric structure, and a first semiconductor structure in a memory manufacturing method provided by an embodiment of the present application;

[0032] Figure 15 This is a schematic diagram of a cross-sectional film layer at point bb after forming a first conductive structure, a first dielectric structure, and a first semiconductor structure in a memory manufacturing method provided by an embodiment of the present application;

[0033] Figure 16 This is a schematic diagram of a cross-sectional film layer at point aa after removing the sacrificial structure in a memory manufacturing method provided by an embodiment of the present application;

[0034] Figure 17 This is a schematic diagram of a cross-sectional film layer at point bb after removing the sacrificial structure in a memory manufacturing method provided by an embodiment of the present application;

[0035] Figure 18 This is a schematic diagram of a cross-sectional film layer at point aa after a gate is formed in a memory manufacturing method provided by an embodiment of the present application;

[0036] Figure 19 This is a schematic diagram of a cross-sectional film layer at point bb after forming a gate in a memory manufacturing method provided by an embodiment of the present application;

[0037] Figure 20 for Figure 18 An enlarged schematic diagram of point A in the membrane structure shown;

[0038] Figure 21 This is a schematic diagram of a cross-sectional film layer at point aa after forming a gate dielectric structure and a semiconductor structure in a memory manufacturing method provided by an embodiment of the present application;

[0039] Figure 22 This is a schematic diagram of a cross-sectional film layer at point bb after forming a gate dielectric structure and a semiconductor structure in a memory manufacturing method provided by an embodiment of the present application;

[0040] Figure 23 for Figure 21 An enlarged schematic diagram of point B in the membrane structure shown;

[0041] Figure 24 This is a schematic diagram of a cross-sectional film layer at point aa after forming a second dielectric structure in a memory manufacturing method provided by an embodiment of the present application;

[0042] Figure 25 This is a schematic diagram of a cross-sectional film layer at point bb after forming a second dielectric structure in a memory manufacturing method provided by an embodiment of the present application;

[0043] Figure 26 for Figure 24 The enlarged schematic diagram of point C in the membrane structure shown;

[0044] Figure 27 This is a schematic diagram of a cross-sectional film layer at point aa after forming a word line in a memory manufacturing method provided by an embodiment of the present application;

[0045] Figure 28 This is a schematic diagram of a cross-sectional film layer at point bb after forming a word line in a memory manufacturing method provided by an embodiment of the present application.

[0046] Description of reference numerals:

[0047] 100 - substrate; 101 - first dielectric film layer; 102 - first conductive film layer; 1021 - first electrode structure;

[0048] 103 - protective layer; 104 - first via hole; 105 - first groove; 106 - semiconductor layer; 1061 - first semiconductor structure;

[0049] 107 - first dielectric layer; 1071 - first dielectric structure; 108 - first conductive layer; 1081 - first conductive structure;

[0050] 109 - second via hole; 110 - sacrificial layer; 1101 - sacrificial structure; 111 - fourth groove; 112 - second dielectric structure;

[0051] 10-field effect transistor; 11-gate; 12-gate dielectric structure; 13-12 and semiconductor structure; 20-bit line; 30-word line; 41-electrode structure. DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0053] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may include plural forms as well.

[0054] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0055] The CMP (Chemical Mechanical Polishing) process involves first chemically reacting the workpiece's surface material with oxidants and catalysts in a polishing solution to form a soft layer that is relatively easy to remove. The abrasive in the polishing solution and the polishing pad then mechanically remove the soft layer, leaving a smooth surface on the workpiece's surface.

[0056] When forming a 3D stacked multi-layer memory cell, it is necessary to form a multi-layer 3D stacked transistor. In some embodiments, the multi-layer 3D stacked transistor is formed in a through hole that penetrates all the film layers. When making the film layers of the transistors formed in the through holes, these film layers are inevitably deposited on the upper surface of the stacked film layers at the same time, and the film layers formed on these upper surfaces are often redundant and need to be removed. In some embodiments, these redundant film layers are removed by means of chemical mechanical polishing. When this method is used to remove these external redundant film layers after the transistors in the through holes are made or during the process of making the transistors, the performance of the transistors in the through holes may be affected or damaged. The new process proposed in the present application can effectively reduce or avoid the impact of removing the redundant film layers on the upper surface of the stacked film layers on the transistors.

[0057] The memory, manufacturing method thereof, and electronic device provided in this application are intended to solve the above technical problems of the prior art.

[0058] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0059] The present invention provides a method for manufacturing a memory device. The flowchart of the method is shown in FIG. Figure 1 As shown, the method includes steps S101 to S104.

[0060] S101 , forming a composite film layer including a plurality of first via holes on one side of a substrate; the composite film layer includes multiple layers of alternately stacked first dielectric film layers and first conductive film layers, and a protective layer is provided on a side of the composite film layer away from the substrate.

[0061] S102 , sequentially forming a semiconductor layer, a first dielectric layer, a first conductive layer, and a sacrificial layer covering the protection layer and the inner wall of the first via hole, wherein the sacrificial layer completely fills the first via hole.

[0062] S103 , etching away the sacrificial layer on the protective layer, and retaining the sacrificial layer in the first via hole. The sacrificial layer in the first via hole is a sacrificial structure.

[0063] Optionally, a portion of the sacrificial layer on a side of the protection layer away from the substrate is removed by etching, and another portion of the sacrificial layer is retained in the first via hole to form a sacrificial structure.

[0064] Optionally, one part and another part constitute the sacrificial layer of each area on the protective layer. One part can be understood as the part located outside the first via area. The other part retained after removing the first part of the sacrificial layer is the sacrificial layer in the first via. The sacrificial layer in the first via serves as a barrier layer for etching the semiconductor layer, the first dielectric layer, and the first conductive layer outside the first via.

[0065] S104 , using the sacrificial structure and the protective layer as etching barriers, removing the first conductive layer, the first dielectric layer, and the semiconductor layer on the protective layer, and retaining the first conductive structure, the first dielectric structure, and the first semiconductor structure in the first via hole.

[0066] In the manufacturing method of the memory provided in the embodiment of the present application, before etching the first conductive layer, the first dielectric layer, and the semiconductor layer, a sacrificial layer covering the first conductive layer is first formed, and then the sacrificial layer is etched to form a sacrificial structure located in the first via hole. Therefore, during the etching process of the first conductive layer, the first dielectric layer, and the semiconductor layer, the sacrificial structure can protect the first conductive layer, the first dielectric layer, and the semiconductor layer located in the first via hole, which is beneficial to reducing the manufacturing difficulty of the transistors in the memory, ensuring the progress of subsequent processes, and ensuring the yield of the memory.

[0067] Moreover, in the manufacturing method of the memory provided in the embodiment of the present application, the first conductive layer, the first dielectric layer and the semiconductor layer located on the protective layer can be removed without using the CMP process, which can avoid the CMP process from damaging other film layers, is beneficial to ensuring the progress of subsequent processes, and is beneficial to ensuring the yield of the memory.

[0068] In order to facilitate readers to intuitively understand the memory manufacturing method provided by the embodiment of the present application and the advantages of the manufacturing method, the following will be combined with Figure 2-Figure 28 A memory manufacturing method is described in detail.

[0069] Optionally, in one embodiment of the present application, before forming a combined film layer including a plurality of first vias 104 on one side of the substrate 100 in the above-mentioned step S101, the step further includes: forming a plurality of alternating stacked first dielectric film layers 101 and first conductive film layers 102 on one side of the substrate 100 based on a deposition process; and forming a protective layer 103 on a side of the first dielectric film layer 101 located at the topmost layer in the combined film layer away from the substrate 100 based on a deposition process.

[0070] Alternatively, as Figure 2 、 Figure 3 as well as Figure 4 As shown, along a direction perpendicular to the substrate 100 and away from the substrate 100 , a first dielectric film layer 101 and a first conductive film layer 102 are alternately stacked in the combined film layer, and the topmost film layer of the combined film layer is the first dielectric film layer 101 .

[0071] Optionally, in an embodiment of the present application, a first dielectric film layer 101 is first formed on one side of the substrate 100 based on a deposition process, and then a first conductive film layer 102 is formed on the side of the first dielectric film layer 101 away from the substrate 100 based on a deposition process, and then a first dielectric film layer 101 is formed on the side of the first conductive film layer 102 away from the substrate 100 based on a deposition process, so that the first dielectric film layer 101 covers the first conductive film layer 102, and the above steps are repeated to form multiple layers of alternately stacked first dielectric film layers 101 and first conductive film layers 102, thereby forming a structure as shown in FIG. Figure 2 、 Figure 3 as well as Figure 4 Then, a protective layer 103 is formed on one side of the first dielectric film layer 101 located on the upper layer based on a deposition process.

[0072] Optionally, the deposition process includes CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), and the like.

[0073] Optionally, in the embodiment of the present application, the first conductive film layer 102 includes the bit line 20 and the first electrode structure 1021, such as Figure 2 and Figure 3 As shown, each word line 20 is connected to a plurality of first electrode structures 1021 . The word lines 20 extend along a second direction parallel to the substrate 100 , and the first electrode structures 1021 extend along the second direction parallel to the substrate 100 .

[0074] It should be noted that, in order to facilitate readers to intuitively understand the structure of the first conductive film layer 102, as shown in FIG. Figure 2 As shown, the protective layer 103 and the uppermost first dielectric film layer 101 are subjected to perspective processing, so that Figure 2 Only the topmost first conductive film layer 102 and the first dielectric film layer 101 located below the first conductive film layer 102 are shown. Figure 2 and Figure 3 As shown, the boundary between the bit line 20 and the first electrode structure 1021 is represented by a dotted line, which does not exist in the actual product. Figure 2 and Figure 3 The dashed line is shown.

[0075] Optionally, in one embodiment of the present application, forming a composite film layer including a plurality of first vias 104 on one side of the substrate 100 in the above step S101 includes: forming a plurality of first vias 104 in the composite film layer based on a patterning process.

[0076] Alternatively, as Figure 5 、 Figure 6 as well as Figure 7 As shown, the first via hole 104 penetrates the protective layer 103 , the multi-layer first dielectric film layer 101 and the multi-layer first conductive film layer 102 of the combined film layer, so that a portion of the substrate 100 is exposed.

[0077] Optionally, in one embodiment of the present application, the above steps form a plurality of first vias 104 in the combined film layer based on a patterning process, including: patterning a multi-layer first dielectric film layer 101 and a multi-layer first conductive film layer 102, so that the formed first vias 104 pass through the first electrode structure 1021 of the first conductive film layer 102.

[0078] Optionally, in the embodiment of the present application, the patterned combined film layer forms a plurality of first via holes 104 penetrating the combined film layer along the third direction.

[0079] Optionally, in an embodiment of the present application, the material used to make the protective layer 103 includes silicon nitride, so that in the process of patterning the multi-layer first dielectric film layer 101 and the multi-layer first conductive film layer 102, the patterned protective layer 103 can act as a hard mask, helping to ensure the patterning of the first dielectric film layer 101 and the first conductive film layer 102.

[0080] Optionally, in an embodiment of the present application, after patterning the combined film layers, the sidewalls of the first via 104 include a plurality of stacked patterned first dielectric film layers 101, a patterned first conductive film layer 102, and a patterned protective layer 103 located on the top layer. At this time, it should be noted that there is no protective layer in the first via.

[0081] Optionally, in the embodiment of the present application, the first electrode structure 1021 of the multi-layer first dielectric film layer 101 and the multi-layer first conductive film layer 102 is patterned so that the formed first via 104 passes through the first electrode structure 1021, thereby preventing the bit line 20 from being etched. In the embodiment of the present application, the first electrode structure 1021 is used to form an electrode structure 41 of a capacitor in a subsequent memory cell.

[0082] Optionally, in one embodiment of the present application, before the above-mentioned step S102 sequentially forms the semiconductor layer, the first dielectric layer, the first conductive layer and the sacrificial layer covering the protective layer and the inner wall of the first via hole, the following steps are included: laterally (in the direction parallel to the substrate 100) etching back the first conductive film layer 102 on the inner wall of the first via hole 104, so that the first conductive film layer 102 after etching is enclosed with the adjacent first dielectric film layer 101 to form a first groove 105.

[0083] Alternatively, as Figure 5 、 Figure 6 as well as Figure 7 As shown, a plurality of first grooves 105 are provided on the inner side wall of the first via hole 104, and the openings of the first grooves 105 face the first via hole 104. Figure 6 and Figure 7 As shown, three annular first grooves 105 are arranged at intervals along the third direction, and the third direction is a direction perpendicular to the substrate 100 and away from the substrate 100 .

[0084] Optionally, in one embodiment of the present application, the above steps include etching back the first conductive film layer 102 on the inner side wall of the first via 104 so that the etched back first conductive film layer 102 and the adjacent first dielectric film layer 101 form a first groove 105, including: etching the first electrode structure 1021 on the inner side wall of the first via 104 to form an electrode structure 41, so that a portion of the bit line 20 arranged in the same layer as the first electrode structure 1021 in the first conductive film layer 102 is exposed; the electrode structure 41, the bit line 20 and the first dielectric film layer 101 are surrounded to form the first groove 105.

[0085] Optionally, in the embodiment of the present application, Figure 6 and Figure 7 As shown, the first electrode structure 1021 on the inner sidewall of the first via hole 104 is etched back, and the remaining portion of the etched first electrode structure 1021 forms the electrode structure 41. Optionally, along the first direction and the second direction, the size of the etched back first electrode structure 1021 is not less than 20 nanometers and not more than 25 nanometers.

[0086] Optionally, in one embodiment of the present application, in the above-mentioned step S102, a semiconductor layer 106, a first dielectric layer 107, a first conductive layer 108 and a sacrificial layer 110 are sequentially formed to cover the protective layer 103 and the inner wall of the first via hole 104, so that the sacrificial layer 110 completely fills the first via hole 104, including: based on the atomic layer deposition process, the semiconductor layer 106, the first dielectric layer 107 and the first conductive layer 108 are sequentially formed to cover the protective layer 103 and the inner wall of the first via hole 104; the first conductive layer 108 located in the first via hole 104 encloses the second via hole 109; based on the atomic layer deposition process, the sacrificial layer 110 is formed to cover the protective layer 103 and completely fill the second via hole 109.

[0087] Optionally, in the embodiment of the present application, Figure 8 and Figure 9 As shown, the formed conductor layer 106 , the first dielectric layer 107 and the first conductive layer 108 all include a portion covering the protection layer 103 and a portion covering the inner wall of the first via hole 104 .

[0088] Optionally, the inner wall of the first via hole 104 includes a side wall and a bottom wall.

[0089] Optionally, in the embodiment of the present application, Figure 10 and Figure 11 As shown, the formed sacrificial layer 110 fills up the first conductive layer 108 to enclose the second via hole 109 , and the sacrificial layer 110 covers the portion of the first conductive layer 108 located above the protection layer 103 .

[0090] Optionally, in an embodiment of the present application, based on the atomic layer deposition process, a semiconductor layer 106, a first dielectric layer 107 and a first conductive layer 108 covering the protective layer 103 and the inner wall of the first via 104 are formed in sequence, including: a single process is used to form the semiconductor layer 106 covering both the protective layer 103 and the inner wall of the first via 104, the semiconductor layer 106 including a second groove located within the first groove 105; a single process is used to form the first dielectric layer 107 covering both the semiconductor layer 106, the first dielectric layer 107 including a third groove located within the second groove; a single process is used to form the first conductive layer 108 covering both the first dielectric layer 107, such that the first conductive layer 108 fills the third groove and covers the sidewall of the first via 104, but does not fill the first via 104.

[0091] Optionally, based on the ALD process, a semiconductor material is deposited on the surface of the protection layer 103 and the inner wall of the first via hole 104 to form a semiconductor layer 106 covering the protection layer 103 and the inner wall of the first via hole 104 .

[0092] Alternatively, as Figure 8 and Figure 9 As shown, the thickness of the semiconductor layer 106 is less than the recessed depth of the first groove 105, so that the semiconductor layer 106 conforms to the inner side wall of the first via hole 104 to form a second groove located within the first groove 105, and also the semiconductor layer 106 located within the first via hole 104 is enclosed to form a hole shape.

[0093] Optionally, in the embodiment of the present application, the material of the semiconductor layer 106 includes a metal oxide semiconductor material.

[0094] Optionally, the metal oxide semiconductor material includes IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide), IWO (Indium Wolfram Oxide, tungsten-doped indium oxide), InGaO (indium gallium oxide), ZnO (zinc oxide), InO (indium oxide), InO (indium oxide), InWO (indium tungsten oxide), SnO (tin oxide), TiO (titanium oxide), InSnO (indium tin oxide), ZnON (nitrogen-doped zinc oxide), MgZnO (magnesium zinc oxide), InZnO (indium zinc oxide), InGaZnO (indium gallium zinc oxide), ZrInZnO (zirconium indium zinc oxide), HfInZnO (hafnium indium zinc oxide), SnInZnO (tin indium zinc oxide), AlZnO (aluminum zinc oxide), AlSnInZnO (aluminum tin indium zinc oxide), SiInZnO (silicon indium zinc oxide), ZnSnO (zinc tin oxide), AlZnSnO (aluminum zinc tin oxide), GaZnSnO (gallium zinc tin oxide), ZrZnSnO (zirconium zinc tin oxide) and InGaSiO (indium gallium silicon oxide).

[0095] Optionally, after the semiconductor layer 106 is formed, a dielectric material, such as aluminum oxide, is deposited on the surface of the semiconductor layer 106 based on an ALD process to form a first dielectric layer 107 covering the semiconductor layer 106 .

[0096] Alternatively, as Figure 8 and Figure 9 As shown, the thickness of the first dielectric layer 107 is less than the depth of the second groove, so that the inner sidewall of the hole formed by the first dielectric layer 107 and the semiconductor layer 106 conforms to the shape, forming a third groove located within the second groove, and also forming a hole shape enclosed by the first dielectric layer 107.

[0097] Optionally, after forming the first dielectric layer 107 , a conductive material, such as ITO, is deposited on the surface of the first dielectric layer 107 based on an ALD process to form a first conductive layer 108 covering the first dielectric layer 107 .

[0098] Alternatively, as Figure 8 and Figure 9 As shown, the first conductive layer 108 completely fills the third groove but does not completely fill the first via 104, so that the first conductive layer 108 in the first via 104 encloses a second via 109. Optionally, the diameter of the second via 109 is not less than 10 nanometers and not more than 20 nanometers.

[0099] Optionally, in an embodiment of the present application, a sacrificial layer 110 covering the protective layer 103 and filling the second via hole 109 is formed based on an atomic layer deposition process, including: depositing a dielectric material on the surface of the first conductive layer 108 and in the second via hole 109 based on an ALD process until the dielectric material fills the second via hole 109 to form the sacrificial layer 110, such as Figure 10 and Figure 11 shown.

[0100] Optionally, in an embodiment of the present application, the material of the sacrificial layer 110 includes silicon oxide.

[0101] Optionally, in one embodiment of the present application, in the above step S103, a portion of the sacrificial layer 110 on the side of the protective layer 103 away from the substrate is etched away, and another portion of the sacrificial layer 110 in the first via 104 is retained to form a sacrificial structure 1101, including: based on a third etching process, etching the sacrificial layer 110 to expose the first conductive layer 108 located on the side of the protective layer 103 away from the substrate 100.

[0102] Optionally, in the embodiment of the present application, Figure 12 and Figure 13 As shown, the sacrificial layer 110 is processed based on the third etching process, so that the portion of the sacrificial layer 110 located on the side of the first conductive layer 108 away from the substrate 100 is etched away to expose the first conductive layer 108 located below the portion of the sacrificial layer 110. Since the thickness of this portion of the sacrificial layer 110 is much smaller than the thickness of the portion of the sacrificial layer 110 located in the second via 109, the portion of the sacrificial layer 110 located in the second via 109 is not etched, thereby forming a sacrificial structure 1101 located in the second via 109.

[0103] Alternatively, as Figure 12 and Figure 13 As shown, the top surface of the sacrificial structure 1101 is coplanar with the top surface of the first conductive layer 108 .

[0104] Optionally, the third etching process includes any one of a wet etching process and a dry etching process. Optionally, the chemical agent of the wet etching process includes hydrofluoric acid with a set concentration range.

[0105] Optionally, in the embodiment of the present application, Figure 12 and Figure 13 As shown, since the sacrificial structure 1101 completely fills the second via 109, the outer wall of the sacrificial structure 1101 can block the portion of the first conductive layer 108 located in the first via 104, so that the sacrificial structure 1101 can protect the first conductive layer 108, the first dielectric layer 107 and the semiconductor layer 106 located in the first via 104.

[0106] Optionally, in one embodiment of the present application, in the above-mentioned step S104, the sacrificial structure 1101 and the protective layer 103 are used as etching barriers to etch away the first conductive layer 108, the first dielectric layer 107 and the semiconductor layer 106 on the protective layer 103 to form a first conductive structure 1081, a first dielectric structure 1071 and a first semiconductor structure 1061 located in the first via 104, including: using the sacrificial structure 1101 as a mask, based on a fourth etching process, removing the first conductive layer 108, the first dielectric layer 107 and the semiconductor layer 106 located on the protective layer 103 at one time.

[0107] Optionally, in the embodiment of the present application, Figure 14 and Figure 15 As shown, the sacrificial structure 1101 is used as a mask and the first conductive layer 108, the first dielectric layer 107 and the semiconductor layer 106 are processed simultaneously based on the fourth etching process, so that the first conductive layer 108, the first dielectric layer 107 and the semiconductor layer 106 located on the side of the protective layer 103 away from the substrate 100 can be removed at one time by the same etching process, thereby simplifying the manufacturing process of the memory, improving the manufacturing efficiency of the memory, and helping to reduce the manufacturing cost of the memory.

[0108] Alternatively, as Figure 14 and Figure 15 As shown, since the sacrificial structure 1101 is used as a mask, the first conductive structure 1081 formed after the first conductive layer 108 is etched, the first dielectric structure 1071 formed after the first dielectric layer 107 is etched, and the first semiconductor structure 1061 formed after the semiconductor layer 106 is etched are all located in the first via hole 104.

[0109] Optionally, the fourth etching process includes a wet etching process, and the chemical agent of the wet etching process includes oxalic acid or hydrochloric acid with a set concentration range.

[0110] Optionally, in one embodiment of the present application, after the sacrificial structure 1101 and the protective layer 103 are used as etching barriers in the above step S104 to etch away the first conductive layer 108, the first dielectric layer 107, and the semiconductor layer 106 on the protective layer 103 to form the first conductive structure 1081, the first dielectric structure 1071, and the first semiconductor structure 1061 located in the first via 104, the step further includes: removing the sacrificial structure 1101; etching away a portion of the first conductive structure 1081 in the first via 104 to form a gate 11 located at least partially in the first groove; and etching away the first dielectric structure 1071 and the first semiconductor structure 1061 in the first via 104 and outside the first groove to form a gate dielectric structure 12 and semiconductor structures 13 corresponding to different memory cells, respectively.

[0111] Optionally, in an embodiment of the present application, removing the sacrificial structure 1101 in the above step includes: removing the sacrificial structure 1101 based on a dry etching process, so that the inner wall of the second via hole 105 is exposed.

[0112] Alternatively, as Figure 16 and Figure 17 As shown, after the sacrificial structure 1101 is removed, the inner wall of the second via hole 105 formed by the first conductive structure 1081 is exposed.

[0113] Optionally, in one embodiment of the present application, etching away a portion of the first conductive structure 1081 in the first via 104 in the above step to form a gate 11 at least partially located in the first groove 105 includes: removing a portion of the first conductive structure 1081 based on a first etching process to form a gate 11 at least partially located in the third groove, so that the first dielectric structure 1071 in each area except the third groove is exposed.

[0114] Optionally, in the embodiment of the present application, Figure 16 and Figure 17 As shown, along a direction parallel to the substrate 100, the thickness of the third groove portion of the first conductive structure 1081 formed in the first dielectric structure 1071 is much greater than the thickness of other portions. Therefore, during the etching process of the first conductive structure 1081, the portion of the first conductive structure 1081 located in the third groove will be retained to form the gate 11 of the subsequently formed field effect transistor.

[0115] Alternatively, as Figure 18 、 Figure 19 as well as Figure 20 As shown, after the first conductive structure 1081 is etched to form the gate 11 , a portion of the first dielectric structure 1071 except the third groove is exposed in the second via hole 109 .

[0116] Alternatively, as Figure 18 、 Figure 19 as well as Figure 20 As shown, the gate 11 is ring-shaped and surrounds the second via hole 109 .

[0117] Alternatively, as Figure 18 、 Figure 19 as well as Figure 20 As shown, the outer sidewall of the gate 11 is flush with the exposed sidewall of the first dielectric structure 1071 .

[0118] Optionally, the first etching process includes a wet etching process, and the chemical agent of the wet etching process includes oxalic acid or hydrochloric acid with a set concentration range. The first etching process has good etching selectivity and can avoid damaging other film layers and structures.

[0119] Optionally, in one embodiment of the present application, the first dielectric structure 1071 and the first semiconductor structure 1061 in the first via 104 and outside the first groove 105 are etched away in the above steps to form a gate dielectric structure 12 and semiconductor structures 13 corresponding to different storage cells, respectively, including: using the gate 11 as a mask, etching the first dielectric structure 1071 and the first semiconductor structure 1061 based on a second etching process to form the gate dielectric structure 12 and the semiconductor structure 13 located in the first groove 105; the first dielectric film layer 101, the gate 11, the gate dielectric structure 12 and the semiconductor structure 13 enclosed to form a fourth groove.

[0120] Optionally, in the embodiment of the present application, since the second etching process has high selectivity for the first dielectric structure 1071 and the first semiconductor structure 1061, the first dielectric structure 1071 and the first semiconductor structure 1061 not blocked by the gate 11 can be etched away using the gate 11 as a mask.

[0121] Optionally, in the embodiment of the present application, the gate 11 is used as a mask, and the first dielectric structure 1071 and the first semiconductor structure 1061 are simultaneously etched based on a second etching process to form a gate dielectric structure 12 and a semiconductor structure 13, respectively.

[0122] Optionally, in order to ensure that the first dielectric structure 1071 and the first semiconductor structure 1061 outside the first groove 105 can be completely etched, the process time of the second etching process is appropriately extended so that part of the first dielectric structure 1071 and part of the first semiconductor structure 1061 located in the first groove 105 are also etched, such as Figure 21 、 Figure 22 as well as Figure 23 As shown, after etching is completed, the first dielectric film layer 101 , the gate 11 , the gate dielectric structure 12 and the semiconductor structure 13 enclose a fourth groove 111 .

[0123] Optionally, the second etching process includes a wet etching process, wherein the chemical agent of the wet etching process includes citric acid, hypochlorous acid, acetic acid or hydrochloric acid with a set concentration range. The second etching process has good etching selectivity and can avoid damaging other film layers and structures.

[0124] Alternatively, as Figure 21 、 Figure 22 as well as Figure 23 As shown, a field effect transistor 10 is formed in each first groove 105 .

[0125] Alternatively, as Figure 21 、 Figure 22 as well as Figure 23As shown, the field effect transistor 10 is a ring field effect transistor, that is, the gate 11, the gate dielectric structure 12 and the semiconductor structure 13 of the field effect transistor 10 are all ring-shaped.

[0126] Alternatively, as Figure 23 As shown, the bit lines 20 and electrode structures 41 arranged in the same layer are connected to the semiconductor structure 13 of the same field effect transistor 10. When the field effect transistor 10 is in working state, part of the bit lines 20 and part of the electrode structure 41 act as the source and drain of the field effect transistor 10.

[0127] Optionally, in one embodiment of the present application, after etching away the first dielectric structure 1071 and the first semiconductor structure 1061 in the first via hole 104 and outside the first groove 105 in the above steps to form the gate dielectric structure 12 and the semiconductor structures 13 corresponding to different memory cells, the further step further includes: forming a second dielectric structure 112 filling the fourth groove 111, so that the outer wall of the second dielectric structure 112 is coplanar with the inner wall of the first via hole 104, exposing the gate 11.

[0128] Optionally, in the embodiment of the present application, a dielectric material is deposited in the first via hole 104 based on an ALD process, so that the dielectric material completely fills the fourth groove 111 to form a second dielectric structure 112 .

[0129] Optionally, during the formation of the second dielectric structure 112 , the dielectric material deposited on the sidewalls of the first via hole 104 and the protective layer 103 may be removed by dry etching or wet etching using the protective layer 103 as a mask.

[0130] Optionally, in the embodiment of the present application, Figure 24 、 Figure 25 as well as Figure 26 As shown, the outer wall of the second dielectric structure 112 is coplanar with the inner wall of the first via 104 , thereby helping to ensure the flatness of the sidewall of the first via 104 , facilitating subsequent processes, and improving the yield of other structures formed in the first via 104 .

[0131] Optionally, in one embodiment of the present application, after the first dielectric structure 1071 and the first semiconductor structure 1061 in the first via hole 104 and outside the first groove 105 are etched away in the above step to form the gate dielectric structure 12 and the semiconductor structures 13 corresponding to different memory cells, respectively; or after the second dielectric structure 112 filling the fourth groove 111 is formed in the above step so that the outer wall of the second dielectric structure 112 is coplanar with the inner wall of the first via hole 104 and the gate 11 is exposed, the further step further includes: forming a word line 30 filling the first via hole 104 so that the word line 30 is connected to all the gates 11 located in the first via hole 104.

[0132] Optionally, a conductive material is deposited in the first via hole 104 based on a deposition process until the conductive material fills the first via hole 104 to form the word line 30 .

[0133] Alternatively, as Figure 27 and Figure 28 As shown, a word line 30 is formed in each first via hole 104 . The word line 30 extends along the third direction. Each word line 30 is connected to all gates 11 located in the first via hole 104 .

[0134] Alternatively, as Figure 27 and Figure 28 As shown, the three gates 11 disposed in each first via hole 104 are connected to the same word line 30 .

[0135] Optionally, the material of the word line 30 is the same as that of the gate 11 , for example, both the material of the word line 30 and the gate 11 are ITO, which helps reduce the resistance between the word line 30 and the gate 11 and helps ensure the turn-on speed of the field effect transistor 10 .

[0136] Optionally, in the embodiment of the present application, Figure 2-Figure 28 It can be seen that the gate 11 is arranged around the outer wall of the word line 30, the gate dielectric structure 12 is arranged around the outer wall of the gate 11, and the semiconductor structure 13 is arranged around the outer wall of the gate dielectric structure 12. The semiconductor structure 13 is connected to both the electrode structure 41 and the bit line 30. Under the control of the word line 30, the field effect transistor 10 is turned on, so that the electrode structure 41 and the bit line 30 are connected through the semiconductor structure 13.

[0137] Optionally, in one embodiment of the present application, before the above step S101 , the method further includes: forming a dielectric layer of a capacitor and another electrode structure.

[0138] Based on the same inventive concept, an embodiment of the present application provides a memory, which is obtained based on any of the above-mentioned memory manufacturing methods. Figure 27 and Figure 28 As shown, the memory includes: a plurality of word lines 30, a plurality of bit lines 20 and multi-layer stacked memory cells.

[0139] In an embodiment of the present application, the memory cell includes a field effect transistor 10 and a capacitor distributed and connected along a first direction parallel to the substrate 100; the bit line 20 extends along a second direction parallel to the substrate 100, and in the memory cells located in the same layer, the bit line 20 is connected to the semiconductor structure 13 of the field effect transistor 10 of a column of memory cells arranged along the second direction; the word line 30 extends along a third direction perpendicular to the substrate 100, and the word line 30 is connected to the gate 11 of the field effect transistor 10 of a group of memory cells stacked along the third direction.

[0140] In the embodiments of the present application, since the memory is obtained based on any of the above-mentioned memory manufacturing methods, its principles and technical effects can be referred to in the above-mentioned embodiments and will not be repeated here.

[0141] Alternatively, as Figure 27 and Figure 28 As shown, in the embodiment of the present application, the memory cell is a 1T (Transistor) 1C (Capacitor) structure, and the field effect transistor 10 and the capacitor of the same memory cell are arranged on the same layer.

[0142] Alternatively, as Figure 27 and Figure 28 As shown, in one embodiment of the present application, the gate 11 , the gate dielectric structure 12 and the semiconductor structure 13 of the field effect transistor 10 are sequentially surrounded by the periphery of the word line 30 .

[0143] Alternatively, as Figure 27 and Figure 28 As shown, in the embodiment of the present application, the gate 11 , the gate dielectric structure 12 and the semiconductor structure 13 of the field effect transistor 10 are all ring-shaped, surrounding the periphery of the word line 30 to help improve the gate control performance of the field effect transistor 10 .

[0144] Alternatively, as Figure 27 and Figure 28 As shown, in one embodiment of the present application, along the first direction, the field effect transistor 10 is located between the bit line 20 and the capacitor; an electrode structure 41 of the capacitor extends along the first direction, and the electrode structure 41 is connected to the semiconductor structure 13 of the field effect transistor 10.

[0145] Alternatively, as Figure 27 and Figure 28 As shown, in one embodiment of the present application, in the memory cells located in the same layer, each bit line 20 is connected to the semiconductor structures 13 of the field effect transistors 10 of two adjacent columns of memory cells.

[0146] Alternatively, as Figure 27 and Figure 28 As shown, in the embodiment of the present application, the memory is a three-dimensional stacked structure memory, and each layer includes multiple memory cells arranged in columns, that is, multiple memory cells are arranged in columns along the second direction. Along the third direction, the memory cells whose orthographic projections on the substrate 100 overlap are grouped.

[0147] like Figure 28 As shown, the semiconductor structures 13 of the field effect transistors 10 of two adjacent columns of memory cells are connected to the same bit line 20 .

[0148] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes: at least one memory as provided in any of the above embodiments.

[0149] In the embodiments of the present application, since the electronic device adopts any one of the memories provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0150] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0151] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any of the memories provided in the above-mentioned embodiments of this application in different devices according to actual application requirements, thereby obtaining the electronic device provided in the embodiments of this application.

[0152] Those skilled in the art will appreciate that the electronic devices provided in the embodiments of the present application may be specially designed and manufactured for the desired purpose, or may also include known devices in general-purpose computers. These devices may include any memory provided in the above embodiments.

[0153] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0154] In the manufacturing method of the memory provided in the embodiment of the present application, before etching the first conductive layer, the first dielectric layer, and the semiconductor layer, a sacrificial layer covering the first conductive layer is first formed, and then the sacrificial layer is etched to form a sacrificial structure located in the first via hole. Therefore, during the etching process of the first conductive layer, the first dielectric layer, and the semiconductor layer, the sacrificial structure can protect the first conductive layer, the first dielectric layer, and the semiconductor layer located in the first via hole, which is beneficial to ensuring the progress of subsequent processes, reducing the difficulty of manufacturing transistors in the memory, and ensuring the yield of the memory.

[0155] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0156] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0157] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0158] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A method for manufacturing a memory, characterized in that: include: forming a composite film layer comprising a plurality of first via holes on one side of the substrate; the composite film layer comprises a plurality of first dielectric film layers and first conductive film layers alternately stacked, and a protective layer is provided on a side of the composite film layer away from the substrate; forming a semiconductor layer, a first dielectric layer, a first conductive layer, and a sacrificial layer in sequence to cover the protective layer and the inner wall of the first via hole, wherein the sacrificial layer completely fills the first via hole; Etching and removing the sacrificial layer on the protective layer, and retaining the sacrificial layer in the first via hole, wherein the sacrificial layer in the first via hole is a sacrificial structure; The sacrificial structure and the protective layer are used as etching barriers to remove the first conductive layer, the first dielectric layer and the semiconductor layer on the protective layer, while retaining the first conductive structure, the first dielectric structure and the first semiconductor structure in the first via hole.

2. The method for manufacturing a memory according to claim 1, wherein: Before sequentially forming a semiconductor layer, a first dielectric layer, a first conductive layer, and a sacrificial layer covering the protective layer and the inner wall of the first via hole, the method includes: The first conductive film layer on the inner sidewall of the first via hole is etched back so that the etched back first conductive film layer and the adjacent first dielectric film layer enclose each other to form a first groove.

3. The method for manufacturing a memory according to claim 2, wherein: Sequentially forming a semiconductor layer, a first dielectric layer, a first conductive layer, and a sacrificial layer covering the protective layer and the inner wall of the first via hole, wherein the sacrificial layer completely fills the first via hole, includes: Based on the atomic layer deposition process, the semiconductor layer, the first dielectric layer, and the first conductive layer covering the protective layer and the first via hole are sequentially formed; the first conductive layer located in the first via hole encloses a second via hole; Based on the atomic layer deposition process, the sacrificial layer covering the protection layer and filling the second via hole is formed.

4. The method for manufacturing a memory according to claim 3, wherein: The semiconductor layer, the first dielectric layer, and the first conductive layer covering the protective layer and the first via hole are sequentially formed based on an atomic layer deposition process, including: forming the semiconductor layer covering the protection layer and the inner wall of the first via hole simultaneously by a single process, wherein the semiconductor layer includes a second groove located in the first groove; forming the first dielectric layer covering both the protective layer and the semiconductor layer in one process, wherein the first dielectric layer includes a third groove located in the second groove; The first conductive layer covering the protection layer and the first dielectric layer is formed in one process, so that the first conductive layer completely fills the third groove and covers the sidewall of the first via hole, but does not completely fill the first via hole.

5. The method for manufacturing a memory according to claim 4, wherein: After removing the first conductive layer, the first dielectric layer, and the semiconductor layer on the protective layer by etching using the sacrificial structure and the protective layer as etching barriers, and retaining the first conductive structure, the first dielectric structure, and the first semiconductor structure in the first via hole, the method further includes: removing the sacrificial structure; Etching and removing a portion of the first conductive structure in the first via hole to form a gate at least partially located in the first groove; The first dielectric structure and the first semiconductor structure in the first via hole and outside the first groove are removed by etching to form a gate dielectric structure and semiconductor structures corresponding to different memory cells respectively.

6. The method for manufacturing a memory according to claim 5, wherein: Etching and removing a portion of the first conductive structure in the first via hole to form a gate at least partially located in the first groove, comprising: removing a portion of the first conductive structure based on a first etching process to form the gate at least partially located within the third groove, so that the first dielectric structure in each region except the third groove is exposed; and etching away the first dielectric structure and the first semiconductor structure in the first via hole and outside the first groove to form a gate dielectric structure and semiconductor structures corresponding to different memory cells, respectively, including: Using the gate as a mask, the first dielectric structure and the first semiconductor structure are etched based on a second etching process to form the gate dielectric structure and the semiconductor structure located in the first groove; the first dielectric film layer, the gate, the gate dielectric structure and the semiconductor structure enclose a fourth groove.

7. The method for manufacturing a memory according to claim 6, wherein: After etching away the first dielectric structure and the first semiconductor structure in the first via hole and outside the first groove to form a gate dielectric structure and semiconductor structures corresponding to different memory cells, the method further includes: A second dielectric structure is formed to fill the fourth groove, so that an outer wall of the second dielectric structure is coplanar with an inner wall of the first via hole, exposing the gate.

8. The method for manufacturing a memory according to claim 5 or 7, characterized in that: After etching away the first dielectric structure and the first semiconductor structure in the first via hole and outside the first groove to form a gate dielectric structure and semiconductor structures corresponding to different memory cells, the method further includes: A word line is formed to fill the first via hole, so that the word line is connected to all the gates located in the first via hole.

9. The method for manufacturing a memory according to claim 1, wherein: Etching and removing the sacrificial layer on the protective layer and retaining the sacrificial layer in the first via hole, wherein the sacrificial layer in the first via hole is a sacrificial structure, includes: Based on a third etching process, etching the sacrificial layer to expose the first conductive layer located on a side of the protection layer away from the substrate; and, using the sacrificial structure and the protective layer as etching barriers, etching away the first conductive layer, the first dielectric layer, and the semiconductor layer on the protective layer, and retaining the first conductive structure, the first dielectric structure, and the first semiconductor structure located in the first via hole, including: The sacrificial structure is used as a mask and based on a fourth etching process, the first conductive layer, the first dielectric layer, and the semiconductor layer located on the protective layer are removed at one time.

10. A memory, characterized in that: The method for manufacturing the memory according to any one of claims 1 to 9 is obtained, wherein the memory comprises: a plurality of word lines, a plurality of bit lines and a plurality of stacked memory cells; The storage unit includes a field effect transistor and a capacitor distributed and connected along a first direction parallel to the substrate; The bit line extends along a second direction parallel to the substrate and is located in the memory cells of the same layer, and the bit line is connected to the semiconductor structures of the field effect transistors of a column of the memory cells arranged along the second direction; The word line extends along a third direction perpendicular to the substrate, and the word line is connected to gates of the field effect transistors of a group of the memory cells stacked along the third direction.

11. The memory according to claim 10, wherein: The gate, gate dielectric structure and semiconductor structure of the field effect transistor surround the periphery of the word line in sequence.

12. The memory according to claim 10, wherein: Along the first direction, the field effect transistor is located between the bit line and the capacitor; An electrode structure of the capacitor extends along the first direction, and the electrode structure is connected to the semiconductor structure of the field effect transistor.

13. The memory according to claim 10, wherein: In the memory cells located in the same layer, the semiconductor structures of the field effect transistors of two adjacent columns of the memory cells are both connected to the same bit line.

14. An electronic device, characterized in that: include: At least one memory as claimed in any one of claims 10 to 13 above.

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