Display substrate and display panel

Abstract

The invention discloses a display substrate and a display panel. The display substrate comprises a substrate body and a plurality of binding electrodes, the binding electrodes are located on one side of the substrate body, each binding electrode comprises a first conductive layer and a second conductive layer, and the first conductive layers and the second conductive layers are sequentially stacked in the direction away from the substrate body; an insulating layer is arranged between the first conducting layer and the second conducting layer, a via hole is formed in the insulating layer, and the first conducting layer and the second conducting layer are electrically connected through the via hole; the first conductive layer comprises at least two first sub-parts, the at least two first sub-parts are sequentially arranged in the first direction, and a first interval is formed between any two adjacent first sub-parts; the second conductive layer comprises at least two second sub-parts, the at least two second sub-parts are sequentially arranged in the first direction, and a second interval is formed between any two adjacent second sub-parts; orthographic projections of the second sub-part and the first sub-part on the substrate are at least partially overlapped; orthographic projections of the second interval and the first interval on the substrate are at least partially overlapped.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and specifically relate to a display substrate and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display screens have attracted widespread attention due to their advantages such as self-luminescence, low power consumption, lightness, flexibility, bright colors, high contrast, and fast response rate. Summary of the invention

[0003] In a first aspect, an embodiment of the present disclosure provides a display substrate having a binding area.

[0004] The display substrate comprises a base and a plurality of binding electrodes, wherein the plurality of binding electrodes are located on one side of the base and in the binding area; the plurality of binding electrodes are arranged in sequence along a first direction;

[0005] The binding electrode comprises a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are sequentially stacked in a direction away from the substrate;

[0006] An insulating layer is disposed between the first conductive layer and the second conductive layer, a via hole is provided in the insulating layer, and the first conductive layer and the second conductive layer are electrically connected through the via hole;

[0007] The first conductive layer includes at least two first sub-portions, the at least two first sub-portions are arranged in sequence along the first direction, and there is a first interval between any two adjacent first sub-portions;

[0008] The second conductive layer includes at least two second sub-portions, the at least two second sub-portions are arranged in sequence along the first direction, and there is a second interval between any two adjacent second sub-portions;

[0009] The orthographic projections of the second sub-portion and the first sub-portion on the substrate at least partially overlap;

[0010] Orthographic projections of the second interval and the first interval on the substrate at least partially overlap.

[0011] In some embodiments, the orthographic projections of the second sub-portion and the first sub-portion on the substrate coincide;

[0012] The orthographic projections of the second interval and the first interval on the substrate coincide with each other.

[0013] In some embodiments, the orthographic projection of the second sub-portion on the substrate covers the orthographic projection of the first sub-portion on the substrate, and the orthographic projection area of ​​the second sub-portion on the substrate is larger than the orthographic projection area of ​​the first sub-portion on the substrate;

[0014] The orthographic projection of the first interval on the substrate covers the orthographic projection of the second interval on the substrate, and an orthographic projection area of ​​the first interval on the substrate is larger than an orthographic projection area of ​​the second interval on the substrate.

[0015] In some embodiments, the orthographic projection of the first sub-portion on the substrate covers the orthographic projection of the second sub-portion on the substrate, and the orthographic projection area of ​​the first sub-portion on the substrate is larger than the orthographic projection area of ​​the second sub-portion on the substrate;

[0016] The orthographic projection of the second interval on the substrate covers the orthographic projection of the first interval on the substrate, and an orthographic projection area of ​​the second interval on the substrate is larger than an orthographic projection area of ​​the first interval on the substrate.

[0017] In some embodiments, the second subsection corresponds one-to-one to the first subsection;

[0018] The second interval corresponds to the first interval one by one.

[0019] In some embodiments, the first conductive layer further includes a third sub-portion, which is located between two adjacent first sub-portions in any of the binding electrodes and is connected to two adjacent first sub-portions in any of the binding electrodes;

[0020] The orthographic projection of the third sub-portion on the substrate is located within the orthographic projection area of ​​the first interval on the substrate.

[0021] In some embodiments, the orthographic projection shape of the third sub-portion on the substrate includes stripes, a grid, or a surface.

[0022] In some embodiments, orthographic projections of the third sub-portion and the first interval on the substrate coincide with each other.

[0023] In some embodiments, it further includes a gate drive circuit and a plurality of clock signal lines, which are located on the same side of the substrate as the binding electrode, and the plurality of clock signal lines are electrically connected to the gate drive circuit;

[0024] The plurality of clock signal lines are electrically connected to the plurality of binding electrodes in a one-to-one correspondence.

[0025] In some embodiments, the number of the via holes is multiple, and the orthographic projections of the multiple via holes on the substrate are located in the overlapping area of ​​the orthographic projections of the second sub-portion and the first sub-portion on the substrate;

[0026] The plurality of via holes are sequentially arranged at intervals along the second direction;

[0027] The second direction intersects with the first direction.

[0028] In some embodiments, the material of the first conductive layer includes metal and / or metal alloy;

[0029] The material of the second conductive layer includes metal oxide.

[0030] In a second aspect, an embodiment of the present disclosure further provides a display panel, which includes the above-mentioned display substrate.

[0031] In some embodiments, a flexible circuit board and a peripheral driving circuit are also included.

[0032] One end of the flexible circuit board is bound and electrically connected to the peripheral driving circuit, and the other end of the flexible circuit board is bound and electrically connected to the binding electrode in the display substrate.

[0033] In some embodiments, the flexible circuit board includes a binding connection end, and the binding connection end at least partially overlaps with an orthographic projection of the second conductive layer in the binding electrode on the display substrate;

[0034] A conductive adhesive is disposed between the binding connection end and the second conductive layer, and at least a portion of the conductive adhesive's orthographic projection on the display substrate is located in an overlapping region of the orthographic projections of the binding connection end and the second conductive layer on the display substrate.

[0035] Beneficial effects of the present invention: The display substrate provided by the present invention can improve or avoid the accumulation of metal particles precipitated after electrochemical corrosion of the first sub-section under the action of high temperature and high voltage difference in the second interval area between adjacent second sub-sections by setting the second conductive layer of the binding electrode into at least two second sub-sections, and a second interval between any two adjacent second sub-sections; the orthographic projections of the second sub-section and the first sub-section on the substrate at least partially overlap; the orthographic projections of the second interval and the first interval on the substrate at least partially overlap, thereby improving or avoiding the accumulation of metal particles precipitated after electrochemical corrosion of the first sub-section under the action of high temperature and high voltage difference in the second interval area between adjacent second sub-sections; at the same time, it can improve or avoid the accumulation of gold ball particles that rebound in the anisotropic conductive adhesive between the binding electrode and the binding end of the flexible circuit board that are pressed and bound under the action of high temperature and high voltage difference in the second interval area between adjacent second sub-sections; thereby improving or avoiding the sharp increase in the on-resistance at the binding electrode position caused by the accumulation of the precipitated metal particles and the rebounded gold ball particles, thereby reducing the current loss at the binding electrode position, improving the charging rate of the display substrate, and finally improving or avoiding display defects such as horizontal stripes that appear when the display substrate is displayed, thereby improving the display effect of the display substrate.

[0036] The display panel provided by the present invention, by adopting the above-mentioned display substrate, can improve or avoid display defects such as horizontal stripes when the display panel is displaying, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0038] Figure 1a A schematic diagram of a high refresh rate display panel having a display defect with horizontal stripes in the related art;

[0039] Figure 1b A schematic diagram of disassembling a display panel with defective horizontal stripes in the related art;

[0040] Figure 1c A schematic top view of a flexible circuit board binding area of ​​a display panel in the related art;

[0041] Figure 1d for Figure 1c Enlarged top view of the middle Z section;

[0042] Figure 1e along Figure 1d Schematic diagram of the cross section of the AA' section line;

[0043] Figure 1f Schematic diagram of clock signals with two frequencies;

[0044] Figure 1g A driving timing diagram of a gate driving circuit in the related art;

[0045] Figure 1h A schematic diagram of the mechanism of electrochemical corrosion occurring at the binding end of the clock signal line of the gate drive circuit;

[0046] Figure 1i Schematic diagram of the rebound of gold sphere particles in anisotropic conductive adhesive after being flattened;

[0047] Figure 2a A schematic top view of a structure showing a substrate binding area in an embodiment of the present disclosure;

[0048] Figure 2b for Figure 2a An enlarged schematic diagram of part B;

[0049] Figure 2c For along Figure 2b Schematic diagram of the structural section view of the CC' section line;

[0050] Figure 2d for Figure 2a Another enlarged schematic diagram of part B;

[0051] Figure 2e For along Figure 2d Schematic diagram of the structural section view of the DD' section line;

[0052] Figure 2f for Figure 2a Another enlarged schematic diagram of part B;

[0053] Figure 2g For along Figure 2f Schematic diagram of the structural section along the EE' section line;

[0054] Figure 3a It is a schematic top view of another structure showing the substrate binding area in an embodiment of the present disclosure;

[0055] Figure 3b for Figure 3a An enlarged schematic diagram of part F;

[0056] Figure 3c For along Figure 3b Schematic diagram of the structural section view of the GG' section line;

[0057] Figure 3d for Figure 3a Another enlarged schematic diagram of part F;

[0058] Figure 3e for Figure 3a Another enlarged schematic diagram of part F in the middle. DETAILED DESCRIPTION

[0059] In order to enable those skilled in the art to better understand the technical solution of the embodiments of the present disclosure, a display substrate and a display panel provided by the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0060] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms and should not be construed as being limited to the embodiments set forth in the present disclosure. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0061] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions, but are not intended to be limiting.

[0062] In the related art, high refresh rate display panels have appeared such as Figure 1a The horizontal stripe defect phenomenon shown is that horizontal stripes appear on the RGB (red, green, blue) screen. Figure 1b As shown, the screen was disassembled and analyzed for the undesirable phenomenon, and it was found that there was a problem in the flexible circuit board bonding area (COF bonding area) of the display panel. Figure 1b The middle I area is the idle signal line binding end (Dummy Lead) of the flexible circuit board binding area. The idle signal line binding end is composed of a metal layer (such as a copper layer and an alloy layer of molybdenum, nickel and titanium). There is no indium tin oxide layer (ITO) on the metal layer in the spacing area between the idle signal line binding end and the other signal line binding ends on its left and right sides. Microscope observation shows that the gold ball particles in the ACF glue (anisotropic conductive glue) between the idle signal line binding end in the I area and the corresponding binding end of the flexible circuit board after compression bonding are in a normal state of being flattened, and no metal particles (such as copper-containing particles) are precipitated around the idle signal line binding end; Figure 1c , Figure 1d and Figure 1eAs shown, the clock signal line binding end (CLK1-CLK6) 5 of the gate drive circuit in the II region is composed of a bottom metal layer 6 and an indium tin oxide 7 stacked thereon, and the upper indium tin oxide 7 and the bottom metal layer 6 are electrically connected through a via 30 provided in the insulating layer 3 between the two; at the same time, in order to improve the binding connection conduction effect between the clock signal line binding end 5 of the gate drive circuit and the corresponding binding end of the flexible circuit board, one clock signal line 4 generally corresponds to two or more clock signal line binding ends 5, and the two or more clock signal line binding ends 5 are formed by dividing the bottom metal layer 6 into two or more independently arranged bottom metal structures, and the upper layer is a whole surface of indium tin oxide layer, which covers the two or more independently arranged bottom metal structures, and is electrically connected to the two or more independently arranged bottom metal structures through the via 30, that is, the adjacent metal structures independently arranged at the bottom are connected and conducted through the upper indium tin oxide layer. Metal particles are precipitated in the area around the clock signal line binding end 5 of the gate drive circuit in the II region, and the precipitated metal particles are concentrated in the area G3 of the upper indium tin oxide layer corresponding to the adjacent bottom metal structures.

[0063] By comparison, it is found that the difference between area I and area II lies in whether the area between adjacent underlying metal structures is covered by the upper indium tin oxide layer. It is speculated that the occurrence of bad horizontal stripes on the display panel is related to the design of the upper indium tin oxide layer at the binding end; in the display panel, other signal line binding ends of the gate drive circuit in the binding area of ​​the flexible circuit board, such as VSS, LVSS, VDD signal line binding ends, etc., the conductive film layer structure of these signal line binding ends is the same as the clock signal line binding end, but there is no metal particle precipitation in the surrounding area of ​​these signal line binding ends, and there is no situation where the precipitated metal particles are concentrated in the upper indium tin oxide layer corresponding to the area between adjacent underlying metal structures; further research found that: for high refresh rate display panels, the higher the refresh frequency, the higher the current density; the refresh frequency of high refresh rate display panels is generally above 144HZ, and the absolute value of the voltage difference between the high level and the low level of the clock signal in its gate drive circuit is about 38V; such as: Figure 1f As shown, the voltage difference of the clock signal with a frequency of 42.7kHz in a display panel with a refresh rate of 60Hz is about 33V; the voltage difference of the clock signal with a frequency of 85.5kHz in a display panel with a refresh rate of 180Hz is about 38V; as the refresh rate increases, the higher the current density, the more serious the heating problem. Under the combined effects of higher voltage difference, higher current density and more severe heating at the binding end of the clock signal line in the gate drive circuit, the bottom metal layer is prone to electrochemical corrosion and metal particles (such as copper-containing particles) are precipitated, and the precipitated metal particles are concentrated in the area of ​​the upper indium tin oxide layer corresponding to the adjacent bottom metal structure.

[0064] For high refresh rate display panels, the higher the refresh rate, the greater the resistance and capacitance of the display panel, and the more difficult it is to achieve an ideal charging rate. In order to achieve the ideal charging rate of high refresh rate display panels, the bottom metal layer of each signal line binding end in the binding area of ​​the flexible circuit board generally adopts a thick metal process. When the clock signal of the gate drive circuit frequently switches between high and low voltages, electrochemical corrosion will occur at each clock signal line binding end connected to the same clock signal line, and electrochemical corrosion will also occur between adjacent clock signal line binding ends connected to different clock signal lines. Figure 1g The figure shows a driving timing diagram of a gate driving circuit in the related art; wherein, for example, the adjacent clock signal line CLK1 and the clock signal line CLK2 will have moments where the high and low voltages overlap, the clock signal line CLK1 is at a high level in the first 3H (1H, 2H, 3H) time, and the clock signal line CLK2 is at a high level in the next 3H (2H, 3H, 4H) time, and in one cycle of the clock signal (i.e. 6H time), there is 1H time when the clock signal line CLK1 is at a low level and the clock signal line CLK2 is at a high level, and the voltage difference between the adjacent clock signal lines may cause electrochemical corrosion between the two.

[0065] like Figure 1h As shown, it is a schematic diagram of the mechanism of electrochemical corrosion at the clock signal line binding end of the gate drive circuit; the specific process of electrochemical corrosion is: under the action of a relatively high voltage difference, metal particles Q in the bottom metal layer of the clock signal line binding end 5 are precipitated and migrate. At the same time, the high temperature of the display panel with a high refresh rate during operation easily causes bubbles to be generated in the upper indium tin oxide layer in the area G3 corresponding to the area between the two adjacent bottom metal structures at the clock signal line binding end 5, and the metal particles Q precipitated from the bottom metal layer are easily accumulated at the bubble position.

[0066] In addition, the greater the current density, the higher the heat generated at the clock signal line binding end, the higher the temperature at this place, and the higher the temperature, the easier it is to cause the gold ball particles 9 in the anisotropic conductive adhesive between the clock signal line binding end 5 and the corresponding binding end 8 of the flexible circuit board to have a poor pressing effect. After the pressing and binding is completed, the flattened gold ball particles 9 may even rebound (such as Figure 1i As shown in the figure, the rebounding gold ball particles 9 are also easily accumulated in the area between the two adjacent underlying metal structures of the upper indium tin oxide layer corresponding to the clock signal line binding end 5, which makes the on-resistance of the clock signal line binding end 5 and the corresponding binding end 8 of the flexible circuit board after being pressed and bound larger. The increase in on-resistance leads to further increase in heat generation, which is a vicious cycle, and eventually causes the gold ball particles 9 in the anisotropic conductive glue between the clock signal line binding end 5 and the corresponding binding end 8 of the flexible circuit board to burn out and cause conduction NG.

[0067] After the electrochemical corrosion occurs at the binding end of the clock signal line, the metal particles precipitated in the underlying metal layer and the gold ball particles rebounded between the pressed binding end of the clock signal line and the corresponding binding end of the flexible circuit board accumulate in the area between the two adjacent underlying metal structures of the binding end of the clock signal line on the upper indium tin oxide layer, which eventually causes the display panel to have horizontal stripes and other display defects when displaying the picture.

[0068] In order to solve the above problems in the related art, in a first aspect, an embodiment of the present disclosure provides a display substrate, such as Figure 2a , Figure 2b and Figure 2c As shown, there is a binding area 100, the display substrate includes a substrate 1 and a plurality of binding electrodes 2, the plurality of binding electrodes 2 are located on one side of the substrate 1 and are located in the binding area 100; the plurality of binding electrodes 2 are arranged in sequence along a first direction X; the binding electrodes 2 include a first conductive layer 21 and a second conductive layer 22, the first conductive layer 21 and the second conductive layer 22 are stacked in sequence along a direction away from the substrate 1; an insulating layer 3 is provided between the first conductive layer 21 and the second conductive layer 22, a via 30 is provided in the insulating layer 3, and the first conductive layer 21 and the second conductive layer 22 are electrically connected through the via 30; the first conductive layer 21 and the second conductive layer 22 are electrically connected through the via 30; The layer 21 includes at least two first sub-portions 211, and the at least two first sub-portions 211 are arranged in sequence along the first direction X, and a first interval G1 is provided between any two adjacent first sub-portions 211; the second conductive layer 22 includes at least two second sub-portions 221, and the at least two second sub-portions 221 are arranged in sequence along the first direction X, and a second interval G2 is provided between any two adjacent second sub-portions 221; the orthographic projections of the second sub-portion 221 and the first sub-portion 211 on the substrate 1 at least partially overlap; the orthographic projections of the second interval G2 and the first interval G1 on the substrate 1 at least partially overlap.

[0069] The binding electrode 2 can be bound and connected to a binding end at one end of a flexible circuit board (such as a chip-on-film (COF), not shown in the figure); the other end of the flexible circuit board is bound and connected to a peripheral circuit board (such as a whole machine mainboard and a driving circuit thereon, not shown in the figure), so that the peripheral circuit board provides a driving signal to the display substrate. In some embodiments, the binding electrode 2 is bound and connected to a binding end at one end of the flexible circuit board through an anisotropic conductive adhesive (ACF).

[0070] In this embodiment, by setting the binding electrode 2 as two conductive layers, on the one hand, it is easy to realize the binding connection between the binding electrode 2 and the binding end of the flexible circuit board; on the other hand, it can reduce the resistance of the binding electrode 2 itself, thereby reducing the conduction resistance after the binding electrode 2 is bound to the binding end of the flexible circuit board, thereby reducing the line loss and improving the charging rate of the display substrate.

[0071] In some embodiments, the first conductive layer 21 is made of metal conductive materials, such as copper, aluminum, etc. The second conductive layer 22 is made of metal oxide materials, such as indium tin oxide, indium gallium zinc oxide, etc.

[0072] In this embodiment, by setting the second conductive layer 22 of the binding electrode 2 to at least two second sub-portions 221, and having a second gap G2 between any two adjacent second sub-portions 221; the orthographic projections of the second sub-portion 221 and the first sub-portion 211 on the substrate 1 at least partially overlap; the orthographic projections of the second gap G2 and the first gap G1 on the substrate 1 at least partially overlap, it can improve or avoid the accumulation of metal particles precipitated after the first sub-portion 211 is electrochemically corroded under the action of high temperature and high voltage difference in the second gap G2 region between adjacent second sub-portions 221; at the same time, it can improve Or avoid the anisotropic conductive glue between the pressed binding electrode 2 and the binding end of the flexible circuit board from accumulating the rebounded gold ball particles in the second interval G2 area between the adjacent second sub-portions 221 under the action of high temperature and high voltage difference; thereby improving or avoiding the sharp increase in the on-resistance at the binding electrode 2 position caused by the accumulation of precipitated metal particles and rebounded gold ball particles, thereby reducing the current loss at the binding electrode 2 position, improving the charging rate of the display substrate, and finally improving or avoiding the display defects such as horizontal stripes that appear on the display substrate during display, thereby improving the display effect of the display substrate.

[0073] In some embodiments, Figure 2b and Figure 2c As shown, the orthographic projections of the second sub-portion 221 and the first sub-portion 211 on the substrate 1 coincide with each other; and the orthographic projections of the second interval G2 and the first interval G1 on the substrate 1 coincide with each other.

[0074] In some embodiments, Figure 2d and Figure 2e As shown, the orthographic projection of the second sub-portion 221 on the substrate 1 covers the orthographic projection of the first sub-portion 211 on the substrate 1, and the orthographic projection area of ​​the second sub-portion 221 on the substrate 1 is larger than the orthographic projection area of ​​the first sub-portion 211 on the substrate 1; the orthographic projection of the first interval G1 on the substrate 1 covers the orthographic projection of the second interval G2 on the substrate 1, and the orthographic projection area of ​​the first interval G1 on the substrate 1 is larger than the orthographic projection area of ​​the second interval G2 on the substrate 1.

[0075] In some embodiments, Figure 2f and Figure 2gAs shown, the orthographic projection of the first sub-portion 211 on the substrate 1 covers the orthographic projection of the second sub-portion 221 on the substrate 1, and the orthographic projection area of ​​the first sub-portion 211 on the substrate 1 is larger than the orthographic projection area of ​​the second sub-portion 221 on the substrate 1; the orthographic projection of the second interval G2 on the substrate 1 covers the orthographic projection of the first interval G1 on the substrate 1, and the orthographic projection area of ​​the second interval G2 on the substrate 1 is larger than the orthographic projection area of ​​the first interval G1 on the substrate 1.

[0076] In some embodiments, the second sub-section 221 corresponds to the first sub-section 211 one-to-one; the second interval G2 corresponds to the first interval G1 one-to-one. In this way, the metal particles precipitated after the electrochemical corrosion of the first sub-section 211 under the action of high temperature and high voltage difference can be better improved or avoided to accumulate in the second interval G2 area between adjacent second sub-sections 221; at the same time, the anisotropic conductive adhesive between the pressed binding electrode 2 and the binding end of the flexible circuit board under the action of high temperature and high voltage difference can be better improved or avoided to accumulate in the second interval G2 area between adjacent second sub-sections 221; thereby improving or avoiding the sharp increase in the on-resistance at the binding electrode 2 position caused by the accumulation of the precipitated metal particles and the rebounded gold ball particles, thereby reducing the current loss at the binding electrode 2 position and improving the charging rate of the display substrate.

[0077] In some embodiments, Figure 3a , Figure 3b and Figure 3c As shown, the first conductive layer 21 also includes a third sub-portion 212, which is located between two adjacent first sub-portions 211 in any binding electrode 2 and connected to two adjacent first sub-portions 211 in any binding electrode 2; the orthographic projection of the third sub-portion 212 on the substrate 1 is located within the orthographic projection area of ​​the first interval G1 on the substrate 1.

[0078] Among them, the setting of the third sub-section 212 can further reduce the resistance of the first conductive layer 21 of the binding electrode 2, thereby further reducing the resistance of the binding electrode 2, and further reducing the conduction resistance between the binding electrode 2 and the binding end of the flexible circuit board, compared with the solution in which the third sub-section 212 is not set between adjacent first sub-sections 211.

[0079] In some embodiments, the orthographic projection shape of the third sub-portion 212 on the substrate 1 includes stripes (eg Figure 3d As shown), grid-like (as Figure 3e as shown) or surface (as shown Figure 3b shown).

[0080] In some embodiments, Figure 3dAs shown, the third sub-section 212 may be a strip electrode or multiple strip electrodes disposed between any two adjacent first sub-sections 211, such as multiple strip-shaped third sub-sections 212 disposed parallel to each other. In some embodiments, the grid-shaped third sub-section 212 may be a grid of any shape.

[0081] In some embodiments, Figure 3b As shown, the orthographic projections of the third sub-portion 212 and the first gap G1 on the substrate 1 coincide. This arrangement can reduce the resistance of the first conductive layer 21 of the binding electrode 2 to a greater extent, thereby reducing the resistance of the binding electrode 2 to a greater extent, and further reducing the conduction resistance between the binding electrode 2 and the binding end of the flexible circuit board to a greater extent.

[0082] In some embodiments, Figure 2a and Figure 3a As shown, the display substrate also includes a gate driving circuit (i.e., GOA, GateDriver on Array, not shown in the figure) and a plurality of clock signal lines 4, which are located on the same side of the substrate 1 as the binding electrodes 2, and the plurality of clock signal lines 4 are electrically connected to the gate driving circuit; the plurality of clock signal lines 4 are electrically connected to the plurality of binding electrodes 2 in a one-to-one correspondence.

[0083] Among them, in a display substrate with a high refresh rate, since the absolute value of the voltage difference between the high and low levels of the clock signal transmitted by the clock signal line 4 is large, and the high refresh rate increases the current density of the clock signal, the binding electrode 2 electrically connected to the clock signal line 4 and the binding end of the flexible circuit board are severely heated during driving after being bound and connected, which is more likely to cause display defects such as horizontal stripes on the display substrate. Therefore, the binding electrode 2 electrically connected to the clock signal line 4 adopts the structural design in this embodiment, which can greatly improve or avoid display defects such as horizontal stripes on the display substrate during display.

[0084] In some embodiments, Figure 2a and Figure 3a As shown, there are multiple vias 30, and the orthographic projections of the multiple vias 30 on the substrate 1 are located in the overlapping area of ​​the orthographic projections of the second sub-section 221 and the first sub-section 211 on the substrate 1; the multiple vias 30 are arranged in sequence along the second direction Y; the second direction Y intersects with the first direction X.

[0085] The provision of the plurality of vias 30 can, on the one hand, enable reliable electrical connection between the first conductive layer 21 and the second conductive layer 22 of the binding electrode 2 , and on the other hand, can also increase the cross-sectional area of ​​the binding electrode 2 , thereby reducing the resistance of the binding electrode 2 itself.

[0086] In some embodiments, the orthographic projection shape of the via hole 30 on the substrate 1 can be any shape such as a circle, an ellipse, a strip, etc.

[0087] In some embodiments, the material of the first conductive layer 21 includes metal and / or metal alloy; the material of the second conductive layer 22 includes metal oxide. For example, the first conductive layer 21 includes a copper layer and an alloy layer of molybdenum (accounting for 60%), nickel (accounting for 20%) and titanium (accounting for 20%) stacked on the upper and lower surfaces of the copper layer. The alloy layer has the characteristics of high strength, corrosion resistance, high temperature resistance, oxidation resistance, high elongation, etc., and the corrosion and oxidation resistance of the alloy layer is better than that of the copper layer. It can prevent the copper layer from being oxidized and diffused by adhering to the surface of the copper layer, and can also prevent the diffused particles (copper-containing particles) of oxidized copper from piercing the gate insulating layer located thereon. The material of the second conductive layer 22 is, for example, indium tin oxide or indium gallium zinc oxide.

[0088] The second conductive layer 22 is in direct contact with the binding end of the flexible circuit board and is connected by pressing with anisotropic conductive adhesive.

[0089] In some embodiments, the first conductive layer 21 of the binding electrode 2, the second conductive layer 22 and the via hole 30 in the insulating layer 3 are all prepared by conventional patterning processes, which will not be described in detail herein.

[0090] The display substrate provided in the present embodiment can improve or avoid the accumulation of metal particles precipitated after electrochemical corrosion of the first sub-section under the action of high temperature and high voltage difference in the second interval area between adjacent second sub-sections by setting the second conductive layer of the binding electrode into at least two second sub-sections, and a second interval between any two adjacent second sub-sections; the orthographic projections of the second sub-section and the first sub-section on the substrate at least partially overlap; the orthographic projections of the second interval and the first interval on the substrate at least partially overlap, thereby improving or avoiding the accumulation of metal particles precipitated after electrochemical corrosion of the first sub-section under the action of high temperature and high voltage difference in the second interval area between adjacent second sub-sections; and at the same time, improving or avoiding the accumulation of gold ball particles rebounding in the anisotropic conductive adhesive between the binding electrode and the binding end of the flexible circuit board under the action of high temperature and high voltage difference in the second interval area between adjacent second sub-sections; thereby improving or avoiding the sharp increase of the on-resistance at the binding electrode position caused by the accumulation of the precipitated metal particles and the rebounding gold ball particles, thereby reducing the current loss at the binding electrode position, improving the charging rate of the display substrate, and finally improving or avoiding the display defects such as horizontal stripes that appear on the display substrate during display, thereby improving the display effect of the display substrate.

[0091] In a second aspect, an embodiment of the present disclosure further provides a display panel, comprising the display substrate in the above embodiment.

[0092] In some embodiments, the display panel further includes a flexible circuit board (such as a chip on film, i.e., COF) and a peripheral driving circuit (such as a complete mainboard and a driving circuit thereon), one end of the flexible circuit board is bound and electrically connected to the peripheral driving circuit, and the other end of the flexible circuit board is bound and electrically connected to a binding electrode in the display substrate, so that the peripheral driving circuit provides a driving signal to the display substrate.

[0093] In some embodiments, the flexible circuit board includes a binding connection end, and the binding connection end at least partially overlaps with the orthographic projection of the second conductive layer in the binding electrode on the display substrate; a conductive glue is arranged between the binding connection end and the second conductive layer, and at least part of the orthographic projection of the conductive glue on the display substrate is located in the overlapping area of ​​the orthographic projection of the binding connection end and the second conductive layer on the display substrate.

[0094] In some embodiments, the conductive glue includes anisotropic conductive glue, which contains gold sphere particles, and the gold sphere particles in the anisotropic conductive glue are flattened at the pressing and binding position of the binding connection end and the binding electrode, thereby achieving electrical conduction between the binding connection end and the binding electrode.

[0095] The display panel provided in this embodiment, by adopting the display substrate in the above embodiment, can improve or avoid display defects such as horizontal stripes when the display panel is displaying, thereby improving the display effect of the display panel.

[0096] The display panel provided in the embodiments of the present disclosure may be any product or component with a display function, such as an OLED panel, an LCD panel, an OLED TV, an OLED billboard, a display, a mobile phone, a navigator, or the like.

[0097] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate having a binding area, The display substrate comprises a base and a plurality of binding electrodes, wherein the plurality of binding electrodes are located on one side of the base and in the binding area; the plurality of binding electrodes are arranged in sequence along a first direction; The binding electrode comprises a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are sequentially stacked in a direction away from the substrate; An insulating layer is disposed between the first conductive layer and the second conductive layer, a via hole is provided in the insulating layer, and the first conductive layer and the second conductive layer are electrically connected through the via hole; The first conductive layer includes at least two first sub-portions, the at least two first sub-portions are arranged in sequence along the first direction, and there is a first interval between any two adjacent first sub-portions; It is characterized in that The second conductive layer includes at least two second sub-portions, the at least two second sub-portions are arranged in sequence along the first direction, and there is a second interval between any two adjacent second sub-portions; The orthographic projections of the second sub-portion and the first sub-portion on the substrate at least partially overlap; Orthographic projections of the second interval and the first interval on the substrate at least partially overlap.

2. The display substrate according to claim 1, characterized in that: The orthographic projections of the second sub-portion and the first sub-portion on the base coincide with each other; The orthographic projections of the second interval and the first interval on the substrate coincide with each other.

3. The display substrate according to claim 1, characterized in that: The orthographic projection of the second sub-portion on the substrate covers the orthographic projection of the first sub-portion on the substrate, and the orthographic projection area of ​​the second sub-portion on the substrate is larger than the orthographic projection area of ​​the first sub-portion on the substrate; The orthographic projection of the first interval on the substrate covers the orthographic projection of the second interval on the substrate, and an orthographic projection area of ​​the first interval on the substrate is larger than an orthographic projection area of ​​the second interval on the substrate.

4. The display substrate according to claim 1, characterized in that: The orthographic projection of the first sub-portion on the substrate covers the orthographic projection of the second sub-portion on the substrate, and the orthographic projection area of ​​the first sub-portion on the substrate is larger than the orthographic projection area of ​​the second sub-portion on the substrate; The orthographic projection of the second interval on the substrate covers the orthographic projection of the first interval on the substrate, and an orthographic projection area of ​​the second interval on the substrate is larger than an orthographic projection area of ​​the first interval on the substrate.

5. The display substrate according to any one of claims 1 to 4, characterized in that: The second sub-section corresponds to the first sub-section one by one; The second interval corresponds to the first interval one by one.

6. The display substrate according to any one of claims 1 to 4, characterized in that: The first conductive layer further includes a third sub-portion, which is located between two adjacent first sub-portions in any of the binding electrodes and is connected to two adjacent first sub-portions in any of the binding electrodes; The orthographic projection of the third sub-portion on the substrate is located within the orthographic projection area of ​​the first interval on the substrate.

7. The display substrate according to claim 6, characterized in that: The orthographic projection shape of the third sub-portion on the substrate includes stripes, a grid or a surface.

8. The display substrate according to claim 6, characterized in that: The orthographic projections of the third sub-portion and the first interval on the substrate coincide with each other.

9. The display substrate according to any one of claims 1 to 4, characterized in that: Also comprising a gate drive circuit and a plurality of clock signal lines, which are located on the same side of the substrate as the binding electrode, and the plurality of clock signal lines are electrically connected to the gate drive circuit; The plurality of clock signal lines are electrically connected to the plurality of binding electrodes in a one-to-one correspondence.

10. The display substrate according to any one of claims 1 to 4, characterized in that: There are multiple via holes, and the orthographic projections of the multiple via holes on the substrate are located in the overlapping area of ​​the orthographic projections of the second sub-portion and the first sub-portion on the substrate; The plurality of via holes are sequentially arranged at intervals along the second direction; The second direction intersects with the first direction.

11. The display substrate according to claim 1, characterized in that: The material of the first conductive layer includes metal and / or metal alloy; The material of the second conductive layer includes metal oxide.

12. A display panel, characterized in that: A display substrate comprising any one of claims 1-11.

13. The display panel according to claim 12, characterized in that: It also includes flexible circuit boards and peripheral drive circuits. One end of the flexible circuit board is bound and electrically connected to the peripheral driving circuit, and the other end of the flexible circuit board is bound and electrically connected to the binding electrode in the display substrate.

14. The display panel according to claim 13, characterized in that: The flexible circuit board comprises a binding connection end, and the binding connection end at least partially overlaps with the orthographic projection of the second conductive layer in the binding electrode on the display substrate; A conductive adhesive is disposed between the binding connection end and the second conductive layer, and at least a portion of the conductive adhesive's orthographic projection on the display substrate is located in an overlapping region of the orthographic projections of the binding connection end and the second conductive layer on the display substrate.

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