Integrated circuit with inductor in magnetic package

Abstract

In one example, an integrated circuit (200) includes: a substrate (206); a semiconductor die (104); a metal interconnect (130, 132, 134, 136), the semiconductor die being mounted to the substrate via the metal interconnect; an inductor (202) mounted to the substrate; and a magnetic material (208) encapsulating the semiconductor die, the inductor, and the metal interconnect, the magnetic material comprising: coated metal particles (510, 512, 514, 520, 522, 524, 526, 528, 530, 532) coated with a first insulating material; and a second insulating material (533) in which the coated metal particles are suspended.

Description

Background Art

[0001] Inductors can store energy in a magnetic field when current flows through them, and can provide current by discharging the stored energy. Inductors can have many applications, such as proximity sensing, energy storage, actuation, power transmission, and filtering. Inductors can be coupled to or can be part of an integrated circuit, which can include circuitry that operates with the inductor to support those applications. In some examples, the inductor and circuitry can be enclosed in an integrated circuit package, which can reduce the footprint of the integrated circuit and shorten the interconnects between the inductor and the circuitry. Summary of the invention

[0002] An integrated circuit includes: a substrate, a semiconductor die, a metal interconnection, an inductor, and a magnetic material. The semiconductor die is mounted to the substrate via the metal interconnection. The inductor is mounted to the substrate. The magnetic material encapsulates the semiconductor die, the inductor, and the metal interconnection, and the magnetic material includes: coated metal particles coated with a first insulating material; and a second insulating material in which the coated metal particles are suspended.

[0003] A method includes: mounting a semiconductor die to a substrate, and mounting an inductor to the substrate. The method further includes depositing a magnetic material on the semiconductor die and the inductor, the magnetic material including: coated metal particles coated with a first insulating material; and a second insulating material in which the coated metal particles are suspended. The method further includes molding the magnetic material, and cutting the magnetic material and the substrate to form an integrated circuit including the corresponding semiconductor die and the inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A and 1B is a schematic diagram of an example integrated circuit.

[0005] Figure 2A , Figure 2B , Figures 3A to 3C and Figures 4A to 4C A schematic diagram of an example of an integrated circuit.

[0006] Figure 5A , Figure 5B and Figure 5C Schematic diagram illustrating the structure of an example magnetic material encapsulated package.

[0007] Fig. 6A and Figure 6B FIG. 1 is a schematic diagram illustrating the structure of another example of a magnetic material encapsulated package.

[0008] Figure 7 FIG. 1 is a schematic diagram illustrating the structure of another example of a magnetic material encapsulated package.

[0009] Figure 8 FIG. 1 is a schematic diagram illustrating the structure of another example of a magnetic material encapsulated package.

[0010] Fig. 9 A flow chart of an example method for fabricating an integrated circuit.

[0011] Fig. 9 A flow chart of an example method for producing a magnetic material.

[0012] Fig.10 For illustration Fig. 9 A diagram of the various operations of the instance method.

[0013] Fig.11 A flow chart of an example method for fabricating an integrated circuit.

[0014] Figures 12A to 12G For illustration Fig.11 A diagram of the various operations of the instance method. DETAILED DESCRIPTION

[0015] Figure 1A and Figure 1B is a schematic diagram illustrating an example integrated circuit 100 . Figure 1A and Figure 1B The perspective view and the side view of the integrated circuit 100 are respectively illustrated. Figure 1A and Figure 1B , the integrated circuit 100 may include an inductor 102 and a semiconductor die 104 mounted to a packaging substrate 106 and encapsulated in an encapsulation package 108. The inductor 102 may include a metal coil surrounding a core. Examples of the inductor core may include an air core, a ferrite core, or a metal particle core. The inductor 102 may also be a molded inductor, wherein the coil and the core may be encapsulated in a package made of a molding compound, such as a magnetic molding compound (MMC) having metal particles (e.g., iron particles) and an insulating material (e.g., a polymer resin) in which the metal particles are suspended. The encapsulation package 108 may shield the coil and the core and increase the magnetic field density, which may improve the efficiency of the inductor 102 in converting between electrical energy and magnetic energy. In addition, the encapsulation package 108 may include a molding compound, such as an epoxy molding compound (EMC), which may electrically insulate the inductor 102 and the semiconductor die 104 from external electrical signals (such as noise signals and electrostatic signals).

[0016] Semiconductor die 104 and inductor 102 may form a system that supports specific applications, such as proximity sensing, energy storage, actuation, power transmission, and filtering. For example, integrated circuit 100 may include a proximity sensor, wherein semiconductor die 104 may include an oscillator and a sensing circuit. The oscillator may drive inductor 102 with an oscillating current signal, and the sensing circuit may sense the frequency of the current signal. A metal object approaching inductor 102 may change the inductance of inductor 102, thereby changing the frequency of the current signal. The sensing circuit may detect the metal object by detecting the frequency change. As another example, integrated circuit 100 may include a switch mode power converter to transfer power from a power source to a load. In such examples, inductor 102 may provide energy storage, and semiconductor die 104 may include a switch to charge and discharge inductor 102 to set the voltage across the load.

[0017] In addition, the package substrate 106 can provide mechanical support to the inductor 102 and the semiconductor die 104, and provide electrical connections between the inductor and the semiconductor die, and between the integrated circuit 100 and external devices. For example, the package substrate 106 can include an electrically insulating material such as a polymer, an Ajinomoto Build-up Film (ABF), or a ceramic material. The package substrate 106 can also include metal pads 110, 112, 114, 116, and 118, which can be copper pads, located on a surface 120 where the inductor 102 and the semiconductor die 104 are mounted.

[0018] In addition, the semiconductor die 104 may include a passivation layer 122, which may be coupled to metal pads 110, 112, 114, and 116 via respective metal interconnects 130, 132, 134, and 136. Each pad may be coupled to a respective metal interconnect via a solder layer. The passivation layer 122 may insulate the circuitry in the semiconductor die 104 from the metal interconnects 130, 132, 134, and 136. The metal interconnects 130 to 136 may include, for example, copper pillars, solder bumps, and under-bump metallization (UBM) interconnects. In addition, the inductor 102 may be coupled to the metal pad 118 via a solder layer. The package substrate 106 may include metal interconnects located on or below the surface 120 to provide electrical connections between the inductor 102 and the semiconductor die 104, such as a metal interconnect 140 between the metal pads 116 and 118.

[0019] The packaging substrate 106 may also include metal pads on a surface 150 opposite to the surface 120, such as metal pads 160, 162, and 164, which may include one or more copper pads made of other metals (e.g., silver or palladium). The packaging substrate 106 may also include metal interconnects, such as copper interconnects, to provide electrical connections between the metal pads on the opposite surfaces. For example, the packaging substrate 106 may include a metal interconnect 170 between the metal pads 110 and 160, a metal interconnect 172 between the metal pads 112 and 162, and a metal interconnect 174 between the metal pads 114 and 164. The metal pads and interconnects on the surface 150 may provide electrical connections between external devices and the integrated circuit 100. For example, metal pads 160, 162, and 164 may be coupled to a printed circuit board (PCB) 176 via respective solder balls 180, 182, and 184, which may provide electrical connections between the integrated circuit 100 and external devices (e.g., a power source) on the PCB 176. The package substrate 106 may also include a solder resist layer 190 on the surface 150 to shield metal interconnects (e.g., metal interconnects 170, 172, and 174) in the package substrate from the solder balls.

[0020] Figure 2A Description and Figure 1A and 1B An example of an integrated circuit 200 may have a reduced footprint compared to the integrated circuit 100 . Figure 2A A side view of integrated circuit 200 is illustrated. Figure 2A , the integrated circuit 200 may include an inductor 202 and a semiconductor die 104 mounted to a packaging substrate 206. The integrated circuit 200 may also include a magnetic material (e.g., MMC) on the packaging substrate 206. The magnetic material may serve as an encapsulation package 208 to encapsulate the inductor 202 and the semiconductor die 104. In some instances, the packaging substrate 206 may include a routable lead frame (RLF). The inductor 202 may include: a coil portion 210, which may include various types of cores, such as a ferrite core and a metal particle core; and pillar portions 212a and 212b, which support the coil portion 210 above the packaging substrate 206. In addition, the semiconductor die 104 may be positioned between the pillar portions 212a and 212b and below the coil portion 210, so that the coil portion 210 and the semiconductor die 104 may form a device stack. In some instances, the coil portion 210 may have an opening facing laterally (e.g., along the x / y axis), such as Figures 3A to 3C In some examples, the coil portion 210 may have an opening facing upward / downward (eg, along the z-axis) above the semiconductor die 104, such as Figures 4A to 4C As shown in .

[0021] The package substrate 206 may include metal pads 220, 222, 224, 226, 228, and 230, which may be copper pads, on a surface 232 to which the inductor 202 and the semiconductor die 104 are attached. The integrated circuit 200 may include metal interconnects 130, 132, 134, and 136 of the semiconductor die 104, which may be coupled to the respective metal pads 222, 224, 226, and 228 via a solder layer. In addition, the pillars 212a and 212b of the inductor 202 may be coupled to the respective metal pads 220 and 230 via a solder layer.

[0022] The package substrate 206 may also include metal pads located on a surface 250 opposite the surface 232, such as metal pads 252, 254, 256, and 258, which may include one or more copper pads made of other metals (e.g., silver and palladium). The metal pads 252, 254, 256, and 258 may be coupled to an external device via solder balls (such as the PCB 176 and solder balls 180 to 184 of FIG. 1) to provide electrical connections between the integrated circuit 200 and the external device. The package substrate 206 may also include metal interconnects, such as copper interconnects, connected between metal pads on the same or different surfaces. For example, the package substrate 206 may include a metal interconnect 260 coupled between metal pads 220 and 222 (on the surface 232) to provide electrical connections between the inductor 202 and the semiconductor die 104. The package substrate 206 may also include a metal interconnect 262 coupled between the metal pads 224 and 252, a metal interconnect 264 coupled between the metal pads 226 and 254, a metal interconnect 266 coupled between the metal pads 228 and 256, and a metal interconnect 268 coupled between the metal pads 230 and 258 to provide electrical connections between external devices and the inductor 202 and / or the semiconductor die 104. The package substrate 206 may include an electrically insulating layer 269, such as a polymer, ABF, or ceramic material, to provide electrical insulation among the metal interconnects and the metal pads. In addition, the package substrate 206 may include a solder mask 270 located below the surface 250 to shield the metal interconnects (e.g., metal interconnects 260, 262, 264, 266, and 268) in the package substrate from solder balls and external devices.

[0023] In addition, as described above, the inductor 202 and the semiconductor die 104 can be encapsulated in the encapsulation package 208 on the packaging substrate 206. The encapsulation package 208 may include a magnetic material, such as MMC. The MMC may have metal particles (e.g., iron particles) and an insulating material (e.g., a polymer resin) in which the metal particles are suspended. The encapsulation package 208 can shield the inductor 202 and increase the magnetic field density, which can improve the efficiency of the inductor 202 in converting between electrical energy and magnetic energy. The MMC material of the encapsulation package 208 can fill the space within the inductor 202, such as the center of the coil portion 210 (e.g., if the inductor 202 has an air core) and the space between the individual coils of the coil portion 210. The MMC material can also fill the space between the coil portion 210 and the semiconductor die 104 and between the metal interconnects 130, 132, 134, and 136.

[0024] Figure 2B Another example of integrated circuit 200 is described. Figure 2B , semiconductor die 104 may be positioned outside and adjacent to inductor 202. Integrated circuit 200 may include another circuit component, such as capacitor 280, positioned below coil portion 210 and pillar portions 212a and 212b, such that coil portion 210 and capacitor 280 may form a device stack. In some examples, semiconductor die 104 and capacitor 280 may be positioned below coil portion 210 and pillar portions 212a and 212b to form a device stack.

[0025] In addition to the metal pads 220-230 located on the surface 232 to which the semiconductor die 104 and the capacitor 280 are attached, the package substrate 206 may also include a metal pad 234 (e.g., a copper pad). The integrated circuit 200 may include metal interconnects 130, 132, and 136 (e.g., copper pillars, solder bumps, or UBM interconnects) coupled between the semiconductor die 104 and the respective metal pads 222, 224, and 226 of the package substrate 206. In addition, the integrated circuit 200 may include metal interconnects 282 and 284 (e.g., copper pillars, solder bumps, or UBM interconnects) coupled between the capacitor 280 and the respective metal pads 228 and 234. The package substrate 206 may also include metal interconnects coupled between the metal pads on the surface 232 and the surface 250 to provide external access to the semiconductor die 104, the inductor 202, and the capacitor 280. For example, package substrate 206 may include metal interconnect 262 coupled between metal pads 222 and 252, metal interconnect 264 coupled between metal pads 224 and 254, metal interconnect 266 coupled between metal pads 228 and 256, and metal interconnect 268 coupled between metal pads 230 and 258. Package substrate 206 may also include metal interconnect 260 coupled among metal pads 220, 226, and 228 to provide internal electrical connections among semiconductor die 104, inductor 202, and capacitor 280.

[0026] By placing the semiconductor die 104 and / or the capacitor 280 below the coil portion 210 of the inductor 202, Figure 2A and Figure 2B The integrated circuit 200 may have a reduced footprint (eg, in the xy plane), which may also shorten the metal interconnects (eg, metal interconnects 260 ) between the semiconductor die 104 and the inductor 202 and reduce their parasitic capacitance. Figure 2A and Figure 2B The arrangement also allows the coil portion of the inductor to cover a majority of the footprint of the integrated circuit 200, and a larger inductor with increased inductance can be included in the integrated circuit 200. In addition, by encapsulating the inductor 202 in the MMC encapsulation package, the magnetic field density within the integrated circuit 200 can be increased, which can improve the efficiency of the inductor 202 in converting between electrical energy and magnetic energy.

[0027] The integrated circuit 200 may be manufactured by mounting a plurality of electronic components (e.g., semiconductor die 104, inductor 202, and / or capacitor 280) to a substrate; depositing an MMC material onto the electronic components and the substrate; molding and hardening the MMC material to form an encapsulation package; and then cutting the molded and hardened MMC material and the substrate into a plurality of integrated circuits 200, such that each integrated circuit 200 may include a set of electronic components (e.g., semiconductor die 104, inductor 202, and / or capacitor 280) mounted to a substrate 206 and encapsulated by an MMC encapsulation package 208.

[0028] Although the MMC encapsulation package can increase the magnetic field density within the integrated circuit 200, the cutting operation can change the structure of the MMC material on the cut surface and reduce the electrical breakdown voltage through the MMC material. Due to the reduced electrical breakdown voltage, the relatively small voltage difference between the metal interconnects can be sufficient to cause leakage current to flow through the MMC material between the metal interconnects, which can increase the risk of electrical short circuits. Therefore, the functionality, reliability, and safety of the integrated circuit 200 may be compromised.

[0029] Figures 5A to 5C FIG. 2 is a schematic diagram illustrating an example structure of an MMC material encapsulating the package 208 of the integrated circuit 200 . Figure 5A and Figure 5B A first view of the MMC encapsulation package 208 and substrate 206 from the x-axis is illustrated, wherein the cut surfaces 502 and 504 are in the xz plane. In addition, Figure 5C illustrate Figure 5A or Figure 5B FIG. 5 is a second view of the MMC encapsulated package 208 and substrate 206 viewed from the y-axis (and including the cut surface 502). The MMC encapsulated package 208 and substrate 206 may encapsulate an electronic device 506. Figure 5A In an example, the electronic device 506 may include Figure 2A The semiconductor die 104, the inductor 202, and the metal interconnects 130 to 136 are provided, wherein the semiconductor die 104 is positioned between the pillar portions 212a and 212b of the inductor 202 and below the coil portion 210. Figure 5B In an example, the electronic device 506 may include Figure 2B The semiconductor die 104, the inductor 202, the capacitor 280, and the metal interconnects 132, 134, 282, and 284 are shown, wherein the capacitor 280 is positioned between the pillar portions 212a and 212b of the inductor 202 and below the coil portion 210, and the semiconductor die 104 is positioned adjacent to the inductor 202. Fig. 6A In FIG. 5 , for simplicity, the electronic device 506 is represented by a dotted box.

[0030] refer to FIG. 5A to FIG. 5C, the MMC material encapsulating package 208 may include metal particles (e.g., iron particles) suspended in epoxy resin 533, such as metal particles 510, 512, 514, 520, 522, 524, 526, 528, 530, and 532. Figure 5A , metal particles 510, 512, 514, 520, 522, and 524 are separated by epoxy, which can reduce electrical leakage through the metal particles (and increase resistance). For example, there can be a leakage current path 535 through metal particles 510, 512, and 514 between metal interconnects 534 and 536, and there can be a leakage current path 542 through metal particles 520, 522, and 524 between metal interconnects 544 and 546. However, because the metal particles are separated by epoxy, which has a relatively high breakdown voltage (e.g., compared to air), the two leakage current paths can have high resistance, and very little leakage current can flow between the metal interconnects through the metal particles and the epoxy.

[0031] However, the cutting operation may remove some of the resin on the cut surfaces 502 and 504, which may expose the metal particles on the cut surfaces and reduce the resistance of the leakage current path through those metal particles. For example, metal particles 526 and 528 on the cut surface 502 and metal particles 530 and 532 on the cut surface 504 may be exposed by removing epoxy 533. Thus, portions of metal particles 526 and 528 may be separated by air gaps 550, and portions of metal particles 530 and 532 may be separated by air gaps 552. Because air may have a lower breakdown voltage than epoxy, the metal particles exposed on the cut surfaces 502 / 504 may provide a leakage current path with reduced resistance. For example, referring to Figure 5C , the resistance of leakage current path 560 located between metal interconnects 562 and 564 and passing through metal particles 566, 532, 530, 568, 570, 572 and 574 and the air gaps between those metal particles can be reduced, thereby causing potential electrical shorts and compromising the functionality, reliability and safety of integrated circuit 200.

[0032] Fig. 6A and Figure 6B Example MMC materials are described that may address at least some of the issues described above. Fig. 6A and Figure 6B, some or all of the metal particles of the MMC material may be coated metal particles coated with an insulating layer 602, and the coated metal particles are suspended in the epoxy resin 533. The insulating layer 602 may include a material with a high breakdown voltage, such as silicon dioxide (e.g., glass) or a metal phosphate (e.g., iron phosphate). The insulating layer 602 can provide electrical insulation, which can increase the electrical insulation provided by the epoxy resin 533 and increase the breakdown voltage of the MMC material. In addition, for metal particles (e.g., metal particles 526, 528, 530, and 532) exposed on the cut surfaces 502 and 504 and separated by air gaps, the insulating layer 602 can also increase the electrical insulation provided by the air gaps. Therefore, the leakage current path through the exposed metal particles, such as Figure 6B The leakage current path 560 between the metal interconnects 562 and 564 in FIG. 2 may have a high resistance, which may reduce potential electrical shorts and improve the functionality, reliability, and safety of the integrated circuit 200 .

[0033] Figure 7 and Figure 8 Additional example MMC materials that can reduce leakage along cut surfaces are described. Figure 7 , some of the metal particles of the MMC material on the cut surface (e.g., cut diced surface 504) may be removed to create cavities between the remaining metal particles, such as cavities 702, 704, 706, 708, 710, and 712. The cavities may be filled with an insulating material (e.g., air or epoxy) to provide additional electrical insulation between the metal particles, which may increase the breakdown voltage and resistance of the current leakage paths through the metal particles. For example, cavity 702 may be along leakage current path 560 between metal particles 566 and 530, cavity 704 may be along leakage current path 560 between metal particles 530 and 570, and cavity 706 may be along leakage current path 560 between metal particles 570 and 574. The insulating material in cavities 702, 704, and 706 may increase the resistance of leakage current path 560 and reduce the amount of leakage current between metal interconnects 562 and 564. In addition, as Figure 8 As shown in , at least some of the metal particles that remain on the cut surface, such as metal particles 530, 566, 570, and 574, may each be coated with an insulating layer 602, which may further increase the breakdown voltage of the MMC material and reduce potential electrical shorts.

[0034] Fig. 9 and Fig.10 Description Fig. 6A and Figure 6B Examples of MMC materials and methods. Fig. 9 A flowchart 900 illustrating an example method of producing an MMC material, and Fig.10 For explanation Fig. 9Schematic diagram of some operations of the instance method.

[0035] refer to Fig. 9 In operation 902, metal particles (eg, iron particles) may be mixed with a solvent to form a mixture. Fig.10 In sub-operation 902a, metal particles 1002 may be added to a solvent 1004, such as water or an organic solvent (e.g., alcohol and kerosene), and then in sub-operation 902b, the metal particles 1002 and the solvent 1004 may be mixed and stirred to become a viscous slurry 1006, in which the metal particles 1002 may be suspended in the solvent 1004.

[0036] In operation 904, at least some of the metal particles may be coated with a first insulating material layer (eg, insulating layer 602). Examples of the first insulating material may include silicon dioxide and phosphate. Referring again to Fig.10 , in sub-operation 904a, reagent 1008 may be added to slurry 1007, followed by sub-operation 904b, where reagent 1008 and slurry 1006 may be heated (eg, by heater 1010) and stirred to form an insulating layer.

[0037] In some examples, the reagent 1008 may generate an X-OH or X-OR bond to coat an insulating layer on the surface of the metal particle 1002, where X represents Si (silicon) or P (phosphorus), OH represents a hydroxide, and R represents an alkyl substituent. Different insulating materials may be coated on the metal particle 1002 using different reagents 1008. For example, in order to coat a silicon dioxide layer on the metal particle 1002, a reagent including an orthosilicate, such as ethyl orthosilicate (Si(OC2H5)4), may be used in operation 904. In addition, in order to coat a phosphate layer on the metal particle 1002, a reagent including phosphoric acid, such as orthophosphoric acid (H3PO4), may be used in operation 904.

[0038] The metal particles coated with the insulating layer may be separated from the solvent in operation 906. The separation may be performed by, for example, passing the slurry 1006 through a filter to remove the solvent 1004 and the reagent 1008 while retaining the metal particles, followed by washing and drying the metal particles.

[0039] In operation 906, the metal particles coated with the insulating layer may be mixed with a second insulating material to form a magnetic molding compound (MMC) material. The second insulating material may include an epoxy resin. As part of operation 906, the metal particles may be mixed with the epoxy resin, followed by a kneading operation in which the mixture may be kneaded with an extruder. The kneaded mixture may be formed into a specific shape (e.g., a sheet) and cooled. The MMC material may then be crushed into particles that may be melted and molded to form an encapsulation package 208.

[0040] Fig.11 and Figures 12A to 12G Description of the invention for manufacturing an integrated circuit having an inductor in a magnetic package, such as Figures 2A to 8 An example of a method of implementing an integrated circuit 200 is provided. Fig.11 A flowchart 1100 illustrating an example method of manufacturing an integrated circuit, and Figures 12A to 12C For illustration Fig.11 A diagram of the various operations of the instance method.

[0041] In operation 1102 , a plurality of semiconductor dies may be mounted on a substrate.

[0042] refer to Fig. 12A , in sub-operation 1102a, substrate 1200 may include metal pads 1202, 1204, 1206, 1208, 1210, 1212 located on surface 1216 and metal pads 1222, 1224, 1226, and 1228 located on surface 1230 opposite to surface 1216. Substrate 1200 may also include metal interconnects 1232, 1234, 1236, and 1238 to provide electrical connections between the metal pads. Substrate 1200 may also include an insulating layer 1240, such as a polymer, ABF, or ceramic material, to provide electrical insulation between the metal interconnects and the metal pads. In some examples, substrate 1200 may include a routable lead frame (RLF).

[0043] In addition, reference Fig. 12B , in sub-operation 1102 b , solder layers 1242 , 1243 , 1244 , 1245 , 1246 , and 1247 are deposited on corresponding metal pads 1202 , 1204 , 1208 , 1210 , and 1212 .

[0044] In addition, reference Fig. 12C , in sub-operation 1102c, the semiconductor die 104 may be mounted to the metal pads 1234-1246 of the substrate 1200 via the metal interconnects 130-136. In some examples, a pick-and-place (PnP) machine may align the metal interconnects 130-136 with the respective solder layers 1243-1246 and then place the semiconductor die 104 on the solder layers.

[0045] Reference again Fig.11 , in operation 1104 , a plurality of inductors may be mounted on a substrate.

[0046] refer to Fig.12D, in sub-operation 1104a, the pillar portions 212a and 212b of the inductor 202 may be mounted to the metal pads 1202 and 1212 of the substrate 1200 via respective solder layers 1242 and 1247, such that the coil portion 210 of the inductor 202 is located on / over the semiconductor die 104. In some examples, the PnP machine may align the pillar portions 212a and 212b of the inductor 202 with the respective solder layers 1242 and 1247, and then place the pillar portions on the solder layers. In addition, referring to Fig.12E In sub-operation 1104b, a reflow operation may be performed, wherein the inductor 202 and the semiconductor die 104 are heated in an oven 1250 together with the substrate 1200 and the solder layers 1242 to 1247. The solder layers may be reflowed in a molten state to form solder joints between the inductor 202 and the semiconductor die 104 and the substrate 1200.

[0047] refer to Fig.11 and Fig.12F In operation 1106, a magnetic material (eg, MMC) is deposited on the semiconductor die, the inductor, and the substrate. The magnetic material includes: coated metal particles coated with a first insulating material; and a second insulating material in which the coated metal particles are suspended. Figures 6A to 8 Examples of magnetic materials are described in . The magnetic material may include coated metal particles such as Figures 6A to 8 6, wherein each coated metal particle is coated with an insulating layer 602, such as a silicon dioxide / phosphoric acid layer, and the coated metal particles are suspended in an epoxy resin to reduce leakage on a cut surface where the epoxy resin can be removed and the metal particles can be exposed. In addition, in operation 1108, the magnetic material can be molded and heated so that the magnetic material can be hardened to form an encapsulation package 208 for the corresponding semiconductor die 104 and the inductor 202.

[0048] refer to Figure 12G In operation 1110, the molded magnetic material and substrate may be cut to form integrated circuits including corresponding semiconductor dies and inductors. Cutting may be performed by, for example, a rotating blade 1260.

[0049] In some examples, cutting may be performed to remove some of the metal particles from the magnetic material to create a cavity, which may be filled with air or another insulating material, such as epoxy. Removal of the metal particles may be performed by increasing the contact time between the metal particles and the blade during the cutting operation. The contact time may be increased by reducing the speed at which the blade moves over the cutting surface (e.g., cutting speed), reducing the rotation speed of the blade (e.g., spindle speed), or both, so that the force exerted by the blade on the metal particles can overcome the bonding force between the metal particles and the epoxy.

[0050] In addition, as described above, the cavity may be filled with air or another insulating material, such as epoxy resin. After the cutting operation, a resin coating may be applied on the cut surface to fill the cavity with resin. In some examples, the resin coating may be applied by spraying or by a spin coating operation.

[0051] Any method described herein can be performed in whole or in part using a computing system comprising one or more processors that can be configured to perform the steps. Therefore, an embodiment may relate to a computing system configured to perform the steps of any method described herein, which may have different components that perform corresponding steps or corresponding step groups. Although presented in numbered steps, the steps of the method herein can be performed at the same time or in different orders. In addition, parts of these steps can be used together with parts of other steps from other methods. In addition, all or part of the steps can be optional. In addition, any step of any method can be performed by a module, a circuit or other components for performing these steps.

[0052] In this description, the term "coupled" may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then: (a) in the first instance, device A is directly coupled to device B; or (b) in the second instance, if the intermediate component C does not substantially change the functional relationship between device A and device B, device A is indirectly coupled to device B through the intermediate component C, so that device B is controlled by device A via the control signal provided by device A.

[0053] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0054] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described herein as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, such as by an end user and / or a third party.

[0055] Certain components may be described herein as belonging to a particular process technology, but these components may be replaced with components of other process technologies. The circuits described herein may be reconfigured to include replacement components to provide functionality at least partially similar to the functionality available before the component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series or in parallel between the same two nodes as the single resistor or capacitor, respectively.

[0056] The use of the phrase "ground voltage potential" in this specification includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "approximately" or "substantially" before a parameter means within + / -10% of the parameter.

[0057] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. An integrated circuit, comprising: substrate; Semiconductor die; a metal interconnect, the semiconductor die being mounted to the substrate via the metal interconnect; an inductor mounted to the substrate; and A magnetic material encapsulates the semiconductor die, the inductor, and the metal interconnects, the magnetic material comprising: coated metal particles coated with a first insulating material; and a second insulating material in which the coated metal particles are suspended. 2 . The integrated circuit of claim 1 , wherein the second insulating material comprises epoxy. 3 . The integrated circuit of claim 1 , wherein the first insulating material comprises a silicon oxide material. The integrated circuit of claim 1 , wherein the first insulating material comprises a phosphate material.

5. The integrated circuit of claim 1, wherein the magnetic material comprises cavities dispersed among at least some of the coated metal particles. The integrated circuit according to claim 5 , wherein the cavity is filled with air or a third insulating material.

7. The integrated circuit of claim 1, wherein the inductor comprises a coil portion and a pillar portion, the pillar portion coupled to the substrate.

8. The integrated circuit of claim 7, wherein the coil portion is located above the semiconductor die.

9. The integrated circuit of claim 7, further comprising a capacitor encapsulated in a magnetic material, wherein the coil portion is located above the capacitor.

10. The integrated circuit of claim 1, wherein the metal interconnect is a first metal interconnect, and the substrate comprises: a first metal pad on a first side of the substrate, the first metal pad coupled to the first metal interconnect and the inductor; a second metal pad located on a second side of the substrate opposite the first side; an insulating layer located between the first side and the second side; and A second metal interconnect is located in the insulating layer and coupled between the first metal pad and the second metal pad.

11. The integrated circuit of claim 10, wherein: The first metal pad and the second metal interconnect comprise copper metal; The second metal backing comprises at least one of palladium metal or silver metal; and The insulating layer includes at least one of the following: a polymer material, an Ajinomoto deposited film, or a ceramic material.

12. The integrated circuit of claim 11, further comprising a solder resist layer on the second side.

13. A method comprising: mounting a semiconductor die to a substrate; mounting an inductor to the substrate; depositing a magnetic material on the semiconductor die and the inductor, the magnetic material comprising: coated metal particles coated with a first insulating material; and a second insulating material in which the coated metal particles are suspended; molding the magnetic material; and The magnetic material and the substrate are diced to form integrated circuits including corresponding semiconductor dies and inductors.

14. The method of claim 13, wherein the mixture is a first mixture, and the method further comprises: mixing the metal particles with a solvent to form a mixture; adding a reagent to the mixture to coat the metal particles with the first insulating material; separating the coated metal particles from the solvent; and The coated metal particles are mixed with the second insulating material.

15. The method of claim 14, wherein the reagent comprises at least one of: an orthosilicate reagent or phosphoric acid.

16. The method of claim 14, further comprising removing at least some of the coated metal particles from a cut surface of the magnetic material.

17. The method of claim 16, wherein the at least some of the coated metal particles are removed from the cut surface during the cutting of the magnetic material. The method of claim 13 , wherein the second insulating material comprises epoxy. The method of claim 13 , wherein the first insulating material comprises a silicon oxide material.

20. The method of claim 13, wherein the first insulating material comprises a phosphate material.

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