Three-dimensional NOR array and manufacturing method thereof

Abstract

A semiconductor structure includes a vertical stack of repeating units, wherein each instance of the repeating unit extends in a first horizontal direction and includes a first conductive strip, a first memory film over the first conductive strip, discrete semiconductor channels laterally spaced apart from each other in the first horizontal direction and over the first memory film, a second memory film over the discrete semiconductor channel, a second conductive strip over the second memory film, and an insulating strip over the first conductive strip. Source / drain openings are arranged along the first horizontal direction, interleaved with the discrete semiconductor channels, and extend vertically through the vertical stack of repeat units, and source / drain pillar structures are located in respective source / drain openings, and extend vertically through the vertical stack of repeat units.

Description

Technical Field

[0001] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 387,389 filed on December 14, 2022, U.S. Provisional Patent Application No. 63 / 387,393 filed on December 14, 2022, and U.S. Provisional Patent Application No. 63,387,398 filed on December 14, 2022, the entire contents of which are hereby incorporated by reference into this document for all purposes. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to three-dimensional NOR arrays and methods of manufacturing the same. Background Art

[0004] NOR memory devices include memory cells connected in parallel. The memory cells are directly connected to the source and drain without passing through adjacent memory cells for source and / or drain connection. Therefore, NOR memory cells can be directly accessed without passing through adjacent memory cells. Therefore, NOR memory devices can provide faster access speeds compared to NAND memory devices and can be used in storage class memory (SCM) devices. Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor structure includes: a vertical alternating stack of insulating strips and conductive strips that are laterally spaced apart from each other by line grooves; a laterally alternating sequence of semiconductor channels and source / drain pillar structures located within a corresponding one of the line grooves; and a memory film located between each adjacent pair of the vertical alternating stack and the laterally alternating sequence, wherein each source / drain pillar structure of a plurality of the source / drain pillar structures is in direct contact with a corresponding pair of vertical semiconductor channels.

[0006] According to another aspect of the present disclosure, a method for forming a semiconductor structure includes: forming a vertical alternating sequence of insulating layers and sacrificial material layers; forming line grooves through the vertical alternating sequence, wherein the vertical alternating sequence is divided into vertical alternating stacks of insulating strips and sacrificial material strips, and the vertical alternating stacks are laterally spaced apart from each other by the line grooves; forming a memory film in each of the line grooves; forming a laterally alternating sequence of semiconductor channels and source / drain column structures in each of the line grooves on a corresponding one of the memory films, wherein each of the multiple source / drain column structures is in direct contact with a corresponding pair of vertical semiconductor channels; and replacing the sacrificial material layer with a conductive strip.

[0007] According to another aspect of the present disclosure, a semiconductor structure includes a vertical stack of repeating units, wherein each instance of the repeating unit extends along a first horizontal direction and includes a first conductive strip, a first memory film located above the first conductive strip, a discrete semiconductor channel laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channel, a second conductive strip located above the second memory film, and an insulating strip located above the first conductive strip. Source / drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and extend vertically through the vertical stack of repeating units, and source / drain pillar structures are located in corresponding source / drain openings and extend vertically through the vertical stack of repeating units.

[0008] According to another aspect of the present disclosure, a method for forming a semiconductor structure includes: forming a vertical stack of multiple instances of a unit layer stack above a substrate, wherein the unit layer stack includes a first sacrificial material layer, a first memory film, a semiconductor material layer, a second memory film, a second sacrificial material layer and an insulating layer; forming a source / drain opening through the vertical stack; forming a source / drain pillar structure in the source / drain opening; forming a linear groove extending laterally through the vertical stack along a first horizontal direction, wherein the vertical stack is divided into a vertical stack of repeating units, wherein the vertical stack of repeating units is staggered with the linear groove along a second horizontal direction perpendicular to the first horizontal direction, and wherein each instance of the repeating unit includes a first sacrificial material strip, a first memory film, a row of discrete semiconductor channels laterally spaced apart from each other along the first horizontal direction, a second memory film, a second sacrificial material strip and an insulating strip; and replacing the first sacrificial material strip and the second sacrificial material strip with the first conductive strip and the second conductive strip through the linear groove.

[0009] According to one aspect of the present disclosure, a three-dimensional memory device includes: a first vertical stack of a first field effect transistor string; and a second vertical stack of a second field effect transistor string. The first vertical stack alternates with the second vertical stack along a first horizontal direction. Each first field effect transistor string in the first field effect transistor string includes a series connection of a corresponding group of first field effect transistors, and the corresponding group of first field effect transistors are electrically connected to each other so that each adjacent pair of first field effect transistors shares a corresponding first source / drain region in a plurality of first source / drain regions. Each second field effect transistor string in the second field effect transistor string includes a series connection of a corresponding group of second field effect transistors, and the corresponding group of second field effect transistors are electrically connected to each other so that each adjacent pair of second field effect transistors shares a corresponding second source / drain region in a second source / drain region. The series connection of the corresponding group of first field effect transistors shares a corresponding word line in a plurality of word lines. The first source / drain regions are located in different vertical levels in the corresponding first source / drain pillar structures, and the second source / drain regions are located in different vertical levels in the corresponding second source / drain pillar structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the case of multiple drawings with the same reference numeral and different letter suffixes, all drawings with the same reference numeral refer to the same structure. Each drawing with the letter figure suffix A is a top view, i.e., a plan view. For example, Figure 1A , Figure 2A , Figure 3A etc. are top views. Each figure with a letter suffix B is a vertical sectional view along the vertical plane B-B' in the figure with the same figure number and with the letter suffix A. If present, each figure with a letter suffix C is a vertical sectional view along the vertical plane C-C' in the figure with the same figure number and with the letter suffix A. If present, each figure with a letter suffix D is a vertical sectional view along the vertical plane D-D' in the figure with the same figure number and with the letter suffix A. If present, each figure with a letter suffix E is a vertical sectional view along the vertical plane E-E' in the figure with the same figure number and with the letter suffix A. For example, Figure 1B is along Figure 1A A vertical cross-section of the plane B-B', Figure 1C is along Figure 1A A vertical section of plane C-C', Figure 1D is along Figure 1A A vertical cross-section of the plane D-D', and Figure 1E is along Figure 1A Some structures are shown in a top view and three vertical cross-sectional views, and some other structures are shown in a top view and two vertical cross-sectional views.

[0011] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E are various views of a first exemplary structure after forming access lines according to the first embodiment of the present disclosure.

[0012] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E are various views of a first exemplary structure after forming a connecting via structure according to the first embodiment of the present disclosure.

[0013] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E are various views of a first exemplary structure after forming a vertically alternating sequence of insulating layers and sacrificial material layers according to the first embodiment of the present disclosure.

[0014] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E are various views of a first exemplary structure after forming line trenches and vertical alternating stacks of insulating strips and sacrificial material strips according to a first embodiment of the present disclosure.

[0015] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E are various views of a first exemplary structure after forming a continuous memory film according to the first embodiment of the present disclosure.

[0016] Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E are various views of a first exemplary structure after patterning a continuous memory film into a plurality of memory films according to the first embodiment of the present disclosure.

[0017] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E are various views of the first exemplary structure after forming an integrated sacrificial trench fill structure according to the first embodiment of the present disclosure.

[0018] Fig. 8A , Figure 8B , Figure 8C , Fig.8D and Fig. 8E 2 are various views of a first exemplary structure after forming a pillar cavity according to the first embodiment of the present disclosure.

[0019] Fig.9A , Fig. 9B , Fig. 9C , Fig.9D and Fig.9E are various views of the first exemplary structure after forming an active area pillar structure and a second active area pillar structure according to the first embodiment of the present disclosure.

[0020] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D and Fig.10E are various views of a first exemplary structure after forming a semiconductor channel cavity according to the first embodiment of the present disclosure.

[0021] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D and Fig.11E are various views of a first exemplary structure after forming a semiconductor channel and a dielectric core according to the first embodiment of the present disclosure.

[0022] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D and Fig.12E are various views of the first exemplary structure after forming a void in a backside trench according to the first embodiment of the present disclosure.

[0023] Fig.13A , Fig. 13B , Fig. 13C , Fig.13D and Fig.13E 2 are various views of a first exemplary structure after forming a back-side recess according to the first embodiment of the present disclosure.

[0024] Fig.14A , Fig. 14B , Fig. 14C , Fig.14D and Fig.14E are various views of a first exemplary structure after forming conductive strips according to the first embodiment of the present disclosure.

[0025] Fig.15A , Fig. 15B , Fig. 15C , Fig.15D and Fig.15EVarious views of a first exemplary structure after forming a dielectric backside trench fill structure in the backside trench and after forming a top source / drain connection via structure according to the first embodiment of the present disclosure.

[0026] Fig.16A , Fig. 16B , Fig. 16C , Fig.16D and Fig.16E are various views of a first exemplary structure after forming a second bit line according to the first embodiment of the present disclosure.

[0027] Fig.17 is a circuit diagram of a NOR memory device including an example of a first exemplary structure in a per-cell unit operation mode according to the first embodiment of the present disclosure.

[0028] Fig.18 is a schematic diagram of a NOR memory device with a bias voltage during a programming operation.

[0029] Fig.19 for Fig.18 Circuit diagram of a NOR memory device.

[0030] Fig. 20 Schematic diagram of a NOR memory device with a bias voltage during an erase operation.

[0031] Fig.21 for Fig. 20 Circuit diagram of a NOR memory device.

[0032] Fig. 22 Schematic diagram of a NOR memory device with a bias voltage during a read operation.

[0033] Fig.23 for Fig. 22 Circuit diagram of a NOR memory device.

[0034] Fig.24 FIG. 1 is an enlarged view of a NOR memory cell during operation in a dual-bit-per-cell operating mode.

[0035] Fig.25 is a circuit diagram of a NOR memory device including an example of a first exemplary structure in a dual-bit-per-cell operation mode according to a first embodiment of the present disclosure.

[0036] Fig.26 is a circuit diagram of a NOR memory device having a bias voltage during a programming operation for programming an A cell.

[0037] Fig. 27is a circuit diagram of a NOR memory device having a bias voltage during a programming operation for programming a B cell.

[0038] Fig.28 is a circuit diagram of a NOR memory device with a bias voltage during an erase operation.

[0039] Fig.29 is a circuit diagram of a NOR memory device having a bias voltage during a read operation for reading an A cell.

[0040] Fig.30 is a circuit diagram of a NOR memory device having a bias voltage during a read operation for reading a B cell.

[0041] Fig.31A and Fig.31B 2 are various views of a second exemplary structure after forming a vertical repetition of a unit layer stack according to a second embodiment of the present disclosure.

[0042] Fig.32A and Fig.32B are various views of a second exemplary structure after forming source / drain openings according to a second embodiment of the present disclosure.

[0043] Fig.33A and Fig.33B Various views of a second exemplary structure after lateral expansion of source / drain openings at the level of a semiconductor channel material layer according to a second embodiment of the present disclosure.

[0044] Fig.34A and Fig.34B are various views of a second exemplary structure after forming source / drain pillars according to the second embodiment of the present disclosure.

[0045] Fig.34C is a vertical cross-sectional view of an alternative configuration of a second exemplary structure after forming source / drain pillars according to a second embodiment of the present disclosure.

[0046] Fig.35A and Fig.35B are various views of a second exemplary structure after forming a dielectric core according to a second embodiment of the present disclosure.

[0047] Fig.36A , Fig.36B and Fig.36C 2 are various views of a second exemplary structure after forming linear trenches according to the second embodiment of the present disclosure.

[0048] Fig.37A , Fig.37B and Fig.37C2 are various views of a second exemplary structure after forming a back-side recess according to the second embodiment of the present disclosure.

[0049] Fig.38A , Fig.38B and Fig.38C are various views of a second exemplary structure after forming various semiconductor silicon oxide liners according to the second embodiment of the present disclosure.

[0050] Fig.39A , Fig.39B and Fig.39C are various views of a second exemplary structure after forming a backside blocking dielectric layer according to the second embodiment of the present disclosure.

[0051] Fig.40A , Fig.40B and Fig.40C 2 are various views of a second exemplary structure after forming a conductive strip according to a second embodiment of the present disclosure.

[0052] Fig.41A , Fig.41B and Fig.41C are various views of a second exemplary structure after forming a backside trench fill structure according to a second embodiment of the present disclosure.

[0053] Fig.42 is a circuit diagram of a NOR memory device according to a second exemplary structure of the second embodiment of the present disclosure.

[0054] Fig.43 is a schematic perspective view of a NOR memory device according to a second exemplary structure of the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] As discussed above, embodiments of the present disclosure relate to three-dimensional NOR arrays and methods of manufacturing the same, various aspects of which are described below.

[0056] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0057] The same reference numerals represent the same elements or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. If two or more elements are not in direct contact with each other, the two elements are "separated" from each other.

[0058] As used herein, a first element positioned "on" a second element may be positioned on the outside of a surface of the second element or on the inside of the second element. As used herein, a first element is positioned "directly" on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is "electrically connected to" a second element if there is a conductive path composed of at least one conductive material between the first element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0059] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0060] refer to Figures 1A to 1E , shows a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 8, which may be a semiconductor substrate such as a commercially available silicon wafer. Optionally, semiconductor devices (not shown) such as complementary metal oxide semiconductor (CMOS) transistors may be formed on the top surface of the substrate 8. The CMOS transistors may include control (i.e., driver) circuitry for controlling a NOR memory array subsequently formed thereon.

[0061] An insulating spacer 12 may be formed over the substrate 8. In the case where a semiconductor device is formed on the top surface of the substrate 8, the insulating spacer 12 may be formed over such semiconductor device (such as a field effect transistor). A first line-level dielectric layer 14 may be formed over the insulating spacer 12. The first line-level dielectric layer 14 includes a dielectric material such as silicon oxide and may have a thickness in the range of 50 nm to 500 nm. A line cavity extending laterally along a first horizontal direction hd1 may be formed through the first line-level dielectric layer 14. At least one conductive material may be deposited in the line cavity, and excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the first line-level dielectric layer 14. The remaining portions of the at least one conductive material include access lines (22, 26). The access lines (22, 26) may include a first bit line 22 that is subsequently electrically connected to a source / drain connection via structure and a source / drain pillar structure, and an optional semiconductor channel bias line 26 that may subsequently be electrically connected to a semiconductor channel contact via structure and a semiconductor channel. According to one aspect of the present disclosure, the first bit line 22 may be used as a source line (connected to the source region of the field effect transistor) or as a drain line (connected to the drain region of the field effect transistor) depending on the operation mode of the field effect transistor.

[0062] The access lines (22, 26) are parallel to each other and extend laterally along a first longitudinal direction, which may be a first horizontal direction hd1. The access lines (22, 26) may have the same line width along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, the first bit line 22 and the semiconductor channel bias line 26 may be staggered along the second horizontal direction hd2. The access lines (22, 26) may be formed as a one-dimensional periodic array having a periodicity along the second horizontal direction hd2. The periodicity along the second horizontal direction hd2 may be a center-to-center distance between adjacent pairs of first bit lines 22 along the first horizontal direction hd1. Memory cells may then be formed over the access lines (22, 26).

[0063] refer to FIG. 2A to FIG. 2E, a first via-level dielectric layer 16 may be formed over the first line-level dielectric layer 14. The first via-level dielectric layer 16 includes a dielectric material such as silicon oxide and may have a thickness in a range of 50 nm to 500 nm. A via cavity may be formed through the first via-level dielectric layer 16. At least one conductive material may be deposited in the via cavity, and excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the first via-level dielectric layer 16. The remaining portions of the at least one conductive material include connecting via structures (24, 28), each of which includes a conductive material. The connecting via structures (24, 28) may include first source / drain connecting via structures 24 and semiconductor channel contact via structures 28. Each first source / drain connecting via structure 24 may be formed on a top surface of a corresponding one of the first bit lines 22. Each semiconductor channel contact via structure 28 may be formed on a top surface of a corresponding one of the semiconductor channel bias lines 26. The layer stack of the insulating spacer layer 12 , the first line-level dielectric layer 14 , and the first via-level dielectric layer 16 is referred to herein as the underlying insulating layer 10 .

[0064] In one embodiment, the first source / drain connection via structures 24 may be formed as a two-dimensional periodic array of the first source / drain connection via structures 24, and each of the first bit lines 22 contacts a corresponding subset of the first source / drain connection via structures 24 and extends laterally along the first horizontal direction hd1. In one embodiment, the semiconductor channel contact via structures 28 may be formed as a two-dimensional array of the semiconductor channel contact via structures 28, and each of the semiconductor channel bias lines 26 contacts a corresponding subset of the semiconductor channel contact via structures 28 and extends laterally along the first horizontal direction hd1.

[0065] According to an embodiment of the present disclosure, a semiconductor channel contact via structure 28 may be formed for each semiconductor channel subsequently formed, and a first source / drain connection via structure 24 may be formed for a first subset of source / drain pillar structures subsequently formed. The first subset of source / drain pillar structures may include approximately half of all source / drain pillar structures subsequently formed. In one embodiment, the semiconductor channel contact via structure 28 may be formed as a row extending laterally along the second horizontal direction hd2 and repeated along the first horizontal direction hd1. In one embodiment, the first source / drain connection via structure 24 may be formed as a row extending laterally along the second horizontal direction hd2 and repeated along the first horizontal direction hd1. In one embodiment, the spacing (i.e., periodicity) of the rows of the first source / drain connection via structures 24 along the first horizontal direction hd1 may be twice the spacing of the rows of the semiconductor channel contact via structures 28. In this case, every other row of semiconductor channel contact via structures 28 may be staggered with the first source / drain connection via structures 24 of the corresponding row along the second horizontal direction hd2.

[0066] refer to FIG. 3A to FIG. 3E, a vertically alternating sequence of a first material layer (such as an insulating layer 32L) and a second material layer (such as a spacer material layer) is formed above the underlying insulating layer 10. As used herein, a "vertically alternating sequence" refers to an alternating sequence of multiple instances of a first element and multiple instances of a second element that are vertically alternating, such that an instance of the second element overlies each instance of the first element and / or potentially underlies each instance of the first element, and an instance of the first element overlies each instance of the second element and / or potentially underlies each instance of the first element. The vertically alternating sequence may include a stack of alternating multiple first material layers (which may be insulating layers 32L) and second material layers (which may be sacrificial material layers 42L). As used herein, a "material layer" refers to a layer that includes a material throughout its entirety. As used herein, an alternating plurality of first elements and second elements refers to a structure in which instances of the first element and instances of the second element are alternating. Each instance of a first element that is not an end element of an alternating plurality of elements is adjacent to two instances of the second element on both sides, and each instance of a second element that is not an end element of an alternating plurality of elements is adjacent to two instances of the first element on both ends. Therefore, the vertical alternating sequence of the first element and the second element is an alternating plurality of first elements and second elements, wherein the alternation of the first element and the second element occurs in the vertical direction. The first element may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, the instance of the first element and the instance of the second element may form a unit that is periodically repeated in the alternating plurality of elements.

[0067] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32L, and each second material layer may be a sacrificial material layer 42L. In this case, the stack may include alternating multiple insulating layers 32L and sacrificial material layers 42L, and constitute a prototype stack including alternating layers of insulating layers 32L and sacrificial material layers 42L. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0068] In one embodiment, the vertically alternating sequence (32L, 42L) may include an insulating layer 32L composed of a first material and a sacrificial material layer 42L composed of a second material, wherein the second material is different from the material of the insulating layer 32L. Insulating materials that can be used for the insulating layer 32L include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 32L may be silicon oxide.

[0069] The second material of the sacrificial material layer 42L is a sacrificial material that is selectively removable with respect to the first material of the insulating layer 32. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0070] The sacrificial material layer 42L may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42L may then be replaced with a conductive electrode, which may be used as a word line. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), or a polycrystalline semiconductor material (such as polycrystalline silicon).

[0071] In one embodiment, insulating layer 32L may include silicon oxide, and sacrificial material layer 42L may include silicon nitride. The first material of insulating layer 32L may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for insulating layer 32L, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42L may be formed, for example, by CVD or atomic layer deposition (ALD).

[0072] The thickness of the insulating layer 32L and the sacrificial material layer 42L may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each insulating layer 32L and each sacrificial material layer 42L. The number of repetitions of the pair of insulating layers 32L and sacrificial material layers 42L (e.g., control gate electrodes or sacrificial material layers) may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each sacrificial material layer 42L in the vertically alternating sequence (32L, 42L) may have a uniform thickness that is substantially constant within each respective sacrificial material layer 42L. In one embodiment, the vertically alternating sequence (32L, 42L) may start at the bottommost one of the insulating layers 32L and end at the topmost one of the insulating layers 32L.

[0073] The topmost layer of the vertical alternating sequence (32L, 42L) may be the topmost insulating layer 32LT. The vertical alternating sequence (32L, 42L) may be patterned in a peripheral region (not shown) relative to the topmost insulating layer 32LT. FIG. 3A to FIG. 3E The memory array region is shown laterally offset along a first horizontal direction hd1 to form a stepped surface. The stepped surface may then be used to form a connecting via structure contacting a corresponding conductive strip. An anti-stepped dielectric material portion may be formed above the stepped surface in a vertical alternating sequence (32L, 42L).

[0074] Although an embodiment is described in which the spacer material layer is a sacrificial material layer 42L that is subsequently replaced with a conductive strip, embodiments are expressly contemplated herein in which the sacrificial material layer is formed as a conductive strip, such as a heavily doped polysilicon strip. In this case, the step of replacing the spacer material layer with the conductive strip may be omitted.

[0075] refer to FIG. 4A to FIG. 4E A photoresist material stack (not shown) including at least a photoresist layer may be formed above the vertical alternating sequence (32L, 42L) and may be photolithographically patterned to form linear openings therein. The linear openings extend laterally along a second horizontal direction hd2 and have a uniform width along a first horizontal direction hd1 perpendicular to the second horizontal direction hd2. Optionally, additional linear openings (referred to herein as backside openings) extending laterally along the first horizontal direction hd1 may be formed such that each of these linear openings abuts against the backside opening.

[0076] The pattern in the photolithographic material stack can be transferred through the vertical alternating sequence (32L, 42L) by at least one anisotropic etching using the patterned photolithographic material stack as an etching mask. The portion below the linear opening in the patterned photolithographic material stack of the vertical alternating sequence (32L, 42L) is etched to form a line groove 31T and an optional back side groove 31B. As used herein, "line groove" refers to a groove having a straight extension laterally in the horizontal direction. In one embodiment, each line groove in the line groove 31T may be adjacent to the back side groove 31B. In an alternative embodiment, the formation of the back side groove 31B can be postponed until after the formation of the source / drain pillar structure and the semiconductor channel.

[0077] The line grooves 31T extend laterally through the vertical alternating sequence (32L, 42L) along the second horizontal direction hd2. In one embodiment, the line grooves 31T may always have the same width, and the spacing between adjacent pairs of line grooves 31T may be the same. In this case, the line grooves 31T may constitute a one-dimensional periodic array of line grooves 31T. The width of the line grooves 31T may be in the range of 30nm to 300nm, such as 40nm to 100nm, but smaller and larger widths may also be used.

[0078] In one embodiment, each of the line grooves 31T may be connected to the backside groove 31B. In this case, the combination of the line groove 31T and the backside groove 31B may be formed as a single continuous cavity and is referred to herein as a groove assembly 31.

[0079] The line trench 31T extends through each layer of the vertical alternating sequence (32L, 42L). The chemical properties of the anisotropic etching process for etching the material through the vertical alternating sequence (32L, 42L) can be alternating to optimize the etching of the first material and the second material in the vertical alternating sequence (32L, 42L). The anisotropic etching can be, for example, a series of reactive ion etching. The sidewalls of the line trench 31T can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0080] Each of the line grooves 31T may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate 8. Each of the line grooves 31T extends vertically through each layer of the vertical alternating sequence (32L, 42L). A row of connecting via structures (24, 28) may be physically exposed at the bottom of each line groove 49. The patterned portion of the insulating layer 32L includes an insulating strip 32 having a uniform width and extending laterally along the second horizontal direction hd2. The patterned portion of the sacrificial material layer 42L includes a sacrificial material strip 42 having a uniform width and extending laterally along the second horizontal direction hd2. Each vertical stack group of insulating strips 32 and sacrificial material strips 42 includes a vertical alternating stack of insulating strips 32 and sacrificial material strips 42. A plurality of vertical alternating stacks (32, 42) are formed above the insulating layer 10 below. In one embodiment, the topmost strip of each vertical alternating stack (32, 42) may include the topmost insulating strip 32T.

[0081] The line trenches 31T extend laterally along the second horizontal direction hd2, and each vertical alternating stack (32, 42) of insulating strips 32 and sacrificial material strips 42 may be located between corresponding adjacent pairs of line trenches 31T that are laterally spaced apart along the first horizontal direction hd1. The vertical alternating stacks (32, 42) of insulating strips 32 and spacer material strips (such as sacrificial material strips 42) are laterally spaced apart from each other by the line trenches 31T. In general, the vertical alternating stacks of insulating strips 32 and spacer material strips may be formed above the substrate 8. Although an embodiment in which the spacer material strips are formed as sacrificial material strips 42 is described, an embodiment in which the spacer material strips are formed as conductive strips is explicitly contemplated herein. In the case in which the spacer material strips are formed as sacrificial material strips 42, each of the sacrificial material strips may be subsequently replaced with a corresponding conductive strip.

[0082] Generally speaking, the line trenches 31T divide the vertical alternating sequence into vertical alternating stacks (32, 42) of insulating strips 32 and sacrificial material strips 42. The vertical alternating stacks (32, 42) are laterally spaced apart from each other by the line trenches 31T. Each line trench 31T extends vertically from a first horizontal plane HP1 including the bottommost surface of the vertical alternating stacks (32, 42) to a second horizontal plane HP2 including the topmost surface of the vertical alternating stacks (32, 42).

[0083] refer to FIG. 5A to FIG. 5E, a continuous memory film 50C may be formed on the physically exposed surface of the line trench 31T and above the vertical alternating stack (32, 42). The continuous memory film 50C extends into each of the line trenches 31T and extends above the vertical alternating stack (32, 42). In one embodiment, the continuous memory film 50C is formed by sequentially depositing a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 into the line trench 31T. The blocking dielectric layer 52 includes at least one dielectric material such as silicon oxide and / or aluminum oxide, and may have a thickness in the range of 3nm to 10nm. The charge storage layer 54 includes a charge storage material such as silicon nitride, and may have a thickness in the range of 3nm to 10nm. The tunneling dielectric layer 56 includes a tunneling dielectric layer 56 such as a silicon oxide layer, a silicon oxynitride layer, or an ONO stack (i.e., a layer stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer), and may have a thickness in the range of 3nm to 10nm.

[0084] The continuous memory film 50C may be patterned by removing a horizontal portion of the continuous memory film 50C. For example, an anisotropic etching process may be performed to sequentially etch through a horizontal portion of the continuous tunneling dielectric layer 56, a horizontal portion of the charge storage layer 54, and a horizontal portion of the blocking dielectric layer 52. The remaining portion of the continuous memory film 50C may be located on the sidewalls of the trench assembly 31. In the absence of the backside trench 31B, the vertically extending remaining portion of the continuous memory film 50C (referred to herein as a memory film) may exist within each line trench 31T. A line cavity 31T' may exist within the volume of each line trench 31T, and a backside cavity 31B' may exist within the volume of the backside trench 31B.

[0085] refer to FIG. 6A to FIG. 6E In the case where the trench component 31 includes a backside trench 31B in addition to a plurality of line trenches 31T, portions of the continuous memory film 50C located on the sidewalls of the backside trenches 31B may be optionally removed without removing portions of the continuous memory film 50C located in the line trenches 31T. For example, a photoresist layer may be applied and photolithographically patterned to fill the line trenches 31T without filling the backside trenches 31B. A set of isotropic etching processes may be performed to sequentially etch the unmasked portions of the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52. The continuous memory film 50C may be divided into a plurality of memory films 50 located in a corresponding one of the line trenches 31T. In the case where the backside trenches 31B are not employed, the continuous memory film 50C may be omitted. FIG. 6A to FIG. 6DIn general, a memory film 50 may be formed in each line trench 31T on the sidewalls of a corresponding pair of vertical alternating stacks (32, 42) of insulating strips 32 and sacrificial material strips 42. Each memory film 50 may include a layer stack including, from one side to the other, a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56.

[0086] refer to 7A to 7E , a sacrificial trench filling material may be deposited in the line cavity 31T' and the backside cavity 31B'. The sacrificial trench filling material includes a material that can selectively remove the material of the outermost layer of the tunnel dielectric layer 56, which may be thermal silicon oxide. For example, the sacrificial trench filling material may include silicon nitride, porous or non-porous organosilicate glass, borosilicate glass, a silicon-germanium alloy containing germanium with an atomic concentration in the range of 15% to 50%, amorphous carbon, diamond-like carbon (DLC), or an organic polymer material. Excess portions of the sacrificial trench filling material may be removed from above a horizontal plane including the top surface of the topmost insulating strip 32T by a planarization process such as a chemical mechanical planarization process and / or a recess etching process. Each remaining portion of the sacrificial trench filling material located within a corresponding one of the line trenches 31L includes a sacrificial line trench filling structure 33L. Each sacrificial line trench filling structure 33L is formed within a corresponding line trench 31L on a corresponding memory film 50. Each sacrificial line trench filling structure 33L may have the shape of a track. The remaining portion of the sacrificial trench fill material within the backside trench 31B comprises a sacrificial backside trench fill structure 36. In one embodiment, the line trench 31L and the backside trench 31B may be formed as a trench assembly 31, and the sacrificial line trench fill structure 33L and the backside trench fill structure 36 may be formed as a single continuous sacrificial fill material portion, which is referred to herein as an integrated sacrificial trench fill structure 33. In this case, the integrated sacrificial trench fill structure 33 may include a plurality of sacrificial line trench fill structures 33L and backside trench fill structures 36.

[0087] refer to FIG. 8A to FIG. 8E , a photoresist layer (not shown) may be applied over the first exemplary structure, and the photoresist layer may be photolithographically patterned to form an array of openings. A first subset of openings in the photoresist layer may be formed over regions of corresponding underlying first source / drain connection via structures 24. A second subset of openings in the photoresist layer may be formed between regions of corresponding adjacent pairs of first source / drain connection via structures 24 that are laterally spaced apart along the first horizontal direction hd1. In one embodiment, a row of openings having uniform spacing may be formed in the photoresist layer over each sacrificial line trench fill structure 33L.

[0088] An anisotropic etching process may be performed to etch a first portion of the sacrificial line trench filling structure 33L located below the opening in the photoresist layer. In one embodiment, the chemistry of the anisotropic etching process may be selected so that the unmasked portion of the sacrificial line trench filling structure 33L is selective to the material of the memory film 50, i.e., the material of the memory film 50 is not etched. A vertically extending cavity is formed in the volume from which the first portion of the sacrificial line trench filling structure 33L is removed. The vertically extending cavity is columnar and may have a horizontal cross-sectional shape that is substantially unchanged when translated in the vertical direction, and is referred to herein as a first columnar cavity 37.

[0089] The top surface of the first via level dielectric layer 16 and the top surface of the first source / drain connection via structure 24 may be physically exposed at the bottom of the first subset of the first column cavities 37. The top surface of the first via level dielectric layer 16 may be physically exposed at the bottom of the second subset of the first column cavities 37 without exposing any first source / drain connection via structure 24 located below the second subset of the first column cavities 37. In one embodiment, the first column cavities 37 may be formed as a two-dimensional periodic array of column cavities 37. Each sacrificial line trench filling structure 33L is divided into a plurality of discrete sacrificial material portions, which may include a row of sacrificial material pillars 34. In general, the array of first column cavities 37 may be formed by removing the first material portion of the sacrificial line trench filling structure 33L. The remaining second material portion of the sacrificial line trench filling structure 33L constitutes an array of sacrificial material pillars 34. Sacrificial backside trench filling structures 36 are present within the backside trenches 31B. The lateral dimension of each first column cavity 37 along the first horizontal direction hd1 may be in the range of 10 nm to 200 nm, such as 20 nm to 100 nm, but smaller and larger lateral dimensions may also be used. The pitch of the two-dimensional array of first column cavities 37 along the second horizontal direction hd2 may be in the range of 20 nm to 500 nm, such as 40 nm to 250 nm, but smaller and larger pitches may also be used.

[0090] refer to 9A to 9E , doped semiconductor material may be deposited in the first column cavity 37. The conductivity type of the semiconductor channel subsequently formed is referred to herein as the first conductivity type, and the conductivity type of the doped semiconductor material deposited in the first column cavity 37 is referred to herein as the second conductivity type. The second conductivity type may be opposite to the first conductivity type. For example, the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. Therefore, the doped semiconductor material deposited in the first column cavity 37 may have a doping of the second conductivity type. In one embodiment, the doped semiconductor material deposited in the first column cavity 37 may include heavily doped polysilicon or heavily doped amorphous silicon (which is subsequently converted to doped polysilicon). The doped semiconductor material may include an atomic concentration of 5.0×1019 / cm 3 Up to 2.0×10 21 / cm 3 The second conductivity type dopant may be present in a range of about 100 to about 100 nm, although smaller and larger atomic concentrations may also be used.

[0091] Excess portions of the doped semiconductor material may be removed from above the top surface of the topmost insulating strip 32T of the vertical alternating stack (32, 42). Each remaining portion of the doped semiconductor material filling the corresponding first column cavity 37 includes a source / drain column structure 64 or an active area column structure. Each source / drain column structure 64 may be used as a common source region of a plurality of charge storage field effect transistors connected in parallel (i.e., in a NOR configuration), or may be used as a common drain region of a plurality of charge storage field effect transistors. As used herein, an active region refers to any of a source region, a drain region, or a doped semiconductor material portion that may be used as a source region or a drain region according to electrical bias conditions. As used herein, a source / drain refers to any doped semiconductor material portion that may be used as a source region and / or a drain region. A first subset of the source / drain column structures 64 may be formed on the top surface of a corresponding first source / drain connection via structure 24. The second subset of source / drain pillar structures 64 does not contact any first source / drain connection via structures 24 .

[0092] Generally, the source / drain pillar structures 64 may be formed in an array of the first pillar cavities 37. Each of the first source / drain connection via structures 24 may contact a horizontal surface of a corresponding one of the source / drain pillar structures 64. In one embodiment, the source / drain pillar structures 64 extend vertically from a first horizontal plane HP1 including the bottommost surface of the vertical alternating stack (32, 46) to a second horizontal plane HP2 including the topmost surface of the vertical alternating stack (32, 46).

[0093] refer to FIG. 10A to FIG. 10E, a second column cavity 39 can be formed by removing the sacrificial material column 34 (which is the second part of the sacrificial line trench filling structure 33L) without removing the source / drain column structure 64 or the sacrificial backside trench filling structure 36. For example, if a sacrificial backside trench filling structure 36 is present, a photoresist layer (not shown) can be applied over the first exemplary structure, and the photoresist layer can be photolithographically patterned to form an opening in the area covering the sacrificial material column 34. Alternatively, if the sacrificial backside trench filling structure 36 is not present in this step, the photoresist layer can be omitted. The sacrificial material column 34 can be removed by performing a selective etching process that selectively etches the sacrificial filling material of the sacrificial material column 34 relative to the material of the memory film 50 and the first through-hole level dielectric layer 16. The selective etching process may include an anisotropic etching process or an isotropic etching process. A second column cavity 39 can be formed in each volume from which the sacrificial material column 34 is removed. A pair of inner sidewalls of the memory film 50 and sidewalls of a pair of source / drain pillar structures 64 may be physically exposed around each second pillar cavity 39. Generally, an array of second pillar cavities 39 may be formed by removing a second material portion of a sacrificial line trench filling structure 33L. In one embodiment, an array of second pillar cavities 39 may be formed by removing a second material portion of a sacrificial line trench filling structure 31L between adjacent pairs of source / drain pillar structures 64.

[0094] refer to FIG. 11A to FIG. 11E , a semiconductor channel material layer may be conformally deposited in the second pillar cavity 39 and over the top surface of the topmost insulating strip 32T. The semiconductor channel material layer includes a doped semiconductor material having a first conductivity type that is opposite to the second conductivity type of the dopant in the source / drain pillar structure 64. The first conductivity type may be p-type and the second conductivity type may be n-type, or vice versa. The atomic concentration of the dopant of the first conductivity type in the semiconductor channel material layer may be in the range of 1.0×10 15 / cm 3 to 1.0×10 18 / cm 3 Such as from 3.0×10 15 / cm 3 Up to 3.0×10 17 / cm 3 The semiconductor channel material layer may be in the range of 3 nm to 30 nm, such as 5 nm to 15 nm, but lower and higher atomic concentrations may also be used. The semiconductor channel material layer may be polycrystalline silicon or amorphous silicon deposited by a conformal deposition process such as a low pressure chemical vapor deposition (LPCVD) process. The thickness of the semiconductor channel material layer may be in the range of 3 nm to 30 nm, such as 5 nm to 15 nm, but smaller and larger thicknesses may also be used.

[0095] Optionally, a planarizable dielectric material such as silicon oxide may be deposited in the remaining unfilled volume of the second column cavity 39, if present. Excess portions of the planarizing dielectric material and the semiconductor channel material layer may be removed from above a second horizontal plane HP2 including the top surface of the topmost insulating strip 32T of the vertical alternating stack (32, 42) by a planarization process. The planarization process may use a chemical mechanical planarization (CMP) process and / or at least one recess etching process. Each remaining portion of the semiconductor channel material layer in the second column cavity 39 includes a semiconductor channel 60 substantially composed of a doped semiconductor material. Each remaining portion of the planarizable dielectric material in the semiconductor channel cavity includes an optional dielectric core 62. In one embodiment, the dielectric core 62 may have a top surface located within a horizontal plane including the topmost surface of the semiconductor channel 60, which may be the second horizontal plane HP2.

[0096] A two-dimensional array of semiconductor channels 60 may be formed in a peripheral volume of the array of second pillar cavities 39. An optional two-dimensional array of dielectric cores 62 may be formed in a central volume of the array of second pillar cavities 39. Each of the dielectric cores 62 may be formed within a corresponding one of the semiconductor channels 60. Each of the semiconductor channels 60 laterally surrounds a corresponding dielectric core 62.

[0097] Generally speaking, a laterally alternating sequence (60, 64) of semiconductor channels 60 and source / drain pillar structures 64 may be formed in each of the line trenches 31T on a corresponding one of the memory films 50. In each laterally alternating sequence (60, 64) of semiconductor channels 60 and source / drain pillar structures 64, a plurality of source / drain pillar structures 64 may be in direct contact with a corresponding pair of vertical semiconductor channels 60. The memory film 50 is located between each adjacent pair of vertical alternating stacks (32, 42) and the laterally alternating sequence (60, 64).

[0098] In one embodiment, each of the semiconductor channels 60 extends vertically from a first horizontal plane HP1 including the bottommost surface of the vertical alternating stack (32, 42) to a second horizontal plane HP2 including the topmost surface of the vertical alternating stack (32, 42). In one embodiment, each of the semiconductor channels 60 includes: a corresponding pair of first outer side walls, the corresponding pair of first outer side walls being parallel to the first horizontal direction hd1; and a corresponding pair of second outer side walls, the corresponding pair of second outer side walls being parallel to the second horizontal direction hd2. In one embodiment, each of the second outer side walls contacts a corresponding one of the memory films 50, and each of the first outer side walls contacts a corresponding one of the source / drain pillar structures 64. In one embodiment, the interface between the semiconductor channel 60 and the source / drain pillar structure 64 is located in a corresponding flat vertical plane perpendicular to the first horizontal plane HP1.

[0099] refer to FIG. 12A to FIG. 12E A photoresist layer (not shown) may be applied over the first exemplary structure and may be photolithographically patterned to cover the vertical alternating stacks (32, 42) and the lateral alternating sequence (60, 64) without covering the sacrificial backside trench fill structures 36. An etching process may be performed to remove the sacrificial backside trench fill structures 36.

[0100] Backside trenches 79 may be formed in the volume from which the sacrificial backside trench fill structures 36 were removed. The sidewalls of each sacrificial material strip 42 may be physically exposed to the backside trenches 79. Alternatively, if sacrificial backside trench fill structures 36 are not present, backside trenches 79 may be formed in a portion of the alternating stack (32, 42).

[0101] refer to FIG. 13A to FIG. 13E , the backside recess 43 may be formed by performing an isotropic etching process that selectively etches the material of the sacrificial material strip 42 to the material of the insulating strip 32 and the memory film 50. An isotropic etchant may be supplied into the backside trench 79 during the isotropic etching process. In an illustrative example, if the sacrificial material strip 42 includes silicon nitride, a wet etching process using hot phosphoric acid may be performed to remove the sacrificial material strip 42. The backside recess 43 may extend laterally along the first horizontal direction hd1. A pair of memory films 50 may be physically exposed to each backside recess 43.

[0102] refer to FIG. 14A to FIG. 14E, an optional backside blocking dielectric layer 44 may be deposited on the physically exposed surface surrounding the backside recess 43 and the backside trench 79. The backside blocking dielectric layer 44 may include a dielectric metal oxide material such as aluminum oxide, hafnium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, any other dielectric transition metal oxide, or alloys or layer stacks thereof. The thickness of the backside blocking dielectric layer 44 may be in the range of 2 nm to 20 nm, such as 3 nm to 10 nm, but smaller and larger thicknesses may also be used.

[0103] At least one conductive material may be deposited in the backside recess 43. The at least one conductive material may be conformally deposited using a precursor gas supplied into the backside recess 43 through the backside trench 79. For example, a metal barrier layer may be deposited directly on the physically exposed surface of the blocking dielectric layer 52 in the backside recess 43. The metal barrier layer includes a conductive metal material that may serve as a diffusion barrier and / or adhesion promoting layer for a subsequently deposited metal fill material. The metal barrier layer may include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer may be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, but smaller and larger thicknesses may also be used. In one embodiment, the metal barrier layer may be substantially composed of a conductive metal nitride such as TiN.

[0104] The metal filling material is deposited in the remaining volume of the back side recess 43, on the sidewalls of the back side trench 79, and above the topmost insulating strip 32T to form a metal filling material portion. The metal filling material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. In one embodiment, the metal filling material portion can be substantially composed of at least one elemental metal. At least one elemental metal of the metal filling material portion can be selected from, for example, tungsten, cobalt, molybdenum, ruthenium, titanium, or tantalum. In one embodiment, the metal filling material portion can be substantially composed of a single elemental metal. In one embodiment, the metal filling material portion includes tungsten deposited using a fluorine-containing precursor gas such as WF6. In one embodiment, the metal filling material portion can be a tungsten layer including residual fluorine atoms as impurities.

[0105] A plurality of conductive strips 46 may be formed in the plurality of backside recesses 43, and a continuous metal material layer (not shown) may be formed on the sidewalls of the backside trenches 79 and over the topmost insulating strip 32T. The continuous metal material layer is etched back from the sidewalls of the backside trenches 79 and over the topmost insulating strip 32T, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Portions of the backside blocking dielectric layer 44 formed within the backside trenches 79 or over the second horizontal plane HP2 may be removed by performing an etching process.

[0106] Each remaining portion of the deposited metal material in the backside recess 43 constitutes a conductive strip 46. Each conductive strip 46 can be a word line (e.g., a control gate electrode of a charge storage transistor). Therefore, after forming the semiconductor channel 60, the sacrificial material strip 42 is replaced by the conductive strip 46. A vertical alternating stack of insulating strips 32 and conductive strips 46 is formed above the substrate 8. The vertical alternating stacks (32, 46) can be laterally spaced apart from each other by line trenches 31L. Each conductive strip 46 includes a portion of a metal barrier layer and a metal filling material portion located between vertically adjacent pairs of dielectric material strips (such as a pair of insulating strips 32) and between laterally adjacent pairs of memory films 50 located within corresponding line trenches 31L.

[0107] Each conductive strip 46 can be used as a combination of a plurality of transistor gate electrodes (e.g., control gate electrodes) located at the same level and a word line that electrically interconnects (i.e., electrically shorts) the plurality of gate electrodes located at the same level. The plurality of gate electrodes within each conductive strip 46 are gate electrodes of charge storage field effect transistors in a NOR configuration. In other words, each conductive strip 46 can be a word line used as a common gate electrode for a plurality of transistors.

[0108] Generally, the sacrificial material strips 42 may be replaced with conductive strips 46. Vertical alternating stacks (32, 46) of insulating strips 32 and conductive strips 46 may be formed over the substrate 8. The vertical alternating stacks (32, 46) may be laterally spaced apart from each other by line trenches 31T filled with respective laterally alternating sequences (60, 64) of semiconductor channels 60 and source / drain pillar structures 64. In one embodiment, each of the conductive strips 46 is laterally spaced apart from a respective nearest one of the memory films 50 by a respective backside blocking dielectric layer 44, and is laterally spaced apart from a respective upper insulating strip 32 and a respective lower insulating strip 32 by a respective backside blocking dielectric layer 44.

[0109] Although embodiments are described in which the spacer material layer is formed as a sacrificial material layer 42L, embodiments are expressly contemplated herein in which the spacer material layer is formed as a conductive layer and is divided into conductive strips 46. In one embodiment, when forming the line trenches 31L, the vertical alternating sequence may be divided into multiple alternating stacks of insulating strips 32 and conductive strips 46.

[0110] Semiconductor channel 60, portions of a pair of source / drain pillar structures 64 contacting semiconductor channel 60, portions of memory film 50 adjacent to semiconductor channel 60, and portions of conductive strip 46 laterally spaced apart from semiconductor channel 60 by portions of memory film 50 constitute a NOR memory cell.

[0111] refer to FIG. 15A to FIG. 15E , a dielectric filling material such as silicon oxide may be deposited in the backside trench 79 to form a dielectric backside trench filling structure 76. In one embodiment, the dielectric backside trench filling structure 76 may fill the entire volume of the backside trench 79. The horizontal portion of the dielectric filling material deposited above the horizontal plane including the top surface of the topmost insulating strip 32T forms a dielectric material layer, which is referred to herein as a second via level dielectric layer 80.

[0112] A conductive second source / drain connection via structure 84 may be formed on a top surface of a corresponding one of the source / drain pillar structures 64 through the second via level dielectric layer 80. Each source / drain pillar structure 64 that is not contacted by a corresponding first source / drain connection via structure 24 may be contacted by a corresponding second source / drain connection via structure 84. Generally speaking, rows of first (e.g., bottom) source / drain connection via structures 24 and rows of second (e.g., top) source / drain connection via structures 84 may alternate along a first horizontal direction hd1. The source / drain pillar structures 64 may be arranged as multiple rows of source / drain pillar structures 64, such that each row of source / drain pillar structures 64 is arranged along a second horizontal direction hd2, and the multiple rows of source / drain pillar structures are laterally spaced apart from each other along the first horizontal direction hd1. When the plurality of rows are numbered with positive integers starting from 1, each odd-numbered row of the source / drain pillar structures 64 may be contacted by the first source / drain connection via structure 24, and each even-numbered row of the source / drain pillar structures 64 may be contacted by the second source / drain connection via structure 84. Alternatively, each even-numbered row of the source / drain pillar structures 64 may be contacted by the first source / drain connection via structure 24, and each odd-numbered row of the source / drain pillar structures 64 may be contacted by the second source / drain connection via structure 84. Each source / drain pillar structure 64 may be contacted by one of the first source / drain connection via structures 24 or one of the second source / drain connection via structures 84.

[0113] refer to FIG. 16A to FIG. 16E , a second line-level dielectric layer 90 may be deposited over the second via-level dielectric layer 80. Second bit lines 82 may be formed on respective subsets of the second source / drain connection via structures 84 in the second line-level dielectric layer 90. In one embodiment, the second bit lines 82 may extend laterally along the first horizontal direction hd1. In one embodiment, each second bit line 82 may contact a second source / drain connection via structure 82 within each row of source / drain connection via structures 82 arranged along the second horizontal direction hd2.

[0114] Common Reference Figures 1A to 16E , a semiconductor structure includes: a vertical alternating stack (32, 46) of insulating strips 32 and conductive strips 46 laterally spaced apart from each other by line trenches 31T; a laterally alternating sequence (60, 64) of semiconductor channels 60 and source / drain pillar structures 64 located within a corresponding one of the line trenches 31T; and a memory film 50 located between each adjacent pair of the vertical alternating stack (32, 46) and the laterally alternating sequence (60, 64), wherein each of a plurality of source / drain pillar structures 64 is in direct contact with a corresponding pair of vertical semiconductor channels 60. In one embodiment, each of the non-edge source / drain pillar structures 64 is in direct contact with a corresponding pair of vertical semiconductor channels 60. The edge source / drain pillar structure 64 located at the end of the line trench 31T may contact only one vertical semiconductor channel 60.

[0115] In one embodiment, each of the semiconductor channels 60 extends vertically from a first horizontal plane HP1 including the bottommost surface of the vertical alternating stack (32, 46) to a second horizontal plane HP2 including the topmost surface of the vertical alternating stack (32, 46). In one embodiment, the line trench 31T extends laterally along the second horizontal direction hd2 and has a corresponding uniform width along the first horizontal direction hd1 perpendicular to the second horizontal direction hd2. In one embodiment, each of the semiconductor channels 60 includes: a corresponding pair of first outer side walls, the corresponding pair of first outer side walls are parallel to the first horizontal direction hd1; and a corresponding pair of second outer side walls, the corresponding pair of second outer side walls are parallel to the second horizontal direction hd2. In one embodiment, each of the first outer side walls contacts a corresponding one of the source / drain pillar structures 64, and each of the second outer side walls contacts a corresponding one of the memory films 50.

[0116] In one embodiment, the source / drain pillar structure 64 extends vertically from a first horizontal plane HP1 including the bottommost surface of the vertical alternating stack (32, 46) to a second horizontal plane HP2 including the topmost surface of the vertical alternating stack (32, 46). In one embodiment, the interface between the semiconductor channel 60 and the source / drain pillar structure 64 is located in a corresponding flat vertical plane perpendicular to the first horizontal plane HP1. In one embodiment, each of the semiconductor channels 60 laterally surrounds a corresponding dielectric core having a top surface located in a horizontal plane including the topmost surface of the semiconductor channel 60.

[0117] In one embodiment, the semiconductor structure also includes a first source / drain connection via structure 24 located below a first subset of source / drain pillar structures 64. Each first source / drain connection via structure in the first source / drain connection 24 via structure contacts the bottom horizontal surface of a corresponding source / drain pillar structure in the first subset of source / drain pillar structures 64. The semiconductor structure also includes a second source / drain connection via structure 84 located above a second subset of source / drain pillar structures 64. Each second source / drain connection via structure in the second source / drain connection via structure 84 contacts the top horizontal surface of a corresponding source / drain pillar structure in the second subset of source / drain pillar structures 64. The semiconductor structure also includes an array of semiconductor channel contact via structures 28. Each semiconductor channel contact via structure in the semiconductor channel contact via structure 28 contacts a corresponding semiconductor channel in the semiconductor channel 60. The semiconductor structure also includes a first bit line 22 and a second bit line 82, wherein the first bit line contacts the bottom surface of the first source / drain connection through-hole structure 24 and extends laterally along a first horizontal direction hd1 perpendicular to the longitudinal second direction hd2 of the line groove 31T, and the second bit line contacts the top surface of the second source / drain connection through-hole structure 82 and extends laterally along a first horizontal direction hd1 perpendicular to the longitudinal second direction hd2 of the line groove 31T.

[0118] In one embodiment, each of the memory films 50 includes a layer stack that includes, from one side to the other, a tunneling dielectric layer 56, a charge storage layer 54, and a blocking dielectric layer 52. In one embodiment, the conductive strips 46 are laterally spaced apart from the respective nearest one of the memory films 50 by the respective backside blocking dielectric layer 44, and are laterally spaced apart from the respective overlying insulating strips 32 and the respective underlying insulating strips 32 by the respective backside blocking dielectric layer 44.

[0119] The vertical alternating stacks (32, 46) of insulating strips 32 and conductive strips 46 may be laterally spaced apart from each other by line trenches 31T. The laterally alternating sequence (60, 64) of semiconductor channels 60 and source / drain pillar structures 64 may be located within a corresponding one of the line trenches 31T. The charge storage field effect transistor in which the source / drain pillar structure (i.e., source region and drain region) 64 is accessed by the first bit line 22 (e.g., connected from below) is referred to herein as a first field effect transistor, and the charge storage field effect transistor in which the source / drain pillar structure (i.e., source region and drain region) 64 is accessed by the second bit line 82 (e.g., connected from above) is referred to herein as a second field effect transistor. A group of all first transistors including a corresponding row of source / drain pillar structures 64 located within a corresponding line trench 31T constitutes a first field effect transistor string. A group of all second field effect transistors including a corresponding row of source / drain pillar structures 64 located in a corresponding line trench 31T constitutes a second field effect transistor string.

[0120] Fig.17 A circuit diagram of a NOR memory device including an example of a first exemplary structure in a per-cell unit operation mode according to a first embodiment of the present disclosure is shown. In general, Fig.17 The NOR memory device shown may include: vertical alternating stacks (32, 46) of insulating strips 32 and conductive strips 46 that are laterally spaced apart from each other by line trenches 31T; a laterally alternating sequence (60, 64) of semiconductor channels 60 and source / drain pillar structures 64 located within a corresponding one of the line trenches 31T; and a three-dimensional array of memory elements. Each of the memory elements is located between a corresponding one of the semiconductor channels 60 and a corresponding one of the conductive strips 46 and includes a portion of the memory film 50 (e.g., a portion of the charge storage layer 54). In general, the vertical alternating stacks (32, 46) may be numbered with positive integers starting from 1 along the first horizontal direction hd1. The i-th vertical alternating stack (32, 46) includes a vertical alternating sequence of insulating strips 32 and conductive strips 46. The conductive strip 46 within the i-th vertical alternating stack (32, 46) includes a plurality of word lines WLk(i), which may be numbered, for example, from bottom to top by a non-negative integer k. In the illustrated example, two word lines WL1(i) and WL2(i) are shown. The peripheral circuit 400 may be disposed below, in, and / or on the first exemplary structure to provide control signals for programming, reading, and erasing each memory cell within the first exemplary structure.

[0121] In one embodiment, each memory cell 100 includes a charge storage transistor (eg, Fig.174 ), the charge storage transistor includes a control gate electrode (including a portion of one conductive strip 46) as part of a word line (e.g., WL1), a semiconductor channel 60 contacting a pair of source / drain pillar structures 64, and a memory film 50 located between the semiconductor channel 60 and the control gate electrode (including a portion of an adjacent conductive strip 46). Two adjacent memory cells 100 (e.g., transistors 1 and 5, or transistors 2 and 6) share a common source / drain pillar structure 64, which is electrically connected to a common bit line (22 or 82). Multiple adjacent memory cells 100 (e.g., transistors 1, 2, 5, and 6) also share the same word line (e.g., WL1). Therefore, the NOR memory device of the first embodiment is more compact than prior art NOR memory devices in which adjacent memory cells do not share a common source / drain pillar structure 64 because prior art NOR memory devices require space for separate bit lines (22, 82) and source / drain pillar structures 64 for each memory cell.

[0122] Refer to the above Fig.17 and will be described below Fig.42 The three-dimensional memory device includes a first vertical stack of a first field effect transistor string S1 and a second vertical stack of a second field effect transistor string S2. The first vertical stack alternates with the second vertical stack along a first horizontal direction.

[0123] Each first field effect transistor string in the first field effect transistor string S1 includes a series connection of a corresponding group of first field effect transistors (100 or 200), which are electrically connected to each other so that each adjacent pair of first field effect transistors share a corresponding first source / drain region in a plurality of first source / drain regions 68. Each second field effect transistor string in the second field effect transistor string S2 includes a series connection of a corresponding group of second field effect transistors (100 or 200), which are electrically connected to each other so that each adjacent pair of second field effect transistors share a corresponding second source / drain region in a second source / drain region 69. The series connection of the corresponding group of first field effect transistors (100 or 200) shares a corresponding word line (e.g., WL1(i)) in a plurality of word lines 46. The first source / drain regions 68 are located in different vertical levels in the corresponding first source / drain pillar structure (64 or 61). The second source / drain regions 69 are located in different vertical levels in the corresponding second source / drain pillar structures ( 64 or 61 ).

[0124] exist Fig.17 , the first field effect transistor 100 is marked with an even number in a circle, and the second field effect transistor 100 is marked with an odd number in a circle.

[0125] In a first embodiment, adjacent pairs of a first field effect transistor string in the first field effect transistor string S1 and a second field effect transistor string in the second field effect transistor string S2 share a corresponding one of the plurality of word lines 46 (e.g., WL1(i)). The source / drain region 68 of each first field effect transistor 100 in the first field effect transistor string S1 is accessible by a corresponding first (e.g., lower) bit line 22, which is located at Fig.17 The subscript p is a positive integer, such as 1, 2, 3, 4, etc. The source / drain region 69 of each second field effect transistor 100 in the second field effect transistor string S2 can be accessed by a corresponding second (e.g., upper) bit line 82, which is located at Fig.17 Subscript q is a positive integer, such as 1, 2, 3, 4, etc. Therefore, each second source / drain pillar structure 64 within the second field effect transistor string includes a vertical stack of second source / drain regions 69 electrically connected to each other.

[0126] In the first embodiment, the three-dimensional memory device includes: a first bit line 22 located below a first source / drain pillar structure 64; and a second bit line 82 located above a second source / drain pillar structure 64. The word lines (eg, conductive strips 46) are laterally spaced apart along a first horizontal direction hd1.

[0127] In various embodiments, each first field effect transistor string in the first field effect transistor string S1 includes a corresponding first memory film 50, which extends continuously through the corresponding series connection of the first field effect transistor (100 or 200) and is shared by the corresponding series connection of the first field effect transistor; and each second field effect transistor string in the second field effect transistor string S2 includes a corresponding second memory film 50, which extends continuously through the corresponding series connection of the second field effect transistor (100 or 200) and is shared by the corresponding series connection of the second field effect transistor.

[0128] refer to Fig.18 and Fig.19, shows a method for programming a selected memory cell 100S within a selected first field effect transistor 6. The selected memory cell 100S may be programmed by: applying a gate programming bias voltage (Vg_pgm) between 6V and 10V (such as 8V) to the word line WL1(i) of the selected memory cell 100S; applying a programming voltage difference (e.g., 3V to 5V) between two first bit lines 22 connected to the source / drain pillar structure 64 of the selected memory cell 100S; and applying 0V to unselected word lines. The programming voltage difference can be provided by the following operations: applying 0V to one of the first bit lines 22 of the source / drain pillar structure 64 (referred to herein as the source side source / drain pillar structure 64) electrically connected to the selected memory cell 100S; and applying a drain side programming bias voltage (Vd_pgm) to the other source / drain pillar structure 64 (referred to herein as the drain side source / drain pillar structure 64) of the selected memory cell 100S. All first bit lines 22 located on one side of the source side source / drain pillar structure 64 can be biased at 0V. All first bit lines 22 located on one side of the drain side source / drain pillar structure 64 can be biased at the drain side programming bias voltage (Vd_pgm). All second bit lines 82 can be biased at the drain side programming bias voltage (Vd_pgm) to prevent programming of any unselected memory cell located in the second field effect transistor. The drain side programming bias voltage Vd_pgm may be lower than the gate programming bias voltage Vg_pgm, and may have a magnitude of 3 V to 5 V. If a memory cell within the second field effect transistor is selected, a similar programming method may be employed to program the selected memory cell.

[0129] Generally speaking, a method of operating a three-dimensional memory device of various embodiments includes: applying 0V to a first source / drain region 68 located on a first side of a semiconductor channel 60 of a selected first field effect transistor 6; applying a drain side programming bias voltage Vd_pgm to another first source / drain region 68 located on a second side of the semiconductor channel 60 of the selected first field effect transistor 6; and applying a gate programming bias voltage Vg_pgm to a first word line WL1(i) of the selected first field effect transistor 6 to program the selected first field effect transistor 6.

[0130] In order to inject channel hot electrons Fig.18 and Fig.19The three-dimensional memory device of the first embodiment shown in the figure is programmed, and the programming method includes: applying 0V to each first source / drain region 68 in the first field effect transistor string S1 located on the first side (for example, the source side) of the semiconductor channel 60 of the selected first field effect transistor 6; and applying a drain-side programming bias voltage Vd_pgm to each first source / drain region 68 in the first field effect transistor string S1 located on the second side (for example, the drain side) of the semiconductor channel 60 of the selected first field effect transistor 6. The method also includes: applying a drain-side programming bias voltage Vd_pgm to each second source / drain region 69 during programming of the selected first field effect transistor 6; and applying 0V to all word lines except the first word line (WL1(i)) among a plurality of word lines (for example, WL2(i)) during programming of the selected first field effect transistor 6.

[0131] refer to Fig. 20 and Fig.21 , the entire memory block in the three-dimensional memory device of the first embodiment can be erased by the following operations: applying an erase bias voltage V_erase (the erase bias voltage may be in the range of -15V to -25V, such as -20V) to each of the first bit line 22 and the second bit line 82; and applying 0V to all word lines WLk(i).

[0132] Generally speaking, the three-dimensional memory device of the first embodiment can be erased by applying an erase bias voltage to the first source / drain region and the second source / drain region (68, 69); and applying 0V to each of the plurality of word lines 46 (eg, WLk(i)).

[0133] refer to Fig. 22 and Fig.23, shows a method of reading a selected memory cell 100S within a selected first field effect transistor 6 of a first embodiment. In one embodiment, the selected memory cell 100S may be read by applying a gate read bias voltage (Vg_read) (e.g., 6V to 10V (such as 8V)) to a selected word line WL1(i) of the selected memory cell 100S; and applying a read voltage difference between two first bit lines 22 connected to a source / drain pillar structure 64 of the selected memory cell 100S. The bit lines (22, 82) not connected to the source / drain pillar structure 64 of the selected memory cell 100S may be electrically biased so that there is no voltage difference between adjacent pairs of first bit lines 22 and between adjacent pairs of second bit lines 82. The read voltage difference can be provided by the following operations: applying 0V to one of the first bit lines 22 that is electrically connected to the source side source / drain pillar structure 64 of the selected memory cell 100S; and applying a bit line read bias voltage (Vb_read) to the drain side source / drain pillar structure 64 of the selected memory cell 100S (the bit line read bias voltage can be in the range of 1V to 1.5V).

[0134] Generally speaking, the selected memory cell 100S within the selected first field effect transistor 6 of the first embodiment can be read by the following operations: applying 0V to each first source / drain region 68 within the first field effect transistor string S1 located on the first side (e.g., the drain side) of the semiconductor channel 60 of the selected first field effect transistor 6; applying a bit line read bias voltage Vb_read to each first source / drain region 68 within the first field effect transistor string S1 located on the second side (e.g., the drain side) of the semiconductor channel 60 of the selected first field effect transistor 6; and applying a gate read bias voltage (Vg_read) to the first word line WL1(i) of the selected first field effect transistor 6 to read the selected first field effect transistor.

[0135] refer to Fig.24 , shows an enlarged view of the NOR memory cell 100S of the first embodiment during operation in a dual-bit per cell operation mode. In this case, each of the field effect transistors in the first exemplary structure (e.g., transistors 1 to 9, such as the selected transistor 6) may include a multi-bit memory element 54M including a corresponding pair of charge storage material portions (54E1, 54E2).

[0136] According to one aspect of the present disclosure, each NOR memory cell can be operated in a dual-bit per cell operation mode, so that each portion of the charge storage layer 54 of the memory film 50 near the interface between the source / drain pillar structure 64 and the semiconductor channel 60 can be used as an independent charge storage element 54E1 or 54E2. Therefore, a charge (e.g., electron) representing a "1" value of a first bit (bit #1) can be stored in a first portion 54E1 of the charge storage layer 54 adjacent to a first source / drain pillar structure 64 (e.g., SL0) electrically connected to a bit line (e.g., BL1), while a separate charge representing a "1" value of a second bit (bit #2) can be stored in a second portion 54E2 of the charge storage layer 54 adjacent to a second source / drain pillar structure 64 (e.g., SL1) electrically connected to another bit line (e.g., BL2). The absence of charge in each of the charge storage material portions (54E1, 54E2) represents a "0" value of the corresponding bit.

[0137] Since each semiconductor channel 60 contacts two different memory films 50 of two different memory cells (i.e., two different charge storage transistors 100), four data bits can be stored in two memory films 50 contacting a single semiconductor channel 60. This increases device density. In contrast, prior art NOR memory cells typically store only one data bit per cell.

[0138] refer to Fig.25 , shows a circuit diagram of a NOR memory device of the first embodiment in a dual bit per cell operation mode. Each charge storage transistor 100 includes a multi-bit memory element 54M including a corresponding pair of charge storage material portions (54E1, 54E2).

[0139] refer to Fig.26 and Fig. 27 , shows an exemplary circuit of the first embodiment of the present disclosure during a programming operation in a dual bit per cell operation mode. Fig.26 represents an electrical biasing scheme for programming the first charge storage material portion 54E1 in the selected first field effect transistor 6, and Fig. 27 : represents an electrical bias scheme for programming the second charge storage material portion 54E2 in the selected first field effect transistor 6. The selected charge storage material portion 54E1 or 54E2 can be programmed by: applying a gate programming bias voltage (Vg_pgm) between 6V and 10V (such as 8V) to the word line WL1(i) of the selected charge storage material portion 54E; applying a programming voltage difference between the two first bit lines 22 connected to the source / drain pillar structure 64 of the selected charge storage material portion 54E1 or 54E2; and applying 0V to the unselected word line 46.

[0140] For the sake of Fig.26 As shown, the "A" cell (i.e., the first data bit) is programmed, and the source / drain pillar structure 64 adjacent to the selected charge storage material portion 54E1 can be biased at Vd_pgm to cause charge tunneling into the selected charge storage material portion 54E1. The programming voltage difference can be provided by the following operations: applying 0V to one of the first bit lines 22 of the source / drain pillar structure 64 electrically connected to the unselected charge storage material portion 54E2 located adjacent to the selected memory cell 100S; and applying a drain side programming bias voltage (Vd_pgm) to the first bit line 22 of the other source / drain pillar structure 64 electrically connected to the selected charge storage material portion 54E1 located adjacent to the selected memory cell 100S. All first bit lines 22 located on the unselected charge storage material portion side 54E2 can be biased at 0V. All first bit lines 22 located on the selected charge storage material portion side 54E1 can be biased at the drain side programming bias voltage (Vd_pgm). All second bit lines 82 may be biased at a drain side programming bias voltage (Vd_pgm). The drain side programming bias voltage Vd_pgm may be lower than the gate programming bias voltage Vg_pgm and may have a magnitude of 3V to 5V.

[0141] For the sake of Fig. 27 The "B" cell (i.e., the second data bit) is shown being programmed, with the selected charge storage material portion side 54E2 being inverted from the unselected charge storage material portion side 54E1, and thus also inverting the application of Vd_pgm and 0V to the bit line 22 on the opposite side of the selected charge storage transistor 6. If a memory cell within the second field effect transistor is selected, a similar programming method may be employed to program the selected memory cell.

[0142] Generally speaking, the selected first field effect transistor 6 includes a first charge storage material portion 54E1 positioned adjacent to a first side (eg, left side) of the semiconductor channel 60 and a second charge storage material portion 54E2 positioned adjacent to a second side (eg, right side) of the semiconductor channel 60. Fig. 27 During programming of the selected first field effect transistor 6, the second charge storage material portion 54E2 corresponding to the second data bit is programmed, while the first charge storage material portion 54E1 corresponding to the first data bit is not programmed.

[0143] refer to Fig.28, shows an exemplary circuit of the first embodiment of the present disclosure during an erase operation in a dual bit per cell operation mode. The entire memory block in the three-dimensional memory device can be erased by applying an erase bias voltage V_erase (the erase bias voltage may be in the range of -15V to -25V, such as -20V) to each of the first bit line 22 and the second bit line 82; and applying 0V to all word lines WLk(i), as described above.

[0144] refer to Fig.29 and Fig.30 , shows an exemplary circuit of the first embodiment of the present disclosure during a read operation in a dual-bit per cell operation mode. The read operation for the A cell and the B cell is the same as the programming operation for the A cell and the B cell, except that a gate read bias voltage (Vg_read) is applied instead of a gate programming bias voltage, and a bit line read bias voltage (Vb_read) is applied instead of a drain programming bias voltage. The first data bit or the second data bit of the selected charge storage field effect transistor 6 can be read without reading the other of the first data bit or the second data bit.

[0145] Generally speaking, the exemplary circuit of the first embodiment of the present disclosure can be read by the following operations: applying 0V to each first source / drain region 68 within the first field effect transistor string S1 located on the first side (e.g., the left side) of the semiconductor channel 60 of the selected first field effect transistor 6; applying a bit line read bias voltage to each first source / drain region 68 within the first field effect transistor string S1 located on the second side (e.g., the right side) of the semiconductor channel 60 of the selected first field effect transistor 6; and applying a gate read bias voltage to the first word line (e.g., WL1(i)) of the selected first field effect transistor 6 to read the second data bit of the selected first field effect transistor.

[0146] refer to Fig.31A and Fig.31B , shows a second exemplary structure according to the second embodiment of the present disclosure. The second exemplary structure includes a vertical repetition of multiple instances of an optional bottommost insulating layer 32LB and a cell layer stack (42LA, 50A, 160L, 50B, 42LB, 32L). The topmost insulating layer 32LT may be located above the vertical repetition of multiple instances of the cell layer stack. Each instance of the cell layer stack may include, for example, a first sacrificial material layer 42LA, a first memory film 50A, a semiconductor material layer 160L, a second memory film 50B, a second sacrificial material layer 42B, and an insulating layer 32L. The first sacrificial material layer 42LA and the second sacrificial material layer 42LB are collectively referred to as sacrificial material layers 42L. The first memory film 50A and the second memory film 50B are collectively referred to as memory films 50.

[0147] The sacrificial material layer 42L in the second exemplary structure may have the same material composition as the sacrificial material layer 42L in the first exemplary structure, and may be formed using the same deposition process as the sacrificial material layer in the first exemplary structure. The insulating layer 32L in the second exemplary structure may have the same material composition as the insulating layer 32L in the first exemplary structure, and may be formed using the same deposition process as the insulating layer in the first exemplary structure. Each memory film 50 in the second exemplary structure may include the same layer stack as the memory film 50 in the first exemplary structure. In one embodiment, each first memory film 50A may include a blocking dielectric layer 56, a charge storage layer 54, and a tunneling dielectric layer 52 from bottom to top; and each second memory film 50B may include a tunneling dielectric layer 52, a charge storage layer 54, and a blocking dielectric layer 56 from bottom to top. Therefore, the tunneling dielectric layer 52 of the two memory films 50A and 50B is positioned adjacent to the corresponding semiconductor material layer 160L located between the first memory film 50A and the second memory film 50B. The semiconductor material layer 160L in the second exemplary structure may have the same material composition as the semiconductor channel 60 in the first exemplary structure. Thus, the semiconductor material layer 160L may include a doped semiconductor material (e.g., polysilicon or amorphous silicon) having a first conductivity type. The thickness of each semiconductor material layer 160L may be in the range of 5 nm to 100 nm, such as 10 nm to 50 nm, but smaller and larger thicknesses may also be employed. The total number of instances of the unit layer stack (42LA, 50A, 160L, 50B, 42LB, 32L) within the vertical repetition may be in the range of from 2 to 1,024, such as 8 to 128. An embodiment is also contemplated in which only a single instance of the unit layer stack (42LA, 50A, 160L, 50B, 42LB, 32L) is employed.

[0148] refer to Fig.32A and Fig.32B A photoresist layer (not shown) may be applied over the second exemplary structure and the photoresist layer may be photolithographically patterned to form rows of discrete openings therein. Each row of discrete openings in the photoresist layer may include a plurality of discrete openings arranged along a first horizontal direction hd1. The rows of source / drain openings may be laterally spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1.

[0149] An anisotropic etching process may be performed to transfer the pattern of discrete openings in the photoresist layer through the topmost insulating layer 32LT and through the vertical repetition of multiple instances of the cell layer stack (42LA, 50A, 160L, 50B, 42LB, 32L). Rows of source / drain openings 29 may be formed through the vertical repetition of multiple instances of the cell layer stack (42LA, 50A, 160L, 50B, 42LB, 32L). Each row of source / drain openings 29 includes a respective set of source / drain openings 29 arranged along a first horizontal direction hd1, and the rows of source / drain openings 29 are laterally spaced apart from each other along a second horizontal direction hd2.

[0150] In one embodiment, a two-dimensional array of source / drain openings 29 may be formed by vertical repetition of multiple instances of the unit layer stack (42LA, 50A, 160L, 50B, 42LB, 32L). The bottom surface of the source / drain opening 29 may be formed in the bottommost insulating layer 32LB. Each source / drain opening in the source / drain opening 29 may have a circular horizontal cross-sectional shape, an elliptical horizontal cross-sectional shape, a rectangular horizontal cross-sectional shape, a rounded rectangular horizontal cross-sectional shape (i.e., a shape obtained from a rectangle by rounding the four corners), or a horizontal cross-sectional shape of any other two-dimensional shape with a closed perimeter. In one embodiment, each source / drain opening in the source / drain opening 29 has a corresponding circular horizontal cross-sectional shape. The maximum lateral dimension (such as a diameter) of each source / drain opening 29 may be in the range of 20nm to 200nm, such as 80nm to 120nm, but smaller and larger thicknesses may also be used. In one embodiment, the source / drain openings 29 may be arranged in a periodic two-dimensional array, such as a hexagonal array or a rectangular array.

[0151] refer to Fig.33A and Fig.33B, an optional isotropic etching process may be performed to selectively and isotropically recess the semiconductor material of the semiconductor material layer 160L relative to the material of the insulating layer 32L, the sacrificial material layer 42L, and the memory film 50. For example, a timed wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) may be performed to laterally recess the physically exposed sidewalls of the semiconductor material layer 160L surrounding each source / drain opening 29. The lateral recess distance of the isotropic etching process is less than half of the nearest neighbor spacing between the source / drain openings 29 and may be in the range of 2 nm to 100 nm, such as 10 nm to 50 nm, although smaller or larger lateral recess distances may also be used. A vertical stack of annular recesses 29R may be formed around each source / drain opening 29. Each annular recess 29R is a lateral extension of a corresponding source / drain opening 29 formed at the level of the semiconductor material layer 160L.

[0152] refer to Fig.34A and Fig.34B , a doped semiconductor material may be conformally deposited in the source / drain opening 29. The doped semiconductor material deposited in the source / drain opening 29 may have a second conductivity type doping opposite to the first conductivity type. In one embodiment, the doped semiconductor material deposited in the source / drain opening 29 may include heavily doped polysilicon or heavily doped amorphous silicon (which is subsequently converted to doped polysilicon). The doped semiconductor material may include an atomic concentration of 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 The second conductivity type dopant may be within a range of , but smaller and larger atomic concentrations may also be used. The thickness of the deposited doped semiconductor material may be selected so that the annular recess 29R (i.e., the lateral protrusion) of the source / drain opening 29 is filled within the deposited doped semiconductor material. An anisotropic etching process may be performed to remove the horizontally extending portion of the deposited doped semiconductor material from above the topmost insulating layer 32LT and at the bottom of each source / drain opening 29. Each remaining portion of the deposited semiconductor material constitutes a source / drain column structure 61.

[0153] In one embodiment, each source / drain column structure 61 may have a cylindrical shape with a sidewall protrusion 61P. In one embodiment, the cylinder may be hollow and may laterally encapsulate the unfilled volume of the corresponding source / drain opening 29, which is referred to herein as the source / drain cavity 29'. Generally speaking, the source / drain column structure 61 may be formed at the peripheral portion of the source / drain opening 29. The source / drain column structure 61 has a doping of a second conductivity type opposite to the first conductivity type. The annular recess 29R of the source / drain opening 29 is filled with the lateral protrusion 61P of the source / drain column structure 61. In one embodiment, each lateral protrusion 61P in the group of lateral protrusions 61P has the same vertical thickness as the vertical sidewall of the semiconductor material layer 160L and contacts the vertical sidewall. The pn junction J is formed at each cylindrical interface between the lateral protrusion 61P of the corresponding source / drain column structure 61 and the corresponding semiconductor material layer 160L.

[0154] Generally speaking, the isotropic etching process that laterally recesses the sidewalls of the semiconductor material layer 160L in the source / drain openings 29 from the sidewalls of the insulating layer 32L, the sacrificial material layer 42L, and the memory film 50 causes each physical sidewall of the semiconductor material layer 160L to be laterally recessed by the same lateral recess distance. Therefore, the sidewall of the lateral protruding portion 61P of each source / drain pillar structure 61 that contacts the corresponding semiconductor material layer 160L may be laterally offset by a distance LOD from the vertical interface between the corresponding source / drain pillar structure 61 and the memory film 50, the insulating layer 32L, and the sacrificial material layer 42L in a plan view, as shown in FIG. Fig.34A shown.

[0155] In one embodiment, the portion of the source / drain opening 29 that passes through the memory film 50, the insulating layer 32L, and the sacrificial material layer 42L may have a corresponding circular horizontal cross-sectional shape, and the sidewall of the lateral protrusion 61P of each source / drain pillar structure 61 that contacts the semiconductor material layer 160L has a corresponding convex vertical surface. In one embodiment, each of the source / drain pillar structures 61 extends vertically from the bottommost layer within the vertical repetition of multiple instances of the unit layer stack (42LA, 50A, 160L, 50B, 42LB, 32L) to the topmost layer within the vertical repetition of multiple instances of the unit layer stack (42LA, 50A, 160L, 50B, 42LB, 32L). In one embodiment, each source / drain pillar structure in the source / drain pillar structure 61 includes a corresponding set of lateral protrusions 61P, and each lateral protrusion in the lateral protrusions 61P includes a corresponding horizontal bottom surface that contacts a corresponding horizontal top surface segment of a first memory film in the first memory film 50A and a corresponding horizontal top surface that contacts a corresponding horizontal bottom surface segment of a second memory film in the second memory film 50B.

[0156] refer to Fig.34C In an alternative configuration of the second embodiment, Fig.33A and Fig.33B Formation of the lateral recess 29R shown. In this alternative configuration, the source / drain pillar structure 61 has no lateral protruding portion 61P after deposition.

[0157] refer to Fig.35A and Fig.35B , an optional dielectric filling material such as silicon oxide may be deposited in the source / drain cavity 29' (if present) by a conformal deposition process. Excess portions of the dielectric filling material may be removed from above a horizontal plane including the top surface of the topmost insulating layer 32LT. Each remaining portion of the dielectric filling material filling the corresponding source / source / drain cavity 29' constitutes a dielectric core 66.

[0158] An activation annealing process may be performed to electrically activate dopants in the semiconductor material layer 160L and the source / drain pillar structures 61. In one embodiment, the duration and elevated temperature of the activation annealing process may be selected such that each pn junction J is offset outwardly from a vertical axis passing through the geometric center of the nearest source / drain pillar structure 61. Thus, each pn junction J may be formed at a target lateral offset distance from a vertical plane that includes the interface between the source / drain pillar structure 61 enclosed by the pn junction and the insulating layer 32L, the sacrificial material layer 42L, and the memory film 50. In one embodiment, each of the source / drain pillar structures 61 laterally surrounds a cylindrical dielectric core 66 that extends vertically through each layer within a vertical repetition of multiple instances of the cell layer stack (42LA, 50A, 160L, 50B, 42LB, 32L).

[0159] Generally speaking, the process conditions of the activation annealing process can be selected to optimize the lateral offset distance of the pn junction. If the formation of the lateral recessed portion 29R of the source / drain opening 29 is omitted, such as Fig.34C As shown, the lateral protrusion 61P is formed by laterally outdiffusion of the first conductivity type dopant from the source / drain pillar structure 61 into the adjacent semiconductor channel 160 during activation annealing. Therefore, in an alternative configuration of the second embodiment, the lateral protrusion 61P is formed after the deposition of the source / drain pillar structure 61.

[0160] refer to FIG. 36A to FIG. 36C A photoresist layer (not shown) may be applied over the vertical repetition of multiple instances of the topmost insulating layer 32LT and the cell layer stack (42LA, 50A, 160L, 50B, 42LB, 32L), and the photoresist layer may be photolithographically patterned to form linear openings extending laterally along the first horizontal direction hd1. Each linear opening in the photoresist layer may be formed between corresponding adjacent pairs of rows of source / drain pillar structures 61 and may extend laterally along the first horizontal direction hd1.

[0161] An anisotropic etching process may be performed to transfer the pattern of the linear openings in the photoresist layer through the topmost insulating layer 32LT and through the vertical repetition of multiple instances of the cell layer stack (42LA, 50A, 160L, 50B, 42LB, 32L). Line trenches 179 extending laterally along the first horizontal direction hd1 may be formed through the vertical repetition of multiple instances of the topmost insulating layer 32LT and the cell layer stack (42LA, 50A, 160L, 50B, 42LB, 32L). Line trenches 179 are formed between corresponding adjacent pairs of rows of source / drain pillar structures 61, i.e., between corresponding adjacent pairs of rows of source / drain openings 29.

[0162] According to one aspect of the present disclosure, each backside trench 179 may cut through the peripheral portion of the two rows of lateral protrusions 61P of the source / drain pillar structures 61. Therefore, when the backside trenches 179 are formed, each semiconductor material layer 160L may be divided into a two-dimensional array of discrete semiconductor channels 160 contacting a corresponding pair of source / drain pillar structures 61. Each lateral protrusion 61P of the source / drain pillar structure 61 may include a pair of flat vertical sidewall segments perpendicular to the second horizontal direction hd2.

[0163] The vertical stack of multiple instances of the unit layer stack (42LA, 50A, 160L, 50B, 42LB, 32L) is divided into a vertical stack of repeating units RU. The vertical stack of repeating units RU is staggered with line trenches 179 along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Each instance of the repeating unit RU includes a first sacrificial material strip 42A, a first memory film 50A, a row of discrete semiconductor channels 160 laterally spaced from each other along the first horizontal direction hd1, a second memory film 50B, a second sacrificial material strip 42B and an insulating strip 32. Each instance of the repeating unit RU extends laterally along the first horizontal direction hd1.

[0164] Each source / drain pillar structure 61 may include a corresponding set of lateral protrusions 61P, and each lateral protrusion 61P in the set of lateral protrusions 61P contacts a corresponding one of the discrete semiconductor channels 160, such as Fig.36B As shown. In one embodiment, each lateral protrusion 61P within the group of lateral protrusions 61P contacts a corresponding additional discrete semiconductor channel in the discrete semiconductor channels 160 for each source / drain pillar structure 61 except the outermost source / drain pillar structure 61 (i.e., except for the two source / drain pillar structures 61 located at the ends of each row of source / drain pillar structures 61 arranged along the first horizontal direction hd1). In one embodiment, the lateral protrusion 61P of the source / drain pillar structure 61 may have a uniform width along the second horizontal direction hd2, which may be the same as the width of the discrete semiconductor channel 160 along the second horizontal direction hd2.

[0165] refer to FIG. 37A to FIG. 37C , the backside recess 43 may be formed by performing an isotropic etching process that etches the material of the sacrificial material strip 42 selectively to the material of the insulating strip 32 and the memory film 50. An isotropic etchant may be supplied into the line trench 179 during the isotropic etching process. In the illustrative example, if the sacrificial material strip 42 includes silicon nitride, a wet etching process using hot phosphoric acid may be performed to remove the sacrificial material strip 42. The memory film 50 and the insulating layer 32 may be physically exposed to each backside recess 43.

[0166] refer to FIG. 38A to FIG. 38C , an oxidation process may be performed to oxidize the semiconductor material of the source / drain pillar structure 61 exposed in the backside recess 43 and various physically exposed surface portions of the lateral protrusion 61P of the source / drain pillar structure 61 and the semiconductor channel 60 exposed in the line trench 179. Various semiconductor oxide liners (57, 59, 67) may be formed by the oxidation process. The various semiconductor oxide liners (57, 59, 67) may include, for example: a tubular semiconductor oxide liner 57 that laterally surrounds the vertical extension of the corresponding source / drain pillar structure 61 and is laterally surrounded by the corresponding backside recess 43; a vertical flat semiconductor oxide liner 59 that contacts the flat vertical sidewall segments of the corresponding row of source / drain pillar structures 61 and the flat vertical sidewall segments of the corresponding row of semiconductor channels 160 and is physically exposed to the corresponding line trench 179; and an annular flat semiconductor oxide liner 67 that covers the annular top surface of the corresponding source / drain pillar structure 61. The thickness of each semiconductor silicon oxide liner (57, 59, 67) may be in the range of 8 nm to 30 nm, such as 10 nm to 20 nm, but smaller and larger thicknesses may also be employed.

[0167] refer to FIG. 39A to FIG. 39C , an optional backside blocking dielectric layer 44 may be deposited on the physically exposed surface surrounding the backside recess 43 and the line trench 179. The backside blocking dielectric layer 44 may include a dielectric metal oxide material such as aluminum oxide, hafnium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, any other dielectric transition metal oxide, or alloys or layer stacks thereof. The thickness of the backside blocking dielectric layer 44 may be in the range of 2 nm to 10 nm, such as 2.5 nm to 5 nm, but smaller and larger thicknesses may also be used.

[0168] refer to Fig.40A , Fig.40B and Fig.40C , at least one conductive material may be deposited in the back side recess 43. The at least one conductive material may include a metal barrier layer and a metal filler material. The at least one conductive material may include, for example, reference FIG. 14A to FIG. 14D A plurality of conductive strips 46 (i.e., strip-shaped conductive strips) may be formed in the plurality of backside recesses 43, and a continuous metal material layer (not shown) may be formed on the sidewalls of the line trenches 179 and over the topmost insulating strip 32T. The continuous metal material layer is etched back from the sidewalls of the line trenches 179 and over the topmost insulating strip 32T, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Portions of the backside blocking dielectric layer 44 formed within the line trenches 179 or over the topmost insulating strip 32T may be removed by performing an etching process.

[0169] Each remaining portion of the deposited metal material in the backside recess 43 constitutes a conductive strip 46. Each conductive strip 46 may be a word line. Therefore, after forming the semiconductor channel 160, the sacrificial material strip 42 is replaced with the conductive strip 46. The conductive strip 46 may include a first conductive strip 46A replacing the first sacrificial material strip 42A and a second conductive strip 46B replacing the second sacrificial material strip 42B. In one embodiment, each conductive strip 46 may include a corresponding metal barrier layer 46M and a corresponding metal filling material portion 46F.

[0170] Each conductive strip 46 can be used as a combination of multiple transistor gate electrodes (e.g., control gate electrodes) located at the same level and a word line that electrically interconnects (i.e., electrically shorts) multiple gate electrodes located at the same level. The multiple gate electrodes within each conductive strip 46 are gate electrodes of charge storage or ferroelectric field effect transistors in a NOR configuration. In other words, each conductive strip 46 can be a word line used as a common gate electrode for multiple NOR memory cells.

[0171] In general, the first sacrificial material strip 42A and the second sacrificial material strip 42B may be replaced with a first conductive strip 46A and a second conductive strip 46B. A vertical stack of repeating units RU may be formed between each adjacent pair of line trenches 179 above the substrate 8. Each instance of the repeating unit RU includes a first conductive strip 46A, a first memory film 50A, a row of discrete semiconductor channels 160 laterally spaced apart from each other along a first horizontal direction hd1, a second memory film 50B, a second conductive strip 46B, and an insulating strip 32. Each instance of the repeating unit RU extends laterally along the first horizontal direction hd1.

[0172] A row of source / drain pillar structures 61 extends vertically through each vertical repetition of multiple instances of the repeating unit RU. Each row of source / drain pillar structures 61 arranged along the first horizontal direction hd1 may be interlaced with a vertical stack of discrete semiconductor channels 160. Each vertical stack of semiconductor channels 160 may contact a pair of source / drain pillar structures 61. The vertical stack of semiconductor channels 160 may be arranged along the first horizontal direction hd1 and may be interlaced with the row of source / drain pillar structures 61. Each of the first conductive strip 46A, the first memory film 50A, the second memory film 50B, the second conductive strip 46B and the insulating strip 32 includes a corresponding row of source / drain openings 29, and a corresponding one of the source / drain pillar structures 61 extends vertically through the row of source / drain openings.

[0173] In one embodiment, each instance of the first conductive strip 46A may be optionally laterally spaced apart from each of the source / drain pillar structures 61 by a corresponding backside blocking dielectric layer 44, and may be vertically spaced apart from a corresponding instance of the first memory film 50A by a corresponding backside blocking dielectric layer 44. In one embodiment, each instance of the second conductive strip 46B may be optionally laterally spaced apart from each of the source / drain pillar structures 61 by a corresponding additional backside blocking dielectric layer 44, and may be vertically spaced apart from a corresponding instance of the second memory film 50B by a corresponding additional backside blocking dielectric layer 52.

[0174] refer to FIG. 41A to FIG. 41C , a dielectric filling material such as silicon oxide may be deposited in the line trenches 179 to form dielectric trench filling structures 76. The dielectric trench filling structures 76 may be staggered with the vertical stacking of the repeating units RU along the second horizontal direction hd2.

[0175] Fig.42 is a circuit diagram of a second exemplary structure of the second embodiment, and Fig.43 is a schematic perspective view of a second exemplary structure of the second embodiment.

[0176] like Fig.42 and Fig.43 As shown, the selected memory cell 200S includes two selected source / drain pillar structures 61 (a portion of one source / drain pillar structure is used as a source 68S, and a portion of the other source / drain pillar structure is used as a drain 68D), a semiconductor channel 160, a second memory film 50B, and a second (e.g., selected) word line 46B. In addition to the selected memory cell 200S, the repeating unit RU also includes an unselected source / drain pillar structure 61, a first memory film 50A, and a first (e.g., unselected) word line 46A. Therefore, the repeating unit RU also includes an unselected memory cell 200U located below the selected memory cell 200S and sharing the semiconductor channel 160 with the selected memory cell 200S. The bottom surface of the shared horizontal semiconductor channel 160 contacts the first memory film 50A of the memory cell 200U, and the top surface of the shared horizontal semiconductor channel 160 contacts the second memory film 50B of the memory cell 200S.

[0177] In one embodiment, the selected memory cell 200S can be programmed and erased by Fowler-Nordheim tunneling. In this embodiment, to program the selected memory cell 200S, a high programming voltage (e.g., 15V to 25V (such as 20V)) is applied to the selected word line 46B, zero volts are applied to the selected source / drain pillar structure 61, and the unselected word line 46A and the unselected source / drain pillar structure 61 are allowed to float. To erase, a high erase voltage (e.g., 15V to 25V (such as 20V)) is applied to the selected source / drain pillar structure 61, zero volts are applied to the selected word line 46B, and the unselected word line 46A and the unselected source / drain pillar structure 61 are allowed to float. For reading, a low read voltage (e.g., approximately 2V to 7V (such as 5V)) lower than the programming voltage is applied to the selected word line 46B, an extremely low voltage (e.g., less than 1V (such as 0.5V to 0.8V)) lower than the read voltage is applied to the selected drain (e.g., the selected left or right source / drain pillar structure 61), zero volts is applied to the selected source (e.g., the other of the selected left or right source / drain pillar structures 61), and the unselected word line 46A and the unselected source / drain pillar structures 61 are allowed to float.

[0178] In another embodiment, the selected memory cell 200S may be programmed by channel hot electron (CHE) injection and erased by hot hole tunneling and injection into the charge storage layer 54 of the second memory film 50B. In this embodiment, in order to program the drain side of the selected memory cell (e.g., the selected transistor) 200S, a positive gate programming bias voltage (e.g., 7V to 15V (such as 9V)) is applied to the selected word line 46B, zero volts are applied to the selected source 68S (e.g., the selected left source / drain pillar structure 61) located on the first side (e.g., the left side) of the semiconductor channel 160 of the selected field effect transistor 200S, and a positive drain side programming bias voltage (e.g., 3V to 6V (such as 5V)) lower than the gate programming bias voltage is applied to the selected drain 68D (e.g., the selected right source / drain pillar structure 61) located on the second side (e.g., the right side) of the semiconductor channel 160 of the selected field effect transistor 200S. The unselected word line 46A and the unselected source / drain pillar structure (i.e., the unselected source / drain region) 61 are allowed to float. This causes charges (eg, electrons) to be stored in the right portion of the second memory film 50B near the drain 68D (eg, at Fig.432 shown in FIG. 1 ). Therefore, the selected field effect transistor 200S includes a first charge storage material portion (e.g., the right side of the memory film 50B) positioned adjacent to a first side (e.g., the right side) of the semiconductor channel 160 and a second charge storage material portion (e.g., the left side of the memory film 50B) positioned adjacent to a second side (e.g., the left side) of the semiconductor channel 160. During programming of the selected first field effect transistor 200S, the second charge storage material portion corresponding to the second data bit (i.e., bit 2) is programmed by channel hot electron injection, while the first charge storage material portion corresponding to the first data bit (e.g., bit 1) is not programmed.

[0179] To program the source side of the selected memory cell 200S, a positive gate programming bias voltage (e.g., 7V to 15V (such as 9V)) is applied to the selected word line 46B, zero volts is applied to the selected drain 68D (e.g., the selected right source / drain pillar structure 61 located on the second side of the semiconductor channel 160 of the selected field effect transistor 200S), a positive drain side programming bias voltage (e.g., 3V to 6V (such as 5V)) lower than the programming voltage is applied to the selected source 68S (e.g., the selected left source / drain pillar structure 61) located on the first side of the semiconductor channel 160 of the selected field effect transistor 200S, and the unselected word line 46A and the unselected source / drain pillar structure 61 are allowed to float. This causes charge (e.g., electrons) to be stored in the left portion of the second memory film 50B near the source 68S (e.g., at Fig.43 shown in position 1).

[0180] Therefore, in this embodiment, two bits can be stored per memory cell 200S. The two bits are physically separated laterally in the memory film 50B of the memory cell 200S. In addition, four bits can be stored in two vertically adjacent memory cells 200S and 200U that share the same semiconductor channel 160 of the repeating unit RU, because two bits can also be stored in the memory cell 200U.

[0181] For erasing, a negative erase bias voltage (e.g., 4V to 8V (such as 6V)) lower than the programming voltage is applied to the selected word line 46B, a positive erase bias voltage (e.g., 3V to 6V (such as 5V)) lower than the programming voltage is applied to the selected drain 68D, while allowing the selected source 68S, the unselected word line 46A, and the unselected source / drain pillar structure 61 to float. This erases bit 2 in the right portion of the second memory film 50B near the drain 68D. Alternatively, a negative erase bias voltage (e.g., 4V to 8V (such as 6V)) lower than the programming voltage is applied to the selected word line 46B, a positive erase bias voltage (e.g., 3V to 6V (such as 5V)) lower than the programming voltage is applied to the selected source 68S, while allowing the selected drain 68D, the unselected word line 46A, and the unselected source / drain pillar structure 61 to float. This erases bit 1 in the left side of the second memory film 50B near the source 68S.

[0182] To read bit 2 near drain 68D, a low positive gate read bias voltage (e.g., 2V to 5V) below the erase voltage is applied to the selected word line 46B, zero volts is applied to the selected drain 68D, a very low positive bit line read voltage (e.g., 1V to 3V) is applied to the selected source 68S, and the unselected word lines 46A and the unselected source / drain pillar structures 61 are allowed to float. To read bit 1 near source 68S, a low positive gate read bias voltage (e.g., 2V to 5V) below the erase voltage is applied to the selected word line 46B, zero volts is applied to the selected source 68S, a very low positive bit line read voltage (e.g., 1V to 3V) is applied to the selected drain, and the unselected word lines 46A and the unselected source / drain pillar structures 61 are allowed to float.

[0183] Common Reference FIG. 31A to FIG. 43 , the semiconductor structure includes a vertical stack of repeating units RU. Each instance of the repeating unit extends along a first horizontal direction hd1 and includes a first conductive strip 46A, a first memory film 50A located above the first conductive strip, a discrete semiconductor channel 160 that is laterally spaced apart from each other along the first horizontal direction hd1 and located above the first memory film, a second memory film 50B located above the discrete semiconductor channel, a second conductive strip 46B located above the second memory film, and an insulating strip 32 located above the first conductive strip. The source / drain openings 29 are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels 160, and extend vertically through the vertical stack of the repeating units RU, and the source / drain pillar structures 61 are located in the corresponding source / drain openings 29 and extend vertically through the vertical stack of the repeating units RU.

[0184] In one embodiment, the semiconductor structure further includes a pair of dielectric trench filling structures 76 extending along the first horizontal direction hd1. Each of the pair of dielectric trench filling structures 76 contacts a corresponding longitudinal sidewall of the vertical stack of the repeating unit RU, and the pair of dielectric trench filling structures are laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0185] In one embodiment, each source / drain pillar structure 61 includes a group of lateral protrusions 61P located at the vertical level of the discrete semiconductor channels 160 in each repeating unit in the repeating unit RU; and each lateral protrusion 61 within the group of lateral protrusions contacts a corresponding one of the discrete semiconductor channels 160.

[0186] In one embodiment, each of the lateral protrusions 61P contacts each of the pair of dielectric trench-fill structures 76; and each of the lateral protrusions within the set of lateral protrusions has the same vertical thickness as a corresponding one of the discrete semiconductor channels 160. In one embodiment, each of the lateral protrusions 61P within the set of lateral protrusions contacts a corresponding additional one of the discrete semiconductor channels 160.

[0187] In one embodiment, each of the lateral protrusions 61P includes a corresponding horizontal bottom surface that contacts a horizontal top surface segment of a corresponding one of the first memory films 50A and a corresponding horizontal top surface that contacts a horizontal bottom surface segment of a corresponding one of the second memory films 50B. The source / drain openings 29 have corresponding circular horizontal cross-sectional shapes; and the sidewalls of the lateral protrusions 61P that contact the corresponding discrete semiconductor channels 160P have convex vertical surfaces.

[0188] In one embodiment, each of the source / drain pillar structures 61 laterally surrounds a cylindrical dielectric core 66 that extends vertically through the vertical stack of repeating units RU. Each of the source / drain pillar structures 61 vertically extends from the bottommost layer within the vertical stack of repeating units to the topmost layer within the vertical stack of repeating units RU.

[0189] In one embodiment, the first conductive strip 46A includes a first selection gate electrode; the second conductive strip 46B includes a second selection gate electrode; and each instance of the first memory film 50A and the second memory film 50B includes a corresponding layer stack, which includes, from one side to the other, a tunneling dielectric layer 56, a charge storage layer 54, and a blocking dielectric layer 52.

[0190] In one embodiment, silicon oxide liner 57 is located between source / drain pillar structure 61 and first and second conductive strips ( 46A, 46B), and source / drain pillar structure 61 includes a doped silicon material.

[0191] In one embodiment, a semiconductor structure includes a three-dimensional NOR memory device. In one embodiment, a method of operating a three-dimensional NOR memory device includes: programming the three-dimensional NOR memory device using Fowler-Nordheim tunneling; and erasing the three-dimensional NOR memory device using Fowler-Nordheim tunneling. In another embodiment, a method of operating a three-dimensional NOR memory device includes: programming the three-dimensional NOR memory device using channel hot electron injection to store two bits in a second memory film of a selected memory cell; and

[0192] The three-dimensional NOR memory device is erased using hot hole tunneling and injection into the charge storage layer of the second memory film of the selected memory cell.

[0193] Various semiconductor devices of embodiments of the present disclosure include a three-dimensional NOR memory array that can be fabricated with high device density and potentially multiple bits of storage capability per cell.

[0194] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments employing specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure, comprising: a vertical stack of repeating units, wherein each instance of the repeating unit extends along a first horizontal direction and includes a first conductive strip, a first memory film over the first conductive strip, discrete semiconductor channels laterally spaced apart from one another along the first horizontal direction and over the first memory film, a second memory film over the discrete semiconductor channels, a second conductive strip over the second memory film, and an insulating strip over the first conductive strip; source / drain openings arranged along the first horizontal direction, interleaved with the discrete semiconductor channels, and extending vertically through the vertical stack of repeating units; and A source / drain pillar structure is located in a corresponding source / drain opening and extends vertically through the vertical stack of repeating units.

2. The semiconductor structure of claim 1 , further comprising a pair of dielectric trench filling structures extending along the first horizontal direction, wherein each of the pair of dielectric trench filling structures contacts a corresponding longitudinal sidewall of the vertical stack of repeating units, and the pair of dielectric trench filling structures are laterally spaced apart along a second horizontal direction perpendicular to the first horizontal direction.

3. The semiconductor structure according to claim 2, wherein: Each of the source / drain pillar structures comprises a set of lateral protrusions located at the vertical level of the discrete semiconductor channels in each of the repeating units; and Each lateral protrusion within the set of lateral protrusions contacts a respective one of the discrete semiconductor channels.

4. The semiconductor structure of claim 3, wherein: Each of the lateral protrusions contacts each of the pair of dielectric trench-fill structures; and Each lateral protrusion within the set of lateral protrusions has a same vertical thickness as the corresponding one of the discrete semiconductor channels.

5. The semiconductor structure of claim 3, wherein each lateral protrusion within the set of lateral protrusions contacts a respective additional one of the discrete semiconductor channels.

6. The semiconductor structure of claim 3 , wherein each of the lateral protrusions comprises a corresponding horizontal bottom surface that contacts a horizontal top surface segment of a corresponding one of the first memory films and a corresponding horizontal top surface that contacts a horizontal bottom surface segment of a corresponding one of the second memory films.

7. The semiconductor structure of claim 6, wherein: The source / drain openings have corresponding circular horizontal cross-sectional shapes; and The sidewalls of the lateral protrusions contacting the respective discrete semiconductor channels have convex vertical surfaces.

8. The semiconductor structure of claim 1, wherein each of the source / drain pillar structures laterally surrounds a cylindrical dielectric core that extends vertically through the vertical stack of the repeating units.

9. The semiconductor structure of claim 1, wherein each of the source / drain pillar structures extends vertically from a bottommost layer within the vertical stack of repeating units to a topmost layer within the vertical stack of repeating units.

10. The semiconductor structure of claim 1, wherein: The first conductive strip includes a first select gate electrode; The second conductive strip includes a second select gate electrode; and Each instance of the first memory film and the second memory film includes a respective layer stack including, from one side to the other side, a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer. 11 . The semiconductor structure of claim 1 , further comprising a silicon oxide liner between the source / drain pillar structure and the first and second conductive strips, wherein the source / drain pillar structure comprises a doped silicon material.

12. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a three-dimensional NOR memory device.

13. A method of operating the three-dimensional NOR memory device according to claim 12, the method comprising: programming the three-dimensional NOR memory device using Fowler-Nordheim tunneling; as well as The three-dimensional NOR memory device is erased using the Fowler-Nordheim tunneling.

14. A method of operating the three-dimensional NOR memory device according to claim 12, the method comprising: programming the three-dimensional NOR memory device using channel hot electron injection to store two bits in the second memory film of the selected memory cell; as well as The three-dimensional NOR memory device is erased using hot hole tunneling and injection into the charge storage layer of the second memory film of the selected memory cell.

15. A method of forming a semiconductor structure, the method comprising: forming a vertical stack of multiple instances of a cell layer stack above a substrate, wherein the cell layer stack includes a first sacrificial material layer, a first memory film, a semiconductor material layer, a second memory film, a second sacrificial material layer, and an insulating layer; forming source / drain openings through the vertical stack; forming a source / drain pillar structure in the source / drain opening; forming line trenches extending laterally through the vertical stack along a first horizontal direction, wherein the vertical stack is divided into a vertical stack of repeating units, wherein the vertical stack of repeating units are staggered with the line trenches along a second horizontal direction perpendicular to the first horizontal direction, and wherein each instance of the repeating unit includes a first strip of sacrificial material, a first memory film, a row of discrete semiconductor channels laterally spaced apart from one another along the first horizontal direction, a second memory film, a second strip of sacrificial material, and an insulating strip; as well as The first and second strips of sacrificial material are replaced with the first and second strips of conductive material through the line trenches.

16. The method according to claim 15, further comprising laterally extending a portion of the source / drain opening at the level of the semiconductor material layer, wherein the laterally extended portion of the source / drain opening is filled with a lateral protruding portion of the source / drain pillar structure.

17. The method of claim 16, further comprising forming a dielectric trench filling structure in the line trench, wherein: each of the dielectric trench-fill structures contacts a longitudinal sidewall of a corresponding vertical repeat of the plurality of vertical repeats; and Each lateral extension of the source / drain pillar structure contacts a corresponding pair of the dielectric trench-fill structures.

18. The method of claim 15, wherein: The substrate semiconductor material layer has a doping of a first conductivity type; and The source / drain pillar structure has a doping of a second conductivity type opposite to the first conductivity type.

19. The method of claim 15, wherein: the source / drain openings comprising a row of source / drain openings arranged along the first horizontal direction; said rows of source / drain openings being laterally spaced apart from one another along said second horizontal direction; and The line trenches are formed between respective adjacent pairs of rows of source / drain openings.

20. The method of claim 15, wherein each instance of the first memory film and the second memory film comprises a respective layer stack including, from one side to the other side, a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer.

21. A semiconductor structure, comprising: vertical alternating stacks of insulating and conductive strips laterally spaced from one another by line trenches; a laterally alternating sequence of semiconductor channels and source / drain pillar structures within a corresponding one of the line-trench lines; and a memory film located between each adjacent pair of the vertical alternating stacks and the lateral alternating sequences, Each of the plurality of source / drain column structures is in direct contact with a corresponding pair of vertical semiconductor channels.

22. The semiconductor structure of claim 21, wherein each of the semiconductor channels extends vertically from a first horizontal plane including a bottommost surface of the vertical alternating stack to a second horizontal plane including a topmost surface of the vertical alternating stack.

23. The semiconductor structure of claim 22, wherein the source / drain pillar structure extends vertically from the first horizontal plane to the second horizontal plane.

24. The semiconductor structure of claim 23, wherein interfaces between the semiconductor channel and the source / drain pillar structures are located in respective flat vertical planes perpendicular to the first horizontal plane.

25. The semiconductor structure of claim 21, wherein the linear trenches extend laterally along a second horizontal direction and have respective uniform widths along a first horizontal direction perpendicular to the second horizontal direction.

26. The semiconductor structure of claim 25, wherein each of the semiconductor channels comprises: a corresponding pair of first outer side walls, wherein the corresponding pair of first outer side walls are parallel to the first horizontal direction; and A corresponding pair of second outer side walls is parallel to the second horizontal direction.

27. The semiconductor structure of claim 26, wherein: Each of the first outer sidewalls contacts a corresponding one of the source / drain column structures; and Each of the second outer sidewalls contacts a corresponding one of the memory films.

28. The semiconductor structure of Claim 21, wherein each of the semiconductor channels laterally surrounds a respective dielectric core, a top surface of the respective dielectric core being located within a horizontal plane that includes a topmost surface of the semiconductor channel.

29. The semiconductor structure of claim 21, further comprising: first source / drain connection via structures, the first source / drain connection via structures being located below a first subset of the source / drain pillar structures, wherein each of the first source / drain connection via structures is in contact with a bottom horizontal surface of a corresponding one of the first subset of the source / drain pillar structures; and A second source / drain connection via structure, wherein the second source / drain connection via structure is located above a second subset of the source / drain column structures, wherein each of the second source / drain connection via structures contacts a top horizontal surface of a corresponding one of the source / drain column structures in the second subset of the source / drain column structures.

30. The semiconductor structure of claim 29, further comprising an array of semiconductor channel contact via structures, wherein each of the semiconductor channel contact via structures contacts a corresponding one of the semiconductor channels.

31. The semiconductor structure of claim 29, further comprising: a first bit line, the first bit line contacts a bottom surface of the first source / drain connection via structure and extends laterally in a first horizontal direction perpendicular to a second longitudinal direction of the line trench; and A second bit line contacts a top surface of the second source / drain connection via structure and extends laterally along the first horizontal direction perpendicular to the longitudinal second direction of the line trench.

32. The semiconductor structure of claim 21, wherein: The semiconductor structure includes a NOR memory device; and Each of the memory films includes a layer stack including, from one side to the other side, a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer.

33. A semiconductor structure according to claim 32, wherein each of the conductive strips is laterally separated from the corresponding nearest one of the memory films by a corresponding backside blocking dielectric layer, and is laterally separated from the corresponding upper insulating strip and the corresponding lower insulating strip by the corresponding backside blocking dielectric layer.

34. A method of forming a semiconductor structure, the method comprising: forming a vertically alternating sequence of insulating layers and sacrificial material layers; forming line trenches through the vertical alternating sequence, wherein the vertical alternating sequence is divided into vertical alternating stacks of insulating strips and sacrificial material strips, and the vertical alternating stacks are laterally spaced apart from each other by the line trenches; forming a memory film in each of the line trenches; forming a laterally alternating sequence of semiconductor channels and source / drain pillar structures in each of the line-trench on a corresponding one of the memory films, wherein each of a plurality of the source / drain pillar structures is in direct contact with a corresponding pair of vertical semiconductor channels; as well as The sacrificial material layer is replaced with a conductive strip.

35. The method of claim 34, further comprising: forming a sacrificial line trench filling structure in each of the line trenches; as well as A first array of pillar cavities is formed by removing first material portions of the sacrificial line trench-fill structures, wherein remaining second material portions of the sacrificial line trench-fill structures constitute an array of sacrificial material pillars.

36. The method of claim 35, further comprising: forming the source / drain column structure in the first column cavity array; as well as A second array of pillar cavities is formed by removing the second material portions of the sacrificial line trench-fill structures between adjacent pairs of source / drain pillar structures.

37. The method of claim 36, wherein the semiconductor channel is formed in the second pillar cavity array.

38. The method of claim 34, further comprising forming a two-dimensional array of dielectric cores, wherein each of the dielectric cores is formed within a corresponding one of the semiconductor channels.

39. The method according to claim 34 further includes forming an array of source / drain connection through-hole structures, wherein each of the source / drain connection through-hole structures contacts a horizontal surface of a corresponding one of the source / drain column structures.

40. The method of claim 39, further comprising forming bit lines, wherein each of the bit lines contacts a respective subset of the source / drain connection via structures and extends laterally in a horizontal direction perpendicular to a longitudinal direction of the line trenches.

41. A three-dimensional memory device, the three-dimensional memory device comprising: a first vertical stack of a first string of field effect transistors; and a second vertical stack of a second string of field effect transistors, in: The first vertical stacks alternate with the second vertical stacks along a first horizontal direction; Each of the first strings of field effect transistors comprises a series connection of a respective set of first field effect transistors, the respective set of first field effect transistors being electrically connected to each other such that each adjacent pair of first field effect transistors shares a respective one of a plurality of first source / drain regions; Each of the second strings of field effect transistors comprises a series connection of a respective set of second field effect transistors, the respective set of second field effect transistors being electrically connected to one another such that each adjacent pair of second field effect transistors shares a respective one of the second source / drain regions; The series connection of the respective set of first field effect transistors shares a respective one of a plurality of word lines; The first source / drain regions are located in different vertical levels in the corresponding first source / drain pillar structures; and The second source / drain regions are located in different vertical levels in the corresponding second source / drain pillar structures.

42. The three-dimensional memory device according to claim 41, further comprising: a first bit line electrically connected to a corresponding subset of the first source / drain pillar structures; and A second bit line is electrically connected to a corresponding subset of the second source / drain pillar structures.

43. The three-dimensional memory device of claim 42, wherein: Each adjacent pair of a first one of the first field effect transistor strings and a second one of the second field effect transistor strings shares the corresponding one of the plurality of word lines; the plurality of word lines being laterally spaced apart along the first horizontal direction; The first bit line is located below the first source / drain pillar structure; and The second bit line is located above the second source / drain pillar structure.

44. The three-dimensional memory device of claim 41, wherein: Each of the first strings of field effect transistors comprises a respective first memory film extending continuously across and shared by the respective series connection of first field effect transistors; and Each of the second field effect transistor strings includes a respective second memory film that continuously extends across and is shared by the respective series connection of second field effect transistors.

45. The three-dimensional memory device of claim 41, wherein each of the first field effect transistors comprises a respective pair of charge storage material portions.

46. ​​A method of operating the three-dimensional memory device according to claim 41, the method comprising: applying 0V to a first source / drain region located on a first side of a semiconductor channel of a selected first field effect transistor; applying a drain-side programming bias voltage to another first source / drain region located on a second side of the semiconductor channel of the selected first field effect transistor; as well as A gate programming bias voltage is applied to a first word line of the selected first field effect transistor to program the selected first field effect transistor.

47. The method of claim 46, further comprising: allowing the first source / drain region and the second source / drain region of corresponding unselected ones of the first field effect transistor and the second field effect transistor to float during the programming of the selected first field effect transistor; as well as All word lines of the plurality of word lines except the first word line are allowed to float during the programming of the selected first field effect transistor.

48. The method of claim 47, wherein: the selected first field effect transistor includes a first charge storage material portion positioned adjacent the first side of the semiconductor channel and a second charge storage material portion positioned adjacent the second side of the semiconductor channel; and During the programming of the selected first field effect transistor, the second charge storage material portion corresponding to the second data bit is programmed by channel hot electron injection, while the first charge storage material portion corresponding to the first data bit is not programmed.

49. The method of claim 48, further comprising: applying 0V to the first source / drain region located on the second side of the semiconductor channel of the selected first field effect transistor; applying the drain-side programming bias voltage to the first source / drain region located on the first side of the semiconductor channel of the selected first field effect transistor; as well as The gate programming bias voltage is applied to the first word line of the selected first field effect transistor to program the first charge storage material portion corresponding to the first data bit by channel hot electron injection without programming the second charge storage material portion corresponding to the second data bit.

50. The method of claim 49, further comprising: allowing the first source / drain region and the second source / drain region of corresponding unselected ones of the first field effect transistor and the second field effect transistor to float during the programming of the first data bit of the selected first field effect transistor; as well as All word lines of the plurality of word lines except the first word line are allowed to float during the programming of the first data bit of the selected first field effect transistor.

51. The method of claim 48, further comprising: applying a positive erase bias voltage to the first source / drain region located on the first side of the semiconductor channel of the selected first field effect transistor; allowing the first source / drain region located on the second side of the semiconductor channel of the selected first field effect transistor to float; as well as A negative erase bias voltage is applied to the first word line of the selected first field effect transistor to erase the second data bit by hot hole injection without erasing the second data bit of the selected first field effect transistor.

52. The method of claim 51, further comprising: allowing the first source / drain region and the second source / drain region of corresponding unselected ones of the first field effect transistor and the second field effect transistor to float during the erasing of the second data bit of the selected first field effect transistor; as well as All word lines except the first word line among the plurality of word lines are allowed to float during the erasing of the second data bit of the selected first field effect transistor.

53. The method of claim 48, further comprising: applying 0 V to the first source / drain region located on the first side of the semiconductor channel of the selected first field effect transistor; applying a bit line read bias voltage to the first source / drain region located on the second side of the semiconductor channel of the selected first field effect transistor; as well as A gate read bias voltage is applied to the first word line of the selected first field effect transistor to read the second data bit of the selected first field effect transistor.

54. The method of claim 53, further comprising: allowing the first source / drain region and the second source / drain region of corresponding unselected ones of the first field effect transistor and the second field effect transistor to float during the reading of the second data bit of the selected first field effect transistor; as well as All word lines except the first word line among the plurality of word lines are allowed to float during the reading of the second data bit of the selected first field effect transistor.

55. The method of claim 46, further comprising: applying 0V to each first source / drain region within the first field effect transistor string located on the first side of the semiconductor channel of the selected first field effect transistor; as well as A drain-side programming bias voltage is applied to each first source / drain region within the first field effect transistor string located on the second side of the semiconductor channel of the selected first field effect transistor.

56. The method of claim 55, further comprising: applying the drain-side programming bias voltage to each of the second source / drain regions during the programming of the selected first field effect transistor; as well as 0 V is applied to all word lines of the plurality of word lines except the first word line during the programming of the selected first field effect transistor.

57. The method of claim 56, wherein: the selected first field effect transistor includes a first charge storage material portion positioned adjacent the first side of the semiconductor channel and a second charge storage material portion positioned adjacent the second side of the semiconductor channel; and During the programming of the selected first field effect transistor, the second charge storage material portion corresponding to the second data bit is programmed, while the first charge storage material portion corresponding to the first data bit is not programmed.

58. The method of claim 57, further comprising: applying 0V to each first source / drain region within the first field effect transistor string located on the first side of the semiconductor channel of the selected first field effect transistor; applying a bit line read bias voltage to each first source / drain region within the first field effect transistor string located on the second side of the semiconductor channel of the selected first field effect transistor; as well as A gate read bias voltage is applied to the first word line of the selected first field effect transistor to read the second data bit of the selected first field effect transistor.

59. The method of claim 56, wherein the second data bit of the selected first field effect transistor is read without reading the first data bit of the selected first field effect transistor.

60. The method according to claim 55, further comprising erasing the three-dimensional memory device by: applying an erase bias voltage to the first source / drain region and the second source / drain region; and 0 V is applied to each of the plurality of word lines.

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