Multi-level power conversion system and control device for multi-level power conversion system

Abstract

In a multi-level power conversion system, a scheme is provided for suppressing a semiconductor element of a power converter from being damaged by an overvoltage due to a thunder surge. A multi-level power conversion system is provided with: a multi-level power converter (30); and a control device (40) having: an operation control unit (51) that, on the basis of a predetermined condition, shifts the operation mode of the multilevel power converter (30) to a standby mode in which power conversion is not performed between the DC input / output unit (31) and the AC input / output unit (32); and a gate signal generation unit (53) that, in the standby mode, generates and outputs a gate signal that causes at least one of the third semiconductor switching element (3) and the second semiconductor switching element (2) to be in an on-state or an on-state.

Description

Technical Field

[0001] The present invention relates to a multi-level power conversion system and a control device of the multi-level power conversion system. Background Art

[0002] Conventionally, for example, there is known a multilevel power converter including a plurality of DC capacitors connected in series with two or more of them on the DC side, and two semiconductor switching elements connected in reverse series with the series connection point of the plurality of DC capacitors (for example, refer to Patent Documents 1 and 2). In addition, hereinafter, in this specification, the DC connection point of the plurality of DC capacitors is also referred to as a "DC neutral point", and the two semiconductor switching elements connected in reverse series with the DC connection point (DC neutral point) of the plurality of DC capacitors are also referred to as "neutral point elements".

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-116020

[0006] Patent Document 2: Japanese Patent Application Publication No. 2019-024290 Summary of the invention

[0007] Problems to be solved by the invention

[0008] Fig. 22 FIG. 1 is a diagram showing an example of a configuration of a multilevel power converter 130 according to one embodiment. Fig. 22 In the figure, as a configuration example 1 of a multilevel power converter, a configuration of a three-phase three-level NPP (Neutral Point Potential) multilevel power converter 130 is shown. Fig. 22 As shown, in the multi-level power converter 130, two DC capacitors C P , C N The three phases are connected in series via a DC neutral point C. At the DC neutral point C, two semiconductor switching elements (neutral point elements) 102 and 103 are connected in series in reverse order to each other. Fig. 22 In the example shown, semiconductor switching elements (neutral point elements) 102 and 103 share the collector side of IGBT (Insulated Gate Bipolar Transistor) and are connected in anti-series.

[0009] Fig.23 FIG. 2 is a diagram showing an example of a configuration of a multilevel power converter 230 of another embodiment. Fig.23In the figure, as a second configuration example of a multilevel power converter, a configuration of a three-phase three-level NPP multilevel power converter 230 is shown. Fig.23 As shown, in the multi-level power converter 230, two DC capacitors C P , C N The three phases are connected in series via a DC neutral point C. At the DC neutral point C, two semiconductor switching elements (neutral point elements) 202 and 203 are connected in series in reverse order to each other. Fig.23 In the example shown, the semiconductor switching elements (neutral point elements) 202 and 203 share the emitter side of the IGBT and are connected in reverse series. Fig. 22 The multi-level power converter 130 and Fig.23 In the multilevel power converter 230 shown, the semiconductor switch elements 102 and 103 and the semiconductor switch elements 202 and 203 have the same configuration except that they are connected in reverse series in opposite directions.

[0010] Fig.24 FIG. 1 is a diagram showing an example of a configuration of a multilevel power converter 330 of another embodiment. Fig.24 In the embodiment of the present invention, as a configuration example 3 of the multilevel power converter, a configuration of a 5-level NPP multilevel power converter 330 for one phase is shown. Fig.24 As shown, in the multi-level power converter 330, four DC capacitors C P , C N The three DC neutral points C are connected in series, and two semiconductor switching elements (neutral point elements) 302 and 303 are connected in anti-series at each DC neutral point C. Fig.24 In the example shown, the semiconductor switching elements (neutral point elements) 302 and 303 are connected in anti-series with the collector side of the IGBT being shared. However, although not shown in the figure, the semiconductor switching elements (neutral point elements) may be connected in anti-series with the emitter side being shared.

[0011] Here, for example, in the case of Figure 22 to Figure 24 In the multilevel power conversion systems such as the multilevel power converters 130, 230, and 330 shown, a surge voltage (lightning surge) caused by lightning may cause the semiconductor element to be damaged by overvoltage. That is, in the multilevel power conversion system, the potential of the positive and negative electrodes (P and N poles) on the DC side of the power converter varies greatly due to the surge voltage caused by lightning, and a part of the surge voltage is charged to the parasitic capacitance of the semiconductor element, and the semiconductor element may be damaged by overvoltage.

[0012] Therefore, an object of the present application is to provide a method for suppressing semiconductor elements of a power converter from being destroyed by overvoltage due to a lightning surge in a multi-level power conversion system.

[0013] Means for solving problems

[0014] A multilevel power conversion system of one embodiment is characterized in that it comprises a multilevel power converter and a control device, wherein the multilevel power converter comprises: a DC input / output section having a positive terminal and a negative terminal connected to a DC power source or a DC load; a plurality of DC capacitors connected in series between the positive terminal and the negative terminal via a DC neutral point; an AC input / output section having an AC terminal connected to an AC power source or an AC load; a first semiconductor switch element and a fourth semiconductor switch element connected in series with the same polarity between the positive terminal and the negative terminal via the AC terminal; a first return diode and a fourth return diode connected in reverse to the first semiconductor switch element and the fourth semiconductor switch element, respectively; The control device is characterized in that the first semiconductor switching element and the second semiconductor switching element are connected in parallel with each other with opposite polarities in series between the DC neutral point and the AC terminal; the third semiconductor switching element and the second semiconductor switching element are connected in reverse parallel with the third semiconductor switching element and the second semiconductor switching element, respectively. The control device comprises: an action control unit, which, based on prescribed conditions, causes the operation mode of the multi-level power converter to be transferred to a standby mode in which no power conversion is performed between the DC input and output unit and the AC input and output unit; and a gate signal generating unit, which, in the standby mode, generates and outputs a gate signal that causes at least one of the third semiconductor switching element and the second semiconductor switching element to be in a conducting state or a switching state.

[0015] A control device for a multilevel power conversion system in one embodiment, characterized in that the multilevel power conversion system includes a multilevel power converter, the multilevel power converter including: a DC input / output unit having a positive terminal and a negative terminal connected to a DC power source or a DC load; a plurality of DC capacitors connected in series between the positive terminal and the negative terminal via a DC neutral point; an AC input / output unit having an AC terminal connected to an AC power source or an AC load; a first semiconductor switch element and a fourth semiconductor switch element connected in series between the positive terminal and the negative terminal with the same polarity via the AC terminal; a first return diode and a fourth return diode connected in series with the first semiconductor switch element and the fourth semiconductor switch element; The components are connected in reverse parallel respectively; the third semiconductor switch element and the second semiconductor switch element are connected in series with opposite polarities between the DC neutral point and the AC terminal; and the third return diode and the second return diode are connected in reverse parallel with the third semiconductor switch element and the second semiconductor switch element respectively, and the control device comprises: an action control unit, based on a prescribed condition, causing the operation mode of the multi-level power converter to be transferred to a standby mode in which no power conversion is performed between the DC input and output unit and the AC input and output unit; and a gate signal generating unit, in the standby mode, generating and outputting a gate signal that causes at least either the third semiconductor switch element or the second semiconductor switch element to be in a conducting state or a switching state.

[0016] Effects of the Invention

[0017] According to the present disclosure, in a multi-level power conversion system, it is possible to suppress semiconductor elements of a power converter from being destroyed by overvoltage due to a lightning surge. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a diagram showing an example of the configuration of a multilevel power conversion system according to the first embodiment.

[0019] Figure 2 Yes means Figure 1 FIG. 1 is a diagram showing an example of a configuration of a control device in a multi-level power conversion system shown in FIG.

[0020] Figure 3 Yes means Figure 1 A circuit diagram showing an example of a circuit configuration of a multi-level power converter shown in FIG.

[0021] Figure 4 Yes means Figure 1 An actual state wiring diagram of an example of the circuit configuration of a multi-level power converter shown.

[0022] Figure 5 Yes means Figure 3 and Figure 4FIG. 1 is a diagram showing an example of charging paths of parasitic capacitances of various components due to lightning strike in a circuit configuration of a multilevel power converter shown in FIG.

[0023] Figure 6 Yes means Figure 5 The equivalent circuit diagram of the charging path is shown.

[0024] Figure 7 is Figure 3 and Figure 4 In the circuit configuration of the multilevel power converter shown, a diagram is organized to show whether or not a neutral point element is destroyed by an overvoltage due to a lightning surge, depending on the situation.

[0025] Figure 8 It means in Figure 3 and Figure 4 FIG. 1 is a diagram showing an example of charging paths of parasitic capacitances of various parts due to lightning strike when the semiconductor element 2 is turned on in the circuit configuration of the multi-level power converter shown.

[0026] Fig. 9 Yes means Figure 8 The equivalent circuit diagram of the charging path is shown.

[0027] Fig.10 It means in Figure 3 and Figure 4 FIG. 1 is a diagram showing an example of charging paths of parasitic capacitances of various parts due to lightning strike when the semiconductor element 3 is turned on in the circuit configuration of the multilevel power converter shown.

[0028] Fig.11 Yes means Fig.10 The equivalent circuit diagram of the charging path is shown.

[0029] Fig.12 Yes means Figure 1 Flowchart showing the procedure of state transition between the power generation mode and the standby mode of the multi-level power conversion system.

[0030] Fig.13 Yes means Figure 2 FIG. 2 is a diagram showing an example of a control configuration of a voltage command generating unit of a control unit shown in FIG.

[0031] Fig.14 Yes means Figure 2 A diagram showing an example of a control configuration of a gate signal generating unit of a control unit shown in FIG.

[0032] Fig.15 It is a diagram showing an example of a control configuration of a gate signal generating section of a control section according to a modification of the first embodiment.

[0033] Fig.16This is a diagram showing an example of a control configuration of a gate signal generating unit of a control unit according to the second embodiment.

[0034] Fig.17 It is a diagram showing an example of a control configuration of a voltage command generating unit of a control unit according to the third embodiment.

[0035] Fig.18 This is a diagram showing an example of a control configuration of a gate signal generating unit of a control unit according to the third embodiment.

[0036] Fig.19 This is a diagram showing an example of a control configuration of a voltage command generating unit of a control unit according to the fourth embodiment.

[0037] Fig. 20 This is a diagram showing an example of a control structure of a gate signal generating unit of a control unit according to the fourth embodiment.

[0038] Fig.21 Yes means Figures 1 to 20 A conceptual diagram of an example of a hardware configuration of a processing circuit included in a control device according to the illustrated embodiment.

[0039] Fig. 22 This is a diagram showing an example of the configuration of a multilevel power converter according to one embodiment.

[0040] Fig.23 FIG. 1 is a diagram showing an example of the configuration of a multilevel power converter of another embodiment.

[0041] Fig.24 FIG. 1 is a diagram showing an example of the configuration of a multilevel power converter of another embodiment. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of a multilevel power conversion system and a control device for the multilevel power conversion system disclosed in the present application will be described with reference to the drawings.

[0043] <Configuration Example of First Embodiment>

[0044] Figure 1 It is a diagram showing an example of the configuration of the multilevel power conversion system 20 according to the first embodiment.

[0045] like Figure 1 As shown, the multi-level power conversion system 20 is Figure 1 The DC side on the left side of the middle is connected to the solar cell 11 via a DC cable 12. In addition, the multi-level power conversion system 20 is Figure 1The AC side on the right side is connected to the AC power system 15 via the AC cable 13 and the transformer 14. The multilevel power conversion system 20 converts the DC power obtained from the solar cell 11 into AC power, and outputs the converted AC power to the AC power system 15 via the transformer 14. Hereinafter, in this specification, etc., the multilevel power conversion system 20 is also referred to as "power conversion system 20".

[0046] The solar cell (PV: Photovoltaics) 11 is also called a solar panel, and is connected to one end side of the power conversion system 20, that is, the input end (DC input / output unit 31 (see Figure 3 , 4 The solar cell 11 generates electricity using sunlight, and supplies the generated DC power to the power conversion system 20 via the DC cable 12. The solar cell 11 is an example of a "DC power source or a DC load", and the "DC power source or a DC load" may be a DC power source such as a "battery (ESS: Energy Storage System)" or other DC loads.

[0047] One end of the DC cable 12 is connected to the solar cell 11, and the other end is connected to a DC end (DC input / output unit 31 (see Figure 3 , 4 The DC cable 12 includes a positive-side cable and a negative-side cable, and supplies the DC power supplied from the solar cell 11 to a multilevel power converter 30 described later.

[0048] One end of the AC cable 13 is connected to an AC end (AC input / output unit 32 (see FIG. 1 ) of a multilevel power converter 30 described later in the power conversion system 20. Figure 3 , 4 )) is connected to the AC power system 15 via a transformer 14. The AC cable 13 is a three-phase three-wire type three-phase AC circuit that uses three wires, cables, and conductors, for example, to supply three-phase AC power composed of three systems of single-phase AC whose current or voltage phases are mutually offset. The AC cable 13 supplies the AC power converted by the multilevel power converter 30 described later to the AC power system 15 side.

[0049] One end of the transformer 14 is connected to the output side of the power conversion system 20 via the AC cable 13, and the other end is connected to the AC power system 15. The transformer 14 transforms the AC power output from the power conversion system 20 into a predetermined voltage and outputs it to the AC power system 15.

[0050] The AC power system (power system) 15 is connected to the transformer 14 and is a system that integrates power generation, power transformation, power transmission, and power distribution for supplying the AC power transformed by the transformer 14 to the power receiving equipment of the demand side. For example, an unspecified load is connected. Hereinafter, in this specification, the AC power system 15 is also referred to as "power system 15". In addition, the AC power system (power system) 15 is an example of "AC power source or AC load", and the "AC power source or AC load" can be a power system, for example, a motor, a generator, or other AC loads.

[0051] The multi-level power conversion system (power conversion system) 20 is, for example, a power conversion system (PV-PCS: Photovoltaics-Power Conditioning System) for solar power generation (solar cell). The power conversion system 20 converts the DC power supplied from the solar cell 11 into AC power, and outputs the converted AC power to the power system 15 side via the transformer 14. In addition, the power conversion system 20 is not limited to solar power generation, for example, it can also be a power conversion system for batteries (ESS-PCS: Energy Storage System-Power Conditioning System) and the like. That is, as long as it is a power conversion system in which the potential on the DC side changes due to lightning strikes during shutdown, the disclosure of this application can be applied.

[0052] The multilevel power conversion system (power conversion system) 20 includes a DC switch 21, an AC reactor 22, an AC capacitor 23, an AC switch 24, a DC voltage sensor 25, an AC current sensor 26, a multilevel power converter 30, and a control device 40. The DC switch 21 and the DC voltage sensor 25 are arranged between the solar cell 11 and the multilevel power converter 30 in the DC cable 12. In addition, the AC reactor 22, the AC capacitor 23, the AC switch 24, and the AC current sensor 26 are arranged between the multilevel power converter 30 and the transformer 14 in the AC cable 13. In addition, hereinafter, in this specification and the like, the multilevel power converter 30 is also referred to as "power converter 30".

[0053] The DC switch (DC breaker) 21 is provided in series between the solar cell 11 and the power converter 30 in the DC cable 12. The DC switch 21 connects (connects) or disconnects (cuts off) the DC cable 12 between the solar cell 11 and the power converter 30, for example, according to a connection instruction or disconnection instruction from the control device 40, a higher-level device (not shown), or an operator. The DC switch 21 is, for example, an electric contactor that can be opened and closed according to an instruction from the control device 40. In addition, the DC switch 21 may be, for example, a DC breaker (breaker) that is usually opened and closed manually and automatically cuts off the DC cable 12 when an overcurrent such as a short-circuit current is detected. When the DC switch 21 is disconnected, the flow of the DC power supplied from the solar cell 11 into the power converter 30 is cut off.

[0054] The AC reactor 22 and the output end of the power converter 30 (AC input and output unit 32 (refer to Figure 3 , 4 )) are connected in series with the AC cables 13 of each phase. The AC reactor 22 is, for example, a smoothing element that has the effect of reducing noise and suppressing surge voltage. The AC reactor 22, for example, together with the AC capacitor 23 connected in an L shape, constitutes an LC filter circuit (filter circuit) that reduces pulsation (vibration) generated when a switching element described later of the power converter 30 is switched.

[0055] The AC capacitor 23 is connected to the AC cable 13 of each phase of the output end of the power converter 30 via a branch point in an L shape. The AC capacitor 23 is an electronic component that stores or releases electricity (charge). The AC capacitor 23, for example, together with the AC reactor 22 connected in an L shape, constitutes an LC filter circuit (filter circuit) that reduces the pulsation (vibration) generated when the switching element described later of the power converter 30 is switched. The AC capacitor 23 suppresses the outflow of higher harmonics (higher harmonic current) to the power system 15 side by constituting a filter circuit together with the AC reactor 22.

[0056] The AC switch (AC circuit breaker) 24 is provided in series between the AC reactor 22 (filter circuit) and the transformer 14 in each phase of the AC cable 13. The AC switch 24 connects (connects) or disconnects (disconnects) the AC cable 13 between the power converter 30 and the power system 15, for example, based on an AC switch operation signal from the control device 40, a connection instruction or a disconnection instruction from a higher-level device (not shown) or an operator. When the AC switch 24 is disconnected, the AC power supplied from the power converter 30 is cut off from flowing to the power system 15 side.

[0057] The DC voltage sensor 25 is, for example, a known DC voltmeter or DC voltage sensor, and is disposed between the solar cell 11 and the power converter 30 to detect a DC voltage value V dc In addition, the position of the DC voltage sensor 25 is not limited to Figure 1 As long as the DC voltage value V can be detected dc In the following, in this specification, the DC voltage value V dc Also known as "DC voltage V dc ” or simply referred to as “voltage V dc The DC voltage V detected by the DC voltage sensor 25 dc Obtained by the control device 40.

[0058] The AC current sensor 26 is, for example, a well-known AC ammeter or AC current sensor, and is disposed between the power converter 30 and the transformer 14 to detect the three-phase AC current value I u ,I v ,I w In addition, the location of the AC current sensor 26 is not limited to Figure 1 As long as the three-phase AC current value I can be detected, u ,I v ,I w The position of the AC current I u ,I v ,I w Also known as "AC I u ,I v ,I w ", "Current measurement value I u ,I v ,I w ” or simply “current I u ,I v ,I w The AC current I detected by the AC current sensor 26 u ,I v ,I w Obtained by the control device 40.

[0059] The DC input / output section 31 (see Figure 3 , 4 )) is connected to the DC switch 21 via the DC cable 12, serving as an AC end (AC input / output unit 32 (refer to Figure 3 , 4)) is connected to the AC reactor 22 (filter circuit) via the AC cable 13. The power converter 30 is constructed by a plurality of switching elements described later, such as IGBTs. The power converter 30 is controlled by a gate drive signal (gate signal) of the switching element, i.e., a pulse width modulation (PWM: Pulse Width MoDulation) signal, generated by the control device 40, for example. That is, the power converter 30 is controlled by a gate signal for operating the power converter 30.

[0060] The power converter 30 obtains the DC power supplied from the solar cell 11 from one end, and converts the obtained DC power into AC power according to the control of the pulse width modulation signal (gate signal), and outputs it from the other end as the output end and supplies it to the AC cable 13. That is, the power converter 30 operates according to the control based on the gate signal. The details of the power converter 30 will be described later (refer to Figure 3 to Figure 11 wait).

[0061] The control device 40 is, for example, disposed inside or outside the power conversion system 20, and a portion of the wiring is omitted in the figure, but the control device 40 is electrically connected to each component of the power conversion system 20 represented by the power converter 30 by wire or wireless. In addition, the control device 40 can also be implemented as a function of an inverter control circuit not shown in the figure. In addition, the control device 40 can also operate according to instructions from an unillustrated upper device, instructions from an unillustrated operator, etc. via an unillustrated operating unit, for example. In addition, the unillustrated upper device can also monitor and control multiple power conversion systems 20 in a unified manner, and be connected to each power conversion system 20 by wire or wireless.

[0062] Figure 2 Yes means Figure 1 FIG. 2 is a diagram showing an example of a configuration of a control device 40 in a multilevel power conversion system 20 shown in FIG.

[0063] The control device 40 obtains the DC voltage V detected by the DC voltage sensor 25. dc According to the control method described below, the AC switch operation signal is output (refer to Figure 1 In addition, the control device 40 obtains the DC voltage V detected by the DC voltage sensor 25. dc and the AC current I detected by the AC current sensor 26 u ,I v ,I w According to the control method described below, the gate signal is output (refer to Figure 1The control device 40 includes an acquisition unit 41, an output unit 42, a storage unit 43, a system bus 45, and a control unit 50. The acquisition unit 41, the output unit 42, the storage unit 43, and the control unit 50 are connected to each other via the system bus 45.

[0064] The acquisition unit 41 is connected to the DC voltage sensor 25, the AC current sensor 26, and the system bus 45. The acquisition unit 41 may also be connected to a higher-level device (not shown). For example, the acquisition unit 41 acquires the DC voltage V detected by the DC voltage sensor 25. dc , and the AC current I detected by the AC current sensor 26 u ,I v ,I w The acquisition unit 41 outputs the acquired voltage values ​​and current values ​​to each component of the control device 40 via the system bus 45 , for example.

[0065] The output unit 42 is connected to the AC switch 24, the power converter 30, and the system bus 45. The output unit 42 may also be connected to a higher-level device (not shown). For example, the output unit 42 outputs an AC switch operation signal to the AC switch 24 or outputs a gate signal to the power converter 30 according to an instruction obtained from the control unit 50 via the system bus 45.

[0066] The storage unit 43 is a volatile or non-volatile storage medium such as a HDD (Hard Disk Drive), an SSD (Solid State Drive), or other semiconductor memory, and is connected to the system bus 45. The storage unit 43 stores, for example, programs required for the operation of each unit of the control device 40, and writes and reads various information through each unit of the control device 40. In addition, the storage unit 43 stores, for example, values ​​detected by each sensor such as the DC voltage sensor 25 and the AC current sensor 26, various calculation expressions used in the calculation of the control unit 50, coefficients, predetermined threshold values, predetermined determination values, and the like.

[0067] The storage unit 43 is connected to each part of the control device 40 through the system bus 45, etc., so that various information can be input and output. In addition, the storage unit 43 can also be set outside the control device 40 and connected to the control device 40 through wired or wireless. In addition, the storage unit 43 can be an external storage medium such as a memory card, a DVD (Digital Versatile Disc), etc., or it can be an online storage, etc. In addition, the storage unit 43 can also be connected to the memory 92 (see Fig.21 )Shared.

[0068] The system bus (bus) 45 is a data transmission path (bus) connecting various components inside the control device 40, and connects the acquisition unit 41, the output unit 42, the storage unit 43 and the control unit 50 to each other so that various information can be input and output.

[0069] The control unit 50 includes, for example, a processor 91 (see FIG. 1 ) described later, such as a CPU (Central Processing Unit) that operates by executing a program. Fig.21 ). The control unit 50 executes the storage unit 43 or the memory 92 described later (see Fig.21 ) to operate the processor 91 and uniformly control the operation of the power conversion system 20. In addition, the control unit 50 may control the operation of the power conversion system 20 according to instructions received from an unillustrated upper device or an unillustrated operator via an unillustrated operation unit.

[0070] The control unit 50 executes the storage unit 43 or the memory 92 (see Fig.21 ) and functions as the following units. The control unit 50 functions as, for example, an operation control unit 51, a voltage command generating unit 52, and a gate signal generating unit 53. In addition, the above functions can be performed by a processing circuit 90 (see Fig.21 ) in the processor 91 described later (refer to Fig.21 ) can be implemented by a program executed by hardware 93 described later (refer to Fig.21 ) is implemented. In addition, the action control unit 51, the voltage command generating unit 52 and the gate signal generating unit 53 execute a predetermined program to perform the following processing.

[0071] The operation control unit 51 controls the DC voltage V detected by the DC voltage sensor 25 based on a predetermined condition, for example. dc , outputs an AC switch operation signal to the AC switch 24 (refer to Figure 1 In addition, the action control unit 51 transfers the operation of the power converter 30 based on a predetermined condition, for example, based on the opening and closing state of the AC switch 24. For example, the action control unit 51 transfers the operation mode of the power converter 30 to a standby mode in which power conversion is not performed between the DC input / output unit and the AC input / output unit described later, or to a power generation mode in which power conversion is performed, based on a predetermined condition. In addition, the action control unit 51 outputs a standby mode signal of 0 (low level) or 1 (high level) and a gate blocking signal to the gate signal generating unit 53 based on a predetermined condition, for example, based on the opening and closing state of the AC switch 24 or the operation mode of the power converter 30.

[0072] The voltage command generating unit 52 is based on, for example, a predetermined output power command value P _ref and the three-phase AC current I detected by the AC current sensor 26 u ,I v ,I w , generate three-phase voltage command value V u_ref 、V V_ref 、V w_ref Then, the voltage command generating unit 52 generates the three-phase voltage command values ​​V u_ref 、V V_ref 、V w_ref Output to the gate signal generating unit 53.

[0073] The gate signal generating unit 53 obtains the voltage command value V outputted from the voltage command generating unit 52. u_ref 、V V_ref 、V w_ref , and the DC voltage V detected by the DC voltage sensor 25 dc In addition, the gate signal generating unit 53 obtains the triangular wave carriers CA1 and CA2 having a predetermined carrier cycle, and the standby mode signal and the gate blocking signal output from the operation control unit 51. The gate signal generating unit 53 generates a gate blocking signal based on the voltage command value V u_ref 、V V_ref 、V w_ref , DC voltage V dc , triangular wave carriers CA1, CA2, standby mode signals and gate blocking signals to generate gate signals. The gate signal generating unit 53 outputs the generated gate signal to the power converter 30, and when the AC switch 24 is disconnected or the power converter 30 is in standby mode, the semiconductor switch element 2 or 3 (see Figure 3 In addition, the gate signal generating unit 53 outputs the generated gate signal to the power converter 30, so that the semiconductor switch elements 1 and 4 (see Figure 3 etc.) become non-conductive.

[0074] The details of the control configuration or processing (operation) of the operation control unit 51, the voltage command generating unit 52, and the gate signal generating unit 53 in the control unit 50 (control block) will be described later (see Figures 12 to 20 wait).

[0075] Figure 3 Yes means Figure 1 FIG. 1 is a circuit diagram of an example of a circuit configuration of a multilevel power converter 30 shown in FIG. Figure 3In order to simplify the description, as an example of the circuit configuration of the power converter 30, the configuration (circuit diagram) of one phase (for example, the U phase) among the three phases is shown. In fact, the power converter 30, for example, has three Figure 3 The circuit shown in FIG. 1 has a three-phase circuit structure (for example, referring to FIG. Fig. 22 , 23 However, in the present disclosure, the number of phases in the circuit configuration of the power converter 30 is not limited to three phases, and may be a single phase or multiple phases other than three phases.

[0076] like Figure 3 As shown, the power converter 30 has a DC input / output unit 31 and an AC input / output unit 32. In addition, the power converter 30 has a positive terminal P, a negative terminal N, a DC capacitor C P , DC capacitor C N , DC neutral point C, power semiconductor module A and power semiconductor module B. Power semiconductor module A has power semiconductor element 1, power semiconductor element 4 and AC terminal AC, and power semiconductor module B has power semiconductor element 3, power semiconductor element 2 and non-connection terminal NC. In addition, in this specification, AC terminal AC is also referred to as "AC (Alternating Current) terminal", and non-connection terminal NC is also referred to as "NC (No Connection) terminal".

[0077] The DC input / output unit 31 is a DC end of the power converter 30 , and has a positive terminal P and a negative terminal N connected to the solar cell 11 (DC power source or DC load).

[0078] The AC input / output unit 32 is an AC end of the power converter 30 , and has an AC terminal AC connected to the power system 15 (AC power source or AC load).

[0079] The positive terminal P and the negative terminal N are connected to the positive electrode (P electrode) side and the negative electrode (N electrode) side of the solar cell (DC power source) 11 via a DC cable 12 , respectively.

[0080] A DC capacitor C is connected in series between the positive terminal P and the negative terminal N via a DC neutral point C. P and DC capacitor C N . DC capacitor C P and DC capacitor C N For example, a DC smoothing capacitor for smoothing voltage fluctuations (ripples) is connected in series via a DC neutral point C.

[0081] In addition, a power semiconductor module A is connected in series between the positive terminal P and the negative terminal N. In the power semiconductor module A, the power semiconductor element 1 and the power semiconductor element 4 are connected in series with the same polarity via the AC terminal AC (AC terminal). In addition, a power semiconductor module B is connected in series between the DC neutral point C and the AC terminal AC. In the power semiconductor module B, the power semiconductor element 3 and the power semiconductor element 2 are connected in series with opposite polarities via the non-connection terminal NC (NC terminal).

[0082] The power semiconductor elements (semiconductor switching elements) 1 to 4 have return diodes D1 to D4, respectively, and the power semiconductor elements 1 to 4 (semiconductor switching elements) are connected in reverse parallel to the return diodes D1 to D4, respectively. The power semiconductor elements 1 to 4 are semiconductor switching elements composed of, for example, IGBTs, and the on / off operation is controlled by a gate signal output from the control device 40.

[0083] In addition, hereinafter, in this specification, etc., the power semiconductor elements 1 and 4 in the power semiconductor module A are respectively referred to as "semiconductor switch elements 1 and 4", "semiconductor elements 1 and 4", or simply "elements 1 and 4". In addition, the power semiconductor elements 2 and 3 in the power semiconductor module B are respectively referred to as "neutral point elements 2 and 3", "semiconductor switch elements 2 and 3", "semiconductor elements 2 and 3", or simply "elements 2 and 3". In addition, the power semiconductor elements (semiconductor switch elements) 1 to 4 are examples of "the first semiconductor switch element" to "the fourth semiconductor switch element", respectively.

[0084] The return diodes D1 to D4 are connected in reverse parallel to the semiconductor elements 1 to 4, respectively, and are return diodes that return energy when the IGBT is turned off, for example. In addition, in the following, in this specification, the return diodes D1 to D4 are respectively referred to as "reverse parallel diodes D1 to D4" or simply "diodes D1 to D4". In addition, the return diodes D1 to D4 are examples of "the first return diode" to "the fourth return diode", respectively.

[0085] Figure 4 Yes means Figure 1 FIG. 1 is a wiring diagram of an actual state of an example of a circuit configuration of a multilevel power converter 30 shown in FIG. Figure 4 In, with Figure 3 The same circuit as shown in the circuit diagram is shown as an actual state wiring diagram.

[0086] exist Figure 4 In the actual state wiring diagram shown in FIG. 1 , for example, bus bars are used in each wiring of the DC cable 12 and the AC cable 13. Figure 4In the figure, power semiconductor module A and power semiconductor module B are arranged on heat sink 33. Sometimes, the shell (heat sink mounting surface) of semiconductor elements 1 to 4 in power semiconductor modules A and B is in electrical contact with heat sink 33, heat sink 33 is grounded, and the shell of semiconductor elements 1 to 4 becomes at ground potential (ground potential GND). That is, heat sink 33 is usually grounded, and therefore is electrically connected to components such as copper plates attached to the shell (heat sink mounting surface) of semiconductor elements 1 to 4, and the shell of semiconductor elements 1 to 4 sometimes becomes at ground potential (ground potential GND). In addition, other structures and Figure 2 The same, therefore the description is omitted.

[0087] <Operation Principle of First Embodiment>

[0088] Figure 5 Yes means Figure 3 and Figure 4 FIG. 1 is a diagram showing an example of charging paths of parasitic capacitances of various components due to lightning strike in the circuit configuration of the multilevel power converter 30 shown.

[0089] The following describes the principle of charging the parasitic capacitances C1 to C4 of the semiconductor elements 1 to 4 by the surge voltage generated by lightning. Figure 5 In FIG. 1 , a situation in which the P-pole and N-pole potentials to the ground are charged with negative polarity due to lightning strike is shown. In addition, hereinafter, in this specification, etc., the surge voltage generated by lightning strike is also referred to as "lightning surge voltage" or simply "surge voltage".

[0090] As described above, sometimes the housings of the semiconductor elements 1 to 4 are in electrical contact with the heat sink 33, the heat sink 33 is grounded, and the housings of the semiconductor elements 1 to 4 are at ground potential (ground potential GND). Figure 5 As shown, there is a parasitic capacitance C between the semiconductor elements 1 and 4 inside the power semiconductor module A and the housing (heat sink mounting surface) of the semiconductor elements 1 and 4. AC Similarly, there is a parasitic capacitance C between the semiconductor elements 3 and 2 inside the power semiconductor module B and the housing (heat sink mounting surface) of the semiconductor elements 3 and 2. NC .

[0091] That is, an insulating substrate (not shown) is arranged between the copper plate attached to the housing (heat sink mounting surface) of the semiconductor elements 1 to 4 and the semiconductor elements 1 to 4. Thus, the insulating substrate (not shown) acts like a capacitor, and a parasitic capacitance C is generated between the copper plate (ground potential) attached to the housing (heat sink mounting surface) of the semiconductor elements 1 to 4 and the semiconductor elements 1 to 4. AC , C NC .

[0092] In addition, if Figure 5As shown, parasitic capacitances C1 to C4 also exist between the terminals of the semiconductor elements 1 to 4. That is, parasitic capacitances C1 to C4 also exist between the collector and the emitter of each IGBT of the semiconductor elements 1 to 4, respectively.

[0093] In this case, for example, when the power conversion system 20 applies a cutoff signal to the gates of the semiconductor switching elements 1 to 4 in the standby state, when the P-pole and N-pole potentials on the DC side are charged to negative polarity with respect to the ground due to lightning, Figure 5 The parasitic capacitance of each part is charged by the path shown. In general, the charging voltage of the ground potential due to lightning may be different at the P pole and the N pole, but Figure 5 In order to simplify the description, the charging voltage V generated by lightning is shown in the figure. LS Charging situation.

[0094] like Figure 5 As shown in the figure, when the P-pole and N-pole are charged with negative potential to the ground due to lightning, Figure 5 As shown by the arrow, the voltage rises. Figure 5 In the example, the current flows through various paths shown by the dotted lines. Figure 5 As shown, a current path is also formed that flows through the parasitic capacitances C2 and C3 of the neutral point elements 2 and 3.

[0095] Generally, the parasitic capacitance C between the copper plate attached to the case (heat sink mounting surface) of the semiconductor elements 2 and 3 and the insulating substrate (not shown) of the semiconductor elements 2 and 3 is NC The parasitic capacitances C2 and C3 of the neutral point components 2 and 3 are larger than the parasitic capacitances C NC Therefore, if the parasitic capacitance C of the insulating substrate (not shown) NC The parasitic capacitances C2 and C3 of the neutral point components 2 and 3 are Figure 5 When the same current flows through the paths shown, the voltage of the smaller capacitance increases. As a result, the voltage applied to the parasitic capacitances C2 and C3 of the neutral point elements 2 and 3 becomes larger than the potential of the non-connection terminal NC (ground potential).

[0096] Figure 6 Yes means Figure 5 The equivalent circuit diagram of the charging path is shown.

[0097] Typically, the DC capacitor C P , C N The capacitance of the DC capacitor C is large enough compared to the parasitic capacitance of each part. P , C N The voltage charged is small enough compared to the voltage charged to the parasitic capacitance of each part and can be ignored. Figure 6 In the equivalent circuit shown in the figure, the DC capacitor C P , C N The parts are regarded as short-circuited, and the parasitic capacitance of each part is charged to the voltage shown in the figure.

[0098] like Figure 6 As shown in FIG. 1 , when the P-pole and N-pole are charged to the ground with negative polarity due to lightning, the charging voltage generated by lightning is set to V LS When the parasitic capacitance C of the non-connected terminal NC NC The voltage is expressed by the following formula (1).

[0099]

Mathematical formula 1

[0100]

[0101] On the other hand, in this case, the voltages of the parasitic capacitances C2 and C3 of the neutral point elements 2 and 3 are expressed by the following equation (2).

[0102]

Mathematical formula 2

[0103]

[0104] As described above, the parasitic capacitance C between the copper plate attached to the case of the semiconductor elements 2 and 3 and the insulating substrate (not shown) of the semiconductor elements 2 and 3 is NC The parasitic capacitances C2 and C3 of the neutral point elements 2 and 3 are relatively large. Therefore, when the P-pole and N-pole potentials on the DC side are charged to the ground with negative polarity due to lightning, the voltage V2=V3 applied to the parasitic capacitances C2 and C3 shown in equation (2) is greater than the voltage V2=V3 applied to the parasitic capacitances C2 and C3 shown in equation (1). NC Applied voltage V NC .

[0105] Therefore, if the surge voltage caused by lightning causes the potential of the P-pole and N-pole on the DC side to change significantly, and part of the surge voltage is charged to the parasitic capacitances C2 and C3 of the neutral point elements 2 and 3, the semiconductor elements 2 and 3 with low module withstand voltage may be destroyed by the overvoltage. LS Since the voltages V2 and V3 are much larger than the withstand voltage of the neutral point elements 2 and 3 , if the voltages V2 and V3 are applied to the neutral point elements 2 and 3 , the voltages V2 and V3 exceed the withstand voltage of the neutral point elements 2 and 3 , and the neutral point elements 2 and 3 may be destroyed by overvoltage.

[0106] Figure 7 is Figure 3 and Figure 4The circuit configuration of the multilevel power converter 30 shown in the figure shows whether the neutral point elements 2 and 3 are destroyed by overvoltage due to a lightning surge.

[0107] exist Figure 7 In the above, the situation is distinguished by whether the P pole and N pole of the DC side or the AC side are charged with positive polarity or negative polarity due to lightning. In addition, the situation is distinguished by whether the connection point of the diodes D2 and D3 of the two neutral point elements 2 and 3 is the anode side or the cathode side. And, in Figure 7 In , the results of these distinctions are represented in a matrix.

[0108] In the above Figure 5 , 6 In the description, the case where the P-pole and N-pole on the DC side are charged with negative polarity to the ground due to lightning is described. However, in reality, it is not known whether the P-pole and N-pole on the DC side are charged with positive polarity or negative polarity to the ground due to lightning, and sometimes they are charged with positive polarity.

[0109] exist Figure 5 In the circuit configuration shown, when the P-pole and N-pole on the DC side are charged with positive polarity to the ground potential, the parasitic capacitance C NC And the parasitic capacitance C AC The charging current passes through the anti-parallel diodes D2 and D4 of the semiconductor elements 2 and 4, so the parasitic capacitances C1 to C4 of the semiconductor elements 1 to 4 are not charged. Figure 5 In the circuit configuration shown, when the P-pole and N-pole on the DC side are charged with positive potential to the ground due to lightning, the diodes bypass the potential, so that overvoltage destruction of the semiconductor elements 1 to 4 does not occur.

[0110] However, if Figure 5 As in the circuit configuration shown, when the cathode sides of the two anti-parallel diodes D2 and D3 of the neutral point elements 2 and 3 are connected, it is as described above, but when the anode sides of the two anti-parallel diodes are connected, it is not as described above.

[0111] For example, Fig.23As shown, when the anode sides of the two anti-parallel diodes are connected, when charged with negative polarity, overvoltage destruction of the semiconductor elements 2 and 3 does not occur, and when charged with positive polarity, overvoltage destruction of the semiconductor elements 2 and 3 occurs. That is, whether the semiconductor elements 2 and 3 are destroyed by overvoltage when charged with positive polarity or when charged with negative polarity changes according to the direction of the anti-parallel diodes D2 and D3. This is because when the cathode sides of the two anti-parallel diodes D2 and D3 of the neutral point elements 2 and 3 are connected, it becomes a circuit equivalent to the case where the signs of the voltage and current are all opposite when the anode sides are connected.

[0112] In addition, Figure 5 In the circuit configuration shown, when the AC side is charged with positive polarity, the ground potential of the P pole is charged with positive polarity through the anti-parallel diode D1 of the semiconductor element 1. In addition, the ground potential of the N pole is charged with positive polarity through the anti-parallel diode D1 of the semiconductor element 1 and the DC capacitor. Therefore, in the case of "the AC side is charged with positive polarity", the same phenomenon as "the case of the ground potential of the P pole and the N pole on the DC side is charged with positive polarity" occurs.

[0113] On the other hand, Figure 5 In the circuit configuration shown, when the AC side is charged with negative polarity, the N-pole ground potential is charged with negative polarity through the anti-parallel diode D4 of the semiconductor element 4. In addition, the P-pole ground potential is charged with negative polarity through the anti-parallel diode D4 of the semiconductor element 4 and the DC capacitor. Therefore, when "the AC side is charged with negative polarity", the same phenomenon as "the DC side P-pole and N-pole ground potential is charged with negative polarity" occurs.

[0114] Therefore, when the AC side is charged by lightning, the P and N poles on the DC side are also charged through the diode. Therefore, the voltage rise caused by lightning will produce the same phenomenon regardless of whether it is the DC side or the AC side as long as the current path changes. Figure 7 This is a diagram that summarizes the above explanation.

[0115] like Figure 7As shown, when the P-pole and N-pole on the DC side or the AC side are charged with positive polarity, when the connection point of the diodes D2 and D3 of the two neutral point elements 2 and 3 is the anode side, the parasitic capacitances C2 and C3 of the neutral point elements 2 and 3 are charged, which may cause overvoltage damage. On the other hand, when the P-pole and N-pole on the DC side or the AC side are charged with positive polarity, when the connection point of the diodes D2 and D3 of the two neutral point elements 2 and 3 is the cathode side, the parasitic capacitances C2 and C3 of the neutral point elements 2 and 3 are not charged, and overvoltage damage of the neutral point elements 2 and 3 will not occur.

[0116] Furthermore, when the P-pole and N-pole on the DC side or the AC side are charged with negative polarity, when the connection point of the diodes D2 and D3 of the two neutral point elements 2 and 3 is the anode side, the parasitic capacitances C2 and C3 of the neutral point elements 2 and 3 are not charged, and overvoltage damage to the neutral point elements 2 and 3 does not occur. On the other hand, when the P-pole and N-pole on the DC side or the AC side are charged with negative polarity, when the connection point of the diodes D2 and D3 of the two neutral point elements 2 and 3 is the cathode side, the parasitic capacitances C2 and C3 of the neutral point elements 2 and 3 are charged, which may cause overvoltage damage.

[0117] Figure 8 It means in Figure 3 and Figure 4 FIG. 1 is a diagram showing an example of charging paths of parasitic capacitances of various components due to lightning strike when the semiconductor element 2 is turned on in the circuit configuration of the multilevel power converter 30 shown in FIG. Figure 8 In, with Figure 5 Similarly, the charging path of the parasitic capacitance of each part is shown when the semiconductor element 2 is turned on (on state) when the P-pole and N-pole ground potentials are charged with negative polarity due to lightning.

[0118] exist Figure 8 In the case where the power converter 30 is in the standby mode (standby state), a gate signal is applied to turn on the semiconductor element 2. Therefore, the parasitic capacitances C2 and C3 of the semiconductor elements 2 and 3 are bypassed by the semiconductor element 2 and are not charged. As a result, overvoltage damage to the semiconductor elements 2 and 3 caused by the application of the charging voltage generated by lightning can be avoided.

[0119] That is, in Figure 5 In the circuit configuration shown, when the P-pole and N-pole are charged to negative potential with respect to the ground due to lightning, the current charges the parasitic capacitances C2 and C3 of the semiconductor elements 2 and 3. Figure 8 In the embodiment, since the semiconductor element 2 is set to the on state in advance, the current is bypassed, and therefore, the parasitic capacitances C2 and C3 of the semiconductor elements 2 and 3 are not charged.

[0120] In addition, Figure 8 In the case where a gate signal is applied to turn on the semiconductor element 2, a small voltage may be applied to the parasitic capacitor C3 of the semiconductor element 3, but the parasitic capacitor C3 of the semiconductor element 3 will not be charged to a voltage that causes overvoltage damage. Figure 8 As shown, when the power converter 30 is in the standby mode, if a gate signal is applied to turn on the semiconductor element 2, even if the P-pole and N-pole ground potentials are charged due to lightning, the neutral point elements 2 and 3 can be protected from being destroyed by overvoltage.

[0121] Fig. 9 Yes means Figure 8 The equivalent circuit diagram of the charging path is shown.

[0122] like Fig. 9 As shown in FIG. 1 , when the P-pole and N-pole are charged to the ground with negative polarity due to lightning, the charging voltage generated by lightning is set to V LS When the parasitic capacitance C of the non-connected terminal NC NC The voltage is expressed by the following formula (3).

[0123]

Mathematical formula 3

[0124] V NC =V LS ……(3)

[0125] On the other hand, in this case, the voltages of the parasitic capacitances C2 and C3 of the neutral point elements 2 and 3 are expressed by the following equation (4).

[0126]

Mathematical formula 4

[0127] V2=V3=0……(4)

[0128] That is, it can be seen from equations (3) and (4) that by setting the semiconductor element 2 to the on state in advance, the current is bypassed and the parasitic capacitances C2 and C3 of the semiconductor elements 2 and 3 are not charged.

[0129] Fig.10 It means in Figure 3 and Figure 4 FIG. 1 is a diagram showing an example of charging paths of parasitic capacitances of various components due to lightning strike when the semiconductor element 3 is turned on in the circuit configuration of the multilevel power converter 30 shown in FIG. Fig.10 In, with Figure 5 Similarly, the charging path of the parasitic capacitance of each part is shown when the semiconductor element 3 is turned on (on state) when the P-pole and N-pole ground potentials are charged with negative polarity due to lightning.

[0130] In the above Figure 8In the case where the power converter 30 is in the standby mode (standby state), a gate signal for turning on the semiconductor element 2 is applied. Fig.10 In the case of a gate signal that turns on the semiconductor element 3, the parasitic capacitances C2 and C3 of the semiconductor elements 2 and 3 are bypassed by the semiconductor element 3 and are not charged. As a result, the overvoltage damage to the semiconductor elements 2 and 3 caused by the charging voltage generated by lightning can be avoided. Fig.10 In the Figure 8 The same, therefore the description is omitted.

[0131] Fig.11 Yes means Fig.10 The equivalent circuit diagram of the charging path is shown. Fig.11 The equivalent circuit shown is basically the same as Fig. 9 The equivalent circuits shown are the same.

[0132] That is, Fig.11 As shown in FIG. 1 , when the P-pole and N-pole are charged to the ground with negative polarity due to lightning, the charging voltage generated by lightning is set to V LS When the parasitic capacitance C of the non-connected terminal NC NC The voltage and Fig. 9 The same is expressed by formula (3).

[0133]

Mathematical formula 5

[0134] V NC =V LS ……(3)

[0135] In this case, the voltages of the parasitic capacitors C2 and C3 of the neutral point elements 2 and 3 are Fig. 9 The same is expressed by formula (4).

[0136]

Mathematical formula 6

[0137] V2=V3=0……(4)

[0138] Therefore, with Fig. 9 Similarly, it can be seen from equations (3) and (4) that by setting the semiconductor element 3 to the on state in advance, the current is also bypassed, and the parasitic capacitances C2 and C3 of the semiconductor elements 2 and 3 are not charged.

[0139] Above, such as Figure 8 to Figure 11As shown, when the power converter 30 is in the standby mode (standby state), if a gate signal is applied to turn on either of the semiconductor elements 2 and 3, the parasitic capacitances C2 and C3 of the semiconductor elements 2 and 3 are bypassed and not charged. Thus, overvoltage damage to the semiconductor elements 2 and 3 caused by the charging voltage generated by lightning can be avoided.

[0140] Here, even if a gate signal is applied to turn both semiconductor elements 2 and 3 into an on state, the same effect as above is achieved by bypassing both parasitic capacitances C2 and C3 of semiconductor elements 2 and 3. In other words, when the power converter 30 is in a standby mode (standby state), if a gate signal is applied to turn either or both semiconductor elements 2 and 3 into an on state, overvoltage damage to semiconductor elements 2 and 3 caused by the charging voltage generated by lightning strike can be avoided. In this case, as long as either or both semiconductor elements 2 and 3 are turned into an on state, either or both semiconductor elements 2 and 3 can be continuously applied with a gate signal to turn into an on state, or can be alternately or irregularly applied with a gate signal to turn into an on state. In other words, as long as a gate signal is applied to turn at least either semiconductor element 2 or 3 into an on state or a switching state.

[0141] In addition, Figure 8 to Figure 11 In, with Figure 5 and Figure 6 Similarly, the case where the P-pole and N-pole are charged with negative polarity to the ground potential due to lightning strike is shown. However, this is not limited to this. Figure 7 As shown in FIG. 1 , whether the P-pole and the N-pole or the AC side are charged with positive polarity or negative polarity due to lightning, as long as a gate signal is applied to turn on either or both of the semiconductor elements 2 and 3, the same effect as described above is achieved. Figure 8 to Figure 11 Same effect.

[0142] <Control Example of First Embodiment>

[0143] Fig.12 Yes means Figure 1 4 is a flowchart of the state transition sequence of the multi-level power conversion system 20 between the power generation mode and the standby mode. For example, when the power conversion system 20 is started (started), the control unit 50 (refer to Figure 2 )start Fig.12 Flowchart shown.

[0144] In step S1, the operation control unit 51 of the control unit 50 determines that the AC switch 24 is in the off (disconnected) state, and shifts the operation mode of the power converter 30 to the standby mode. When shifting the operation mode of the power converter 30 to the standby mode, the operation control unit 51 may output a predetermined standby mode signal and a gate blocking signal to the gate signal generating unit 53 (see Figure 2 , Fig.14 In addition, the standby mode is, for example, an operation mode in which the AC switch 24 is turned off (disconnected) at night or in bad weather, and the power conversion from the solar cell 11 to the power system 15 is not performed through the power converter 30. In other words, the standby mode is an operation mode in which the DC input / output unit 31 (see Figure 3 , 4 ) and the AC input and output unit 32 (refer to Figure 3 , 4 ) is an operating mode in which no power conversion is performed between the two.

[0145] Here, in the conventional power converter, the control device cuts off the gate signals of all semiconductor switching elements (applies a gate signal that turns off all semiconductor switching elements) when the power converter is in the standby mode. On the other hand, the control unit 50 in the control device 40 disclosed in the present application applies a gate signal that turns on either or both of the neutral point elements 2 and 3 connected in reverse series, and applies a gate signal that turns off the semiconductor elements 1 and 4 other than the neutral point elements 2 and 3, in the standby mode. In this way, overvoltage damage to the semiconductor elements 1 to 4 caused by lightning surges in the standby mode can be avoided. In addition, the details of the control structure or processing (action) of the voltage command generating unit 52 and the gate signal generating unit 53 in the standby mode will be described later (refer to Fig.13 , Fig.14 wait).

[0146] In step S2, the motion control unit 51 of the control unit 50 determines whether it is sunrise. Specifically, the motion control unit 51 determines whether it is sunrise or not via the acquisition unit 41 (see Figure 2 ) obtains the DC voltage V detected by the DC voltage sensor 25 dc , determine the DC voltage V dc Does it exceed 1000V (V dc >1000V). Then, the action control unit 51 controls the DC voltage V dc Whether it is sunrise is determined by whether the voltage exceeds 1000V for more than 2 seconds.

[0147] For example, the operation control unit 51 determines that the DC voltage V dcIf the voltage exceeds 1000 V for more than 2 seconds (Yes), it is determined to be sunrise, and the process is transferred to step S3. dc If the voltage does not exceed 1000V for more than 2 seconds ("No" side), it is determined that there is no sunrise, and the processing of steps S1 and S2 is repeated until sunrise is determined. The numerical values ​​such as 2 seconds and 1000V are examples.

[0148] In step S3, the operation control unit 51 of the control unit 50 outputs the signal to the output unit 42 (see Figure 2 ) outputs an AC switch operation signal to the AC switch 24 to turn on (close) the AC switch 24.

[0149] In step S4, the operation control unit 51 of the control unit 50 determines that the AC switch 24 is in the on state, and switches the operation mode of the power converter 30 to the power generation mode. The operation control unit 51 may output a predetermined standby mode signal and a gate blocking signal to the gate signal generating unit 53 (see Figure 2 , Fig.14 Alternatively, the operation control unit 51 may also output a predetermined operation mode signal (generation mode signal) to the gate signal generating unit 53 when the operation mode of the power converter 30 is shifted to the generation mode. In addition, the generation mode is an operation mode in which there is power generation from the solar cell 11, the AC switch 24 is turned on (connected), and a gate signal is applied to the semiconductor elements 1 to 4 of the power converter 30 for switching, thereby converting the power of the solar cell 11 and supplying power to the power system 15 side. In other words, the generation mode is when the DC input / output unit 31 (refer to Figure 3 , 4 ) and the AC input and output unit 32 (refer to Figure 3 , 4 ) in the power generation mode. In addition, the control or processing (action) of the control unit 50 in the power generation mode is the same as that of the conventional power converter, so the description is omitted.

[0150] In step S5, the motion control unit 51 of the control unit 50 determines whether it is sunset. Specifically, the motion control unit 51 determines whether it is sunset via the acquisition unit 41 (see Figure 2 ) obtains the DC voltage V detected by the DC voltage sensor 25 dc , determine the DC voltage V dc Is it less than 900V (V dc <900V). Then, the action control unit 51 controls the DC voltage V dc Whether it is sunrise is determined by whether the voltage is less than 900V for more than 60 seconds.

[0151] The operation control unit 51 determines that the DC voltage V dc For example, if the voltage is less than 900 V for more than 60 seconds ("Yes" side), it is determined to be sunset, and the process is transferred to step S6. dc If the voltage is less than 900 V for not more than 60 seconds ("No"), it is determined that there is no sunset, and the processing of steps S4 and S5 is repeated until it is determined that there is sunset. The numerical values ​​of 60 seconds and 900 V are examples.

[0152] In step S6, the operation control unit 51 of the control unit 50 outputs the signal to the output unit 42 (see Figure 2 ) outputs an AC switch operation signal to the AC switch 24 to turn off (open) the AC switch 24.

[0153] In step S7, the control unit 50 determines whether the operation of the power conversion system 20 has ended. The operation of the power conversion system 20 may end, for example, due to maintenance or failure of the power conversion system 20, or when instructions are received from a higher-level device or operator (not shown). When the control unit 50 determines that the operation of the power conversion system 20 has ended ("Yes" side), the processing of this flowchart ends. On the other hand, when the control unit 50 determines that the operation of the power conversion system 20 has not ended ("No" side), the processing returns to step S1 and the processing of steps S1 to S7 is repeated.

[0154] Fig.13 Yes means Figure 2 FIG. 1 is a diagram showing an example of a control configuration of a voltage command generating unit 52 of a control unit 50. Fig.13 , the control configuration examples of the three phases of the U phase, the V phase, and the W phase are respectively illustrated, but in the following description, the control common to each phase is described by taking the control of the U phase as an example.

[0155] In step S11, the voltage command generating unit 52 obtains a predetermined output power command value P _ref , based on the obtained output power command value P _ref , output U phase current command value I u_ref In addition, the output power command value P _ref For example, it is acquired based on a predetermined power demand, a predetermined calculation result, or the like, or is acquired from the storage unit 43 , a higher-level device (not shown), or the like.

[0156] In step S12, the voltage command generating unit 52 obtains the U-phase current command value I outputted by the process in step S11. u_ref In addition, the voltage command generating unit 52 is provided via, for example, the acquiring unit 41 (see Figure 2) is obtained by the AC current sensor (refer to Figure 1 ) The detected AC current I of phase U u (U phase current measured value I u Then, the voltage command generating unit 52 generates a voltage command value I of the U-phase current from the obtained voltage command value I u_ref Subtract the U-phase current measured value I obtained u , output the subtracted value.

[0157] In step S13, the voltage command generating unit 52 performs proportional control based on the value output by the process of step S12 and the proportional control gain Kp, and converts the U-phase voltage command value V obtained by the proportional control into u_ref Output to the gate signal generating unit 53 (refer to Figure 2 , Fig.14 wait).

[0158] In addition, the voltage command generating unit 52 obtains the V-phase voltage command value V in the same manner as the U-phase in steps S11 to S13. V_ref and V phase voltage command value V w_ref , the obtained V phase voltage command value V V_ref and V phase voltage command value V w_ref Output to the gate signal generating unit 53.

[0159] In addition, by Fig.13 The processing performed by the voltage command generating unit 52 described in the above is the same as the processing generally performed by the control of a normal power converter.

[0160] Fig.14 Yes means Figure 2 FIG. 1 is a diagram showing an example of a control structure of the gate signal generating unit 53 of the control unit 50 shown in FIG. Fig.14 , the control configuration examples of the three phases of the U phase, the V phase, and the W phase are respectively illustrated, but in the following description, the control common to each phase is described by taking the control of the U phase as an example.

[0161] In step S21, the gate signal generating unit 53 obtains the U-phase voltage command value V outputted from the voltage command generating unit 52. u_ref (x) In addition, the gate signal generating unit 53 obtains the DC voltage V detected by the DC voltage sensor 25. dc The gate signal generation unit 53 divides the obtained value (x) by the obtained value (y) (x / y) to obtain the U-phase modulated wave D u , and output the obtained U-phase modulation wave D u In addition, the modulation wave D is a voltage command value normalized by half of the DC voltage. _ref Divide by the DC voltage Vdc The value is obtained by performing a low-pass filter and halving it.

[0162] In step S22a, the gate signal generating unit 53 uses a comparator to compare the U-phase modulated wave D outputted in the process of step S21. u The gate signal generating unit 53 compares the triangular wave carrier wave CA1 generated by the carrier generator. u When it is greater than the triangular wave carrier CA1, it outputs a 1 signal. u When it is less than the triangular wave carrier CA1, a signal of 0 is output. In addition, the triangular wave carrier CA1 is a triangular wave signal that changes between 0 and 1 in a certain carrier cycle.

[0163] In step S22b, the gate signal generating unit 53 uses a comparator to compare the U-phase modulated wave D outputted in the process of step S21. u The gate signal generating unit 53 compares the triangular wave carrier wave CA2 generated by the carrier generator. u When it is greater than the triangular wave carrier CA2, it outputs a 1 signal. u When it is less than the triangular wave carrier CA2, a signal of 0 is output. In addition, the triangular wave carrier CA2 is a triangular wave signal that changes between -1 and 0 in a certain carrier cycle.

[0164] In step S23a, the gate signal generating unit 53 outputs a signal obtained by delaying the value of the signal output in the process of step S22a by the dead time generator. The dead time generator is used to prevent short circuits caused by simultaneous conduction of semiconductor switching elements and outputs a signal obtained by delaying the rise time of the pulse command value.

[0165] In step S23b, the gate signal generating unit 53 outputs a signal obtained by delaying the negative logic (NOT) value of the signal output in the process of step S22a by the dead time generator. That is, when the signal output by the gate signal generating unit 53 in step S22a is 0, it is delayed by 1 by the dead time generator and output, and when it is 1, it is delayed by 0 by the dead time generator and output.

[0166] In step S23 c , the gate signal generating unit 53 outputs a signal obtained by delaying the signal output in the process of step S22 b by the dead time generator.

[0167] In step S23d, the gate signal generating unit 53 outputs a signal obtained by delaying the negative logic (NOT) value of the signal output in the process of step S22b by the dead time generator. That is, when the signal output by the gate signal generating unit 53 in step S22b is 0, it is delayed by 1 by the dead time generator and output, and when it is 1, it is delayed by 0 by the dead time generator and output.

[0168] In step S24a, the gate signal generating unit 53 outputs an AND operation (AND) of the value of the signal output in step S23a and the value of the negative logic (NOT) of the standby mode signal. That is, the gate signal generating unit 53 outputs the value of the signal output in step S23a and the value of the negative logic of the standby mode signal to the AND circuit. In this case, when the standby mode signal is 1, the negative logic of the standby mode signal is 0, and therefore, regardless of the value output from the dead time generator, 0 is output from the AND circuit. On the other hand, when the standby mode signal is 0, the negative logic of the standby mode signal is 1, and therefore, the same value as the value output from the dead time generator is output from the AND circuit. In addition, the standby mode signal is obtained from, for example, the action control unit 51.

[0169] In step S24b, the gate signal generating unit 53 outputs an OR operation of the value of the signal output in the process of step S23b and the value of the standby mode signal. That is, the gate signal generating unit 53 inputs the value of the signal output in the process of step S23b and the value of the standby mode signal to the OR circuit. Then, when at least one of the value of the standby mode signal and the value output from the dead time generator is 1, 1 is output from the OR circuit. In this case, when the standby mode signal is 1, 1 is output from the OR circuit regardless of the value output from the dead time generator. On the other hand, when the standby mode signal is 0, the same value as the value output from the dead time generator is output from the OR circuit.

[0170] In step S24c, the gate signal generating unit 53 outputs an OR operation of the value of the signal output in the process of step S23c and the value of the standby mode signal. That is, the gate signal generating unit 53 outputs the value of the signal output in the process of step S23c and the value of the standby mode signal to the OR circuit. Then, when at least one of the value of the standby mode signal and the value output from the dead time generator is 1, 1 is output from the OR circuit. In this case, when the standby mode signal is 1, 1 is output from the OR circuit regardless of the value output from the dead time generator. On the other hand, when the standby mode signal is 0, the same value as the value output from the dead time generator is output from the OR circuit.

[0171] In step S24d, the gate signal generating unit 53 outputs an AND operation (AND) of the value of the signal output in the process of step S23d and the value of the negative logic (NOT) of the standby mode signal. That is, the gate signal generating unit 53 inputs the value of the signal output in the process of step S23d and the value of the negative logic of the standby mode signal to the AND circuit. In this case, when the standby mode signal is 1, the negative logic of the standby mode signal is 0, and therefore, regardless of the value output from the dead time generator, 0 is output from the AND circuit. On the other hand, when the standby mode signal is 0, the negative logic of the standby mode signal is 1, and therefore, the same value as the value output from the dead time generator is output from the AND circuit.

[0172] In step S25a, the gate signal generating unit 53 outputs the gate signal gu1 based on the AND operation (AND) of the value of the signal output in the process of step S24a and the value of the negative logic (NOT) of the gate blocking signal. That is, the gate signal generating unit 53 inputs the value of the signal output in the process of step S24a and the value of the negative logic of the gate blocking signal into the AND circuit. Then, when the gate blocking signal is 1, the negative logic of the gate blocking signal is 0, and therefore, regardless of the value of the signal output in the process of step S24a, 0 is output from the AND circuit as the gate signal gu1. On the other hand, when the gate blocking signal is 0, the negative logic of the gate blocking signal is 1, and therefore, the same value as the value of the signal output in the process of step S24a is output from the AND circuit as the gate signal gu1. In addition, the gate signal gu1 is a gate signal for the semiconductor element 1 (refer to Figure 3 to Figure 11 The gate blocking signal is obtained from the action control unit 51, for example.

[0173] In step S25b, the gate signal generating unit 53 outputs the gate signal gu3 based on the AND operation (AND) of the value of the signal output in the process of step S24b and the value of the negative logic (NOT) of the gate blocking signal. That is, the gate signal generating unit 53 inputs the value of the signal output in the process of step S24b and the value of the negative logic of the gate blocking signal into the AND circuit. Then, when the gate blocking signal is 1, the negative logic of the gate blocking signal is 0, and therefore, regardless of the value of the signal output in the process of step S24b, 0 is output from the AND circuit as the gate signal gu3. On the other hand, when the gate blocking signal is 0, the negative logic of the gate blocking signal is 1, and therefore, the same value as the value of the signal output in the process of step S24b is output from the AND circuit as the gate signal gu3. In addition, the gate signal gu3 is a gate signal generated by the semiconductor element (neutral point element) 3 (refer to Figure 3 to Figure 11 The gate blocking signal is obtained from the action control unit 51, for example.

[0174] In step S25c, the gate signal generating unit 53 outputs the gate signal gu2 based on the AND operation (AND) of the value of the signal output in the process of step S24c and the value of the negative logic (NOT) of the gate blocking signal. That is, the gate signal generating unit 53 inputs the value of the signal output in the process of step S24c and the value of the negative logic of the gate blocking signal into the AND circuit. Then, when the gate blocking signal is 1, the negative logic of the gate blocking signal is 0, and therefore, regardless of the value of the signal output in step S24c, 0 is output from the AND circuit as the gate signal gu2. On the other hand, when the gate blocking signal is 0, the negative logic of the gate blocking signal is 1, and therefore, the same value as the value of the signal output in the process of step S24c is output from the AND circuit as the gate signal gu2. In addition, the gate signal gu2 is a gate signal generated by the semiconductor element (neutral point element) 2 (refer to Figure 3 to Figure 11 The gate blocking signal is obtained from the action control unit 51, for example.

[0175] In step S25d, the gate signal generating unit 53 outputs the gate signal gu4 based on the AND operation (AND) of the value of the signal output in the process of step S24d and the value of the negative logic (NOT) of the gate blocking signal. That is, the gate signal generating unit 53 inputs the value of the signal output in the process of step S24d and the value of the negative logic of the gate blocking signal into the AND circuit. Then, when the gate blocking signal is 1, the negative logic of the gate blocking signal is 0, and therefore, regardless of the value of the signal output in step S24d, 0 is output from the AND circuit as the gate signal gu4. On the other hand, when the gate blocking signal is 0, the negative logic of the gate blocking signal is 1, and therefore, the same value as the value of the signal output in the process of step S24d is output from the AND circuit as the gate signal gu4. In addition, the gate signal gu4 is a gate signal for the semiconductor element 4 (refer to Figure 3 to Figure 11 The gate blocking signal is obtained from the action control unit 51, for example.

[0176] In addition, the gate signal generating unit 53 also performs the processing shown in the above steps S21 to S25d in the V phase and the W phase in the same manner as in the U phase, and outputs the gate signals gv1 to gv4 and the gate signals gw1 to gw4 for controlling the operation of the semiconductor elements 1 to 4.

[0177] Above, in Fig.14 The contents of the processing of the gate signal generating unit 53 described in the above also include contents generally performed in the control of a normal three-level power converter. For example, the following control is generally performed: the voltage command value V of each phase is set to _refThe normalized modulation wave D is compared with the two carrier waves CA1 and CA2, and the result is input to the dead time generator to output the gate signal g. Fig.14 The processing of the gate signal generating section 53 shown has the following features.

[0178] That is, in Fig.14 In the control configuration shown in FIG. 1 , a standby mode signal is used to cope with lightning surges. Fig.14 In the control configuration shown, for example, when the AC switch 24 is off and there is no need to output power to the AC power system 15 (when power conversion is not performed) (standby mode), the standby mode signal is 1.

[0179] In the control of the general power converter 30, when the AC switch 24 is turned off and there is no need to output power to the AC power system 15, a gate signal is outputted to turn off all gates by making the gate blocking signal 1. Fig.14 In the control configuration shown, for example, when the AC switch 24 is turned off and there is no need to output power to the AC power system 15 (when power conversion is not performed) (standby mode), the gate cutoff signal is 0.

[0180] Thus, when the power converter 30 of the present embodiment is in the standby mode, the standby mode signal is 1 and the gate blocking signal is 0. Therefore, for example, in the U phase, in the AND circuits of steps S25a and S25d, 0 is output as gate signals gu1 and gu4. On the other hand, in the AND circuits of steps S25b and S25c, 1 is output as gate signals gu3 and gu2.

[0181] In other words, when the standby mode signal is 1, in the AND circuits of steps S24a and S24d, no matter what signal reaches the other side, 0 is output, and therefore, 0 is also output from the AND circuits of steps S25a and S25d as gate signals gu1 and gu4. On the other hand, when the standby mode signal is 1, in the OR circuits of steps S24b and S24c, no matter what signal reaches the other side, 1 is output, and therefore, 1 is also output from the AND circuits of steps S25b and S25c as gate signals gu3 and gu2.

[0182] Thus, when the power converter 30 is in the standby mode, the standby mode signal is 1, so the semiconductor elements 1 and 4 of each phase are definitely turned off, and the semiconductor elements (neutral point elements) 2 and 3 of each phase are definitely turned on. In addition, when the standby mode signal is 0 (power generation mode), the gate blocking signal is also 0, and the same values ​​as those output from the dead time generator are output as gate signals gu1, gu3, gu2, and gu4, respectively.

[0183] <Effects of the First Embodiment>

[0184] Above, according to Figure 1 to Figure 14 In the first embodiment shown, when the power converter 30 is in the standby mode, a gate signal for turning on the semiconductor elements (neutral point elements) 2 and 3 of each phase is applied. Therefore, according to this embodiment, when the power converter 30 is in the standby mode, even if the ground potential of the P pole and the N pole is charged due to lightning, one or both of the neutral point elements 2 and 3 are turned on. Therefore, according to this embodiment, in the multi-level power conversion system 20, it is possible to suppress the semiconductor elements 1 to 4 of the power converter 30 from being destroyed by overvoltage due to lightning surge, and it is possible to protect the neutral point elements 2 and 3 from being destroyed by overvoltage due to lightning surge.

[0185] <Modification of the First Embodiment>

[0186] Fig.15 FIG. 1 is a diagram showing an example of a control structure of a gate signal generating unit 53 ′ of a control unit 50 according to a modification of the first embodiment. Fig.15 In the modified example of the first embodiment shown in FIG. Figure 1 to Figure 14 The same or similar structures or processes as those in the first embodiment are denoted by the same reference numerals, and the detailed description thereof will be omitted or simplified.

[0187] In addition, in the modified example of the first embodiment, in addition to Fig.15 Except for the control structure of the gate signal generating unit 53' shown in FIG. Figure 1 to Figure 14 The first embodiment shown is the same or the same. Fig.15 In the control shown, Fig.14 The processing of steps S21 to S22b shown in FIG. 1 is the same as or similar to the processing of steps S21 to S22b, and the processing of steps S26a to S28d is performed instead of the processing of steps S23a to S25d. Fig.14 The description is the same as that of , and the control common to each phase is described by taking the control of phase U as an example.

[0188] The processing of steps S21 to S22b is Fig.14 The processing shown is the same or identical, so the description is omitted.

[0189] In step S26a, the gate signal generating unit 53' outputs an AND operation of the value of the signal output in step S22a and the negative logic (NOT) value of the standby mode signal.

[0190] In step S26b, the gate signal generating unit 53' outputs an OR of the value of the signal output in the process of step S22b and the value of the standby mode signal.

[0191] In step S27a, the gate signal generating unit 53' outputs a signal obtained by delaying the value of the signal output in the process of step S26a by the dead time generator.

[0192] In step S27b, the gate signal generating unit 53' outputs a signal obtained by delaying the negative logic (NOT) value of the signal output in the process of step S26a by the dead time generator.

[0193] In step S27c, the gate signal generating unit 53' outputs a signal obtained by delaying the signal output in the process of step S26b by the dead time generator.

[0194] In step S27d, the gate signal generating unit 53' outputs a signal obtained by delaying the negative logic (NOT) value of the signal output in the process of step S26b by the dead time generator.

[0195] In steps S28a to S28d, the gate signal generating unit 53' obtains the value of the signal output in the process of steps S27a to S27d and the negative logic (NOT) value of the gate blocking signal. Then, the gate signal generating unit 53' outputs the gate signals gu1, gu3, gu2, and gu4 respectively based on the AND operation (AND) of the value of the signal output in the process of steps S27a to S27d and the negative logic (NOT) value of the gate blocking signal.

[0196] In addition, the gate signal generating unit 53 ′ also performs the processing shown in the above steps S21 to S22 b and S26 a to S28 d in the V phase and the W phase, respectively, similarly to the U phase, and outputs the gate signals gv1 to gv4 and the gate signals gw1 to gw4 for controlling the operation of the semiconductor elements 1 to 4 .

[0197] Above, in Fig.15 In the process of the modification of the first embodiment shown in FIG. Fig.14 The processing of the first embodiment shown is the same, and when the power converter 30 is in the standby mode, the standby mode signal is 1 and the gate blocking signal is 0. Therefore, for example, in the U phase, in the AND circuits of steps S28a and S28d, 0 is output as gate signals gu1 and gu4. On the other hand, in the AND circuits of steps S28b and S28c, 1 is output as gate signals gu3 and gu2.

[0198] Therefore, in Fig.15 In the process shown, Fig.14The processing shown is the same. When the power converter 30 is in the standby mode, the standby mode signal is 1, so the semiconductor elements 1 and 4 of each phase are definitely turned off, and the semiconductor elements (neutral point elements) 2 and 3 of each phase are definitely turned on. In addition, when the standby mode signal is 0 (power generation mode), the gate blocking signal is also 0, and the AND circuits of steps S28a to S28d output the same values ​​as the values ​​output from the dead time generator as gate signals gu1, gu3, gu2, and gu4, respectively.

[0199] <Functions and Effects of Modification Example of First Embodiment>

[0200] Above, according to Fig.15 The modified example of the first embodiment shown in FIG. Figure 1 to Figure 14 Therefore, according to this embodiment, in the multi-level power conversion system 20, it is possible to suppress the semiconductor elements 1 to 4 of the power converter 30 from being destroyed by overvoltage due to lightning surge, and to protect the neutral point elements 2 and 3 from being destroyed by overvoltage due to lightning surge.

[0201] <Second Embodiment>

[0202] Fig.16 FIG. 2 is a diagram showing an example of a control structure of a gate signal generating unit 53A of a control unit 50A according to the second embodiment. Fig.16 In the second embodiment shown, Figure 1 to Figure 15 The same or similar configurations or processes in the first embodiment and the modification examples of the first embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted or simplified.

[0203] In the second embodiment, in addition to Fig.16 Except for the control structure of the gate signal generating unit 53A of the control unit 50A shown in FIG. 1 , the other structures and controls are the same as those of FIG. Figure 1 to Figure 14 That is, although the illustration is omitted, in the second embodiment, in the third embodiment, instead of Figure 2 The control unit 50 of the first embodiment shown in FIG. 1 is replaced with a control unit 50A. Figure 2 The gate signal generating unit 53 of the control unit 50 of the first embodiment shown in FIG. 1 includes a gate signal generating unit 53A. Fig.14 The description is the same as that of , and the control common to each phase is described by taking the control of phase U as an example.

[0204] In the standby mode, the control unit 50A of the second embodiment sends a signal to the AC side (AC input / output unit 32 (refer to Figure 3 , 4)) outputs a gate signal generated by outputting a voltage command value substantially equal to the DC neutral point C (voltages deemed to be equal) to the power converter 30. In addition, a voltage substantially equal to the DC neutral point C can be achieved by applying a voltage command of 0 (zero) in an output voltage control method generally used in a three-level power converter.

[0205] In step S31, the gate signal generating unit 53A generates the U-phase voltage command value V output from the voltage command generating unit 52. u_ref The gate signal generating unit 53A selects the U-phase voltage command value V 0 (zero) and the standby mode signal obtained by the selector. Then, the gate signal generating unit 53A selects the U-phase voltage command value V 1 (zero) and the standby mode signal obtained by the selector according to whether the standby mode signal obtained by the selector is 0 or 1. u_ref and 0 (zero), and outputs the selected voltage command value.

[0206] That is, Fig.16 As shown in step S31, when the standby mode signal obtained by the selector is 0, the gate signal generating unit 53A selects the U-phase voltage command value V through the selector. u_ref , so the output U phase voltage command value V u_ref . On the other hand, when the standby mode signal obtained by the selector is 1, the gate signal generating unit 53A selects the U-phase voltage command value of 0 (zero) through the selector, and thus outputs the U-phase voltage command value of 0 (zero). Therefore, when the power converter 30 is in the standby mode, the standby mode signal is 1, so the voltage command value of 0 (zero) is definitely selected by the selector, and the voltage command value of 0 (zero) is definitely output from the selector. In addition, the selector (multiplexer) is a circuit that selects any one signal (voltage command value) from a plurality of input signals (voltage command values) according to the value of the control signal (standby mode signal) and outputs it.

[0207] In step S32, the gate signal generating unit 53A obtains the U-phase voltage command value V outputted from the selector in the process of step S31. u_ref Or the voltage command value (x) of 0 (zero). In addition, the gate signal generating unit 53A obtains the DC voltage V detected by the DC voltage sensor 25. dc The gate signal generation unit 53 then divides the obtained value (x) by the obtained value (y) (x / y) to obtain the U-phase modulated wave D u , output the obtained U phase modulation wave D u Here, when the value (x) output from the selector in the process of step S31 is a voltage command value of 0 (zero), the value (x / y) obtained must also be 0. Therefore, in this case, in the process of step S32, the U-phase modulated wave Du The output must be 0.

[0208] In step S33a, the gate signal generating unit 53A uses a comparator to compare the U-phase modulated wave D outputted in the process of step S32. u The gate signal generating unit 53 compares the triangular wave carrier wave CA1 generated by the carrier generator. u When it is greater than the triangular wave carrier CA1, it outputs a 1 signal. u When it is less than the triangular wave carrier CA1, it outputs a 0 signal.

[0209] Here, when the power converter 30 is in the standby mode and the standby mode signal is 1, the value (x) output from the selector in the process of step S31 is definitely a voltage command value of 0 (zero), and the U-phase modulated wave D output in the process of step S32 is u The value of must also be 0. As mentioned above, the triangular wave carrier CA1 is a triangular wave signal that changes between 0 and 1 in a certain carrier cycle. Therefore, in the U phase modulation wave D u When the value of is 0, the U phase modulation wave D u Therefore, when the power converter 30 is in the standby mode and the standby mode signal is 1, the U-phase modulation wave D u is definitely smaller than the triangular wave carrier CA1, and therefore, in this case, in the process of step S33a, a signal of 0 is definitely output from the comparator.

[0210] In step S33b, the gate signal generating unit 53A uses a comparator to compare the U-phase modulated wave D outputted in the process of step S32. u The gate signal generating unit 53 compares the triangular wave carrier wave CA2 generated by the carrier generator. u When it is greater than the triangular wave carrier CA2, it outputs a 1 signal. u When it is less than the triangular wave carrier CA2, it outputs a 0 signal.

[0211] Here, when the power converter 30 is in the standby mode and the standby mode signal is 1, as described above, the U-phase modulated wave D output in the process of step S32 is u The value of must also be 0. As mentioned above, the triangular wave carrier CA2 is a triangular wave signal that changes between -1 and 0 in a certain carrier cycle. Therefore, in the U phase modulation wave D u When the value of is 0, the U phase modulation wave D u Therefore, when the power converter 30 is in the standby mode and the standby mode signal is 1, the U-phase modulation wave D uIt is definitely greater than the triangular wave carrier CA2, and therefore, in this case, in the process of step S33b, a signal of 1 is definitely output from the comparator.

[0212] The processing of steps S34a to S35d is Fig.15 The processes of steps S27a to S28d shown are the same or similar, and therefore description thereof is omitted.

[0213] Above, in Fig.16 In the process of the second embodiment shown in FIG. Fig.14 and Fig.15 The processing of the first embodiment and its modified example shown is the same, and when the power converter 30 is in the standby mode, the standby mode signal is 1 and the gate blocking signal is 0. Therefore, for example, in the U phase, in the AND circuit of steps S35a and S35d, 0 is output as the gate signals gu1 and gu4. On the other hand, in the AND circuit of steps S35b and S35c, 1 is output as the gate signals gu3 and gu2.

[0214] Therefore, in Fig.16 In the process shown, Fig.14 and Fig.15 The processing shown is the same. When the power converter 30 is in the standby mode, the standby mode signal is 1, so the semiconductor elements 1 and 4 of each phase are definitely turned off, and the semiconductor elements (neutral point elements) 2 and 3 of each phase are definitely turned on. In addition, when the standby mode signal is 0 (power generation mode), the gate blocking signal is also 0, and the AND circuits of steps S35a to S35d output the same values ​​as the values ​​output from the dead time generator as gate signals gu1, gu3, gu2, and gu4, respectively.

[0215] <Effects of the Second Embodiment>

[0216] Above, according to Fig.16 The second embodiment shown in FIG. Figure 1 to Figure 15 The same functions and effects as those of the first embodiment and its modified examples are shown.

[0217] That is, according to Fig.16 In the second embodiment shown, when the power converter 30 is in the standby mode, a voltage command of 0 (zero) is applied, and gate signals gu3 and gu2 generated based on a voltage command value that outputs a voltage substantially equal to the DC neutral point C to the AC side are output. Thus, it is possible to suppress the semiconductor elements 1 to 4 of the power converter 30 from being destroyed by overvoltage due to a lightning surge, and it is possible to protect the neutral point elements 2 and 3 from being destroyed by overvoltage due to a lightning surge.

[0218] <Third Embodiment>

[0219] Fig.17FIG. 2 is a diagram showing an example of a control configuration of a voltage command generating unit 52B of a control unit 50B according to the third embodiment. Fig.17 and the following Fig.18 In the third embodiment shown, Figures 1 to 16 The same or similar configurations or processes in the first to second embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted or simplified.

[0220] In the third embodiment, in addition to Fig.17 The voltage command generating unit 52B of the control unit 50B shown in the figure and the voltage command generating unit 52B described later Fig.18 Except for the control structure of the gate signal generating unit 53B of the control unit 50B shown in FIG. 1 , the other structures and controls are the same as those of FIG. Figure 1 to Figure 14 That is, although the illustration is omitted, in the third embodiment, instead of Figure 2 The control unit 50 of the first embodiment shown in FIG. 1 is replaced with a control unit 50B. Figure 2 The voltage command generating unit 52 of the control unit 50 of the first embodiment shown in FIG. 1 includes a voltage command generating unit 52B, and a gate signal generating unit 53B instead of the gate signal generating unit 53. In the following description, Fig.13 The description is the same as that of , and the control common to each phase is described by taking the control of phase U as an example.

[0221] In step S41, the voltage command generating unit 52B obtains a predetermined output power command value P _ref , based on the obtained output power command value P _ref Output U phase current command value I u_ref .

[0222] In step S42, the voltage command generating unit 52B generates the U-phase current command value I outputted in the process of step S41. u_ref The U-phase current command value I of 0 (zero) and the standby mode signal are obtained by the selector. Then, the voltage command generating unit 52B selects the U-phase current command value I of 0 (zero) through the selector according to whether the standby mode signal obtained by the selector is 0 or 1. u_ref and 0 (zero), and outputs the selected current command value.

[0223] That is, Fig.17 As shown in step S42, when the standby mode signal obtained by the selector is 0, the voltage command generating unit 52B selects the U-phase current command value I through the selector. u_ref , so the output U phase current command value I u_refOn the other hand, when the standby mode signal obtained by the selector is 1, the voltage command generating unit 52B selects the U-phase current command value of 0 (zero) through the selector, and thus outputs the U-phase current command value of 0 (zero). Therefore, when the power converter 30 is in the standby mode, the standby mode signal is 1, and therefore, the current command value of 0 (zero) is definitely selected by the selector, and the current command value of 0 (zero) is definitely output from the selector.

[0224] In step S43, the voltage command generating unit 52B obtains the U-phase current command value I outputted in the process of step S42. u_ref Or the U-phase current command value of 0 (zero). In addition, the voltage command generating unit 52B is obtained, for example, via the acquiring unit 41 (see Figure 2 ) is obtained by the AC current sensor (refer to Figure 1 ) The detected AC current I of phase U u (U phase current measured value I u Then, the voltage command generating unit 52B generates a voltage command value I of the U-phase current command value I obtained. u_ref Or the U-phase current command value of 0 (zero) minus the obtained U-phase current measurement value I u , output the subtracted value.

[0225] In step S44, the voltage command generating unit 52B performs proportional control based on the value output in the process of step S43 and the proportional control gain Kp, and changes the U-phase voltage command value V obtained by the proportional control to u_ref Output to the gate signal generating unit 53B (refer to Fig.18 ).

[0226] In addition, the voltage command generating unit 52B obtains the V-phase voltage command value V in the same manner as the U-phase in steps S41 to S44. V_ref And the V phase voltage command value V w_ref , the obtained V phase voltage command value V V_ref The V phase voltage command value V w_ref Output to the gate signal generating unit 53B.

[0227] Fig.18 FIG. 5 is a diagram showing an example of a control structure of a gate signal generating unit 53B of a control unit 50B according to the third embodiment. Fig.14 The description is the same as that of , and the control common to each phase is described by taking the control of phase U as an example.

[0228] The processing of steps S51 to S53d is Fig.14 The processes of steps S21 to S23d shown are the same or similar, and therefore description thereof is omitted.

[0229] In steps S54a to S54d, the gate signal generating unit 53B obtains the value of the signal output in the process of steps S53a to S53d and the negative logic (NOT) value of the gate blocking signal. Then, the gate signal generating unit 53B outputs gate signals gu1, gu3, gu2, and gu4 respectively based on the AND operation (AND) of the value of the signal output in the process of steps S53a to S53d and the negative logic (NOT) value of the gate blocking signal.

[0230] In addition, the gate signal generating unit 53 also performs the processing shown in the above steps S51 to S55d in the V phase and the W phase in the same manner as in the U phase, and outputs the gate signals gv1 to gv4 and the gate signals gw1 to gw4 for controlling the operation of the semiconductor elements 1 to 4.

[0231] In addition, by Fig.18 The processing performed by the gate signal generating unit 53B shown is the same as the processing generally performed in the control of a normal power converter, except that the gate cutoff signal is also 0 in the standby mode.

[0232] Above, in Fig.17 and Fig.18 In the process shown in the figure, in the standby mode, the AC side (AC input / output unit 32 (refer to Figure 3 , 4 )) is output to the power converter 30 by generating a gate signal with a voltage command value such that the output current of each phase of the AC side of the power converter 30 is approximately 0 (regarded as 0). In addition, in the output current control method generally used in the three-level power converter, the voltage command value such that the output current of each phase of the AC side of the power converter 30 is approximately 0 can be achieved by applying a voltage command of 0 (zero). That is, in order to make the current 0 when the AC switch 24 is turned off (disconnected), it is sufficient to set the voltage to 0. In other words, in order to maintain the current at 0, the voltage command value itself is made approximately 0, and the voltage is made 0.

[0233] exist Fig.17 In the process shown, when the standby mode signal is 1, the U-phase current command value output in the process of step S42 is 0 (zero), and as a result, the U-phase current measured value I is subtracted in the process of step S43. u The value of is also stabilized to be approximately 0. As a result, the voltage command value V output in the process of step S44 is u_ref The value of is also roughly stable at 0. Therefore, Fig.18 The illustrated gate signal generating unit 53B outputs a gate signal generated based on a voltage command value such that the output current of each phase on the AC side of the power converter 30 becomes substantially zero to the power converter 30 in the standby mode.

[0234] Above, in Fig.17 and Fig.18 In the processing of the third embodiment shown in FIG. Figure 13 to Figure 16 The processing of the first embodiment to the second embodiment shown is the same, and when the power converter 30 is in the standby mode, the standby mode signal is 1 and the gate blocking signal is 0. Therefore, for example, in the U phase, in the AND circuits of steps S54a and S54d, 0 is output as the gate signals gu1 and gu4. On the other hand, in the AND circuits of steps S54b and S54c, 1 is output as the gate signals gu3 and gu2. In addition, when the standby mode signal is 0 (power generation mode), the gate blocking signal is also 0, and the AND circuits of steps S54a to S54d output the same values ​​as the values ​​output from the dead time generator as the gate signals gu1, gu3, gu2, and gu4, respectively.

[0235] <Effects of the Third Embodiment>

[0236] Above, according to Fig.17 and Fig.18 The third embodiment shown in FIG. Figures 1 to 16 The same effects as those of the first and second embodiments shown in the drawings can be achieved. Fig.17 and Fig.18 In the third embodiment shown, a voltage command of 0 (zero) is applied in the standby mode, thereby outputting gate signals gu3 and gu2 generated based on a voltage command value such that the output current of each phase on the AC side of the power converter 30 is 0. As a result, it is also possible to suppress the semiconductor elements 1 to 4 of the power converter 30 from being destroyed by overvoltage due to lightning surge, and it is possible to protect the neutral point elements 2 and 3 from being destroyed by overvoltage due to lightning surge.

[0237] In addition, Fig.16 In the second embodiment shown in FIG. 1 , the voltage command value itself is directly set to 0, and gate signals gu3 and gu2 generated based on the voltage command value that outputs a voltage equal to the DC neutral point C to the AC side are output. Fig.17 and Fig.18 In the third embodiment shown in the figure, the voltage command value itself is not directly changed, but the current command value is set to 0, resulting in the voltage command value being 0, which has the same effect as Fig.16 The same effects as those of the second embodiment shown are achieved.

[0238] <Fourth Implementation Method>

[0239] Fig.19 FIG. 4 is a diagram showing an example of a control configuration of a voltage command generating unit 52C of a control unit 50C according to the fourth embodiment. Fig.19 and the following Fig. 20 In the fourth embodiment shown in FIG. Figures 1 to 18 The same or similar configurations or processes in the first to third embodiments are denoted by the same reference numerals, and detailed descriptions thereof are omitted or simplified.

[0240] In addition, in the fourth embodiment, in addition to Fig.19 The voltage command generating unit 52C of the control unit 50C shown in the figure and the voltage command generating unit 52C described later Fig. 20 Except for the control structure of the gate signal generating unit 53C of the control unit 50C shown in FIG. 1 , the other structures and controls are the same as those of FIG. Figure 1 to Figure 14 That is, although the illustration is omitted, in the fourth embodiment, instead of Figure 2 The control unit 50 of the first embodiment shown in FIG. 1 is replaced with a control unit 50C. Figure 2 The voltage command generating unit 52 of the control unit 50 of the first embodiment shown in FIG. 1 includes a voltage command generating unit 52C, and a gate signal generating unit 53C instead of the gate signal generating unit 53. In the following description, Fig.13 The description is the same as that of , and the control common to each phase is described by taking the control of phase U as an example.

[0241] The processing of steps S61 to S63 is Fig.13 The processing of steps S11 to S13 shown in the figure is the same or similar, so the description is omitted. Fig.19 The processing performed by the voltage command generating unit 52C shown in FIG. Fig.13 The processing performed by the voltage command generating unit 52 described above is the same as that performed generally in the control of a normal power converter.

[0242] Fig. 20 FIG. 5 is a diagram showing an example of a control structure of a gate signal generating unit 53C of a control unit 50C according to the fourth embodiment. Fig.14 The description is the same as that of , and the control common to each phase is described by taking the control of phase U as an example.

[0243] The processing of steps S71 to S74d is Fig.18 The processing of steps S51 to S54d shown in the figure is the same or similar, so the description is omitted. Fig. 20 The processing performed by the gate signal generating unit 53C shown is similar to that performed by Fig.18 The processing performed by the gate signal generating unit 53B described in , is the same as the processing generally performed in the control of a normal power converter except that the gate cutoff signal is also 0 in the standby mode.

[0244] Above, in Fig.19 and Fig. 20In the processing of the fourth embodiment shown in FIG. 1 , a general control method is performed as described above. However, generally, when the power converter does not need to be operated, the control device stops all gate signals when the AC switch 24 is turned off or in standby mode. On the other hand, Fig.19 and Fig. 20 In the processing of the fourth embodiment shown, when the AC switch 24 is open or in standby mode (standby state), the control device 40 outputs a gate signal generated based on an arbitrary voltage command value or an arbitrary current command value to the power converter 30, just as in the operating state.

[0245] <Function and Effect of the Fourth Embodiment>

[0246] Above, according to Fig.19 and Fig. 20 The fourth embodiment shown in FIG. Figures 1 to 18 The same effects as those of the first to third embodiments shown in the drawings can be achieved. Fig.19 and Fig. 20 The fourth embodiment shown can also suppress the semiconductor elements 1 to 4 of the power converter 30 from being destroyed by overvoltage due to a lightning surge, and can protect the neutral point elements 2 and 3 from being destroyed by overvoltage due to a lightning surge.

[0247] That is, in a general control method, when the AC switch 24 is open or in standby mode (standby state), as long as the power converter 30 is driven according to a certain voltage command value (current command value), one or both of the neutral point elements 2 and 3 will be turned on. Fig.19 and Fig. 20 In the fourth embodiment shown, when the AC switch 24 is open or in the standby mode (standby state), the power converter 30 is driven in the same manner as in the operating state. Fig.19 and Fig. 20 The fourth embodiment shown can also play a role in Figures 1 to 18 The same functions and effects as those of the first to third embodiments shown above are achieved.

[0248] In addition, Fig.19 and Fig. 20 In the fourth embodiment shown, when the gate signal is output to the power converter 30 in the standby state with the AC switch 24 open, the so-called voltage matching operation is performed. In this case, the neutral point elements 2 and 3 are repeatedly turned on and off, so the power consumption for driving the gate increases compared to the case where the neutral point elements 2 and 3 are not turned on and off. In addition, there is an AC capacitor 23 (see Figure 1), an excess current flows through the AC capacitor, and therefore, compared with a case where no current flows through the AC capacitor 23, the life of the AC capacitor 23 is shortened.

[0249] On the other hand, according to Figure 16 to Figure 18 The second and third embodiments shown in the figure output a voltage command value of 0 (zero) or a voltage command value close to 0 (zero). Therefore, although it depends on the control method, the neutral point elements 2 and 3 are always in the on state, and the other semiconductor elements 1 and 4 are always in the off state. In this case, the neutral point elements 2 and 3 are not repeatedly turned on / off, so compared with the case where the neutral point elements 2 and 3 are repeatedly turned on / off, the power consumption for driving the gate can be reduced. In addition, there is an AC capacitor 23 (see Figure 1 ), no current flows through the AC capacitor 23, and therefore, the life of the AC capacitor 23 becomes longer than when a voltage such that a current flows is applied to the AC capacitor 23. Assuming that the voltage command value becomes a value other than 0 (zero) due to noise in current measurement, etc., and the neutral point element is turned on / off to flow current, the current flowing is small, and therefore, the life of the AC capacitor 23 becomes relatively long.

[0250] Therefore, from the perspective of power consumption and the life of the AC capacitor 23, Fig.19 and Fig. 20 Compared with the fourth embodiment shown in the figure, the power consumption is small and the life of the AC capacitor 23 is long. Figure 16 to Figure 18 The second and third embodiments shown are more preferable. However, from the perspective of protecting the semiconductor elements 1 to 4 (neutral point elements 2 and 3) from overvoltage damage caused by lightning surge, Fig.19 and Fig. 20 The fourth embodiment shown, Figure 16 to Figure 18 The second embodiment and the third embodiment shown above both have the same operational effects.

[0251] <Hardware Configuration Example>

[0252] Fig.21 Yes means Figures 1 to 20 A conceptual diagram of a hardware configuration example of a processing circuit 90 included in the control device 40 of the embodiment shown. The above-mentioned functions are implemented by the processing circuit 90. In one embodiment, the processing circuit 90 includes at least one processor 91 and at least one memory 92. In another embodiment, the processing circuit 90 includes at least one dedicated hardware 93.

[0253] When the processing circuit 90 includes a processor 91 and a memory 92, each function is implemented by software, firmware, or a combination of software and firmware. At least one of the software and firmware is described as a program. At least one of the software and firmware is stored in the memory 92. The processor 91 reads out the program stored in the memory 92 and executes it, thereby implementing each function.

[0254] When the processing circuit 90 is provided with dedicated hardware 93 , the processing circuit 90 is, for example, a single circuit, a complex circuit, a programmed processor, or a combination thereof. Each function is implemented by the processing circuit 90 .

[0255] Each function of the control device 40 may be partially or entirely constituted by hardware, or may be constituted as a program executed by a processor. That is, the control device 40 may also be implemented by a computer and a program, and the program may be stored in a storage medium or provided via a network.

[0256] <Supplementary matters regarding implementation>

[0257] Above, according to Figure 1 to Figure 21 The embodiment shown is divided into Figure 1 to Figure 15 The first embodiment and its modified examples shown, Fig.16 The second embodiment shown, Fig.17 and Fig.18 The third embodiment shown, and Fig.19 and Fig. 20 The fourth embodiment shown. However, any one or more of these embodiments may be combined in series or in parallel. The combined embodiment can also achieve the same effects as the effects achieved by the embodiments before the combination.

[0258] In addition, Figure 1 to Figure 21 In the embodiment shown, Fig.12 In the flowchart shown in FIG. 1 , the control unit 50 controls the DC voltage V dc The determination of sunrise and sunset is performed to change the state of the operation mode of the power converter 30. However, the present invention is not limited to this. The control unit 50 may also replace the DC voltage V dc , and based on the value, time or moment of the DC current, the state transition of the operation mode of the power converter 30 is performed. In this case, although not shown in the figure, the power conversion system 20 may also include a DC current sensor, a timer or a clock. In this case, the control unit 50 may also perform the state transition of the operation mode of the power converter 30 in steps S2 and S5 based on the value, time or moment of the DC current obtained from the DC current sensor, timer or clock. This can also play a role in Figure 1 to Figure 21 The same effects as those of the embodiments shown.

[0259] In addition, Figure 1 to Figure 21 In the illustrated embodiment, when the operation mode of the power converter 30 is the standby mode, the control units 50 to 50C apply a gate signal that causes one or both of the series-connected neutral point elements 2 and 3 to be in the on state. Furthermore, when the operation mode of the power converter 30 is the standby mode, the control units 50 to 50C apply a gate signal that causes the semiconductor elements 1 and 4 other than the neutral point elements 2 and 3 to be in the off state. However, this is not limited to this, and the control units 50 to 50C may apply a gate signal as described above only when it is determined that the AC switch 24 is in the off (disconnected) state, regardless of whether the operation mode of the power converter 30 is the standby mode or the power generation mode. This can also play a role in Figure 1 to Figure 21 The same effects as those of the embodiments shown.

[0260] In addition, Figure 1 to Figure 21 In the embodiment shown, the AC side of the power converter 30 (AC input / output unit 32 (refer to Figure 3 , 4 )) is connected to the AC power system 15 as an example. However, it is not limited to this, and the AC side of the power converter 30 may also be connected to a motor, a generator, or an AC load. Figure 1 to Figure 21 The same effects as those of the embodiments shown.

[0261] In addition, according to Figure 1 to Figure 21 The embodiment shown can suppress the semiconductor elements 1 to 4 of the power converter 30 from being damaged by overvoltage due to lightning surge, and can protect the neutral point elements 2 and 3 from being damaged by overvoltage due to lightning surge. However, this effect is not limited to the lightning surge. Figure 1 to Figure 21 The embodiment shown has the same effect when the ground potential of the DC side or AC side of the power converter 30 changes greatly due to a switching surge, an accident of other peripheral circuits, etc., in addition to a lightning surge. Therefore, the present application can be applied to a switching surge, an accident of other peripheral circuits, etc., in addition to a lightning surge.

[0262] In addition, according to Figure 1 to Figure 21 The embodiment shown is described as one mode disclosed in the present application, taking the power conversion system 20 and the control device 40 (control units 50 to 50C) thereof as an example, but is not limited thereto. The present application can also be implemented as a control method for performing the processing steps of each unit of the control device 40 (control units 50 to 50C).

[0263] Furthermore, the present disclosure may be realized as a control program that causes a computer to execute the processing procedures of each unit of the control device 40 (control units 50 to 50C).

[0264] In addition, the present disclosure may also be implemented as a storage medium (non-temporary computer-readable storage medium) storing a control program. The control program can be stored in a removable medium such as a CD (Compact Disc), a DVD (Digital Versatile Disc), or a USB (UnIversal Serial Bus) memory for distribution. In addition, the control program can be uploaded to the network via a network interface (not shown) of the control device 40, or downloaded from the network and stored in the storage unit 43, the memory 92, or the like.

[0265] Through the above detailed description, the characteristic points and advantages of the embodiment become clear. This means that the scope of the patent claim involves the characteristic points and advantages of the above-mentioned embodiment within the scope of its spirit and scope of rights. In addition, as long as it is a person with common knowledge in the technical field, it should be easy to think of all improvements and changes. Therefore, it is not intended to limit the scope of the inventive embodiment to the above situation, and it is also possible to include appropriate improvements and equivalents within the scope disclosed in the embodiment.

[0266] Explanation of symbols:

[0267] 1: power semiconductor element (first semiconductor switch element, semiconductor switch element, semiconductor element, element); 2: power semiconductor element (second semiconductor switch element, neutral point element, semiconductor switch element, semiconductor element, element); 3: power semiconductor element (third semiconductor switch element, neutral point element, semiconductor switch element, semiconductor element, element); 4: power semiconductor element (fourth semiconductor switch element, semiconductor switch element, semiconductor element, element); 11: solar cell (DC power supply); 12: DC cable; 13: AC cable; 14: transformer 15: AC power system (power system); 20: multi-level power conversion system (power conversion system); 21: DC switch; 22: AC reactor; 23: AC capacitor; 24: AC switch; 25: DC voltage sensor; 26: AC current sensor; 30: multi-level power converter (power converter); 31: DC input and output unit; 32: AC input and output unit; 33: radiator; 40: control device; 41: acquisition unit; 42: output unit; 43: storage unit; 45: system bus (bus); 50, 50A, 50B, 50C: Control unit; 51: action control unit; 52, 52B, 52C: voltage command generating unit; 53, 53', 53A, 53B, 53C: gate signal generating unit; 90: processing circuit; 91: processor; 92: memory; 93: hardware; 101: semiconductor switch element; 102: semiconductor switch element (neutral point element); 103: semiconductor switch element (neutral point element); 104: semiconductor switch element; 130: multi-level power converter (power converter); 201: semiconductor switch element; 202: semiconductor switch element (neutral point element); 203: semiconductor switch element (neutral point element); 204: semiconductor switch element; 230: multi-level power converter (power converter); 301: semiconductor switch element; 302: semiconductor switch element (neutral point element); 303: semiconductor switch element (neutral point element); 304: semiconductor switch element; 330: multi-level power converter (power converter); A: power semiconductor module; AC: AC terminal (AC terminal); B: power semiconductor module; C: DC neutral point; C1-C4: parasitic capacitance; CA1, CA2: triangular wave carrier; C AC , C NC : parasitic capacitance; C N , C P : DC capacitor; D: modulation wave; D1~D4: reflux diode (anti-parallel diode, diode); D u : U phase modulation wave; D v : V phase modulation wave; D w: W phase modulation wave; GND: ground potential; g, gu1~gu4, gv1~gv4, gw1~gw4: gate signal; I u : AC current value (AC current, current, U-phase current measurement value); I v : AC current value (AC current, current, V-phase current measurement value); I w : AC current value (AC current, current, W-phase current measurement value); I u_ref : U phase current command value (current command value); I v_ref : V-phase current command value (current command value); I w_ref : W-phase current command value (current command value); Kp: proportional control gain; N: negative terminal (N terminal); NC: non-connected terminal (NC terminal); P: positive terminal (P terminal); P _ref : Output power command value; V _ref : Voltage command value; V2, V3: voltage; V dc : DC voltage value (DC voltage, voltage); V LS : Charging voltage; V NC : voltage; V u_ref : U phase voltage command value (voltage command value); V V_ref : V phase voltage command value (voltage command value); V w_ref : W-phase voltage command value (voltage command value).

Claims

1. A multi-level power conversion system, characterized in that: A multi-level power converter and a control device are provided. The multi-level power converter has: A DC input and output unit having a positive terminal and a negative terminal connected to a DC power source or a DC load; A plurality of DC capacitors are connected in series between the positive terminal and the negative terminal via a DC neutral point; An AC input and output unit having AC terminals connected to an AC power source or an AC load; The first semiconductor switch element and the fourth semiconductor switch element are connected in series with the same polarity between the positive terminal and the negative terminal via the AC terminal; A first return diode and a fourth return diode are connected in reverse parallel to the first semiconductor switch element and the fourth semiconductor switch element, respectively; The third semiconductor switch element and the second semiconductor switch element are connected in series with opposite polarities between the DC neutral point and the AC terminal; as well as The third return diode and the second return diode are connected in anti-parallel to the third semiconductor switch element and the second semiconductor switch element, respectively. The control device has: an operation control unit that, based on a predetermined condition, causes the operation mode of the multilevel power converter to shift to a standby mode in which power conversion is not performed between the DC input / output unit and the AC input / output unit; as well as The gate signal generating unit generates and outputs a gate signal for turning on or switching at least one of the third semiconductor switch element and the second semiconductor switch element in the standby mode.

2. The multi-level power conversion system according to claim 1, characterized in that: The multilevel power conversion system further comprises an AC switch connected between the AC input / output unit of the multilevel power converter and the AC power source or the AC load. The gate signal generating unit generates and outputs a gate signal for turning on or switching at least one of the third semiconductor switch element and the second semiconductor switch element when the AC switch is turned off and in the standby mode.

3. The multi-level power conversion system according to claim 1, characterized in that: The gate signal generating unit generates and outputs a gate signal for placing both the first semiconductor switch element and the fourth semiconductor switch element in a non-conductive state when in the standby mode.

4. The multi-level power conversion system according to claim 1, characterized in that: The gate signal generating unit generates and outputs a gate signal for operating the multilevel power converter based on a zero voltage command value for causing the AC input / output unit to output a voltage substantially equal to the DC neutral point when in the standby mode.

5. The multi-level power conversion system according to claim 1, characterized in that: The control device further comprises a voltage command generating unit, The voltage command generating unit generates a voltage command value based on a zero current command value for causing the AC input / output unit of the multilevel power converter to output a current of substantially zero when in the standby mode. The gate signal generating unit generates and outputs a gate signal for operating the multilevel power converter based on the voltage command value generated by the voltage command generating unit.

6. A control device for a multi-level power conversion system, characterized in that: The multilevel power conversion system comprises a multilevel power converter. The multi-level power converter has: A DC input and output unit having a positive terminal and a negative terminal connected to a DC power source or a DC load; A plurality of DC capacitors are connected in series between the positive terminal and the negative terminal via a DC neutral point; An AC input and output unit having AC terminals connected to an AC power source or an AC load; The first semiconductor switch element and the fourth semiconductor switch element are connected in series with the same polarity between the positive terminal and the negative terminal via the AC terminal; A first return diode and a fourth return diode are connected in reverse parallel to the first semiconductor switch element and the fourth semiconductor switch element, respectively; The third semiconductor switch element and the second semiconductor switch element are connected in series with opposite polarities between the DC neutral point and the AC terminal; as well as The third return diode and the second return diode are connected in anti-parallel to the third semiconductor switch element and the second semiconductor switch element, respectively. The control device has: an operation control unit that, based on a predetermined condition, causes the operation mode of the multilevel power converter to shift to a standby mode in which power conversion is not performed between the DC input / output unit and the AC input / output unit; as well as The gate signal generating unit generates and outputs a gate signal for turning on or switching at least one of the third semiconductor switch element and the second semiconductor switch element in the standby mode.

Images