Three-dimensional memory device including integrated

Abstract

A semiconductor structure includes: an alternating stack of insulating layers and conductive layers; a memory opening extending vertically through the alternating stack; a memory opening fill structure including a vertical channel and a memory element positioned in the memory opening; a contact through-hole cavity, the contact through-hole cavity extending vertically through the alternating stack; and an integrated contact and support assembly positioned in the contact through hole cavity. The integrated contact and support assembly includes a dielectric support pillar and a conductive layer contact via structure that electrically contacts a top surface of a first of the conductive layers surrounding the contact via cavity. A dielectric spacer is positioned in the contact via cavity, covers sidewalls of the first conductive layer in the contact via cavity, and extends over the top surface of the first conductive layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 18 / 351,828, entitled “THREE-DIMENSIONAL MEMORY DEVICE CONTAININGINTEGRATED CONTACT-AND-SUPPORT ASSEMBLIES AND METHODS OF MAKING THE SAME,” filed in the U.S. Patent and Trademark Office on July 13, 2023, and is hereby incorporated by reference in its entirety for all purposes, and claims priority to U.S. Provisional Application No. 63 / 476,448, filed on December 21, 2022. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to three-dimensional memory devices including integrated contact and support components and methods of manufacturing the same. Background Art

[0004] Three-dimensional vertical NAND strings with one bit per cell are disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor structure includes: an alternating stack of insulating layers and conductive layers; a memory opening extending vertically through the alternating stack; a memory opening filling structure including a vertical channel and a memory element positioned in the memory opening; a contact through-hole cavity extending vertically through the alternating stack; and an integrated contact and support assembly positioned in the contact through-hole cavity. The integrated contact and support assembly includes a dielectric support column and a conductive layer contact through-hole structure, the conductive layer contact through-hole structure electrically contacting the top surface of a first conductive layer in the conductive layer surrounding the contact through-hole cavity. A dielectric spacer is positioned in the contact through-hole cavity, covers the sidewalls of the first conductive layer in the contact through-hole cavity, and extends above the top surface of the first conductive layer.

[0006] According to another aspect of the present disclosure, a method for forming a semiconductor structure includes: forming an alternating stack of insulating layers and sacrificial material layers; forming a memory stack structure through the alternating stack, wherein each memory stack structure in the memory stack structure includes a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements formed at the level of the sacrificial material layer; forming a stepped through-hole cavity through the alternating stack so that an annular surface of a first sacrificial material layer in the sacrificial material layer surrounding the stepped through-hole cavity is physically exposed; forming a sacrificial annular plate by selectively growing a sacrificial plate material from the physically exposed annular surface of the first sacrificial material layer; replacing the sacrificial material layer with a conductive layer and replacing the sacrificial annular plate with a conductive annular pad positioned on the first conductive layer; and forming a conductive layer contact through-hole structure contacting the conductive annular pad.

[0007] According to another aspect of the present disclosure, a method for forming a semiconductor structure includes: forming an alternating stack of insulating layers and sacrificial material layers; forming a memory stack structure through the alternating stack, wherein each memory stack structure in the memory stack structure includes a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements formed at the level of the sacrificial material layer; forming a stepped surface by patterning the alternating stack; forming an insulating spacer on a vertically extending surface segment of the stepped surface; forming an etch stop layer above the insulating spacer and the horizontal surface segment of the stepped surface; forming a backward-facing etching stop layer above the etch stop layer; A stepped dielectric material portion; forming a via cavity through the backward stepped dielectric material portion, the etch stop layer and the alternating stack; isotropically expanding the via cavity by selectively recessing the backward stepped dielectric material portion and the insulating layer relative to the sacrificial material layer to form a fin-shaped via cavity; conformally depositing a dielectric material at a peripheral portion of the fin-shaped via cavity; anisotropically etching the dielectric material to form a stepped via cavity, wherein the remainder of the dielectric material includes a fin-shaped dielectric support column; replacing the sacrificial material layer with a conductive layer; and forming a conductive layer contact via structure that contacts the top surface of a first conductive layer in the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a vertical cross-sectional view of the first exemplary structure after forming a semiconductor device, a lower level dielectric layer, a lower level metal interconnect structure, and a source level material layer in process according to the first embodiment of the present disclosure.

[0009] Figure 1B yes Figure 1A A top view of the first exemplary structure of FIG. The vertical plane A-A' is Figure 1A A plane of a vertical section.

[0010] Figure 1C It is along Figure 1B A vertical cross-sectional view of the first exemplary structure along a vertical plane CC'.

[0011] Figure 2 is a vertical cross-sectional view of the first exemplary structure after forming a first vertical alternating sequence of first insulating layers and first spacer material layers according to the first embodiment of the present disclosure.

[0012] Figure 3 is a vertical cross-sectional view of the first exemplary structure after patterning the first stepped surface, the first backward stepped dielectric material portion, and the interlayer dielectric layer according to the first embodiment of the present disclosure.

[0013] Figure 4A is a vertical cross-sectional view of a first exemplary structure after forming a first layer memory opening according to the first embodiment of the present disclosure.

[0014] Figure 4B yes Figure 4A A top view of the first exemplary structure. The sawtooth vertical plane AA' corresponds to Figure 4A A plane of a vertical section.

[0015] Figure 5 is a vertical cross-sectional view of the first exemplary structure after forming a sacrificial memory opening filling portion according to the first embodiment of the present disclosure.

[0016] Figure 6 is a vertical cross-sectional view of the first exemplary structure after forming a second vertical alternating sequence of second insulating layers and second spacer material layers, a second stepped surface, a second backward stepped dielectric material portion, and a drain select level isolation structure according to the first embodiment of the present disclosure.

[0017] Fig. 7A is a vertical cross-sectional view of the first exemplary structure after forming a second layer memory opening according to the first embodiment of the present disclosure.

[0018] Figure 7B It is along Fig. 7A The horizontal cross-sectional view of the first exemplary structure of the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig. 7A A plane of a vertical section.

[0019] Figure 8 is a vertical cross-sectional view of the first exemplary structure after forming an inter-layer memory opening according to the first embodiment of the present disclosure.

[0020] 9A to 9D are sequential vertical cross-sectional views of inter-layer memory openings during formation of a memory opening filling structure according to a first embodiment of the present disclosure.

[0021] Fig. 10A is a vertical cross-sectional view of the first exemplary structure after forming a memory opening filling structure according to the first embodiment of the present disclosure.

[0022] Fig. 10B It is along Fig. 10A The horizontal cross-sectional view of the first exemplary structure of the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig. 10A A plane of a vertical section.

[0023] FIG. 11A to FIG. 11G are sequential vertical cross-sectional views of stepped regions of a first exemplary structure during integration of contact and support components during a forming process according to a first embodiment of the present disclosure.

[0024] Fig. 12A is a vertical cross-sectional view of the first exemplary structure after forming backside trenches according to the first embodiment of the present disclosure.

[0025] Fig. 12B It is along Fig. 12A The horizontal cross-sectional view of the first exemplary structure of the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig. 12A A plane of a vertical section.

[0026] FIG. 13A to FIG. 13E Sequential vertical cross-sectional views of regions of a first exemplary structure during formation of a source level material layer according to a first embodiment of the present disclosure are shown.

[0027] Fig.14 is a vertical cross-sectional view of the first exemplary structure after forming a source level material layer according to the first embodiment of the present disclosure.

[0028] Fig.15 is a vertical cross-sectional view of a first exemplary structure after forming a backside recess according to the first embodiment of the present disclosure.

[0029] Fig.16A is a vertical cross-sectional view of a first exemplary structure after forming a conductive layer in a backside recess according to the first embodiment of the present disclosure.

[0030] Fig. 16B It is along Fig.16A The horizontal cross-sectional view of the first exemplary structure of the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.16A A plane of a vertical section.

[0031] Fig.17 is a vertical cross-sectional view of the first exemplary structure after forming a backside trench fill structure according to the first embodiment of the present disclosure.

[0032] FIG. 18A to FIG. 18F are sequential vertical cross-sectional views of stepped regions of a first exemplary structure during formation of an integrated contact and support assembly, a drain contact via structure, and a connecting via structure according to a first embodiment of the present disclosure.

[0033] Figure 18G is a vertical cross-sectional view of a stepped region of an alternative configuration of the first exemplary structure after forming an integrated contact and support assembly, a drain contact via structure, and a connecting via structure according to the first embodiment of the present disclosure.

[0034] Fig.19A and Fig.19B are sequential vertical cross-sectional views of stepped regions of a second exemplary structure during integration of contact and support components during formation according to a second embodiment of the present disclosure.

[0035] FIG. 20A to FIG. 20E are sequential vertical cross-sectional views of a stepped region of a second exemplary structure during formation of an integrated contact and support assembly, a drain contact via structure, and a connecting via structure according to a second embodiment of the present disclosure.

[0036] FIG. 21A to FIG. 21G are sequential vertical cross-sectional views of stepped regions of a third exemplary structure during integration of contact and support components during formation according to a third embodiment of the present disclosure.

[0037] FIG. 22A to FIG. 22F are sequential vertical cross-sectional views of a stepped region of a third exemplary structure during formation of an integrated contact and support assembly, a drain contact via structure, and a connecting via structure according to a third embodiment of the present disclosure.

[0038] FIG. 23A to FIG. 23D are sequential vertical cross-sectional views of stepped regions of a fourth exemplary structure during integration of contact and support components during formation according to a fourth embodiment of the present disclosure.

[0039] FIG. 24A to FIG. 24E are sequential vertical cross-sectional views of stepped regions of a fourth exemplary structure during formation of an integrated contact and support assembly, a drain contact via structure, and a connecting via structure according to a fourth embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The present disclosure relates to a three-dimensional memory device including integrated contact and support components and a method of manufacturing the same, various aspects of which are described in detail below.

[0041] The accompanying drawings are not drawn to scale. Multiple instances of elements can be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of elements. Serial numbers such as "first", "second" and "third" are only used to identify similar elements, and different serial numbers can be used throughout the specification and claims of the present disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. As used herein, a first element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0042] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0043] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0044] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stack" element refers to an element that extends vertically through a memory level.

[0045] As used herein, "semiconductor material" refers to a semiconductor material having a -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m, and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material (i.e., providing a conductivity greater than 1.0×10 5 S / m) of a semiconductor material. A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 7 S / m in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0046] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167, entitled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory levels before bonding, but since the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. The substrate may include integrated circuits manufactured thereon, such as driver circuits for memory devices.

[0047] Various three-dimensional memory devices disclosed herein include single three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein. Single three-dimensional NAND strings are positioned in a single three-dimensional NAND string array located above a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

[0048] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded through, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0049] refer to Figures 1A to 1C, showing a first exemplary structure according to an embodiment of the present disclosure. The first exemplary structure includes a semiconductor substrate 8 and a peripheral circuit 710 formed thereon. The first exemplary structure includes: a memory array region 100, where a three-dimensional memory array will be formed subsequently; a stepped region 200, where a stepped surface of a conductive layer and a contact via structure will be formed subsequently; and a connection region 400, where a peripheral contact via structure will be formed subsequently.

[0050] A substrate such as a semiconductor substrate 8 includes a substrate semiconductor layer 9 at least at an upper portion thereof. The semiconductor substrate may include a silicon wafer, and the substrate semiconductor layer 9 may include an upper portion of a silicon wafer containing various doped wells and / or epitaxial silicon layers. A shallow trench isolation structure 720 may be formed in the upper portion of the substrate semiconductor layer 9 to provide electrical isolation between semiconductor devices. The peripheral circuit 710 includes field effect transistors, which include corresponding transistor active regions 742 (i.e., source regions and drain regions), channel regions 746, and gate structures 750. The field effect transistors may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758.

[0051] The peripheral circuit 710 may include additional semiconductor devices other than the p-type field effect transistor and the n-type field effect transistor, which may be used to control the operation of the memory structure to be formed subsequently. The peripheral circuit 710 includes a driver circuit, which is also referred to as a peripheral circuit. As used herein, a peripheral circuit refers to any one, each, or all of a word line decoder circuit, a word line switching circuit, a bit line decoder circuit, a bit line sensing and / or switching circuit, a power supply / distribution circuit, a data buffer, and / or a latch, or may be any other semiconductor circuit that may be implemented outside the memory array structure of the memory device. For example, the semiconductor device may include a word line switching device for electrically biasing the word lines of the three-dimensional memory structure to be formed subsequently.

[0052] A dielectric material layer is formed over the semiconductor device, which is referred to herein as a lower level dielectric material layer 760. The lower level dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks diffusion of mobile ions and / or applies appropriate stress to the underlying structure), a first dielectric material layer 764 overlying the dielectric liner 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier) 766 overlying the first dielectric material layer 764, and at least one second dielectric layer 768.

[0053] The dielectric layer stack (which includes the lower level dielectric material layer 760) serves as a matrix of lower level metal interconnect structures 780 that provide electrical routing between various nodes of the semiconductor device and the landing pads of the through memory level contact via structures to be formed subsequently. The lower level metal interconnect structures 780 are embedded within the dielectric layer stack of the lower level dielectric material layer 760 and include lower level metal line structures positioned below and optionally contacting the bottom surface of the silicon nitride layer 766.

[0054] For example, the lower level metal interconnect structure 780 may be embedded in the first dielectric material layer 764. The first dielectric material layer 764 may be a plurality of dielectric material layers in which various elements of the lower level metal interconnect structure 780 are sequentially embedded. Each dielectric material layer in the first dielectric material layer 764 may include any one of doped silicate glass, undoped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, and dielectric metal oxide (such as aluminum oxide). In one embodiment, the first dielectric material layer 764 may include or be substantially composed of a dielectric material layer having a dielectric constant not exceeding 3.9 of the dielectric constant of undoped silicate glass (silicon oxide). The lower level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes contacting the corresponding source and drain nodes or gate electrode contacts of the device), intermediate lower level metal line structures 784, and lower level metal via structures 786, as well as landing pads 788 for through-memory level interconnect via structures to be formed subsequently.

[0055] At least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer in at least one second dielectric material layer 768 may include any one of doped silicate glass, undoped silicate glass, and organic silicate glass. In one embodiment, at least one second dielectric material layer 768 may include or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9 of the dielectric constant of undoped silicate glass (silicon oxide).

[0056] The peripheral circuit 710 may include peripheral devices for memory level components to be formed later. The lower level metal interconnect structure 780 is embedded in the lower level dielectric layer 760. The combination of the lower level dielectric layer 760 and the lower level metal interconnect structure 780 covers the peripheral circuit 710.

[0057] The lower level metal interconnect structure 780 may be electrically connected to an active node (e.g., transistor active region 742 or gate electrode 754) of the peripheral circuit 710 (e.g., a CMOS device) and is positioned at the level of the lower level dielectric layer 760. A through memory level contact via structure may then be formed directly on the lower level metal interconnect structure 780 to provide electrical connection to a memory device to be subsequently formed.

[0058] A process source level material layer 110' including a layer stack of material layers may be formed above the lower level dielectric layer 760. The process source level material layer 110' may include various layers that are subsequently modified to form the source level material layer. The source level material layer includes a source contact layer when formed, which serves as a common source region of a vertical field effect transistor of a three-dimensional memory device. In one embodiment, the process source level material layer 110' may include, from bottom to top, a lower source level material layer 112, a lower sacrificial liner 103, a source level sacrificial layer 104, a higher sacrificial liner 105, a higher source level material layer 116, a source level insulating layer 117, and an optional source selection level conductive layer 118.

[0059] The lower source level material layer 112 and the higher source level material layer 116 may include doped semiconductor materials, such as doped polysilicon or doped amorphous silicon. The doped semiconductor material of the lower source level material layer 112 is referred to herein as a first doped semiconductor material, and the doped semiconductor material of the higher source level material layer 116 is referred to herein as a second doped semiconductor material, which may be the same as or different from the first doped semiconductor material. The conductivity type of the lower source level material layer 112 and the higher source level material layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conductivity type, the lower source level material layer 112 and the higher source level material layer 116 have a doping of a second conductivity type opposite to the first conductivity type. The thickness of each of the lower source level material layer 112 and the higher source level material layer 116 may be in the range of 10nm to 300nm, such as 20nm to 150nm, but smaller and larger thicknesses may also be used.

[0060] The source level sacrificial layer 104 includes a sacrificial material that can be selectively removed for the lower sacrificial pad 103 and the upper sacrificial pad 105. In one embodiment, the source level sacrificial layer 104 can include a dielectric material, such as silicon nitride, or a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source level sacrificial layer 104 can be in the range of 30nm to 400nm, such as 60nm to 200nm, but smaller and larger thicknesses can also be used.

[0061] The lower sacrificial liner 103 and the upper sacrificial liner 105 include materials that can be used as etch stop materials during the removal of the source level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can include silicon oxide, silicon nitride, and / or dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 can include a silicon oxide layer having a thickness in the range of 2nm to 30nm, although lesser and greater thicknesses can also be used.

[0062] The source level insulating layer 117 may include a dielectric material, such as silicon oxide. The thickness of the source level insulating layer 117 may be in the range of 20 nm to 400 nm, such as 40 nm to 200 nm, although smaller and larger thicknesses may also be used. The optional source select level conductive layer 118 may include a conductive material that may be used as a source select level gate electrode. For example, the optional source select level conductive layer 118 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon, which may subsequently be converted into doped polysilicon by an annealing process. The thickness of the optional source level conductive layer 118 may be in the range of 30 nm to 200 nm, such as 60 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0063] The source level material layer 110' can be formed directly above a subset of semiconductor devices on a semiconductor substrate 8 (e.g., a silicon wafer) during the process. As used herein, a first element is positioned "directly above" a second element if the element is positioned above a horizontal plane that includes the topmost surface of the second element and the area of ​​the element and the area of ​​the second element has an area overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the substrate 8).

[0064] The in-process source level material layer 110' may be patterned to provide openings in areas where through memory level contact via structures and through dielectric contact via structures are subsequently formed. Patterned portions of the in-process source level material layer 110' are present in each memory array region 100 where a three-dimensional memory stacked structure is subsequently formed. At least one second dielectric material layer 768 may include: a blanket layer portion that is below the in-process source level material layer 110'; and a patterned portion that fills gaps between patterned portions of the in-process source level material layer 110'.

[0065] The source level material layer 110' may be patterned in the process so that the opening extends over the step region 200 where the contact via structure for contacting the word line conductive layer is to be formed laterally. In one embodiment, the step region 200 may be laterally spaced apart from the memory array region 100 along a first horizontal direction hd1. A horizontal direction perpendicular to the first horizontal direction hd1 is referred to herein as a second horizontal direction hd2.

[0066] See also Figure 2 , subsequently forming an alternating stack of first material layers and second material layers. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. Where at least another alternating stack of material layers is subsequently formed above the alternating stack of first material layers and second material layers, the alternating stack is referred to herein as a first vertical alternating sequence. The levels of the first vertical alternating sequence are referred to herein as first level levels, and the levels of the alternating stack to be subsequently formed immediately above the first level levels are referred to herein as second level levels, and so on.

[0067] The first vertical alternating sequence may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although the present disclosure is described using an embodiment in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby eliminating the need to perform a replacement process) are clearly contemplated herein.

[0068] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. Alternating multiple first insulating layers 132 and first sacrificial material layers 142 may be formed above the source level material layer during the process. As used herein, "sacrificial material" refers to a material that is removed during subsequent processing steps.

[0069] As used herein, the alternating stacking of an element and a second element refers to a structure in which an instance of an element and an instance of a second element are alternated. Each instance of an element that is not an end element of a plurality of elements that are alternated adjoins two instances of a second element on both sides, and each instance of a second element that is not an end element of a plurality of elements that are alternated adjoins two instances of an element on both ends. The element may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. Alternating multiple first material layers and second material layers may start with an instance of a first material layer or an instance of a second material layer, and may end with an instance of a first material layer or an instance of a second material layer. In one embodiment, an instance of an element and an instance of a second element may form a unit that is periodically repeated within an alternating plurality of elements.

[0070] The first vertical alternating sequence (132, 142) may include a first insulating layer 132 composed of a first material and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0071] The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selectively to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0072] The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced by a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride.

[0073] In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0074] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 pair may be in the range of 2 to 1024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each first sacrificial material layer 142 in the first vertical alternating sequence (132, 142) may have a uniform thickness that is substantially constant within each corresponding first sacrificial material layer 142.

[0075] A first insulating capping layer 170 may then be formed over the alternating stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which may be any dielectric material that may be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the insulating capping layer 170 may be in the range of 20 nm to 300 nm, although lesser and greater thicknesses may also be employed.

[0076] refer to Figure 3 , the first insulating capping layer 170 and the first vertical alternating sequence (132, 142) may be patterned to form a first stepped surface in the stepped region 200. The stepped region 200 may include a corresponding first stepped region and a second stepped region, in which a first stepped surface is formed, and in which an additional stepped surface is subsequently formed in a second layer structure (which is subsequently formed above the first layer structure) and / or an additional layer structure. The first stepped surface may be formed, for example, by forming a mask layer having an opening therein, etching a cavity within the level of the first insulating capping layer 170 and iteratively extending the etching region, and vertically recessing the cavity by etching each first insulating layer 132 and first sacrificial material layer 142 pair directly below the bottom surface of the etching cavity positioned in the etching region. In one embodiment, the top surface of the first sacrificial material layer 142 may be physically exposed at the first stepped surface. The cavity covering the first stepped surface is referred to herein as a first stepped through-hole cavity.

[0077] A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped via cavity. Excess portions of the dielectric fill material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the dielectric fill material filling the region overlying the first stepped surface constitutes a first backward stepped dielectric material portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. The first vertical alternating sequence (132, 142) and the first backward stepped dielectric material portion 165 together constitute a first layer structure, which is a process structure that is subsequently modified.

[0078] An interlayer dielectric layer 180 may be optionally deposited over the first layer structure (132, 142, 170, 165). The interlayer dielectric layer 180 includes a dielectric material, such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may include doped silicate glass, which has a greater etching rate than the material of the first insulating layer 132 (which may include undoped silicate glass). For example, the interlayer dielectric layer 180 may include phosphosilicate glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30nm to 300nm, but smaller and larger thicknesses may also be used.

[0079] refer to Figure 4A and Figure 4B , the first layer memory opening 149 can be formed through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and partially through the in-process source level material layer 110'. For example, a photoresist layer (not shown) can be applied over the interlayer dielectric layer 180 and can be photolithographically patterned to form an opening therethrough. The pattern of the opening in the photoresist layer can be transferred through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and partially through the in-process source level material layer 110' to form the first layer memory opening 149 by a first anisotropic etching process.

[0080] The first layer memory openings 149 are formed in the memory array region 100 through each layer within the first alternating stack (132, 142) and are subsequently used to form a memory stack structure therein. The bottom surface of the first layer memory openings 149 may be a recessed surface of the source level sacrificial layer 104. Thus, each first layer memory opening 149 may have a bottom surface between a horizontal plane including the bottom surface of the source level sacrificial layer 104 and a horizontal plane including the top surface of the source level sacrificial layer 104. In one embodiment, the bottom surface of the first layer memory openings 149 may be formed within the lower source level material layer 112.

[0081] In one embodiment, the first layer memory openings 149 may be formed into clusters that are laterally spaced apart from each other along a second horizontal direction hd2. Each cluster of the first layer memory openings 149 may include a respective two-dimensional array of first layer memory openings 149 having a first pitch along one horizontal direction and a second pitch along another horizontal direction. In one embodiment, the direction of the first memory structure pitch may be a first horizontal direction (e.g., a word line direction) hd1, and the direction of the second memory structure pitch may be a second horizontal direction (e.g., a bit line direction) hd2, or vice versa.

[0082] The interlayer dielectric layer 180 may include a dielectric material (such as borosilicate glass) having a greater etching rate than the first insulating layer 132 (which may include undoped silicate glass). In one embodiment, the bottom surface of each first-level memory opening 149 may be formed between the top surface and the bottom surface of the source-level sacrificial layer 104. In this case, the surface of the source-level sacrificial layer 104 may be exposed at the bottom portion of each first-level memory opening 149. Figure 4B The positions of the steps S in the first vertical alternating sequence (132, 142) are shown in dashed lines.

[0083] refer to Figure 5 , a sacrificial first-layer memory opening filling portion 148 may be formed in the first-layer memory opening 149. For example, a sacrificial filling material is simultaneously deposited in each of the first-layer memory openings 149. The sacrificial filling material includes a material that can be selectively removed from the material of the first insulating layer 132 and the first sacrificial material layer 142.

[0084] In one embodiment, the sacrificial fill material may include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop layer (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be employed prior to depositing the sacrificial first layer of fill material. The sacrificial fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0085] In another embodiment, the sacrificial fill material may include a silicon oxide material having a higher etching rate than the materials of the first insulating layer 132, the first insulating capping layer 170, and the interlayer insulating layer 180. For example, the sacrificial fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etching rate at least 100 times higher than the etching rate of dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and then densifying in an annealing process) in 100:1 diluted hydrofluoric acid. In this case, a thin etch stop layer (such as a silicon nitride layer with a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer of fill material. The sacrificial fill material may be formed by non-conformal deposition or conformal deposition methods.

[0086] In yet another embodiment, the sacrificial fill material may include a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently selectively removed with respect to the material of the first alternating stack (132, 142).

[0087] Portions of the deposited sacrificial fill material may be removed from above the topmost layer of the first vertical alternating sequence (132, 142), such as from above the interlayer dielectric layer 180. For example, the sacrificial fill material may be recessed to the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 may be used as an etch stop layer or a planarization stop layer.

[0088] The remaining portions of the sacrificial fill material include sacrificial first layer memory opening filling portions 148. Specifically, each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial first layer memory opening filling portion 148. The top surface of the sacrificial first layer memory opening filling portion 148 may be coplanar with the top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer memory opening filling portions 148 may or may not include a cavity therein.

[0089] refer to Figure 6, a second layer structure may be formed above the first layer structure (132, 142, 170, 165, 148). The second layer structure may include an additional vertical alternating sequence of additional insulating layers and additional spacer material layers, which may be additional sacrificial material layers. The second vertical alternating sequence is also referred to as a second alternating stack. For example, a second alternating stack (232, 242) of material layers may be subsequently formed on the top surface of the first alternating stack (132, 142). The second stack (232, 242) includes a plurality of alternating third material layers and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0090] In one embodiment, the third material layer may be a second insulating layer 232, and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be a second insulating layer 232 and a second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that may be selectively removed for the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device.

[0091] In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second stack (232, 242) may include alternating multiple second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0092] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that may be used for the second insulating layer 232 may be any material that may be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that may be selectively removed with respect to the third material of the second insulating layer 232. The sacrificial material that may be used for the second sacrificial material layer 242 may be any material that may be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

[0093] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and the second sacrificial material layer 242 pair can be in the range of 2 to 1024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each second sacrificial material layer 242 in the second alternating stack (232, 242) can have a uniform thickness that is substantially constant within each corresponding second sacrificial material layer 242.

[0094] The same set of processing steps as those used to form the first stepped surface in the first stepped region may be used, while appropriately adjusting the pattern of at least one mask layer, to form a second stepped surface in the second stepped region of the stepped region 200. A second backward stepped dielectric material portion 265 may be formed over the second stepped surface in the stepped region 200.

[0095] A second insulating capping layer 270 may then be formed over the second alternating stack (232, 242) and the second backward stepped dielectric material portion 265. The second insulating capping layer 270 includes a dielectric material that is different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating capping layer 270 may include silicon oxide. In one embodiment, the first sacrificial material layer and the second sacrificial material layer (142, 242) may include silicon nitride.

[0096] Optionally, a drain selection level isolation structure 72 may be formed through the second insulating cap layer 270 and through a subset of the layers in the upper portion of the second vertical alternating sequence (232, 242). The second sacrificial material layer 242 cut by the drain selection level shallow trench isolation structure 72 corresponds to a level at which a drain selection level conductive layer is subsequently formed. The drain selection level isolation structure 72 includes a dielectric material such as silicon oxide. The drain selection level isolation structure 72 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0097] Generally speaking, at least one vertical alternating sequence of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed above the source level material layer 110' during the process, and at least one backward stepped dielectric material portion (165, 265) can be formed above the stepped region on at least one alternating stack (132, 142, 232, 242). Each of the insulating layers (132, 232) and the spacer material layers (such as sacrificial material layers (142, 242)) can be formed as a respective single continuous material layer. In this case, the insulating layers (132, 232) can be referred to as continuous insulating layers, and the spacer material layers can be referred to as continuous spacer material layers (such as continuous sacrificial material layers).

[0098] refer to Fig. 7A and Figure 7B , a second layer memory opening 249 can be formed through the second layer structure (232, 242, 265, 270, 72). A photoresist layer (not shown) can be applied over the second insulating cap layer 270 and can be photolithographically patterned to form an opening therethrough. The pattern of the opening can be the same as the pattern of the various first layer memory openings 149, which is the same as the sacrificial first layer memory opening filling portion 148. Therefore, the photolithographic mask used to pattern the first layer memory openings 149 can be used to pattern the photoresist layer. The pattern of the opening in the photoresist layer can be transferred through the second layer structure (232, 242, 265, 270, 72) to form the second layer memory opening 249 by a second anisotropic etching process.

[0099] The second layer memory opening 249 is formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening filling portions 148. Figure 7B The positions of the steps S in the first vertical alternating sequence (132, 142) and the second vertical alternating sequence (232, 242) are shown in dashed lines.

[0100] refer to Figure 8 A and Figure 8 B, the sacrificial fill material can be removed from under the second layer memory opening 249 using an etching process that selectively etches the sacrificial fill material with respect to the materials of the first and second insulating layers (132, 232), the first and second sacrificial material layers (142, 242), the first and second insulating capping layers (170, 270), and the interlayer dielectric layer 180. A memory opening 49 (also referred to as an interlayer memory opening 49) is formed in each volume from which the sacrificial first layer memory opening fill portion 148 is removed.

[0101] 9A to 9D Sequential cross-sectional views of memory openings 49 are provided during the formation of memory opening fill structures 58. The same structural changes occur in each memory opening 49. Fig.9A , showing Figure 8 A and Figure 8 The memory opening 49 in the exemplary device structure of B. The memory opening 49 extends through the first layer structure and the second layer structure.

[0102] refer to Fig. 9B , a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide.Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0103] Subsequently, the charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coinciding sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. As used herein, a first surface and a second surface "vertically coincide" if there is a second surface located above or below the first surface and if there is a vertical plane that intersects both the first surface and the second surface. Alternatively, the sacrificial material layer (142, 242) can be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 can be in the range of 2nm to 20nm, but smaller and larger thicknesses can also be used.

[0104] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be employed. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores a memory bit.

[0105] The semiconductor channel material layer 60L includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel material layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0106] refer to Fig. 9C , in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organic silicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)), or by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the second insulating cap layer 270 can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0107] refer to Fig.9D , a doped semiconductor material may be deposited in a cavity covering the dielectric core 62. The doped semiconductor material has a doping of a conductivity type opposite to the doping conductivity type of the semiconductor channel material layer 60L. Thus, the doped semiconductor material has a doping of a second conductivity type. Portions of the deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and blocking dielectric layer 52 covering the horizontal plane (which includes the top surface of the second insulating cap layer 270) may be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0108] Each remaining portion of the doped semiconductor material having the doping of the second conductivity type constitutes a drain region 63. The drain region 63 may have a doping of the second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration of the drain region 63 may be between 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3 The doped semiconductor material may be, for example, doped polysilicon.

[0109] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the backside recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0110] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunnel dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening filling structure 58. In the process, the source level material layer 110', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265, 72), the interlayer dielectric layer 180, and the memory opening filling structure 58 together constitute a memory level component.

[0111] refer to Fig. 10A and Fig. 10B , shows a first exemplary structure after forming a memory opening filling structure 58 in the memory opening 49 .

[0112] FIG. 11A to FIG. 11G are sequential vertical cross-sectional views of a stepped region of a first exemplary structure during integration of contact and support components during the formation process.

[0113] refer to Fig.11A , an optional dielectric capping layer 271 may be formed over the second insulating capping layer 270. The optional dielectric capping layer 271, if employed, includes a dielectric capping material such as undoped silicate glass or doped silicate glass.

[0114] refer to Fig. 11BA photoresist layer (not shown) may be applied over the optional dielectric cover layer 271 and the second insulating cap layer 270, and the photoresist layer may be photolithographically patterned to form openings on the horizontal surface segments of the stepped surface in the stepped region 200. In one embodiment, each of the openings in the photoresist layer may be positioned within the region of a corresponding horizontally extending surface segment within the stepped surface in the stepped region 200. The lateral dimension (such as diameter) of each opening in the photoresist layer may be in the range of 30 nm to 600 nm, such as 60 nm to 300 nm, although smaller or larger lateral dimensions may also be employed.

[0115] An anisotropic etching process may be performed to transfer the pattern of openings in the photoresist layer through the optional dielectric cap layer 271, the second insulating cap layer 270, the rear stepped dielectric material portion (165, 265), the horizontally extending surface segments of the stepped surface, and the alternating stack {(132, 142), (232, 242)} and into the in-process sacrificial material layer 110'. A via cavity is formed through the alternating stack {(132, 142), (232, 242)} and into at least one semiconductor material layer (112, 114, 116) of the in-process source level material layer 110' and is therefore referred to herein as a through-stack via cavity 89. The photoresist layer may then be removed, for example, by ashing. Each of the through-stack via cavities 89 may have respective straight sidewalls extending vertically from above the second insulating cap layer 270 to the lower source level semiconductor layer 112.

[0116] refer to Fig. 11C , an isotropic recess etching process may be performed to selectively and isotropically recess the materials of the insulating layer (132, 232), the source level insulating layer 117, the backward stepped material portion (165, 265), the insulating capping layer (170, 270), the interlayer dielectric layer 180, and the optional dielectric capping layer 271 relative to the materials of the sacrificial material layer (142, 242) and the various semiconductor material layers (112, 104, 116, 118). In one embodiment, the insulating layer (132, 232), the source level insulating layer 117, the backward stepped material portion (165, 265), the insulating capping layer (170, 270), the interlayer dielectric layer 180, and the optional dielectric capping layer 271 may include corresponding semiconductor oxide materials, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass, and the isotropic recess etching process may include a wet etching process using dilute hydrofluoric acid. The recess distance of the isotropic recess etch process may be in the range of 10 nm to 200 nm, such as 20 nm to 100 nm, although smaller or larger recess distances may also be employed.

[0117] The through-stack via cavity 89 extends laterally at the level of the insulating layer (132, 232) and the source level insulating layer 117 and above the corresponding horizontally extending surface segment of the stepped surface (i.e., at the level of the rearward stepped dielectric material portion (165, 265), the insulating cap layer (170, 270) and the optional dielectric cover layer 271). The optional dielectric cover layer 271 can be incidentally thinned by an isotropic recess etching process. Each through-stack via cavity 89 is converted into a corresponding fin-shaped via cavity 87, which includes at least one fin cavity 87F formed at the level of a corresponding set of at least one insulating layer (132, 232) and an optional additional fin cavity formed at the level of the source level insulating layer 117 (if present). Each fin cavity 87F can have a volume of a corresponding cylindrical ring. Generally, the fin via cavity 87 may be formed by isotropically extending the through-stacked via cavity 89 by selectively recessing laterally at least the back-stepped dielectric material portion (165, 265) and the insulating layer (132, 232) relative to the sacrificial material layer (142, 242).

[0118] refer to Fig.11D , a dielectric material (such as silicon oxide) may be conformally deposited to form a dielectric material layer 82L. The dielectric material layer 82L may fill a peripheral portion of the fin-shaped via cavity 87 (e.g., the entire volume of the fin-shaped cavity 87F). In one embodiment, the thickness of the dielectric material layer 82L may be greater than half the thickness of the sacrificial material layer (142, 242). In one embodiment, the dielectric material layer 82L may be deposited by a chemical vapor deposition process. The thickness of the dielectric material layer 82L may be in the range of 10 nm to 100 nm, such as 20 nm to 50 nm, but smaller and larger thicknesses may also be used. The dielectric material liner 82L may be deposited directly on all physically exposed sidewalls of the sacrificial material layer (142, 242), on the sidewalls of the insulating layer (132, 232) surrounding the fin-shaped via cavity 87, and on the physically exposed sidewalls of the rearward stepped dielectric material portion (165, 265), the insulating cap layer (170, 270), the interlayer dielectric layer 180, and the optional dielectric cover layer 271. Each unfilled volume of the fin-shaped via cavity 87 constitutes a stepped via cavity 87', which includes an upper portion having a larger lateral extent and a lower portion having a smaller lateral extent. The upper portion of each stepped via cavity 87' may include a first cylindrical cavity 87A, and the lower portion of each stepped via cavity 87' may include a second cylindrical cavity 87B.

[0119] refer to Fig.11E, an anisotropic etching process may be performed to remove the horizontally extending portions of the dielectric material layer 82L. Each remaining portion of the dielectric material layer 82L positioned in the first cylindrical cavity 87A overlying the corresponding horizontally extending surface segment of the stepped surface may have a tubular configuration and is referred to herein as a tubular dielectric liner 82T. Each remaining portion of the dielectric material layer 82L positioned in the second cylindrical cavity 87B located below the horizontally extending surface segment of the stepped surface constitutes a dielectric support column 81. According to one aspect of the present disclosure, each dielectric support column 81 may include: a vertically extending dielectric material portion 81V, which extends through at least one sacrificial material layer (142, 242); and at least one annular dielectric fin portion 81F, which protrudes laterally outward from the vertically extending dielectric material portion 81V, filling the corresponding fin cavity 87F. Each annular dielectric fin portion 81F may be positioned at the level of a corresponding insulating layer (132, 232) and may contact a cylindrical sidewall of the corresponding insulating layer (132, 232). In one embodiment, the vertically extending dielectric material portion 81V includes a tubular material portion having an inner cylindrical sidewall that extends vertically continuously through at least one sacrificial material layer (142, 242). After anisotropically etching the dielectric material layer 82L, the annular horizontal top surface 42 of the corresponding first sacrificial material layer (142 or 242) is physically exposed at the bottom of the first cylindrical cavity 87A.

[0120] refer to Fig.11F , a selective deposition process may be performed to selectively deposit sacrificial material on the physically exposed surfaces of the sacrificial material layer (142, 242) (e.g., on the corresponding annular horizontal top surface 42) while inhibiting the sacrificial material from growing from the physically exposed surfaces of the remaining portion of the dielectric material layer 82L, that is, while inhibiting the sacrificial material from growing from the physically exposed surfaces of the tubular dielectric liner 82T and the dielectric support column 81. A sacrificial annular plate 47 may grow from each physically exposed annular horizontal top surface 42 of the conductive layer (142, 242). The sacrificial material of the sacrificial annular plate 47 is referred to herein as a sacrificial plate material. In general, the sacrificial plate material may be the same as or may be different from the material of the sacrificial material layer (142, 242).

[0121] In an illustrative example, the sacrificial material layer (142, 242) may include a first silicon nitride material and / or may consist essentially of the first silicon nitride material, and the sacrificial annular plate 47 may include a second silicon nitride material and / or may consist essentially of the second silicon nitride material. The second silicon nitride material may be the same as or different from the first silicon nitride material. For example, one of the first silicon nitride material and the second silicon nitride material may be stoichiometric, and the other of the first silicon nitride material and the second silicon nitride material may be non-stoichiometric (e.g., silicon-rich). Alternatively, both the first silicon nitride material and the second silicon nitride material may be stoichiometric (i.e., include Si3N4).

[0122] Generally speaking, the selective deposition process may use a precursor gas for the sacrificial plate material that has a longer time on the surface of the insulating layer (132, 232) relative to the surface 42 of the sacrificial material layer (142, 242).

[0123] Generally speaking, the sacrificial annular plate 47 can be formed by selectively growing the sacrificial plate material from the physically exposed annular surface 42 of the sacrificial material layer (142, 242) while inhibiting the growth of the sacrificial plate material from the physically exposed surface of the tubular dielectric liner 82T and the dielectric support column 81. Each sacrificial annular plate 47 can be isotropically grown from the physically exposed surface 42 of the corresponding sacrificial material layer (142, 242). Therefore, the section of the physically exposed surface of the sacrificial annular plate 47 can be equidistant from the most proximal interface between the corresponding sacrificial material plate 47 and the surface 42 of the corresponding sacrificial material layer (142, 242). The distance between the physically exposed surface of the sacrificial annular plate 47 and the interface of the surface 42 of the corresponding one of the sacrificial material layers (142, 242) can be in the range of 4nm to 100nm, such as from 6nm to 50nm, but smaller or larger distances can also be used. In one embodiment, each of the sacrificial annular plates 47 may include an annular flat surface section 47P parallel to a corresponding horizontal plane and a convex conical annular surface section 47T adjacent to the inner periphery of the annular flat surface section 47P and having a convex vertical cross-sectional profile and an annular top-down profile. The duration of the selective deposition process may be selected so that each sacrificial annular plate 47 includes a central hole 47H therethrough.

[0124] refer to Fig.11G, a dielectric liner 84 can be formed directly on the physically exposed surfaces of the tubular dielectric liner 82T, the dielectric support pillar 81, and the sacrificial annular plate 47 by performing a conformal deposition process. The dielectric liner 84 includes a dielectric material, such as silicon oxide or a dielectric metal oxide. The dielectric liner 84 can be formed, for example, by chemical vapor deposition or atomic layer deposition. The thickness of the dielectric liner 84 can be in the range of 2 nm to 50 nm, such as 4 nm to 25 nm, but smaller and larger thicknesses can also be used.

[0125] The sacrificial via fill material may be deposited in the stepped via cavity 87' by a conformal or non-conformal deposition process. The sacrificial via fill material includes a material that is selectively removable relative to the material of the dielectric liner 84. The sacrificial via fill material may include a semiconductor material (such as amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy), a carbon-based material (such as amorphous silicon, diamond-like carbon, or a doped derivative thereof), an organosilicate glass material, or a polymer material.

[0126] The portions of the sacrificial via filling material and the dielectric liner 84 that overlie the horizontal plane including the top surface of the dielectric cap layer 271 may be removed by performing a planarization process. The planarization process may include a chemical mechanical polishing process (CMP) and / or a recess etching process. Each remaining portion of the sacrificial via filling material is referred to herein as a sacrificial via filling material portion 85. In one embodiment, an encapsulation cavity (i.e., an air gap) 169 may be present within one or more of the sacrificial via filling material portions 85, such as the portion 85 positioned within the second cylindrical cavity 87B. Alternatively, the air gap may be omitted.

[0127] Each combination of all material portions filling a corresponding fin-shaped via cavity 87 is referred to herein as an in-process integrated contact and support assembly 186. Each in-process integrated contact and support assembly 186 includes a dielectric support post 81, a tubular dielectric liner 82T, a sacrificial via filling material portion 85, a dielectric liner 84, and an optional encapsulation cavity 169.

[0128] refer to Fig. 12A and Fig. 12BA photoresist layer (not shown) may be applied over the dielectric cap layer 271 and may be photolithographically patterned to form openings in regions extending across the memory array region 100 and the step region 200. The openings in the photoresist layer may extend laterally along the first horizontal direction hd1 between each adjacent cluster of memory opening fill structures 58. Backside trenches 79 may be formed by transferring the pattern in the photoresist layer through the dielectric cap layer 271, the second alternating stack (232, 242, 270, 265, 72), the first alternating stack (132, 142, 170, 165), and the source level material layer 110' during the process. The dielectric cap layer 271, the second alternating stack (232, 242, 270, 265, 72), the first alternating stack (132, 142, 170, 165), and the portion of the source level material layer 110' in the process below the opening in the photoresist layer may be removed to form backside trenches 79. In one embodiment, backside trenches 79 may be formed between clusters of memory opening filling structures 58. The clusters of memory opening filling structures 58 may be laterally spaced apart by backside trenches 79 along a second horizontal direction hd2.

[0129] In general, at least one vertical alternating sequence of continuous insulating layers (132, 232) and continuous spacer material layers (such as continuous sacrificial material layers (142, 242)) can be divided into alternating stacks {(132, 146), (232, 246)} of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) by forming backside trenches 79 extending laterally along a first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2. The dielectric cover layer 271 is divided into a plurality of dielectric cover layers 271 by the backside trenches 79.

[0130] refer to Fig.13A , a backside trench spacer 77 may be formed on the sidewalls of each backside trench 79. For example, a conformal spacer material layer may be deposited in the backside trench 79 and over the dielectric cap layer 271, and may be anisotropically etched to form the backside trench spacers 77. The backside trench spacers 77 include a material different from that of the source level sacrificial layer 104. For example, the backside trench spacers 77 may include silicon oxide, a dielectric metal oxide, or silicon nitride.

[0131] refer to Fig. 13BIn an isotropic etching process, an etchant that selectively etches the material of the source level sacrificial layer 104 relative to the material of the first alternating stack (132, 142), the second alternating stack (232, 242), the first insulating cap layer and the second insulating cap layer (170, 270), the higher dielectric liner layer 105 and the lower dielectric liner layer 103 can be introduced into the backside trench 79. For example, if the source level sacrificial layer 104 comprises undoped amorphous silicon or undoped polysilicon, the backside trench spacer 77 comprises silicon nitride, and the upper dielectric liner layer and the lower dielectric liner layer (105, 103) comprise silicon oxide, a wet etching process (which employs thermal trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH)) can be used to selectively remove the source level sacrificial layer 104 relative to the backside trench spacer 77 and the upper dielectric liner layer and the lower dielectric liner layer (105, 103). Alternatively, if the source level sacrificial material layer 104 comprises silicon nitride, the backside trench spacers 77 comprise silicon oxide or dielectric metal oxide, and the upper and lower dielectric liner layers (105, 103) comprise silicon oxide, a wet etching process (which employs hot phosphoric acid) may be employed to selectively remove the source level sacrificial layer 104 relative to the backside trench spacers 77 and the upper and lower dielectric liner layers (105, 103). A source cavity 109 is formed in the volume from which the source level sacrificial layer 104 is removed.

[0132] refer to Fig. 13C , a series of isotropic etchants (such as wet etchants) can be applied to the physically exposed portions of the memory film 50 through the backside trenches 79 and the source cavity 109 to sequentially etch the various component layers of the memory film 50 from the outside to the inside, and physically expose the bottom surface and cylindrical side surfaces of the vertical semiconductor channel 60 at the level of the source cavity 109. The higher dielectric liner layer and the lower dielectric liner layer (105, 103) can be incidentally etched during the removal of the portion of the memory film 50 positioned at the level of the source cavity 109. The volume of the source cavity 109 can be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the higher dielectric liner layer and the lower dielectric liner layer (105, 103). The top surface of the lower source level semiconductor layer 112 and the bottom surface of the higher source level semiconductor layer 116 can be physically exposed to the source cavity 109. After removing the physically exposed portion of the memory film 50, the outer sidewall of each vertical semiconductor channel 60 is physically exposed to the source cavity 109. A dielectric material stack 150 is formed under each physically exposed cylindrical surface of the vertical semiconductor channel 60. Each dielectric material stack 150 is a remaining portion of the memory film 50 and includes the same dielectric material stack as the memory film 50.

[0133] Therefore, the upper source level material layer 116 can act as an etch stop layer during the selective etching of the memory film 50 through the source cavity 109 and can prevent lateral expansion of the source cavity 109. This prevents a short circuit between the source select level conductive layer 118 and a source contact layer that is subsequently formed in the source cavity 109 during a subsequent step.

[0134] refer to Fig.13D The source contact layer 114 may be formed by a selective deposition process of a doped semiconductor material having a second conductivity type, which is referred to herein as a third doped semiconductor material. The doped semiconductor material may include amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy. The third doped semiconductor material of the source contact layer 114 may be grown from a physically exposed semiconductor surface surrounding the source cavity 109. The average atomic concentration of the second conductivity type dopant in the source contact layer 114 may be 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 range, but smaller and larger dopant concentrations may also be used.

[0135] In-process source level material layer 110' may be replaced with source level material layer 110. Source level material layer 110 includes a layer stack that includes, from bottom to top, a lower source level material layer 112, a source contact layer 114, an upper source level material layer 116, a source level insulating layer 117, and an optional source select level conductive layer 118. The combination of lower source level material layer 112, source contact layer 114, and upper source level material layer 116 constitutes a source layer (112, 114, 116). When source level sacrificial layer 104 is replaced with source contact layer 114, in-process source level material layer 110' is converted into a source level material layer 110 including source layer (112, 114, 116).

[0136] refer to Fig.13E and Fig.14 , the backside trench spacers 77 can be removed selectively relative to the semiconductor material of the source contact layer 114. For example, if the backside trench spacers 77 include silicon nitride, a wet etching process using hot phosphoric acid can be used to remove the backside trench spacers 77. If the backside trench spacers 77 include silicon oxide, a wet etching process using dilute hydrofluoric acid can be used to remove the backside trench spacers 77. The sidewalls of the first alternating stack and the second alternating stack (132, 142, 232, 242), the higher source level material layer 116, the source level insulating layer 117, and the optional source select level conductive layer 118 can be physically exposed after removing the backside trench spacers 77.

[0137] A thermal oxidation process may be performed to convert physically exposed surface portions of various semiconductor materials into semiconductor oxide portions. Specifically, physically exposed surface portions of source contact layer 114, upper source level material layer 116, and source select level conductive layer 118 (if present) are converted into thermal semiconductor oxide material portions. As used herein, "thermal semiconductor oxide" refers to a material formed by thermal oxidation of a semiconductor material. Unlike semiconductor oxide materials formed by chemical vapor deposition, thermal semiconductor oxide materials do not include carbon or hydrogen above trace levels unless the semiconductor material from which the semiconductor oxide material is derived includes carbon prior to the thermal oxidation process.

[0138] The thermal oxidation process forms a semiconductor oxide plate 122 at the bottom of each backside trench 79 and forms a semiconductor oxide rail 124 on the sidewalls of the source select level conductive layer 118. Fig.14 The semiconductor oxide rail 124 is not shown in FIG. The semiconductor oxide plate 122 includes various thermal semiconductor oxide material portions formed by thermal conversion of surface portions of the source contact layer 114 and the upper source level material layer 116.

[0139] The layer stack including the lower source level material layer 112, the source contact layer 114 and the upper source level material layer 116 constitutes a source layer (112, 114, 116), which is a buried source layer used as a common source region that connects each of the vertical semiconductor channels 60 and has a doping of the second conductivity type. The average dopant concentration of the buried source layer (112, 114, 116) can be 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 range, although smaller and larger dopant concentrations may also be used.

[0140] refer to Fig.15, an etchant that selectively etches the material of the first sacrificial material layer and the second sacrificial material layer (142, 242) relative to the material of the first and second insulating layers (132, 232), the material of the first and second backward stepped dielectric material portions (165, 265), and the material of the outermost layer of the memory film 50 can be introduced into the backside trench 79, for example, using an isotropic etching process. For example, the first and second sacrificial material layers (142, 242) can include silicon nitride, and the first and second insulating layers (132, 232), the first and second insulating capping layers (170, 270), the material of the first and second backward stepped dielectric material portions (165, 265), and the material of the outermost layer of the memory film 50 can include silicon oxide material. The first backside recess 143 is formed in the volume from which the first sacrificial material layer 142 is removed. The second backside recess 243 is formed in the volume from which the second sacrificial material layer 242 is removed.

[0141] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced in a vapor phase into the backside trench 79. For example, if the first sacrificial material layer and the second sacrificial material layer (142, 242) include silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0142] Each of the first backside recess and the second backside recess (143, 243) can be a laterally extending cavity whose lateral dimension is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the first backside recess and the second backside recess (143, 243) can be greater than the height of the corresponding backside recess (143, 243). A plurality of first backside recesses 143 can be formed in a volume from which the material of the first sacrificial material layer 142 is removed. A plurality of second backside recesses 243 can be formed in a volume from which the material of the second sacrificial material layer 242 is removed. Each of the first backside recess and the second backside recess (143, 243) can extend substantially parallel to the top surface of the substrate 8. The backside recess (143, 243) can be vertically defined by the top surface of the underlying insulating layer (132 or 232) and the bottom surface of the insulating layer (132 or 232) covering it. In one embodiment, each of the first backside recess and the second backside recess (243, 243) may have a uniform height throughout.

[0143] refer to FIG. 16A to FIG. 16B, a backside blocking dielectric layer (not shown) may be optionally deposited in the backside recesses and the backside trenches 79 and over the dielectric cap layer 271. At least one conductive material may be deposited in the plurality of backside recesses (243, 243), on the sidewalls of the backside trenches 79 and over the dielectric cap layer 271. The at least one conductive material may include at least one metal material, i.e., a conductive material including at least one metal element.

[0144] A plurality of conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous metal material layer (not shown) may be formed on the sidewalls of each backside trench 79 and over the dielectric cap layer 271. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) may be replaced with the first conductive material layer and the second conductive material layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the backside blocking dielectric layer and the conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. The backside cavity exists in the portion of each backside trench 79 that is not filled with the continuous metal material layer.

[0145] The metal material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. The metal material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy, such as a metal silicide, an alloy thereof, and a combination or stack thereof. Non-limiting exemplary metal materials that can be deposited in the back side recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metal material may include a metal, such as tungsten and / or a metal nitride. In one embodiment, the metal material for filling the back side recess may be a combination of a titanium nitride layer and a tungsten filling material. In one embodiment, the metal material may be deposited by chemical vapor deposition or atomic layer deposition.

[0146] The deposited metal material of the continuous metal material layer may be etched back, for example, by anisotropic or isotropic etching, from the sidewalls of each backside trench 79 and from above the dielectric cap layer 271. Each remaining portion of the deposited metal material in the first backside recess constitutes a conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes a second conductive layer 246. Each conductive layer (146, 246) may be a conductive line structure.

[0147] A subset of the second conductive layer 246 positioned at the level of the drain select level isolation structure 72 constitutes a drain select gate electrode. A subset of the conductive layers (146, 246) positioned below the drain select gate electrode can be used as a combination of a control gate and a word line positioned at the same level. The control gate electrode within each conductive layer (146, 246) is a control gate electrode for a vertical memory device including the memory stack structure 55. The source select level conductive layer 118 is used as a source select gate electrode.

[0148] Each memory opening filling structure in the memory opening filling structure 58 (which includes a corresponding memory stack structure 55) includes a vertical stack of memory elements positioned at each level of the conductive layer (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. The semiconductor devices in the peripheral device area 700 below may include word line switch devices that are configured to control bias voltages to corresponding word lines. The memory level component includes all structures positioned above the topmost surface of the lower level metal interconnect structure 780, and is positioned above the substrate semiconductor layer 9 and vertically spaced apart from the substrate semiconductor layer. The memory level component includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 that vertically extends through at least one alternating stack (132, 146, 232, 246). Each alternating stack (132, 146, 232, 246) includes alternating layers of a respective insulating layer (132 or 232) and a respective conductive layer (146 or 246). At least one alternating stack (132, 146, 232, 246) includes a stepped region including steps in which each underlying conductive layer (146, 246) extends further along a first horizontal direction hd1 than any overlying conductive layer (146, 246) within the memory hierarchy assembly.

[0149] An alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) is formed, the alternating stack being laterally spaced apart from each other along a second horizontal direction hd2 by backside trenches 79. The source layer (112, 114, 116) includes: a lower source level material layer 112 including a first doped semiconductor material; a higher source level material layer 116 including a second doped semiconductor material; and a source contact layer 114 including a third doped semiconductor material positioned between the higher source level material layer 116 and the lower source level material layer 112. In one embodiment, each of the vertical semiconductor channels 60 is in contact with the source contact layer 114. In one embodiment, each of the memory opening filling structures 58 includes a corresponding memory film 50 that laterally surrounds a corresponding vertical semiconductor channel 60, has a corresponding annular concave bottom surface that contacts the source contact layer 114, and has a corresponding cylindrical outer surface that contacts the upper source level material layer 116 and each insulating layer within a corresponding one of the alternating stacks {(132, 146), (232, 246)}.

[0150] refer to Fig.17 , a dielectric fill material such as silicon oxide can be conformally deposited in the backside trench 79. The dielectric fill material can be deposited by a conformal deposition process such as a low pressure chemical vapor deposition (LPCVD) process. The duration of the deposition process for depositing the dielectric fill material can be selected so that the dielectric fill material fills the backside trench 79. A recess etching process can then be performed to remove the portion of the dielectric fill material deposited above the dielectric cap layer 271. For example, the recess etching process can include an isotropic etching process such as a wet etching process. Each remaining portion of the dielectric fill material filling the backside trench 79 constitutes a backside trench filling structure 76.

[0151] FIG. 18A to FIG. 18F are sequential vertical cross-sectional views of a stepped region 200 of a first exemplary structure during formation of an integrated contact and support component 187 , a drain contact via structure 88 , and a connecting via structure 286 according to a first embodiment of the present disclosure.

[0152] refer to Fig.18A , showing that in Fig.17 A and Fig.17FIG. 2 is a diagram showing a step region 200 of a first exemplary structure at a processing step of FIG. B. Generally, during the formation of the backside groove (143, 243), the sacrificial annular plate 47 is removed together with the sacrificial material layer (142, 242). A pad cavity connected to the corresponding backside recess (143, 242) is formed after the sacrificial annular plate 47 is removed. The sacrificial annular plate 47 is replaced with a conductive annular pad portion 46A, which is formed in the pad cavity during the formation of the conductive layer (146, 246). Each conductive layer (146, 246) may include a corresponding conductive annular pad portion 46A protruding above a corresponding first horizontal plane HP1, the corresponding first horizontal plane including the top surface of the portion of the corresponding conductive layer (146, 246) filling the corresponding backside recess (143, 243) in the memory array area 100. In one embodiment, each conductive annular pad portion 46A may include a contoured top surface including an annular flat surface segment APS contained within a respective second horizontal plane HP2 overlying a respective first horizontal plane HP1, and each conductive annular pad portion may also include a convex conical annular surface segment CTAS adjacent to an inner periphery of the annular flat surface segment APS and having a convex vertical cross-sectional profile and an annular top-down profile. The annular flat surface segment APS may extend vertically downward from the second horizontal plate HP2 to at least the first horizontal plane HP1. Each conductive annular pad portion 46A is positioned above an annular portion of a respective conductive layer (146, 246) that laterally surrounds an opening through the respective conductive layer (146 or 246) that is filled by an integrated contact and support assembly 186.

[0153] refer to Fig.18B , the sacrificial via filling material portion 85 may be selectively removed relative to the material of the dielectric liner 84 to form the contact via cavity 83. The contact via cavity 83 may include an upper cavity portion 83A having a larger lateral dimension and a lower cavity portion 83B having a smaller lateral dimension. For example, if the sacrificial via filling material portion 85 includes silicon, a wet etching process using thermal trimethyl-2-hydroxyethylammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH) may be performed to remove the first sacrificial via filling material portion 85. If the sacrificial via filling material portion 85 includes a carbon-based material, an ashing process may be performed to remove the sacrificial via filling material portion 85.

[0154] refer to Fig.18C, an anisotropic etching process may be performed to remove the horizontally extending portion of the dielectric liner 84. Each dielectric liner 84 surrounding the corresponding contact via cavity 83 may be divided into a corresponding upper dielectric liner 84U and a lower dielectric liner 84L. The annular flat surface segment APS and the convex conical annular surface segment CTAS of each conductive annular pad portion 46A of the conductive layer 46 may be physically exposed after the anisotropic etching process. If the bottom horizontal portion of the dielectric liner 84 at the bottom of the lower cavity portion 83B is also removed during the anisotropic etching, the lower source level semiconductor layer 112 may be exposed at the bottom of the lower cavity portion 83B.

[0155] refer to Fig.18D , an optional oxidation process (such as a thermal oxidation process or a plasma oxidation process) may be performed to convert physically exposed semiconductor material portions (such as physically exposed surface portions of the lower source level semiconductor layer 112) into semiconductor oxide portions (e.g., silicon oxide portions) 111. In contrast, if the bottom horizontal portion of the dielectric liner 84 at the bottom of the lower cavity portion 83B is not removed during the anisotropic etching, the etching may be omitted. Fig.18D oxidation step.

[0156] refer to Fig.18E , at least one conductive material may be deposited in the contact via cavity 83. The at least one conductive material may include a combination of a metal barrier material (such as TiN, TaN, WN, MoN, TiC, TaC, WC or a combination thereof) and a metal filling material (such as W, Ti, Ta, Mo, Ru, Co, Cu, etc.). Excess portions of the at least one conductive material may be removed from above a horizontal plane including the dielectric cap layer 271 by a planarization process, which may include a chemical mechanical polishing (CMP) process and / or a recess etching process. Each remaining portion of the at least one conductive material filling the corresponding contact via cavity 83 constitutes a conductive layer contact via structure 86. Each conductive layer contact via structure 86 contacts the conductive ring pad portion 46A of the corresponding conductive layer (146 or 246). Each conductive layer contact via structure 86 may include a corresponding lower portion extending vertically through an opening in at least one pair of insulating layers (132, 232) and the conductive layer (146, 246). In one embodiment, one, a plurality of, or each of the conductive layer contact via structures 86 may include a respective lower portion extending at least partially vertically through at least one source level semiconductor layer (112, 114, 116).

[0157] In general, each sacrificial via filling material portion 85 can be replaced with a corresponding conductive layer contact via structure (e.g., a word line contact via structure or a select gate electrode contact via structure) 86. The integrated contact and support assembly 186 is converted into a corresponding integrated contact and support assembly 187 in each process. Each integrated contact and support assembly 187 includes a vertical stack of dielectric support pillars 81 and conductive layer contact via structures 86. The conductive layer contact via structure 86 contacts the top surface of the corresponding first conductive layer (146 or 246). The conductive layer contact via structure 86 includes an upper portion 86U covering the dielectric support pillars 81 and a lower portion 86L surrounded by the dielectric support pillars 81. The upper portion 86U is wider than the lower portion 86L. The dielectric support pillar 81 separates the lower portion of the corresponding conductive layer contact via structure 86 from the conductive layer ( 146 , 246 ) below the conductive ring-shaped pad portion 46A that contacts the bottom of the upper portion 86U of the corresponding conductive layer contact via structure 86 .

[0158] In one embodiment, the alternating stack {(132, 146), (232, 246)} includes a stepped region 200, wherein the lateral extent of the conductive layer (146, 246) decreases with vertical distance from at least one semiconductor material layer (112, 114, 116). At least one backward stepped dielectric material portion (165, 265) overlies a stepped surface of the alternating stack {(132, 146), (232, 246)} positioned in the stepped region 200. Each conductive layer contact via structure 86 extends vertically through at least one backward stepped dielectric material portion (165, 265).

[0159] refer to Fig.18F , a contact level dielectric layer 280 may be formed over the dielectric cap layer 271. A drain contact via structure 88 may be formed on the top surface of the corresponding drain region 63 through the contact level dielectric layer 280 and the dielectric cap layer 271. A connecting via structure 286 may be formed on the top surface of the corresponding conductive layer contact via structure 86 through the contact level dielectric layer 280.

[0160] Additional dielectric material layers (referred to herein as higher-level dielectric material layers), bit lines electrically connected to drain contact via structures 88 , and additional metal interconnect structures (referred to herein as higher-level metal interconnect structures) may be formed over contact-level dielectric layer 280 .

[0161] refer to Figure 18G, shows an alternative configuration of the first exemplary structure after forming the integrated contact and support component 187, the drain contact via structure 88, and the connecting via structure 286. In general, the duration of the anisotropic etching process performed to remove the horizontally extending portion of the dielectric liner 84 can be selected so that the lower dielectric liner 84L may or may not contact the inner sidewall surface segment of the conductive ring pad portion 46A of the corresponding conductive layer (146, 246). Fig.18F In FIG. 4 , the lower dielectric liner 84L does not contact the inner sidewall surface section of the conductive annular pad portion 46A. In contrast, in Figure 18G In the embodiment, the lower dielectric liner 84L contacts the inner sidewall surface section of the conductive annular pad portion 46A. Figure 18G In an alternative configuration, an encapsulation cavity (ie, air gap 169 ) may exist in a lower portion 86L of the conductive layer contact via structure 86 .

[0162] In the first embodiment, the dielectric spacer 90 is positioned in the contact via cavity 83, covers the sidewalls of the first conductive layer (146 or 246) in the contact via cavity 83, and extends above the top surface of the first conductive layer (146 or 246). In the first embodiment, the dielectric spacer 90 may include an upper portion of the dielectric support column 81 and / or the dielectric liner 84. For example, as Figure 18G As shown, dielectric spacer 90 comprises an upper portion of dielectric liner 84 .

[0163] Fig.19A and Fig.19B are sequential vertical cross-sectional views of a stepped region 200 of a second exemplary structure during the formation of an integrated contact and support assembly 186 according to a second embodiment of the present disclosure.

[0164] refer to Fig.19A , the second exemplary structure according to the second embodiment of the present disclosure can be Fig.11F The processing steps are the same as those of the first exemplary structure. An opening 47A is positioned in each sacrificial annular plate 47. The lower portion of each stepped through-hole cavity 87' positioned below the opening 47A includes a second cylindrical cavity 87B.

[0165] refer to Fig.19B ,refer to Fig.11G The described processing steps may be performed by modifying the increase in thickness of the dielectric liner 84. In this embodiment, the dielectric liner 84 may block the opening 47A through the sacrificial annular plate 47 within the same via fin cavity 87. In one embodiment, the encapsulation cavity 169 may exist within the lower portion of the dielectric liner 84 within the second cylindrical cavity 87B of the via fin cavity 87.

[0166] The sacrificial via filling material described above may be deposited in the stepped via cavity 87' by a conformal or non-conformal deposition process. The sacrificial via filling material includes a material that can be selectively removed relative to the material of the dielectric liner 84. The sacrificial via filling material may include a semiconductor material (such as amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy), a carbon-based material (such as amorphous silicon, diamond-like carbon, or a doped derivative thereof), an organic silicate glass material, or a polymer material. In a second embodiment, the second cylindrical cavity 87B in the lower portion of each stepped via cavity 87' is not filled with a sacrificial via filling material because the dielectric liner 84 inserts the opening 47A into the second cylindrical cavity 87B.

[0167] The portion of the sacrificial via filling material and the dielectric liner 84 covering the horizontal plane including the top surface of the dielectric cap layer 271 can be removed by performing a planarization process. The planarization process may include a chemical mechanical polishing process (CMP) and / or a recess etching process. Each remaining portion of the sacrificial via filling material is referred to herein as a sacrificial via filling material portion 85.

[0168] Each combination of all material portions filling a corresponding fin-shaped via cavity 87 is referred to herein as an in-process integrated contact and support assembly 186. Each in-process integrated contact and support assembly 186 includes a dielectric support post 81, a tubular dielectric liner 82T, a sacrificial via filling material portion 85, a dielectric liner 84, and an optional encapsulation cavity 169.

[0169] Subsequently, you can execute the reference FIG. 12A to FIG. 17 Describe the processing steps.

[0170] FIG. 20A to FIG. 20E are sequential vertical cross-sectional views of a stepped region of a second exemplary structure during formation of an integrated contact and support assembly, a drain contact via structure, and a connecting via structure according to a second embodiment of the present disclosure.

[0171] refer to Fig. 20A , in the corresponding Fig.17 A second exemplary structure is shown at processing step 87 of , except that the sacrificial via fill material portion 85 does not extend into the second cylindrical cavity 87B in the lower portion of each stepped via cavity 87 ′.

[0172] refer to Fig. 20B , the sacrificial via fill material portion 85 may be selectively removed relative to the material of the dielectric liner 84 to form a contact via cavity 83. The contact via cavity 83 does not contain the above-described first embodiment. Fig.18B Lower cavity portion 83B is depicted because dielectric liner 84 blocks opening 47A.

[0173] refer to Fig. 20C, an anisotropic etching process may be performed to remove the horizontally extending portions of the dielectric liner 84. Each dielectric liner 84 surrounding the corresponding contact via cavity 83 may be divided into a corresponding upper dielectric liner 84U and a lower dielectric liner 84L. The top component of the lower dielectric liner 84L fills the opening 47A between the pad portions 46A. The annular flat surface section APS and the convex conical annular surface section CTAS of each conductive annular pad portion 46A of the conductive layer 46 may be physically exposed after the anisotropic etching process.

[0174] refer to Fig.20D , at least one conductive material may be deposited in the contact via cavity 83. The at least one conductive material may include a combination of a metal barrier material (such as TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof) and a metal filling material (such as W, Ti, Ta, Mo, Ru, Co, Cu, etc.). Excess portions of the at least one conductive material may be removed from above a horizontal plane including the dielectric cap layer 271 by a planarization process, which may include a chemical mechanical polishing (CMP) process and / or a recess etching process. Each remaining portion of the at least one conductive material filling the corresponding contact via cavity 83 constitutes a conductive layer contact via structure 86. Each conductive layer contact via structure 86 contacts the conductive ring pad portion 46A of the corresponding conductive layer (146 or 246). Each conductive layer contact via structure 86 may include a bottommost surface that contacts the topmost surface of the filled opening 47A of the corresponding lower dielectric liner 84L.

[0175] Therefore, unlike the first embodiment, in the second embodiment, the conductive layer contact via structure 86 does not extend into the second cylindrical cavity 87B in the lower portion of each stepped via cavity 87'. Instead, only the corresponding lower dielectric liner 84L, the dielectric support pillar 81 and the optional air gap 169 are positioned in the second cylindrical cavity 87B in the lower portion of each stepped via cavity 87'.

[0176] In general, each sacrificial via filling material portion 85 can be replaced with a corresponding conductive layer contact via structure 86. In each process, the integrated contact and support assembly 186 is converted into a corresponding integrated contact and support assembly 187. Each integrated contact and support assembly 187 includes a vertical stack of dielectric support posts 81 and conductive layer contact via structures 86. The conductive layer contact via structure 86 contacts the top surface of the corresponding first conductive layer (146 or 246) in the conductive layer (146, 246). The conductive layer contact via structure 86 includes a portion covering the dielectric support posts 81.

[0177] refer to Fig.20E, a contact level dielectric layer 280 may be formed over the dielectric cap layer 271. A drain contact via structure 88 may be formed on the top surface of the corresponding drain region 63 through the contact level dielectric layer 280 and the dielectric cap layer 271. A connecting via structure 286 may be formed on the top surface of the corresponding conductive layer contact via structure 86 through the contact level dielectric layer 280. A higher level dielectric material layer and additional metal interconnect structures may be formed over the contact level dielectric layer 280 as described above.

[0178] In the second embodiment, the dielectric spacer 90 comprises an upper portion of the dielectric liner 84 .

[0179] FIG. 21A to FIG. 21G are sequential vertical cross-sectional views of a stepped region 200 of a third exemplary structure during the formation process of an integrated contact and support assembly 186 according to a third embodiment of the present disclosure.

[0180] refer to Fig.21A , in the corresponding Fig.18A A third exemplary structure is shown at the processing step of the processing steps shown. The third exemplary structure can be derived from the first exemplary structure by forming insulating spacers (221, 222) on vertically extending surface segments of the stepped surface and by forming an etch stop layer (251, 252) over horizontally extending surface segments of the stepped surface and over the insulating spacers (221, 222). The third exemplary structure can be derived from the first exemplary structure by performing a first set of additional processing steps after forming the first stepped surface on the first vertical alternating sequence (132, 142) and before forming the first backward stepped dielectric material portion 165, and by performing a second set of additional processing steps after forming the second stepped surface on the second vertical alternating sequence (232, 242) and before forming the second backward stepped dielectric material portion 265.

[0181] Each set of additional processing steps may include an insulating material layer deposition step of depositing insulating material over the respective stepped surface; an anisotropic etching step (e.g., a sidewall spacer etching step) of removing horizontally extending portions of the insulating material and forming a respective set of insulating spacers (221, 222); and a conformal deposition step of depositing a respective etch stop layer (251, 252) over the respective set of horizontally extending surface segments of the respective stepped surface and over the respective set of insulating spacers (221, 222). The insulating spacers (221, 222) may include a first insulating spacer 221 formed on the first stepped surface and a second insulating spacer 222 formed on the second stepped surface. The etch stop layer (251, 252) may include a first etch stop layer 251 formed over the first insulating spacer 221 and a second etch stop layer 222 formed over the second insulating spacer 222.

[0182] The insulating spacers (221, 222) may be formed on the vertically extending surface segments of the corresponding set of stepped surfaces. The insulating spacers (221, 222) include an insulating material different from the material of the sacrificial material layer (142, 242). The insulating spacers (221, 222) may include a silicon oxide material (such as undoped silicate glass or doped silicate glass) or a dielectric metal oxide material (such as aluminum oxide, hafnium oxide, tantalum oxide, titanium oxide, lanthanum oxide, etc.). The lateral thickness of the insulating spacers (221, 222) may be in the range of 3nm to 50nm, such as 6nm to 30nm, but smaller and larger thicknesses may also be used.

[0183] Each etch stop layer (251, 252) includes a material that is resistant to etching chemicals used to form the fin cavity 87F around the through-stack via cavity to be formed subsequently. For example, the etch stop layer (251, 252) may include silicon nitride or a dielectric metal oxide material. In one embodiment, the etch stop layer (251, 252) may include the same material as the sacrificial material layer (142, 242). The thickness of each etch stop layer (251, 252) may be in the range of 20nm to 100nm, such as 30nm to 60nm, but smaller and larger thicknesses may also be used.

[0184] In the case where the etch stop layer (251, 252) comprises the same material as the sacrificial material layer (142, 242) (e.g., silicon nitride), the etch stop layer (251, 252) can be patterned so that the etch stop layer (251, 252) is not exposed to the backside trench when forming the backside trench 79 during subsequent processing steps. In other words, the etch stop layer (251, 252) is laterally offset from the backside trench 79 along the second horizontal direction.

[0185] refer to Fig. 21B An anisotropic etching process may be performed to form the above-mentioned through-stack via cavity 89 through the optional dielectric cover layer 271, the second insulating cap layer 270, the backward stepped dielectric material portion (165, 265), the etch stop layer (251, 252) and the alternating stack {(132, 142), (232, 242)}, and at least partially into the in-process sacrificial material layer 110'.

[0186] refer to Fig. 21CThe above-mentioned isotropic recess etching process can be performed to selectively and isotropically recess the materials of the insulating layer (132, 232), the source level insulating layer 117, the backward stepped material portion (165, 265), the insulating cap layer (170, 270), the interlayer dielectric layer 180 and the optional dielectric cover layer 271 relative to the materials of the sacrificial material layer (142, 242), the etch stop layer (251, 252) and the various semiconductor material layers (112, 104, 116, 118).

[0187] The through-stack via cavity 89 extends laterally at the level of the insulating layer (132, 232) and the source level insulating layer 117 and above the corresponding horizontally extending surface segments of the stepped surface (i.e., at the level of the rearward stepped dielectric material portion (165, 265), the insulating cap layer (170, 270) and the optional dielectric cover layer 271). The optional dielectric cover layer 271 can be incidentally thinned by an isotropic recess etching process. Each through-stack via cavity 89 is converted into a corresponding fin-shaped via cavity 87, which includes at least one fin cavity 87F formed at the level of a corresponding set of at least one insulating layer (132, 232) and an optional additional fin cavity formed at the level of the source level insulating layer 117 (if present), as described above.

[0188] refer to Fig.21D , a dielectric material (such as silicon oxide) may be conformally deposited to form a dielectric material layer 82L, as described above. The dielectric material layer 82L may fill the peripheral portion of the fin-shaped via cavity 87, including the entire volume of the fin cavity 87F. Each unfilled volume of the fin-shaped via cavity 87 constitutes a stepped via cavity 87', which includes an upper portion having a larger lateral extent and a lower portion having a smaller lateral extent. The upper portion of each stepped via cavity 87' may include a first cylindrical cavity 87A, and the lower portion of each stepped via cavity 87' may include a second cylindrical cavity 87B, as described above.

[0189] refer to Fig.21E , an anisotropic etching process may be performed to remove the horizontally extending portions of the dielectric material layer 82L. Each remaining portion of the dielectric material layer 82L overlying the corresponding horizontally extending surface segment 253 of the stepped surface (e.g., the exposed top surface of the etch stop layer 251) may have a tubular configuration and is referred to herein as a tubular dielectric liner 82T. Each remaining portion of the dielectric material layer 82L is located below the horizontally extending surface segment of the stepped surface of the dielectric support column 81 described above.

[0190] refer to Fig.21F, an anisotropic etching process may be performed to remove unshielded portions of the etch stop layer (251, 252) within each stepped via cavity 87'. Thus, each portion of the etch stop layer (251, 252) that is not shielded by the corresponding overlying rearward stepped dielectric material portion (165, 265) may be removed after forming the fin-shaped via cavity 87 and subsequently forming the stepped via cavity 87'. The contoured top surface of the dielectric support post 81 may be physically exposed within each stepped via cavity 87'. Each contoured top surface may include an annular topmost surface segment 81T, a cylindrical surface segment 81C having a top periphery adjacent to the outer periphery of the annular top surface segment 81T, and a recessed annular surface segment 81R adjacent to the bottom periphery of the cylindrical surface segment 81C. Generally speaking, at least the annular top surface of the dielectric support post 81 may be physically exposed around each stepped via cavity 87'.

[0191] See also Figure 21G , the sacrificial via filling material may be deposited in the stepped via cavity 87' by a conformal or non-conformal deposition process. The sacrificial via filling material includes a material that can be selectively removed relative to the material of the tubular dielectric liner 82T and the dielectric support pillar 81. The sacrificial via filling material may include a semiconductor material (such as amorphous silicon, polycrystalline silicon, or silicon-germanium alloy), a carbon-based material (such as amorphous silicon, diamond-like carbon, or a doped derivative thereof), an organosilicate glass material, or a polymer material.

[0192] The portion of the sacrificial via filling material covering the horizontal plane above the top surface of the dielectric cover layer 271 can be removed by performing a planarization process. The planarization process may include a chemical mechanical polishing process (CMP) and / or a recess etching process. Each remaining portion of the sacrificial via filling material is referred to herein as a sacrificial via filling material portion 85. Each combination of all material portions that fill the corresponding fin-shaped via cavity 87 is referred to herein as an in-process integrated contact and support component 186. Each in-process integrated contact and support component 186 includes a dielectric support column 81, a tubular dielectric liner 82T, and a sacrificial via filling material portion 85.

[0193] Subsequently, you can execute the reference FIG. 12A to FIG. 17 Describe the processing steps.

[0194] FIG. 22A to FIG. 22F are sequential vertical cross-sectional views of a stepped region 200 of a third exemplary structure during formation of an integrated contact and support component 187 , a drain contact via structure 88 , and a connecting via structure 286 according to a third embodiment of the present disclosure.

[0195] refer to Fig.22A , in the corresponding Fig.17 A third exemplary structure is shown at the processing step of the processing step of .

[0196] refer to Fig. 22B , the sacrificial via filling material portion 85 is selectively removed relative to the material of the dielectric support pillar 81 and the tubular dielectric liner 82T to form the above-mentioned contact via cavity 83. The contact via cavity 83 may include an upper cavity portion 83A having a larger lateral dimension and a lower cavity portion 83B having a smaller lateral dimension.

[0197] refer to Fig. 22C , an anisotropic etching process may be performed to vertically recess the unmasked portion of the dielectric support pillar 81. The duration of the anisotropic etching process may be selected so that the annular top surface 46T of the corresponding conductive layer (146, 246) is physically exposed by the anisotropic etching process, while the sidewall of the corresponding conductive layer (146, 246) adjacent to the annular top surface is covered by the remaining portion of the corresponding dielectric support pillar 81.

[0198] refer to Fig.22D An optional oxidation process (such as a thermal oxidation process or a plasma oxidation process) may be performed to convert physically exposed semiconductor material portions (such as physically exposed surface portions of the lower source level semiconductor layer 112 ) into semiconductor oxide portions 111 .

[0199] refer to Fig.22E , at least one conductive material may be deposited in the contact via cavity 83. The at least one conductive material may include a combination of a metal barrier material (such as TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof) and a metal filling material (such as W, Ti, Ta, Mo, Ru, Co, Cu, etc.). Excess portions of the at least one conductive material may be removed from above a horizontal plane including the dielectric cap layer 271 by a planarization process, which may include a chemical mechanical polishing (CMP) process and / or a recess etching process. Each remaining portion of the at least one conductive material filling the corresponding contact via cavity 83 constitutes a conductive layer contact via structure 86. Each conductive layer contact via structure 86 contacts an annular surface segment 46T of a corresponding conductive layer (146 or 246). Each conductive layer contact via structure 86 may include a bottommost surface contacting a topmost surface of a corresponding semiconductor oxide portion 111.

[0200] Generally, each sacrificial via filling material portion 85 may be replaced with a corresponding conductive layer contact via structure 86. In each process, the integrated contact and support assembly 186 is converted into a corresponding integrated contact and support assembly 187. Each integrated contact and support assembly 187 includes a vertical stack of dielectric support pillars 81 and conductive layer contact via structures 86. The conductive layer contact via structures 86 contact the top surface 46T of the corresponding first conductive layer (146 or 246).

[0201] refer to Fig.22F , a contact level dielectric layer 280 may be formed over the dielectric cap layer 271. A drain contact via structure 88 may be formed on the top surface of the corresponding drain region 63 through the contact level dielectric layer 280 and the dielectric cap layer 271. A connecting via structure 286 may be formed on the top surface of the corresponding conductive layer contact via structure 86 through the contact level dielectric layer 280. Additional dielectric material layers and additional metal interconnects may be formed over the contact level dielectric layer 280, as described above.

[0202] In the third embodiment, the dielectric spacer 90 comprises an upper portion of the dielectric support pillar 81 .

[0203] FIG. 23A to FIG. 23D are sequential vertical cross-sectional views of a stepped region 200 of a fourth exemplary structure during the formation process of an integrated contact and support assembly 186 according to a fourth embodiment of the present disclosure.

[0204] refer to Fig.23A , by increasing the thickness of the dielectric liner 82L, the Fig.21D The third exemplary structure described leads to a fourth exemplary structure according to a fourth embodiment of the present disclosure. In one embodiment, the thickness of the dielectric liner 82L can be increased so that the lower portion of each fin-shaped via cavity 87 located below the corresponding portion of the etch stop layer (251, 252) is completely filled with the dielectric material of the dielectric liner 82L.

[0205] refer to Fig. 23B , an anisotropic etching process may be performed to remove the horizontally extending portions of the dielectric material layer 82L. Each remaining portion of the dielectric material layer 82L overlying the corresponding horizontally extending portion of the etch stop layer (251, 252) may have a tubular configuration and is referred to herein as a tubular dielectric liner 82T. Each remaining portion of the dielectric material layer 82L located below the corresponding horizontally extending portion of the etch stop layer (251, 252) constitutes a dielectric support column 81. After anisotropically etching the dielectric material layer 82L, an annular surface section of the corresponding etch stop layer (251, 252) is physically exposed below each through-hole cavity 87'.

[0206] refer to Fig.23C, an anisotropic etching process may be performed to remove unshielded portions of the etch stop layer (251, 252) within each through-hole cavity 87'. Thus, each portion of the etch stop layer (251, 252) that is not shielded by the corresponding overlying backward stepped dielectric material portion (165, 265) may be removed after forming the fin-shaped through-hole cavity 87 and subsequently forming the through-hole cavity 87". The wavy top surface of the dielectric support column 81 may be physically exposed within each through-hole cavity 87". Each wavy top surface may include a central topmost surface segment 81T, a cylindrical surface segment 81C having a top periphery adjacent to the periphery of the central top surface segment 81T, and a recessed annular surface segment 81R adjacent to the bottom periphery of the cylindrical surface segment. Generally speaking, at least the annular top surface of the dielectric support post 81 can be physically exposed around each through-hole cavity 87", which now comprises a stepped through-hole cavity due to the step between segments 81R and 81T. The contoured top surface of the dielectric support post 81 of the fourth embodiment differs from that of the third embodiment in that there is no opening through the central top surface segment 81T in the fourth embodiment.

[0207] refer to Fig.23D , forming a sacrificial via filling material portion 85 in cavity 87", as described above. Each combination of all material portions that fill the corresponding fin-shaped via cavity 87 is referred to herein as an in-process integrated contact and support assembly 186. Each in-process integrated contact and support assembly 186 includes a dielectric support column 81, a tubular dielectric liner 82T and a sacrificial via filling material portion 85.

[0208] Subsequently, you can execute the reference FIG. 12A to FIG. 17 Describe the processing steps.

[0209] FIG. 24A to FIG. 24E are sequential vertical cross-sectional views of stepped regions of a fourth exemplary structure during formation of an integrated contact and support assembly 187 , a drain contact via structure 88 , and a connecting via structure 286 according to a fourth embodiment of the present disclosure.

[0210] refer to Fig.24A , in the corresponding Fig.17 A fourth exemplary structure is shown at the processing step of the processing step.

[0211] refer to Fig. 24B , the sacrificial via fill material portion 85 may be selectively removed relative to the material of the dielectric support pillar 81 and the tubular dielectric liner 82T to form the contact via cavity 83 , as described above.

[0212] refer to Fig.24C, an anisotropic etching process may be performed to vertically recess the unmasked portion of the dielectric support pillar 81. The duration of the anisotropic etching process may be selected so that the annular top surface 46T of the corresponding conductive layer (146, 246) is physically exposed by the anisotropic etching process, while the sidewall of the corresponding conductive layer (146, 246) adjacent to the annular top surface is covered by the remaining portion of the corresponding dielectric support pillar 81.

[0213] refer to Fig.24D , a conductive layer contact via structure 86 is formed in the contact via cavity 83, as described above. Each conductive layer contact via structure 86 contacts the annular surface segment 46T of the corresponding conductive layer (146 or 246). In one embodiment, the entirety of each conductive layer contact via structure 86 can be positioned above the interface between the conductive layer contact via structure 86 and the corresponding conductive layer (146, 246). In one embodiment, the bottom portion of the conductive layer contact via structure 86 contacts the top portion of the vertically extending dielectric material portion 81V.

[0214] In general, each sacrificial via filling material portion 85 can be replaced with a corresponding conductive layer contact via structure 86. In each process, the integrated contact and support assembly 186 is converted into a corresponding integrated contact and support assembly 187. Each integrated contact and support assembly 187 includes a vertical stack of dielectric support posts 81 and conductive layer contact via structures 86. The conductive layer contact via structures 86 contact the top surface 46T of the corresponding first conductive layer (146 or 246). The entirety of the conductive layer contact via structure 86 covers the corresponding dielectric support posts 81.

[0215] refer to Fig.24E , a contact level dielectric layer 280 may be formed over the dielectric cap layer 271. A drain contact via structure 88 may be formed on the top surface of the corresponding drain region 63 through the contact level dielectric layer 280 and the dielectric cap layer 271. A connecting via structure 286 may be formed on the top surface of the corresponding conductive layer contact via structure 86 through the contact level dielectric layer 280. Additional dielectric material layers and additional metal interconnect structures may be formed over the contact level dielectric layer 280.

[0216] In the fourth embodiment, the dielectric spacer 90 comprises an upper portion of the dielectric support pillar 81 .

[0217] With reference to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a semiconductor structure is provided, comprising: an alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246); a memory opening 49 extending vertically through the alternating stack {(132, 146), (232, 246)}; a memory opening filling structure 58 positioned in the memory opening 49, wherein each of the memory stack structures 55 comprises a corresponding vertical semiconductor channel 60 and a corresponding vertical stack of memory elements (e.g., portions of a memory film 50) positioned at the level of the conductive layers (146, 246); a contact through-hole cavity 83 extending vertically through the alternating stack, and an integrated contact and support assembly 187 being located in the contact through-hole cavity 83. The integrated contact and support assembly 187 includes a dielectric support post 81 and a conductive layer contact via structure 86 that electrically contacts a top surface of a first conductive layer (146 or 246) of the conductive layers (146, 246) surrounding a contact via cavity 83. A dielectric spacer 90 is positioned in the contact via cavity 83, covers sidewalls of the first conductive layer (146 or 246) in the contact via cavity 83, and extends above the top surface of the first conductive layer (146 or 246).

[0218] In one embodiment, the dielectric support column 81 includes: a vertically extending dielectric material portion 81V, which extends through a first subset of the conductive layer (146, 246) located below the first conductive layer (146 or 246); and a plurality of annular dielectric fin portions 81F, which protrude laterally outward from the vertically extending dielectric material portion 81V and are positioned at the level of a subset of the insulating layer (132, 232) below the first conductive layer (146 or 246).

[0219] In the first and second embodiments, the vertically extending dielectric material portion 81V comprises a tubular material portion having an inner cylindrical sidewall that extends vertically continuously through the plurality of conductive layers (146, 246). In one embodiment, the integrated contact and support assembly 187 further comprises a dielectric liner 84 (such as a lower dielectric liner 84L portion) having an outer cylindrical sidewall that contacts the inner cylindrical sidewall of the vertically extending dielectric material portion 81V of the dielectric support column 81. The dielectric spacer 90 comprises an upper portion of the dielectric liner 84.

[0220] In a first embodiment, the conductive layer contact via structure 86 also includes a lower portion that is laterally surrounded by a dielectric liner (such as lower dielectric liner 84L) and extends vertically continuously through a first subset of the conductive layers (146, 246).

[0221] In the first and second embodiments, the vertically extending dielectric material portion 81V and the dielectric liner 84 extend vertically through the contact via opening 83 opened in the first conductive layer (146 or 246). The first conductive layer (146 or 246) has a uniform vertical thickness; the conductive ring pad 46A is positioned on and protrudes above the annular portion of the top surface of the first conductive layer (146 or 246), the annular portion laterally surrounding the contact via opening 83; and the conductive layer contact via structure 86 directly physically contacts the conductive ring pad 46A.

[0222] In the first and second embodiments, the conductive annular pad portion 46A includes a wavy top surface, which includes an annular flat surface segment APS and a convex conical annular surface segment CTAS, which is adjacent to the inner periphery of the annular flat surface segment APS and has a convex vertical cross-sectional profile and an annular top-down profile.

[0223] In a second embodiment, the dielectric liner 84 completely fills the contact via cavity 83 at the level of the conductive ring pad 46 and embeds the air gap 189 below the first conductive layer (146 or 246); and the bottommost surface section of the conductive layer contact via structure 86 contacts the top surface of the dielectric liner 84.

[0224] In some embodiments, such as the third and fourth embodiments, the dielectric spacer 90 comprises an upper portion of the dielectric support pillar 81 .

[0225] In a third embodiment, the upper portion of the dielectric support column 81 includes a wavy top surface, which includes an annular topmost surface segment 81T, a cylindrical surface segment 81C having a top periphery adjacent to the outer periphery of the annular top surface segment 81T, and a recessed annular surface segment 81R adjacent to the bottom periphery of the cylindrical surface segment 81C.

[0226] In the third and fourth embodiments, the dielectric spacer protrudes 84 into a recess in a bottom portion of the conductive layer contact via structure 86 .

[0227] In the third and fourth embodiments, insulating spacers (121, 122) are located on vertically extending surface segments of the alternatingly stacked stepped surfaces; dielectric etch stop layers (151, 152) are positioned over horizontally extending surface segments of the stepped surfaces and over the insulating spacers.

[0228] In various embodiments, the alternating stack {(132, 146), (232, 246)} includes a stepped region 200, wherein the lateral extent of the conductive layer (146, 246) decreases with the vertical distance from the substrate 8 located below the alternating stack; a backward stepped dielectric material portion (165, 265) overlies the stepped surface of the alternating stack {(132, 146), (232, 246)} positioned in the stepped region 200, and the conductive layer contact via structure 86 extends vertically through the backward stepped dielectric material portion (165, 265).

[0229] The dielectric spacers 90 of various embodiments cover the sidewalls of the first conductive layer (146 or 246) in the contact via cavity 83 and prevent or reduce short circuits between the conductive layer contact via structure 86 and the second conductive layer located below the first conductive layer. Without the dielectric spacers 90, the dielectric layer positioned in the contact via cavity 83 may be over-etched during the formation of the step via cavity 87' and expose both the first conductive layer and the second conductive layer in the contact via cavity 83. This may cause a short circuit between the conductive layer contact via structure 86 deposited in the contact via cavity 83 and the second conductive layer having an exposed surface in the contact via cavity 83.

[0230] During the replacement of the sacrificial material layer (142, 242) with the conductive layer (146, 246), the integrated contact and support component 186 in the process of the embodiment of the present disclosure can be used as a support structure. In addition, the integrated contact and support component 187 of the present disclosure includes a corresponding conductive layer contacting the via structure 86 that contacts a corresponding one of the conductive layers 46. Therefore, the integrated contact and support component 186 and the integrated contact and support component 187 in the process of the present disclosure can be used to provide structural support and electrical contact for the word lines in the three-dimensional memory device of the present disclosure.

[0231] Although specific embodiments are mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure, comprising: Alternating stacking of insulating and conducting layers; a reservoir opening extending vertically through the alternating stacks; a memory opening filling structure positioned in the memory opening, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements positioned at the level of the conductive layer; a contact via cavity extending vertically through the alternating stack; and an integrated contact and support assembly positioned in the contact via cavity, in: The integrated contact and support assembly includes a dielectric support post and a conductive layer contact via structure electrically contacting a top surface of a first conductive layer of the conductive layer surrounding the contact via cavity; and A dielectric spacer is positioned in the contact via cavity, covers a sidewall of the first conductive layer in the contact via cavity, and extends above the top surface of the first conductive layer.

2. The semiconductor structure of claim 1 , wherein the dielectric support pillar comprises: a vertically extending portion of dielectric material extending through a first subset of the conductive layers underlying the first conductive layer; and A plurality of annular dielectric fin portions project laterally outwardly from the vertically extending dielectric material portion and are positioned at the level of a subset of the insulating layers beneath the first conductive layer.

3. The semiconductor structure according to claim 2, wherein: The vertically extending dielectric material portion includes a tubular material portion having an inner cylindrical sidewall extending vertically continuously through the plurality of conductive layers; The integrated contact and support assembly further includes a dielectric liner having an outer cylindrical sidewall that contacts the inner cylindrical sidewall of the vertically extending dielectric material portion of the dielectric support post; and The dielectric spacer includes an upper portion of the dielectric liner. 4 . The semiconductor structure of claim 3 , wherein the conductive layer contact via structure further comprises a lower portion that is laterally surrounded by the dielectric liner and extends vertically continuously through the first subset of the conductive layer.

5. The semiconductor structure of claim 3, wherein: The vertically extending dielectric material portion and the dielectric liner extend vertically through a contact via opening in the first conductive layer; The first conductive layer has a uniform vertical thickness; a conductive ring-shaped pad positioned on and protruding above an annular portion of the top surface of the first conductive layer, the annular portion laterally surrounding the contact via opening; and The conductive layer contact via structure directly physically contacts the conductive ring pad.

6. The semiconductor structure of claim 5 , wherein the conductive annular pad comprises a contoured top surface, the contoured top surface comprising an annular flat surface segment and a convex conical annular surface segment, the convex conical annular surface segment being adjacent to an inner periphery of the annular flat surface segment and having a convex vertical cross-sectional profile and an annular top-down profile.

7. The semiconductor structure of claim 3, wherein: The dielectric liner completely fills the contact via cavity at the level of the conductive ring pad and embeds an air gap below the first conductive layer; and A bottommost surface section of the conductive layer contacting the via structure contacts a top surface of the dielectric liner.

8. The semiconductor structure of claim 2, wherein the dielectric spacer comprises an upper portion of the dielectric support pillar.

9. A semiconductor structure according to claim 8, wherein the upper portion of the dielectric support column includes a wavy top surface, the wavy top surface including an annular topmost surface segment, a cylindrical surface segment having a top periphery adjacent to the outer periphery of the annular top surface segment, and a recessed annular surface segment adjacent to the bottom periphery of the cylindrical surface segment.

10. The semiconductor structure of claim 8, wherein the dielectric spacer protrudes into a recess in a bottom portion of the conductive layer contact via structure.

11. The semiconductor structure according to claim 8, further comprising: insulating spacers positioned on vertically extending surface sections of the alternatingly stacked stepped surfaces; and A dielectric etch stop layer is positioned over the horizontally extending surface segments of the stepped surface and over the insulating spacers.

12. The semiconductor structure of claim 1, wherein: the alternating stack comprising a stepped region wherein the lateral extent of the conductive layer decreases with vertical distance from a substrate underlying the alternating stack; A rear stepped dielectric material partially overlies the stepped surfaces of the alternating stacks positioned in the stepped region; and The conductive layer contact via structure extends vertically through the rear stepped dielectric material portion.

13. A method of forming a semiconductor structure, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers; forming a memory stack structure through the alternating stacks, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements formed at the level of the sacrificial material layer; forming a stepped via cavity through the alternating stack such that an annular surface of a first sacrificial material layer of the sacrificial material layers surrounding the stepped via cavity is physically exposed; forming a sacrificial annular plate by selectively growing a sacrificial plate material from the physically exposed annular surface of the first layer of sacrificial material; replacing the sacrificial material layer with a conductive layer and replacing the sacrificial annular plate with a conductive annular pad positioned on a first conductive layer; and A conductive layer contact via structure contacting the conductive ring pad is formed.

14. The method according to claim 13, further comprising: forming an in-process integrated contact and support assembly in the stepped via cavity, wherein the in-process integrated contact and support assembly includes a dielectric support post and a sacrificial via fill material portion; as well as The sacrificial via filling material portion is replaced with the conductive layer contact via structure to form an integrated contact and support assembly including the dielectric support post and the conductive layer contact via structure.

15. The method according to claim 14, further comprising: forming a stepped surface by patterning the alternating stacks; forming a backward stepped dielectric material portion over said stepped surfaces of said alternating stacks; forming a via cavity through the backward stepped dielectric material portion and the alternating stack; isotropically expanding the via cavity by selectively recessing the rearwardly stepped dielectric material portion and the insulating layer laterally relative to the sacrificial material layer to form a fin-shaped via cavity; conformally depositing a dielectric material at a peripheral portion of the via-fin cavity; as well as The dielectric material is anisotropically etched to form the stepped via cavity, wherein a remaining portion of the dielectric material includes the dielectric support post.

16. The method according to claim 15, further comprising: forming a dielectric liner over the dielectric support pillar; as well as The sacrificial via fill material portion is formed over the dielectric support pillar.

17. A method of forming a semiconductor structure, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers; forming a memory stack structure through the alternating stacks, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements formed at the level of the sacrificial material layer; forming a stepped surface by patterning the alternating stacks; forming insulating spacers on vertically extending surface segments of the stepped surface; forming an etch stop layer over the insulating spacers and horizontal surface segments of the stepped surface; forming a backward stepped dielectric material portion over the etch stop layer; forming a via cavity through the backward stepped dielectric material portion, the etch stop layer, and the alternating stack; isotropically expanding the via cavity by selectively recessing the rearwardly stepped dielectric material portion and the insulating layer laterally relative to the sacrificial material layer to form a fin-shaped via cavity; conformally depositing a dielectric material at a peripheral portion of the via-fin cavity; anisotropically etching the dielectric material to form a stepped via cavity, wherein a remaining portion of the dielectric material comprises a fin-shaped dielectric support post; replacing the sacrificial material layer with a conductive layer; as well as A conductive layer contact via structure is formed contacting a top surface of a first conductive layer among the conductive layers.

18. The method according to claim 17, further comprising: forming a sacrificial via fill material portion on a top surface of the fin-shaped dielectric support pillar prior to replacing the sacrificial material layer with a conductive layer; removing the sacrificial via fill material portion after replacing the sacrificial material layer with the conductive layer; A portion of the fin-shaped dielectric support pillar is anisotropically etched to expose the top surface of the first conductive layer after removing the sacrificial via fill material portion, wherein the conductive layer contact via structure is formed on the annular top surface of the first conductive layer.

19. The method of claim 17, wherein: The fin-shaped dielectric support pillar partially fills a lower portion of the stepped via cavity; and A lower portion of the conductive layer contact via structure is positioned in the lower portion of the stepped via cavity and is surrounded by the fin-shaped dielectric support pillar.

20. The method of claim 17, wherein: The fin-shaped dielectric support pillar completely fills a lower portion of the stepped via cavity; and The conductive layer contact via structure is positioned on the fin-shaped dielectric support pillar.

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