Hard mask, preparation method and application method thereof and coating jig

Abstract

The invention provides a hard mask plate, a preparation method and an application method thereof, and a coating jig. The hard mask plate comprises a coating through hole; a step structure is arranged on the side wall of the coating through hole, the step structure comprises more than one coating step, and the distance between the tread of the coating step and the second surface is smaller than the distance between the first surface and the second surface. According to the hard mask, the film coating steps are arranged on the side walls of the film coating through holes of the hard mask, so that the problem of non-uniform film coating caused by shielding of the edges of the film coating through holes is avoided, and the mechanical strength of the hard mask is ensured; meanwhile, a clamping microstructure corresponding to the MEMS wafer is arranged on the hard mask plate, so that precise positioning is realized, and the coating position precision is improved; in addition, the height of the connecting area among the plurality of coating through holes in the chip area is set, so that uneven coating caused by shielding of the connecting area among the coating through holes with small intervals is avoided, and the mechanical strength of the connecting area is ensured; and finally, a coating jig is arranged to fasten and position the aligned hard mask plate and MEMS wafer, so that the coating position precision is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor and optical technology, and in particular relates to a hard mask and a preparation method, an application method and a coating jig thereof. Background Art

[0002] Optical coating refers to the process of coating a single or multiple layer of metal or dielectric film on the surface of an optical device or part to meet the requirements of optical properties such as light reflection, beam splitting, color separation, filtering, polarization, etc. Optical coating mainly includes vacuum evaporation, sputtering and other process methods. Usually, these optical coating processes form a film on the entire surface of the optical device, and it is difficult to form a film graphically in a specified area. For optical MEMS devices that have developed rapidly in recent years, coating is usually only allowed on the optical mirror surface to reduce the significant impact of optical films deposited in areas outside the optical mirror surface on the mechanical, electrical and other performances of the optical MEMS device; at the same time, optical MEMS devices also have higher requirements for the uniformity of film formation of optical films to maximize the effective optical film area.

[0003] In the prior art, when optical thin films are patterned using photolithography, not only will the active structure of the MEMS device be destroyed, but the formed optical thin film may also be contaminated, and is not suitable for optical MEMS devices with released active structures. At the same time, since optical thin film materials are usually different from thin film materials used in MEMS and semiconductor processes, the etching process of the optical thin film is incompatible with the etching process of the MEMS and semiconductor thin films, making it difficult to implement.

[0004] When the hard mask in the prior art is used to block the area outside the optical mirror for patterned coating, the hard mask has a certain wafer thickness (usually 250 microns to 550 microns), so it will partially block the oblique incident thin film material atoms, molecules or ions at the edge of the film forming area, so that the film cannot be formed at the edge of the MEMS micro mirror, resulting in the coating area being thick in the middle and thin at the edge, uneven film formation, and greatly reducing the effective use area of ​​the MEMS micro mirror, especially for micro mirrors with a diameter of less than 1 mm. An overly thin hard mask will greatly reduce the mechanical rigidity of the hard mask shielding structure, resulting in the hard mask MEMS wafer of the optical film being easily damaged during MEMS processing and coating, and poor bonding with the MEMS wafer to be coated.

[0005] Therefore, there is an urgent need for a structure or method that can perform optical thin film patterning on MEMS devices and form a uniform film that is suitable for MEMS devices and processes.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0007] In view of the above shortcomings of the prior art, the object of the present invention is to provide a hard mask and its preparation method, application method and coating jig, which are used to solve the problems in the prior art of poor optical coating uniformity and incompatibility with MEMS process devices when patterning optical thin films on MEMS devices.

[0008] To achieve the above object, the present invention provides a hard mask, the hard mask comprising a first surface and a second surface arranged opposite to each other, the hard mask further comprising more than one chip area, each of the chip areas comprising more than one plated through hole, each of the plated through holes penetrating the first surface and the second surface;

[0009] The side wall of each of the coated through holes is provided with a stepped structure, the bottom surface of the stepped structure is flush with the second surface, and the stepped structure of each of the coated through holes includes more than one coated step, and the distance between the tread of the coated step and the second surface is smaller than the distance between the first surface and the second surface.

[0010] Optionally, when each of the chip areas includes one of the plated through holes, a scribing street area is provided between two adjacent chip areas, and two adjacent plated through holes are connected by the stepped structure of two side walls and the scribing street area, the distance from the top surface of the scribing street area to the second surface is greater than the distance from the tread of the plated step farthest from the plated through hole to the second surface, the distance from the top surface of the scribing street area to the second surface is less than or equal to the distance from the first surface to the second surface, and the bottom surface of the scribing street area is flush with the second surface.

[0011] Optionally, each of the step structures further comprises a first step, the tread of the first step is flush with the first surface, and the line where the tread of the first step intersects with the riser is the first line;

[0012] When the step structure includes only one coated step, the line where the tread and riser of the coated step intersect is the second line, and the surface where the first line and the second line are located is the corresponding slope of the step structure;

[0013] When the step structure includes more than two coated steps, the line where the tread and the riser of each coated step in each of the step structures intersect is a step line, and the distance between the step line of the coated step away from the coated through hole and the second surface decreases successively from the distance between the step line and the second surface toward the distance between the step line and the second surface. The first line and the step line of each coated step are coplanar, and the surface where the first line and the step line are located is the corresponding slope surface of the step structure;

[0014] The angle between the slope surface and the second surface is θ;

[0015] The hard mask is used for the coating process of the micro-mirror surface of the MEMS wafer, and the coating through hole includes a preset coating area and an additional exposure area. The preset coating area is the area of ​​the micro-mirror surface of the MEMS wafer preset for coating, and the additional exposure area is the area within the coating through hole but beyond the preset coating area; the curved surface perpendicular to the first surface through the boundary of the preset coating area is the reference curved surface, the minimum vertical distance between the riser of the coating step and / or the first step and the reference curved surface is Δx, and the corresponding distance between the tread of the coating step and / or the first step and the second surface is H, Δx>Htan(90°-θ).

[0016] Optionally, when each of the chip areas includes more than two of the plated through holes, a scribe line area is arranged between two adjacent chip areas, and the distance from the top surface of the scribe line area to the second surface is greater than the distance from the tread of the plated step farthest from the plated through hole to the second surface; a connection area is arranged between two adjacent plated through holes in the same chip area, and the distance from the top surface of the connection area to the bottom surface of the connection area is less than the distance from the first surface to the second surface, and the distance from the top surface of the connection area to the bottom surface of the connection area is greater than the distance from the tread of the plated step closest to the plated through hole to the second surface, and the bottom surface of the connection area is flush with the second surface.

[0017] Optionally, each of the step structures further comprises a first step, the tread of the first step of the step structure in contact with the connection area is the top surface of the connection area, the tread of the first step of the step structure not in contact with the connection area is flush with the first surface, and the line where the tread of the first step intersects with the riser is the first line;

[0018] When the step structure includes only one coated step, the line where the tread and riser of the coated step intersect is the second line, and the surface where the first line and the second line are located is the corresponding slope of the step structure;

[0019] When the step structure includes more than two coated steps, the line where the tread and the riser of each coated step in each of the step structures intersect is a step line, and the distance between the step line of the coated step away from the coated through hole and the second surface decreases successively from the distance between the step line and the second surface toward the distance between the step line and the second surface. The first line and the step line of each coated step are coplanar, and the surface where the first line and the step line are located is the corresponding slope surface of the step structure;

[0020] The angle between the slope surface and the second surface is θ;

[0021] The hard mask is used for the coating process of the micro-mirror surface of the MEMS wafer, and the coating through hole includes a preset coating area and an additional exposure area. The preset coating area is the area of ​​the micro-mirror surface of the MEMS wafer preset for coating, and the additional exposure area is the area within the coating through hole but beyond the preset coating area; the curved surface perpendicular to the first surface through the boundary of the preset coating area is the reference curved surface, the minimum vertical distance between the riser of the coating step and / or the first step and the reference curved surface is Δx, and the corresponding distance between the tread of the coating step and / or the first step and the second surface is H, Δx>Htan(90°-θ).

[0022] Optionally, the hard mask also includes a non-chip area, and the second surface of the non-chip area is provided with more than two first locking microstructures, and the positions of the first locking microstructures of the hard mask can be locked and aligned with the corresponding second locking microstructures on the MEMS wafer to which the hard mask is to be aligned.

[0023] The present invention also provides a method for preparing a hard mask, the method being used to prepare any of the hard mask described above, the method comprising:

[0024] Providing an SOI structure, wherein the SOI structure comprises, from bottom to top, a substrate layer, a buried oxide layer and a top layer of single crystal silicon, wherein the lower surface of the substrate layer is the first surface of the SOI structure, and the upper surface of the top layer of single crystal silicon is the second surface of the SOI structure;

[0025] Disposing a first groove on the lower surface of the substrate layer of the SOI structure;

[0026] A second groove is provided on the upper surface of the top monocrystalline silicon of the SOI structure, wherein the projection of the first groove on the first surface is located within the projection of the second groove on the first surface;

[0027] One or more third grooves are continuously arranged on the bottom surface of the second groove in a direction close to the buried oxide layer, the buried oxide layer is exposed by the third grooves, the third grooves form plated through holes, and the projection of the third grooves on the first surface is located within the projection of the first groove on the first surface;

[0028] A fourth groove is provided on the bottom surface of the first groove in a direction close to the buried oxide layer. The fourth groove passes through the buried oxide layer. The fourth groove, the first groove and the third groove form a stepped structure.

[0029] Optionally, the fourth groove coincides with the projection of the first groove on the first surface, the fourth groove and the first groove constitute a first through groove, and the connection area between any two adjacent first through grooves is flush with the first surface; the projection of the third groove on the first surface is located within the projection of the first through groove on the first surface;

[0030] Or the projections of two or more adjacent fourth grooves on the first surface are located within the projection of the first groove on the first surface, so that the connecting area between the adjacent fourth grooves in the corresponding area is flush with the bottom surface of the first groove; the projection of the third groove on the first surface is located within the projection of the fourth groove on the first surface.

[0031] The present invention also provides a coating jig, which is used for temporarily fastening and positioning any one of the above-mentioned hard masks and the MEMS wafer aligned and fastened with the hard mask, and the coating jig comprises: a supporting bottom layer, a reinforcing top layer, a reinforcing spring sheet and a fastening structure;

[0032] The supporting bottom layer and the reinforcing top layer are both provided with a hollow area and a pressing area, the hollow area is used to expose the surfaces corresponding to the chip area of ​​the hard mask and the MEMS wafer, and the pressing area is used to fasten the hard mask and the MEMS wafer after being clamped; a detachable fastening structure is provided between the supporting bottom layer and the reinforcing top layer outside the hollow area and the pressing area, and the fastening structure can fasten the supporting bottom layer and the reinforcing top layer with the clamped hard mask and the MEMS wafer placed in the middle;

[0033] The reinforcing spring sheet is located above the reinforcing top layer, and the reinforcing spring sheet includes a fixing portion and an elastic portion. The fastening structure fastens the reinforcing spring sheet to the reinforcing top layer via the fixing portion, and the elastic portion of the reinforcing spring sheet can apply a rebound force to the reinforcing top layer.

[0034] The present invention also provides a method for applying a hard mask, wherein the method uses the hard mask, and the method comprises:

[0035] Providing a MEMS wafer to be aligned, wherein the upper surface of the MEMS wafer includes a second engaging microstructure corresponding to the first engaging microstructure of the hard mask;

[0036] Aligning the hard mask with the second engaging microstructure of the MEMS wafer through the first engaging microstructure;

[0037] Placing the hard mask and the MEMS wafer that are aligned and locked in place in the above-mentioned coating fixture for fastening;

[0038] Performing a micro-mirror coating process on the MEMS wafer from the first surface of the hard mask;

[0039] After micro-mirrors are plated in the corresponding plated through holes of the MEMS wafer, the plated fixture is opened and the hard mask is removed.

[0040] As described above, the hard mask and its preparation method, application method and coating jig of the present invention have the following beneficial effects:

[0041] The present invention arranges a coating step on the side wall of the coating through hole of the hard mask to avoid the problem of uneven coating caused by the edge of the coating through hole being blocked, and ensures the mechanical strength of the hard mask.

[0042] The present invention realizes precise positioning and improves the accuracy of coating position by setting a clamping microstructure corresponding to the MEMS wafer on the hard mask template;

[0043] The present invention sets the height of the connection area between the plurality of plated through holes in the chip area to avoid the blocking of the connection area between the plated through holes with small spacing, which leads to uneven coating, and ensures the mechanical strength of the connection area.

[0044] The present invention improves the accuracy of film coating position by arranging a film coating fixture to tightly position the aligned hard mask template and the MEMS wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Shown is a schematic side cross-sectional view of the hard mask in Embodiment 1 of the present invention.

[0046] Figure 2 It is a schematic perspective view of a hard mask template in Embodiment 1 of the present invention.

[0047] Figure 3 Shown is a schematic top view of a hard mask in an example of embodiment 1 of the present invention.

[0048] Figure 4 Shown is a schematic side cross-sectional view of a hard mask and a corresponding MEMS wafer in an example of Embodiment 1 of the present invention.

[0049] Figure 5 Shown is a schematic diagram of a partially enlarged side cross-sectional view of a plated through hole in an example of Embodiment 1 of the present invention.

[0050] Figure 6 Shown is a schematic top view of a hard mask in Embodiment 2 of the present invention.

[0051] Figure 7 Shown is a schematic side cross-sectional view of a hard mask and a corresponding MEMS wafer in Embodiment 2 of the present invention.

[0052] Figure 8 It is a schematic diagram of a side cross-sectional view of a SOI structure provided in step 1 of a method for preparing a hard mask according to embodiment 3 of the present invention.

[0053] Fig. 9 It is a schematic side cross-sectional view of setting an oxide layer in step 1 of an example of a method for preparing a hard mask according to embodiment 3 of the present invention.

[0054] Fig.10 It is a schematic side cross-sectional view of providing a first groove in step 2 of the method for preparing a hard mask according to embodiment 3 of the present invention.

[0055] Fig.11 It is a schematic side cross-sectional view of setting a second groove in step 3 of the method for preparing a hard mask according to embodiment 3 of the present invention.

[0056] Fig.12 It is a schematic side cross-sectional view of providing a third groove in step 4 of the method for preparing a hard mask according to embodiment 3 of the present invention.

[0057] Fig.13 It is a schematic side cross-sectional view of providing a fourth groove in step 5 of the method for preparing a hard mask according to embodiment 3 of the present invention.

[0058] Fig.14 It is a schematic diagram of a side cross-sectional view of a SOI structure provided in step 1 of a method for preparing a hard mask according to embodiment 4 of the present invention.

[0059] Fig.15 It is a schematic side cross-sectional view of setting an oxide layer in step 1 of an example of a method for preparing a hard mask according to embodiment 4 of the present invention.

[0060] Fig.16 It is a schematic side cross-sectional view of setting a first groove in step 2 of the method for preparing a hard mask according to embodiment 4 of the present invention.

[0061] Fig.17 It is a schematic side cross-sectional view of providing a second groove in step 3 of the method for preparing a hard mask according to embodiment 4 of the present invention.

[0062] Fig.18 It is a schematic side cross-sectional view of providing a third groove in step 4 of the method for preparing a hard mask according to embodiment 4 of the present invention.

[0063] Fig.19 It is a schematic side cross-sectional view of providing a third oxide layer in an example of step 4 of the method for preparing a hard mask according to embodiment 4 of the present invention.

[0064] Fig. 20 It is a schematic side cross-sectional view of providing a fourth groove in step 5 of the method for preparing a hard mask according to embodiment 4 of the present invention.

[0065] Fig.21 It is a schematic side cross-sectional view of removing the exposed oxide layer in an example of step 5 of the method for preparing a hard mask according to embodiment 4 of the present invention.

[0066] Fig. 22 It is a schematic top view of a coating fixture with a hard mask and a MEMS wafer placed therein according to Embodiment 5 of the present invention.

[0067] Fig.23 It is a schematic side cross-sectional view of a coating fixture with a hard mask and a MEMS wafer placed therein according to Embodiment 5 of the present invention.

[0068] Fig.24 Shown is a schematic top view of a coating fixture with a hard mask and a MEMS wafer placed in an example of Embodiment 5 of the present invention.

[0069] Fig.25 Shown is a schematic side cross-sectional view of a coating fixture with a clamped hard mask and a MEMS wafer placed in an example of embodiment 5 of the present invention.

[0070] Component number description

[0071] 100, hard mask; 101, first surface; 102, second surface; 120, plated through hole; 121, preset plated area; 122, additional exposed area; 130, stepped structure; 131, plated step; 132, first step; 133, riser; 134, tread; 135, slope; 136, first line; 137, second line; 138, step line; 140, chip area; 141, connection area; 150, scribe line area; 160, non-chip area; 161, first engaging microstructure; 170, SOI structure; 171, substrate layer; 172, buried oxide layer; 173, top single crystal silicon; 174, first oxide layer; 175, second oxide layer; 176, third oxide layer; 181, first groove; 182, second groove; 183, third groove; 184, fourth groove;

[0072] 200, MEMS wafer; 201, second engaging microstructure; 203, micro mirror;

[0073] 310, supporting bottom layer; 320, reinforcing top layer; 330, hollow area; 340, pressing area; 350, fastening structure; 360, reinforcing spring sheet; 361, fixing part; 362, elastic part; 370, pressure strip. DETAILED DESCRIPTION

[0074] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0076] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0077] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0078] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0079] Embodiment 1:

[0080] This embodiment provides a hard mask template 100, such as Figure 1-Figure 2 As shown, Figure 1 for Figure 2A side cross-sectional view of the structure, with the section line OO', wherein the hard mask 100 includes a first surface 101 and a second surface 102 that are arranged opposite to each other, and the hard mask 100 also includes more than one chip area 140, each of the chip area 140 includes more than one plated through hole 120, and each of the plated through hole 120 passes through the first surface 101 and the second surface 102;

[0081] The side wall of each of the coated through holes 120 is provided with a stepped structure 130, the bottom surface of the stepped structure 130 is flush with the second surface 102, and the stepped structure 130 of each of the coated through holes 120 includes more than one coated step 131, and the distance between the tread 134 of the coated step 131 and the second surface 102 is smaller than the distance between the first surface 101 and the second surface 102.

[0082] In the prior art, when optical MEMS devices are provided with optical mirrors by patterned coating, two methods are generally used: photolithography and hard mask 100. When the optical thin film is patterned by photolithography, not only will the active structure of the MEMS device be destroyed, but the formed optical thin film may also be polluted, and it is not suitable for optical MEMS devices with released active structures; at the same time, since the optical thin film material is usually different from the thin film material of MEMS and semiconductor processes, the etching process of the optical thin film is incompatible with the etching process of MEMS and semiconductor thin films, and is difficult to implement. When the hard mask 100 is used to shield the area outside the optical mirror for patterned coating, the hard mask 100 has a certain wafer thickness (usually 250 microns to 550 microns), so it will partially shield the thin film material atoms, molecules or ions that are obliquely incident at the edge of the film forming area, so that the film cannot be well formed at the edge area of ​​the MEMS micro mirror 203, resulting in the coating area being thick in the middle and thin at the edge, uneven film formation, and greatly reducing the effective use area of ​​the MEMS micro mirror 203, especially for the micro mirror 203 with a diameter of less than 1 mm. And too thin hard mask 100 will greatly reduce the mechanical rigidity of the shielding structure of the hard mask 100, resulting in the hard mask 100 MEMS wafer 200 used for optical thin film coating being easily damaged during MEMS processing and coating, and poor bonding with the MEMS wafer 200 to be coated.

[0083] The present invention sets a step structure 130 on the side wall of the coating through hole 120 so that the coating step 131 in the step structure 130 is lower than the overall height of the hard mask 100, thereby forming a slope 135, so that the edge of the coating through hole 120 originally blocked by the thickness of the hard mask 100 can be well coated due to the reduced height, thereby achieving uniform coating of the coating area in the coating through hole 120, and at the same time, because the step structure 130 reduces the thickness of the edge of the coating through hole 120 in a step-by-step manner, the mechanical strength of the hard mask 100 is guaranteed, and the problems of the hard mask 100 being easily caused by directly using an overly thin hard mask 100, such as cracking of the hard mask 100 and poor bonding with the MEMS wafer 200, are avoided; and because the use of the hard mask 100 does not require additional thin film etching of the coating surface of the MEMS device, the released active MEMS parts will not be damaged, and the hard mask 100 can be compatible with the MEMS process, thereby reducing the process difficulty and improving the quality of the optical film.

[0084] Specifically, although the solution of the present invention focuses on solving the coating problem of the micro-mirror 203 of the MEMS optical device, it can also be used in the design of other hard mask plates 100 that need to achieve uniform patterned coating, all of which are within the protection scope of the present invention.

[0085] Specifically, the "tread 134" mentioned in this embodiment and other embodiments is a horizontal surface of a step in a broad sense, and the "riser surface 133" is a vertical surface of a step in a broad sense. In the actual structure, the "tread 134" may not be completely parallel to the first surface 101, and the "riser surface 133" may not be completely perpendicular to the first surface 101. The "tread 134" and "riser surface 133" are only used to refer to two different surfaces of the step structure.

[0086] In this embodiment, Figure 3-Figure 5 As shown, Figure 4 for Figure 3 Side profile of Figure 3 AA' in the figure, each of the chip areas 140 includes a plated through hole 120, a scribing street area 150 is arranged between two adjacent chip areas 140, and two adjacent plated through holes 120 are connected to the scribing street area 150 through the stepped structures 130 on two side walls, the distance from the top surface of the scribing street area 150 to the second surface 102 is greater than the distance from the tread 134 of the plated step 131 farthest from the plated through hole 120 to the second surface 102, the distance from the top surface of the scribing street area 150 to the second surface 102 is less than or equal to the distance from the first surface 101 to the second surface 102, and the bottom surface of the scribing street area 150 is flush with the second surface 102.

[0087] Specifically, since each chip area 140 in the present embodiment includes one of the coating through holes 120, the connection area 141 between two adjacent coating through holes 120 is the scribing road area 150. The width of the connection area 141 between two adjacent coating through holes 120 is relatively large. Therefore, the slope angle requirement of uniform coating can be met by reducing the width of the scribing road area 150 and cooperating with the setting of the step structure 130. Therefore, the thickness of the scribing road area 150 can be equal to the thickness of the hard mask 100. When the width of the connection area 141 between the coating through holes 120 is so narrow that it is difficult to meet the coating angle requirement by narrowing the scribing road area 150, the height of the scribing road area 150 can only be reduced to allow the coating particle beam to be incident on the preset coating area 121, so as to achieve uniformity of micro-mirror coating.

[0088] In one embodiment, the hard mask 100 is a 4-inch single crystal silicon wafer, including 16 chip areas 140 distributed in 4 rows and 4 columns, and the coating through hole 120 in each chip area 140 is used to set the coating area of ​​the micro-reflector.

[0089] In one embodiment, each of the step structures 130 further includes a first step 132 , a tread 134 of the first step 132 is flush with the first surface 101 , and a line where the tread 134 of the first step 132 intersects with the riser 133 is a first line 136 ;

[0090] When the step structure 130 includes only one coated step 131, the line where the tread 134 and the riser 133 of the coated step 131 intersect is the second line 137, and the surface where the first line 136 and the second line 137 are located is the corresponding slope 135 of the step structure 130;

[0091] When the step structure 130 includes more than two coating steps 131, the line where the tread 134 and the riser 133 of each coating step 131 in each of the step structures 130 intersect is a step line 138, and the distance between the step line 138 of the coating step 131 away from the coating through hole 120 and the second surface 102 decreases successively from the coating through hole 120 to the coating through hole 120, and the first line 136 and the step line 138 of each coating step 131 are coplanar, and the surface where the first line 136 and the step line 138 are located is the corresponding slope surface 135 of the step structure 130;

[0092] The angle between the slope surface 135 and the second surface 102 is θ;

[0093] The hard mask 100 is used for the coating process of the micro mirror 203 of the MEMS wafer 200. Figure 4-Figure 5 As shown, Figure 5 for Figure 4The partially enlarged view of the M part in the figure, the coating through hole 120 includes a preset coating area 121 and an additional exposure area 122, the preset coating area 121 is the area where the micro mirror surface 203 of the MEMS wafer 200 is preset for coating, and the additional exposure area 122 is the area within the coating through hole 120 but beyond the preset coating area 121; the curved surface perpendicular to the first surface 101 through the boundary of the preset coating area 121 is the reference curved surface, the minimum vertical distance between the riser 133 of the coating step 131 and / or the first step 132 and the reference curved surface is Δx, and the corresponding distance between the tread 134 of the coating step 131 and / or the first step 132 and the second surface 102 is H, Δx>Htan(90°-θ).

[0094] Specifically, Figure 4-Figure 5 As shown, the minimum vertical distance between the riser 133 of the coated step 131 and the reference curved surface is Δx1, and the corresponding distance between the tread 134 of the coated step 131 and the second surface 102 is H1; the minimum vertical distance between the riser 133 of the first step 132 and the reference curved surface is Δx2, and the corresponding distance between the tread 134 of the first step 132 and the second surface 102 is H2.

[0095] The present invention sets a minimum vertical distance between the riser 133 of the coating step 131 and the first step 132 and the reference curved surface to ensure that the coating particle beam incident on the coating through hole 120 can fall into the preset coating area 121, thereby obtaining a micro-mirror 203 uniformly distributed according to a preset area, thereby maximizing the effective use area of ​​the micro-mirror 203.

[0096] In one embodiment, the angle θ between the slope 135 and the second surface 102 is ≤60°. Preferably, the angle θ between the slope 135 and the second surface 102 is ≤45°.

[0097] In one embodiment, the minimum vertical distance Δx between the riser 133 of the coating step 131 and / or the first step 132 and the reference curved surface is 3 microns to 20 microns. Preferably, the minimum vertical distance Δx between the riser 133 of the coating step 131 and / or the first step 132 and the reference curved surface is 5 microns.

[0098] Specifically, the riser 133 of the coating step 131 closest to the coating through hole 120 is the side wall of the coating through hole 120 .

[0099] In one embodiment, the angle θ between the slope 135 and the second surface 102 is 40°, the distance H between the tread 134 of the coated step 131 closest to the coated through hole 120 (the side wall of the coated through hole 120) and the second surface 102 is 5 microns, and the minimum vertical distance between the riser 133 of the coated step 131 closest to the coated through hole 120 and the reference curved surface is Δx=10 microns.

[0100] In one embodiment, the angle θ between the slope 135 and the second surface 102 is 40°, the distance H between the tread 134 of the first step 132 and the second surface 102 is equal to the distance between the first surface 101 and the second surface 102, which is 400 microns, and the minimum vertical distance between the riser 133 of the first step 132 and the reference surface is Δx=500 microns.

[0101] In one embodiment, the minimum vertical distance between the tread 134 of the coating step 131 closest to the coating through hole 120 and the second surface 102 is 5 micrometers to 20 micrometers.

[0102] Preferably, the minimum vertical distance between the tread 134 of the coating step 131 closest to the coating through hole 120 and the second surface 102 is 5 micrometers to 10 micrometers.

[0103] In one embodiment, Figure 3 As shown, the hard mask 100 also includes a non-chip area 160, and the second surface 102 of the non-chip area 160 is provided with more than two first locking microstructures 161. The position of the first locking microstructure 161 of the hard mask 100 can be locked and aligned with the corresponding second locking microstructure 201 on the MEMS wafer 200 to be aligned with the hard mask 100.

[0104] The present invention arranges a first locking structure in the non-chip area 160 of the hard mask 100 and engages with a second locking structure of the MEMS wafer 200 to achieve alignment between the hard mask 100 and the MEMS wafer 200, thereby greatly improving the alignment accuracy.

[0105] Specifically, through the configuration of this solution, the alignment accuracy of the hard mask 100 and the MEMS wafer 200 can reach 0.5 microns to 5 microns.

[0106] In one embodiment, Figure 3 As shown, the first engaging microstructures 161 are disposed at both lateral ends and longitudinal ends of the second surface 102 of the hard mask 100 , and the first engaging microstructures 161 are symmetrically distributed on the hard mask 100 .

[0107] The present invention can further improve the stability of the engagement by arranging the first engagement microstructures 161 to be symmetrically distributed on the hard mask 100, thereby further improving the alignment accuracy.

[0108] In one embodiment, Figure 4 As shown, the first engaging microstructure 161 is a boss, and the second engaging microstructure 201 is a groove corresponding to the position of the boss, and the boss can be engaged with the groove.

[0109] In one embodiment, Figure 4 As shown, the first engaging microstructure 161 includes four bosses, each of which has a projection of a square with a side length of 500 microns on the second surface 102, each boss protrudes from the second surface 102 by 18 microns, and the alignment accuracy between the boss and the groove on the MEMS wafer 200 is 1 micron.

[0110] In one embodiment, the material of the hard mask 100 may be single crystal silicon, metal material, plastic, polymer, or other suitable hard mask 100 materials.

[0111] In one embodiment, the overall thickness of the hard mask 100 is 250 micrometers to 1000 micrometers.

[0112] Specifically, Figure 4 As shown, the hard mask 100 is consistent in size with the MEMS wafer 200 .

[0113] The present invention helps to improve the alignment accuracy by setting the hard mask 100 and the MEMS wafer 200 to be consistent in size.

[0114] In one embodiment, the thermal expansion coefficients of the hard mask 100 and the MEMS wafer 200 are consistent.

[0115] The present invention sets the thermal expansion coefficients of the hard mask 100 and the MEMS wafer 200 to be consistent, thereby avoiding the adverse effects of temperature changes during the coating process on the structure and avoiding the problem of structural deformation or cracking caused by uneven stress at the engaging position.

[0116] Embodiment 2:

[0117] This embodiment provides a hard mask 100, and other features of the hard mask 100 are substantially the same as those in Embodiment 1, except that:

[0118] In this embodiment, Figure 6-Figure 7 As shown, Figure 7 for Figure 6 Side profile of Figure 6 BB' in the figure, each of the chip areas 140 includes more than two of the plated through holes 120, and a scribe line area 150 is provided between two adjacent chip areas 140, and the distance from the top surface of the scribe line area 150 to the second surface 102 is greater than the distance from the tread 134 of the plated step 131 farthest from the plated through hole 120 to the second surface 102; a connection area 141 is provided between two adjacent plated through holes 120 in the same chip area 140, and the distance from the top surface of the connection area 141 to the bottom surface of the connection area 141 is less than the distance from the first surface 101 to the second surface 102, and the distance from the top surface of the connection area 141 to the bottom surface of the connection area 141 is greater than the distance from the tread 134 of the plated step 131 closest to the plated through hole 120 to the second surface 102, and the bottom surface of the connection area 141 is flush with the second surface 102.

[0119] Since there are multiple plated through holes 120 in the same chip area 140 in this embodiment, the spacing between the connecting structures of the plated through holes 120 in the same chip area 140 is relatively narrow, and it is difficult to directly meet the coating slope angle requirement of the plated through hole 120 at the edge by narrowing the width of the connecting structure. The present invention sets the height of the connecting area 141 between the plated through holes 120 in the same chip area 140 to be lower than the first surface 101 and higher than the tread 134 of the lowest coating step 131, so that the connecting area 141 can pass through the ion beam for coating the edge of the mirror, thereby maximizing the effective use area of ​​the MEMS micro-mirror, while maintaining the mechanical strength of the connecting area 141, and improving the service life and product reliability of the hard mask 100.

[0120] Specifically, the processing accuracy of the connecting area 141 is generally not less than 5 microns. Therefore, when the width of the connecting area 141 is 5 microns and still cannot meet the requirements of the particle beam being incident on the preset coating area 121, the height of the connecting area 141 is lowered in this embodiment to achieve the incidence of the coated particle beam on the preset coating area 121.

[0121] In one embodiment, the hard mask 100 is a 4-inch single crystal silicon wafer, including four chip areas 140 distributed in 2 rows and 2 columns, each of the chip areas 140 has four coated through holes 120 distributed in 2 rows and 2 columns, and the four coated through holes 120 are used to set the micro-mirror coating area in the micro-mirror array distributed in 2 rows and 2 columns.

[0122] In one embodiment, Figure 7 As shown, the stepped structure 130 that is not in contact with the connecting region 141 has a tread surface 134 of the coating step 131 that is flush with the top surface of the connecting region 141 .

[0123] The present invention arranges the stepped structure 130 which is not in contact with the connecting area 141 so that a tread 134 of the coating step 131 is flush with the top surface of the connecting area 141, so that the coating step 131 and the connecting area 141 can be obtained synchronously through the implementation of a single groove process without setting grooves of different heights multiple times, which is beneficial to improving process efficiency and reducing process costs.

[0124] In one embodiment, each of the step structures 130 further includes a first step 132, a tread 134 of the first step 132 of the step structure 130 in contact with the connection area 141 is the top surface of the connection area 141, a tread 134 of the first step 132 of the step structure 130 not in contact with the connection area 141 is flush with the first surface 101, and a line where the tread 134 of the first step 132 intersects with the riser 133 is a first line 136;

[0125] like Figure 7 As shown, when the step structure 130 includes only one coating step 131, the line where the tread 134 and the riser 133 of the coating step 131 intersect is the second line 137, and the surface where the first line 136 and the second line 137 are located is the corresponding slope 135 of the step structure 130;

[0126] When the step structure 130 includes more than two coating steps 131, the line where the tread 134 and the riser 133 of each coating step 131 in each of the step structures 130 intersect is a step line 138, and the distance between the step line 138 of the coating step 131 away from the coating through hole 120 and the second surface 102 decreases successively from the coating through hole 120 to the coating through hole 120, and the first line 136 and the step line 138 of each coating step 131 are coplanar, and the surface where the first line 136 and the step line 138 are located is the corresponding slope surface 135 of the step structure 130;

[0127] The angle between the slope surface 135 and the second surface 102 is θ;

[0128] The hard mask 100 is used for the coating process of the micro-mirror 203 of the MEMS wafer 200. The coating through hole 120 includes a preset coating area 121 and an additional exposure area 122. The preset coating area 121 is the area of ​​the micro-mirror 203 of the MEMS wafer 200 that is preset for coating, and the additional exposure area 122 is the area within the coating through hole 120 but beyond the preset coating area 121; the curved surface perpendicular to the first surface 101 passing through the boundary of the preset coating area 121 is the reference curved surface, the minimum vertical distance between the riser 133 of the coating step 131 and / or the first step 132 and the reference curved surface is Δx, and the corresponding distance between the tread 134 of the coating step 131 and / or the first step 132 and the second surface 102 is H, Δx>Htan(90°-θ).

[0129] Specifically, Figure 6-Figure 7 As shown, the minimum vertical distance between the riser 133 of the coated step 131 and the reference curved surface is Δx1, and the corresponding distance between the tread 134 of the coated step 131 and the second surface 102 is H1; the minimum vertical distance between the riser 133 of the first step 132 and the reference curved surface is Δx2, and the corresponding distance between the tread 134 of the first step 132 and the second surface 102 is H2.

[0130] The present invention ensures that the coating particle beam can be incident from the edge of the stepped structure 130 to the preset coating area 121 for setting the micro-reflector by setting the minimum vertical distance between the riser 133 of the coating step 131 and / or the first step 132 and the reference curved surface, thereby maximizing the effective use area of ​​the micro-reflector.

[0131] Specifically, the riser surface 133 of the coating step 131 closest to the coating through hole 120 is the side wall of the coating through hole 120 .

[0132] In one embodiment, the minimum vertical distance Δx between the riser 133 of the coating step 131 and / or the first step 132 and the reference curved surface is 3 microns to 20 microns. Preferably, the minimum vertical distance Δx between the riser 133 of the coating step 131 and / or the first step 132 and the reference curved surface is 5 microns.

[0133] In one embodiment, the minimum vertical distance between the sidewall of the plated through hole 120 and the reference curved surface is 3 micrometers to 20 micrometers.

[0134] Preferably, the minimum vertical distance between the sidewall of the plated through hole 120 and the reference curved surface is 5 micrometers to 10 micrometers.

[0135] In one embodiment, the angle θ between the slope 135 and the second surface 102 is 40°, the distance H between the tread 134 of the coated step 131 closest to the coated through hole 120 (the side wall of the coated through hole 120) and the second surface 102 is 5 microns, and the minimum vertical distance between the riser 133 of the coated step 131 closest to the coated through hole 120 and the reference curved surface is Δx=10 microns.

[0136] In one embodiment, the angle θ between the slope 135 and the second surface 102 is 40°, the distance H between the tread 134 of the first step 132 of the stepped structure 130 in contact with the connecting area 141 and the second surface 102 is 80 microns, and the minimum vertical distance between the riser 133 of the first step 132 of the stepped structure 130 in contact with the connecting area 141 and the reference curved surface is Δx=100 microns.

[0137] In one embodiment, the angle θ between the slope 135 and the second surface 102 is 40°, the distance H between the tread 134 of the first step 132 of the stepped structure 130 that is not in contact with the connecting area 141 and the second surface 102 is equal to the distance 400 microns between the first surface 101 and the second surface 102, and the minimum vertical distance between the riser 133 of the first step 132 of the stepped structure 130 that is not in contact with the connecting area 141 and the reference curved surface is Δx=500 microns.

[0138] In one embodiment, the minimum vertical distance between the tread 134 of the coating step 131 closest to the coating through hole 120 and the second surface 102 is 5 micrometers to 20 micrometers.

[0139] Preferably, the minimum vertical distance between the tread 134 of the coating step 131 closest to the coating through hole 120 and the second surface 102 is 5 micrometers to 10 micrometers.

[0140] Embodiment 3:

[0141] This embodiment provides a method for preparing a hard mask 100, and the method is used to prepare the hard mask 100 described in any one of Embodiments 1-2, and the method includes:

[0142] Providing an SOI structure 170, the SOI structure 170 sequentially including a substrate layer 171, a buried oxide layer 172 and a top layer of single crystal silicon 173 from bottom to top, the bottom surface of the substrate layer 171 being the first surface 101 of the SOI structure 170, and the top surface of the top layer of single crystal silicon 173 being the second surface 102 of the SOI structure 170;

[0143] A first groove 181 is provided on the lower surface of the substrate layer 171 of the SOI structure 170;

[0144] A second groove 182 is provided on the upper surface of the top monocrystalline silicon 173 of the SOI structure 170 , and a projection of the first groove 181 on the first surface 101 is located within a projection of the second groove 182 on the first surface 101 ;

[0145] One or more third grooves 183 are continuously provided on the bottom surface of the second groove 182 in a direction close to the buried oxide layer 172 , the third grooves 183 expose the buried oxide layer 172 , the third grooves 183 form the plated through holes 120 , and the projection of the third grooves 183 on the first surface 101 is located within the projection of the first groove 181 on the first surface 101 ;

[0146] A fourth groove 184 is provided on the bottom surface of the first groove 181 in a direction close to the buried oxide layer 172 . The fourth groove 184 passes through the buried oxide layer 172 . The fourth groove 184 , the first groove 181 and the third groove 183 form a stepped structure 130 .

[0147] In this embodiment, the fourth groove 184 coincides with the projection of the first groove 181 on the first surface 101, the fourth groove 184 and the first groove 181 constitute a first through groove, and the connecting area 141 between any two adjacent first through grooves is flush with the first surface 101; the projection of the third groove 183 on the first surface 101 is located within the projection of the first through groove on the first surface 101.

[0148] The present invention utilizes the top layer of single crystal silicon 173 and other layered structures in the SOI structure 170 to directly perform a groove etching process in the entire SOI structure 170 to prepare the hard mask 100, thereby avoiding the tedious process of setting each layer first and improving the efficiency of the preparation process; at the same time, the extremely thin buried oxide layer 172 in the SOI structure 170 is used to isolate the third groove 183 from the first groove 181 and the fourth groove 184, and the third groove 183 is set as the coating step 131 closest to the second surface 102, which can maximize the coating uniformity of the edge of the coating area without increasing the process difficulty; and the boss around the second groove 182 of the non-chip area 160 obtained in the preparation process is used as the first engaging microstructure 161, further improving the preparation efficiency.

[0149] Specifically, when two adjacent first through grooves are located in the same chip area 140, the connection area 141 is the connection area 141 described in Example 2; when two adjacent first through grooves are located in two adjacent chip areas 140, the connection area 141 is the dicing road area 150 described in Example 1 or 2.

[0150] The preparation method of the hard mask 100 of this embodiment will be described in detail below with reference to the accompanying drawings. It should be noted that the following sequence does not strictly represent the sequence of the preparation method of the hard mask 100 protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0151] First, proceed to step 1, such as Figure 8 As shown, a SOI structure 170 is provided, and the SOI structure 170 includes a substrate layer 171, a buried oxide layer 172 and a top single crystal silicon layer 173 from bottom to top, the lower surface of the substrate layer 171 is the first surface 101 of the SOI structure 170, and the upper surface of the top single crystal silicon layer 173 is the second surface 102 of the SOI structure 170.

[0152] In one embodiment, the thickness of the substrate layer 171 of the SOI structure 170 is 400 microns, the thickness of the buried oxide layer 172 is 1 micron, and the thickness of the top layer of single crystal silicon 173 is 25 microns.

[0153] In one embodiment, Fig. 9 As shown, before setting the first groove 181 , the first surface 101 and the second surface 102 of the SOI structure 170 are oxidized to form a first oxide layer 174 on the first surface 101 and a second oxide layer 175 on the second surface 102 .

[0154] The present invention sets the first oxide layer 174 and the second oxide layer 175 as masks for setting the first groove 181, first patterns the first oxide layer 174 and the second oxide layer 175, and then uses the corresponding oxide layer as a mask for further patterning etching. Since the oxide layer is relatively thin, the formation and patterning process is simple, the operation is convenient, and the process efficiency is high.

[0155] In one embodiment, the thickness of the first oxide layer 174 is 2 micrometers, and the thickness of the second oxide layer 175 is 2 micrometers.

[0156] Then, proceed to step 2, such as Fig.10 As shown, a first groove 181 is disposed on the lower surface of the substrate layer 171 of the SOI structure 170 .

[0157] In one embodiment, when the first oxide layer 174 and the second oxide layer 175 exist, the first groove 181 is disposed to penetrate the first oxide layer 174 .

[0158] In one embodiment, the first groove 181 is formed by oxide layer etching, photolithography and KOH wet etching.

[0159] Next, proceed to step 3, such as Fig.11 As shown, a second groove 182 is provided on the upper surface of the top monocrystalline silicon 173 of the SOI structure 170 , and the projection of the first groove 181 on the first surface 101 is located within the projection of the second groove 182 on the first surface 101 .

[0160] In one embodiment, Fig.11 As shown, when the first oxide layer 174 and the second oxide layer 175 exist, the second groove 182 is set to penetrate the second oxide layer 175 .

[0161] In one embodiment, the second groove 182 is obtained by etching the oxide layer and photolithography with an etching depth of 17 micrometers.

[0162] Then, proceed to step 4, such as Fig.12 As shown, one or more third grooves 183 are set on the bottom surface of the second groove 182 in the direction close to the buried oxide layer 172, and the third grooves 183 expose the buried oxide layer 172. The third grooves 183 form a plated through hole 120, and the projection of the third groove 183 on the first surface 101 is located within the projection of the first groove 181 on the first surface 101.

[0163] Finally, proceed to step 5, such as Fig.13 As shown, a fourth groove 184 is set on the bottom surface of the first groove 181 in a direction close to the buried oxide layer 172, and the fourth groove 184 passes through the buried oxide layer 172. The fourth groove 184 coincides with the projection of the first groove 181 on the first surface 101, and the fourth groove 184 and the first groove 181 constitute a first through groove, and the connection area 141 between any two adjacent first through grooves is flush with the first surface 101; the projection of the third groove 183 on the first surface 101 is located within the projection of the first through groove on the first surface 101, and the first through groove and the third groove 183 constitute a stepped structure 130.

[0164] In one embodiment, the fourth groove 184 is obtained by etching the oxide layer, photolithography and removing the oxide layer.

[0165] In one embodiment, the hard mask 100 is manufactured using a MEMS bulk silicon process.

[0166] Specifically, grooves may be provided multiple times on the basis of this solution to obtain a stepped structure 130 with more steps, which may further improve the coating uniformity at the edge of the coating area and the mechanical strength of the hard mask 100 itself.

[0167] Embodiment 4:

[0168] This embodiment provides a method for preparing a hard mask 100, which is substantially the same as the method for preparing the hard mask 100 in Embodiment 3, except that:

[0169] In this embodiment, the projections of two or more adjacent fourth grooves 184 on the first surface 101 are located within the projection of the first groove 181 on the first surface 101, so that the connecting area 141 between the adjacent fourth grooves 184 in the corresponding area is flush with the bottom surface of the first groove 181; the projection of the third groove 183 on the first surface 101 is located within the projection of the fourth groove 184 on the first surface 101.

[0170] The present invention utilizes the top layer of single crystal silicon 173 and other layered structures in the SOI structure 170 to directly perform a groove etching process in the entire SOI structure 170 to prepare the hard mask 100, thereby avoiding the tedious process of setting each layer first and improving the efficiency of the preparation process. At the same time, the third groove 183 is isolated from the first groove 181 and the fourth groove 184 by utilizing the extremely thin buried oxide layer 172 in the SOI structure 170, and the third groove 183 is set as the coating step 131 closest to the second surface 102, so that the coating uniformity of the edge of the coating area can be maximized without increasing the process difficulty. In addition, by arranging two or more adjacent fourth grooves 184 on the bottom surface of the first groove 181, the connection area 141 between the two adjacent fourth grooves 184 is made to take the bottom surface of the first groove 181 as the top surface, so that the height control of the connection area 141 is achieved synchronously, and the process efficiency is improved. Finally, the boss around the second groove 182 of the non-chip area 160 obtained in the preparation process is used as the first engaging microstructure 161, which further improves the preparation efficiency.

[0171] Specifically, “the adjacent fourth grooves 184 in the corresponding area” refers to the adjacent fourth grooves 184 whose projections on the first surface 101 are within the projection of the same first groove 181 .

[0172] Specifically, when two adjacent fourth grooves 184 in the corresponding area are located in the same chip area 140, the connection area 141 is the connection area 141 described in Example 2; when two adjacent fourth grooves 184 are located in two adjacent chip areas 140, the connection area 141 is the scribing street area 150 described in Example 1 or 2, and the two adjacent fourth grooves 184 corresponding to the scribing street area 150 are not necessarily in the corresponding area. When the surface height of the scribing street area 150 is set to be consistent with the height of the connection area 141 in the chip, the two adjacent fourth grooves 184 corresponding to the scribing street area 150 are in the corresponding area.

[0173] The preparation method of the hard mask 100 of this embodiment will be described in detail below with reference to the accompanying drawings. It should be noted that the following sequence does not strictly represent the sequence of the preparation method of the hard mask 100 protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0174] First, proceed to step 1, such as Fig.14 As shown, a SOI structure 170 is provided, and the SOI structure 170 includes a substrate layer 171, a buried oxide layer 172 and a top single crystal silicon layer 173 from bottom to top, the lower surface of the substrate layer 171 is the first surface 101 of the SOI structure 170, and the upper surface of the top single crystal silicon layer 173 is the second surface 102 of the SOI structure 170.

[0175] In one embodiment, the thickness of the substrate layer 171 of the SOI structure 170 is 400 microns, the thickness of the buried oxide layer 172 is 1 micron, and the thickness of the top layer of single crystal silicon 173 is 25 microns.

[0176] In one embodiment, Fig.15 As shown, before setting the first groove 181 , the first surface 101 and the second surface 102 of the SOI structure 170 are oxidized to form a first oxide layer 174 on the first surface 101 and a second oxide layer 175 on the second surface 102 .

[0177] In one embodiment, the thickness of the first oxide layer 174 is 2 micrometers, and the thickness of the second oxide layer 175 is 2 micrometers.

[0178] Then, proceed to step 2, such as Fig.16 As shown, a first groove 181 is disposed on the lower surface of the substrate layer 171 of the SOI structure 170 .

[0179] In one embodiment, when the first oxide layer 174 and the second oxide layer 175 exist, the first groove 181 is disposed to penetrate the first oxide layer 174 .

[0180] Next, proceed to step 3, such as Fig.17 As shown, a second groove 182 is provided on the upper surface of the top monocrystalline silicon 173 of the SOI structure 170 , and the projection of the first groove 181 on the first surface 101 is located within the projection of the second groove 182 on the first surface 101 .

[0181] In one embodiment, Fig.17 As shown, when the first oxide layer 174 and the second oxide layer 175 exist, the second groove 182 is set to penetrate the second oxide layer 175 .

[0182] In one embodiment, etching is performed using the patterned oxide layer as a mask with an etching depth of 17 micrometers to obtain the second groove 182 .

[0183] Then, proceed to step 4, such as Fig.18 As shown, one or more third grooves 183 are set on the bottom surface of the second groove 182 in the direction close to the buried oxide layer 172, and the third grooves 183 expose the buried oxide layer 172. The third grooves 183 form a plated through hole 120, and the projection of the third groove 183 on the first surface 101 is located within the projection of the first groove 181 on the first surface 101.

[0184] In one embodiment, Fig.19 As shown, when the first oxide layer 174 and the second oxide layer 175 exist, after the third groove 183 is set, the surface of the obtained structure is thermally oxidized, and the third oxide layer 176 is formed on the surfaces exposed by the first groove 181, the second groove 182 and the third groove 183.

[0185] In one embodiment, the thickness of the third oxide layer 176 is set to 1 micrometer.

[0186] Next, proceed to step 5, such as Figure 20-21 As shown, a fourth groove 184 is set on the bottom surface of the first groove 181 in a direction close to the buried oxide layer 172, and the fourth groove 184 passes through the buried oxide layer 172. The projections of two or more adjacent fourth grooves 184 on the first surface 101 are located within the projection of the first groove 181 on the first surface 101, so that the connection area 141 between adjacent fourth grooves 184 is flush with the bottom surface of the first groove 181; the projection of the third groove 183 on the first surface 101 is located within the projection of the fourth groove 184 on the first surface 101, and the fourth groove 184, the first groove 181 and the third groove 183 form a stepped structure 130.

[0187] In one embodiment, the fourth groove 184 is obtained by etching the oxide layer, photolithography and removing the oxide layer.

[0188] In one embodiment, Fig. 20 As shown, when the third oxide layer 176 exists, when the fourth groove 184 is provided, the fourth groove 184 penetrates the original third oxide layer 176 on the bottom surface of the first groove 181 .

[0189] In one embodiment, Fig.21 As shown, when there are the first oxide layer 174, the second oxide layer 175 and the third oxide layer 176, after setting the fourth groove 184, the remaining exposed first oxide layer 174, the second oxide layer 175 and the third oxide layer 176 and the oxide layer of the SOI itself (ie, the buried oxide layer 172) are removed.

[0190] Specifically, grooves may be provided multiple times on the basis of this solution to obtain a stepped structure 130 with more steps, which may further improve the coating uniformity at the edge of the coating area and the mechanical strength of the hard mask 100 itself.

[0191] Embodiment 5:

[0192] This embodiment provides a coating jig, which is used to temporarily fix the hard mask 100 described in any one of the embodiments 1-2 and the MEMS wafer 200 aligned and clamped by the hard mask 100. Figure 22-Figure 23 As shown, Fig.23 for Fig. 22 Side profile of Fig. 22 CC' in the coating fixture includes: a supporting bottom layer 310, a reinforcing top layer 320, a reinforcing spring sheet 360 and a fastening structure 350;

[0193] The supporting bottom layer 310 and the reinforcing top layer 320 are both provided with a hollow area 330 and a pressing area 340, wherein the hollow area 330 is used to expose the surfaces corresponding to the chip area 140 of the hard mask 100 and the MEMS wafer 200, and the pressing area 340 is used to fasten the hard mask 100 and the MEMS wafer 200 after being clamped; a detachable fastening structure 350 is provided between the supporting bottom layer 310 and the reinforcing top layer 320 outside the hollow area 330 and the pressing area 340, and the fastening structure 350 can fasten the supporting bottom layer 310 and the reinforcing top layer 320 with the clamped hard mask 100 and the MEMS wafer 200 placed in the middle;

[0194] The reinforcing spring sheet 360 is located above the reinforcing top layer 320 , and the reinforcing spring sheet 360 includes a fixing portion 361 and an elastic portion 362 . The fastening structure 350 fastens the reinforcing spring sheet 360 to the reinforcing top layer 320 via the fixing portion 361 , and the elastic portion 362 of the reinforcing spring sheet 360 can apply a rebound force to the reinforcing top layer 320 .

[0195] The present invention sets a coating jig, utilizes the reinforcement top layer 320, the support bottom layer 310 and the fastening structure 350 to fasten and position the aligned hard mask 100 and the MEMS wafer 200, and cooperates with the reinforcement spring piece 360 ​​to reinforce the position of the hard mask 100 closer to the chip area 140, so as to avoid misalignment between the hard mask 100 and the MEMS wafer 200 during the process, and at the same time, can further ensure the engagement reliability between the first engaging microstructure 161 and the second engaging microstructure 201, so as to ensure the alignment accuracy of the hard mask 100 and the MEMS wafer 200 and improve the coating position accuracy.

[0196] In one embodiment, when the coating jig is used to fix the hard mask 100 described in Example 1 after being positioned and clamped, the thickness of the reinforced top layer 320 is 8 mm and the diameter is 170 mm, and the minimum distance between the inner edge of the pressing area 340 of the reinforced top layer 320 and the projection of the chip area 140 of the hard mask 100 on the first surface 101 is 1 cm; the thickness of the supporting bottom layer 310 is 1 cm and the diameter is 170 mm, and the hollow area 330 of the supporting bottom layer 310 coincides with the projection of the chip area 140 of the hard mask 100 on the first surface 101.

[0197] In one embodiment, when the coating jig is used to fix the hard mask 100 described in Example 2 after being positioned and clamped, the thickness of the reinforced top layer 320 is 5 mm and the diameter is 170 mm, and the minimum distance between the inner edge of the pressing area 340 of the reinforced top layer 320 and the projection of the chip area 140 of the hard mask 100 on the first surface 101 is 1 cm; the thickness of the supporting bottom layer 310 is 1 cm and the diameter is 170 mm, and the hollow area 330 of the supporting bottom layer 310 coincides with the projection of the chip area 140 of the hard mask 100 on the first surface 101.

[0198] In one embodiment, the supporting substrate 310 is a supporting ring.

[0199] In one embodiment, Figure 22-Figure 23 As shown, the fastening structure 350 is a screw, and corresponding screw holes are provided at positions of the supporting bottom layer 310 and the reinforcing top layer 320 corresponding to the fastening structure 350 .

[0200] In one embodiment, Figure 24-25 As shown, Fig.25 for Fig.24 Side profile of Fig.24 DD' in the figure, the coating jig further includes a bead 370, the bead 370 is located above the position corresponding to the scribing street area 150 on the hard mask 100, and the bead 370 is fixedly connected to the reinforcement top layer 320. Specifically, when the height or width of the bead 370 on the hard mask 100 causes obstruction to the coating process, the height and width of the bead 370 can be adjusted to ensure that the setting of the bead 370 does not affect the coating process.

[0201] The present invention further improves the clamping reliability between the hard mask 100 and the MEMS wafer 200 by setting the pressure bar 370 in the dicing area 150; at the same time, by setting the height and width of the pressure bar 370, the obstruction of the coating process caused by the height formed by the pressure bar 370 on the surface of the hard mask 100 is reduced to ensure the uniformity of the coating.

[0202] In one embodiment, the minimum distance between the pressing bar 370 and the projection of the chip region 140 of the hard mask 100 on the first surface 101 is 1 cm.

[0203] Specifically, Figure 22-Figure 23 As shown, when the width of the dicing street area 150 itself is relatively narrow, the pressure bar 370 may not be provided.

[0204] In one embodiment, the pressure strip 370 and the reinforcement top layer 320 are an integrated structure.

[0205] Embodiment 6:

[0206] This embodiment provides an application method of a hard mask 100, wherein the application method uses the hard mask 100 described in any one of Embodiments 1-2, and the application method includes:

[0207] Providing a MEMS wafer 200 to be aligned, wherein the upper surface of the MEMS wafer 200 includes a second engaging microstructure 201 corresponding to the first engaging microstructure 161 of the hard mask 100;

[0208] The hard mask 100 is engaged and aligned with the second engaging microstructure 201 of the MEMS wafer 200 through the first engaging microstructure 161;

[0209] The hard mask 100 and the MEMS wafer 200 that are aligned and locked are placed in the coating fixture described in Example 5 for fastening;

[0210] Performing a coating process of a micro-mirror 203 on the MEMS wafer 200 from the first surface 101 of the hard mask 100;

[0211] After the micro-mirrors 203 are plated in the corresponding plated through holes 120 of the MEMS wafer 200 , the plated jig is opened and the hard mask 100 is removed.

[0212] The present invention improves the alignment accuracy between the hard mask 100 and the MEMS wafer 200 by setting the microstructure of the hard mask 100 and cooperating with the coating fixture. At the same time, the structure of the hard mask 100 itself is adjusted to improve the uniformity of the coating and maximize the effective use area of ​​the micro-mirror.

[0213] In summary, the hard mask and its preparation method, application method and coating jig of the present invention can avoid the problem of uneven coating caused by the edge of the coating through hole being blocked by setting a coating step on the side wall of the coating through hole of the hard mask, and ensure the mechanical strength of the hard mask; at the same time, a locking microstructure corresponding to the MEMS wafer is set on the hard mask to achieve precise positioning and improve the coating position accuracy; in addition, the height of the connection area between multiple coating through holes in the chip area is set to avoid the coating blocking of the connection area between the coating through holes with small spacing, resulting in uneven coating, and ensure the mechanical strength of the connection area; finally, a coating jig is set to tightly position the aligned hard mask and MEMS wafer to improve the coating position accuracy.

[0214] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0215] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A hard mask, characterized in that: The hard mask plate includes a first surface and a second surface arranged opposite to each other, and the hard mask plate also includes more than one chip area, each of the chip areas includes more than one plated through hole, and each of the plated through holes passes through the first surface and the second surface; The side wall of each of the coated through holes is provided with a stepped structure, the bottom surface of the stepped structure is flush with the second surface, and the stepped structure of each of the coated through holes includes more than one coated step, and the distance between the tread of the coated step and the second surface is smaller than the distance between the first surface and the second surface.

2. The hard mask according to claim 1, wherein: When each of the chip areas includes a plated through hole, a scribing street area is arranged between two adjacent chip areas, and two adjacent plated through holes are connected to the scribing street area through the stepped structure of two side walls, the distance from the top surface of the scribing street area to the second surface is greater than the distance from the tread of the plated step farthest from the plated through hole to the second surface, the distance from the top surface of the scribing street area to the second surface is less than or equal to the distance from the first surface to the second surface, and the bottom surface of the scribing street area is flush with the second surface.

3. The hard mask according to claim 2, wherein: Each of the step structures further comprises a first step, the tread of the first step is flush with the first surface, and the line where the tread of the first step intersects with the riser is the first line; when the step structure comprises only one of the coated steps, the line where the tread of the coated step intersects with the riser is the second line, and the surface where the first line and the second line are located is the corresponding slope of the step structure; When the step structure includes more than two coated steps, the line where the tread and the riser of each coated step in each of the step structures intersect is a step line, and the distance between the step line of the coated step away from the coated through hole and the second surface decreases successively from the distance between the step line and the second surface toward the distance between the step line and the second surface. The first line and the step line of each coated step are coplanar, and the surface where the first line and the step line are located is the corresponding slope surface of the step structure; The angle between the slope surface and the second surface is θ; The hard mask is used for the coating process of the micro-mirror surface of the MEMS wafer, and the coating through hole includes a preset coating area and an additional exposure area. The preset coating area is the area of ​​the micro-mirror surface of the MEMS wafer preset for coating, and the additional exposure area is the area within the coating through hole but beyond the preset coating area; the curved surface perpendicular to the first surface through the boundary of the preset coating area is the reference curved surface, the minimum vertical distance between the riser of the coating step and / or the first step and the reference curved surface is Δx, and the corresponding distance between the tread of the coating step and / or the first step and the second surface is H, Δx>Htan(90°-θ).

4. The hard mask according to claim 1, wherein: When each of the chip areas includes more than two of the plated through holes, a scribe line area is provided between two adjacent chip areas, and the distance from the top surface of the scribe line area to the second surface is greater than the distance from the tread of the plated step farthest from the plated through hole to the second surface; a connection area is provided between two adjacent plated through holes in the same chip area, and the distance from the top surface of the connection area to the bottom surface of the connection area is less than the distance from the first surface to the second surface, and the distance from the top surface of the connection area to the bottom surface of the connection area is greater than the distance from the tread of the plated step closest to the plated through hole to the second surface, and the bottom surface of the connection area is flush with the second surface.

5. The hard mask according to claim 4, wherein: Each of the step structures further comprises a first step, the tread of the first step of the step structure in contact with the connection area is the top surface of the connection area, the tread of the first step of the step structure not in contact with the connection area is flush with the first surface, and the line where the tread of the first step intersects with the riser is the first line; When the step structure includes only one coated step, the line where the tread and riser of the coated step intersect is the second line, and the surface where the first line and the second line are located is the corresponding slope of the step structure; When the step structure includes more than two coated steps, the line where the tread and the riser of each coated step in each of the step structures intersect is a step line, and the distance between the step line of the coated step away from the coated through hole and the second surface decreases successively from the distance between the step line and the second surface toward the distance between the step line and the second surface. The first line and the step line of each coated step are coplanar, and the surface where the first line and the step line are located is the corresponding slope surface of the step structure; The angle between the slope surface and the second surface is θ; The hard mask is used for the coating process of the micro-mirror surface of the MEMS wafer, and the coating through hole includes a preset coating area and an additional exposure area. The preset coating area is the area of ​​the micro-mirror surface of the MEMS wafer preset for coating, and the additional exposure area is the area within the coating through hole but beyond the preset coating area; the curved surface perpendicular to the first surface through the boundary of the preset coating area is the reference curved surface, the minimum vertical distance between the riser of the coating step and / or the first step and the reference curved surface is Δx, and the corresponding distance between the tread of the coating step and / or the first step and the second surface is H, Δx>Htan(90°-θ).

6. The hard mask according to any one of claims 1 to 5, characterized in that: The hard mask also includes a non-chip area, and the second surface of the non-chip area is provided with more than two first locking microstructures. The positions of the first locking microstructures of the hard mask can be locked and aligned with the corresponding second locking microstructures on the MEMS wafer to be aligned with the hard mask.

7. A method for preparing a hard mask, characterized in that: The preparation method is used to prepare the hard mask according to any one of claims 1 to 6, and the preparation method comprises: Providing an SOI structure, wherein the SOI structure comprises, from bottom to top, a substrate layer, a buried oxide layer and a top layer of single crystal silicon, wherein the lower surface of the substrate layer is the first surface of the SOI structure, and the upper surface of the top layer of single crystal silicon is the second surface of the SOI structure; Disposing a first groove on the lower surface of the substrate layer of the SOI structure; A second groove is provided on the upper surface of the top monocrystalline silicon of the SOI structure, wherein the projection of the first groove on the first surface is located within the projection of the second groove on the first surface; One or more third grooves are continuously arranged on the bottom surface of the second groove in a direction close to the buried oxide layer, the buried oxide layer is exposed by the third grooves, the third grooves form plated through holes, and the projection of the third grooves on the first surface is located within the projection of the first groove on the first surface; A fourth groove is provided on the bottom surface of the first groove in a direction close to the buried oxide layer. The fourth groove passes through the buried oxide layer. The fourth groove, the first groove and the third groove form a stepped structure.

8. The method for preparing a hard mask according to claim 7, characterized in that: The fourth groove coincides with the projection of the first groove on the first surface, the fourth groove and the first groove constitute a first through groove, and the connection area between any two adjacent first through grooves is flush with the first surface; the projection of the third groove on the first surface is located within the projection of the first through groove on the first surface; Or the projections of two or more adjacent fourth grooves on the first surface are located within the projection of the first groove on the first surface, so that the connecting area between the adjacent fourth grooves in the corresponding area is flush with the bottom surface of the first groove; the projection of the third groove on the first surface is located within the projection of the fourth groove on the first surface.

9. A coating fixture, characterized in that: The coating jig is used to temporarily fix the hard mask described in any one of claims 1 to 6 and the MEMS wafer aligned and clamped with the hard mask after positioning and clamping, and the coating jig includes: a supporting bottom layer, a reinforcing top layer, a reinforcing spring sheet and a fastening structure; The supporting bottom layer and the reinforcing top layer are both provided with a hollow area and a pressing area, the hollow area is used to expose the surfaces corresponding to the chip area of ​​the hard mask and the MEMS wafer, and the pressing area is used to fasten the hard mask and the MEMS wafer after being clamped; a detachable fastening structure is provided between the supporting bottom layer and the reinforcing top layer outside the hollow area and the pressing area, and the fastening structure can fasten the supporting bottom layer and the reinforcing top layer with the clamped hard mask and the MEMS wafer placed in the middle; The reinforcing spring sheet is located above the reinforcing top layer, and the reinforcing spring sheet includes a fixing portion and an elastic portion. The fastening structure fastens the reinforcing spring sheet to the reinforcing top layer via the fixing portion, and the elastic portion of the reinforcing spring sheet can apply a rebound force to the reinforcing top layer.

10. A method for applying a hard mask, characterized in that: The application method uses the hard mask described in claim 6, and the application method comprises: Providing a MEMS wafer to be aligned, wherein the upper surface of the MEMS wafer includes a second engaging microstructure corresponding to the first engaging microstructure of the hard mask; Aligning the hard mask with the second engaging microstructure of the MEMS wafer through the first engaging microstructure; Placing the hard mask and the MEMS wafer that are aligned and locked in place in the coating fixture described in claim 9 for fastening; Performing a micro-mirror coating process on the MEMS wafer from the first surface of the hard mask; After micro-mirrors are plated in the corresponding plated through holes of the MEMS wafer, the plated fixture is opened and the hard mask is removed.

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