Preparation method of nanowire channel and detection chip
By forming concave and convex nanowire channels on the detection chip, the problem of insufficient detection performance of the existing detection chip is solved, and higher sensitivity and detection upper limit are achieved, which simplifies the process and improves operability.
Patent Information
- Application Number
- CN202310800035.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-30
- Publication Date
- 2024-12-31
AI Technical Summary
The detection performance of existing detection chips has not yet reached the optimal level, especially in biological or environmental detection, and the detection performance needs to be improved to achieve higher sensitivity and detection limits.
By forming a first dielectric layer on the substrate and depositing a second dielectric layer thereon, adding conductive particles and foaming components, a porous conductive layer is formed, and a nanowire channel is formed through a patterning process so that its outer wall is Concave and convex shape, thereby increasing the surface area to attach more sensitive probes.
By increasing the surface area of the nanowire channel, the detection performance of the detection chip is improved, including higher sensitivity and detection upper limit, and the process of porous conductive layer is simplified and operability is improved.
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Figure CN119224054A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a nanowire channel and a detection chip. Background Art
[0002] As a common device in the field of semiconductor technology, field effect transistors have many advantages. Compared with traditional sensors (such as sensors using electrodes), applying field effect transistors to the detection field to prepare detection chips can not only make the detection chip have an extremely small size, but also improve its detection performance.
[0003] Taking the detection chip used for biological or environmental detection as an example, it has a structure similar to that of a field effect transistor, including a source terminal, a drain terminal and a channel between the source and drain terminals on a substrate, and a probe is arranged on the surface of the channel to combine with the sample to be detected to achieve detection through a slight change in resistance or potential. However, the detection performance of the above detection chip can be further improved. Summary of the invention
[0004] The purpose of the present invention is to provide a method for preparing a nanowire channel and a detection chip, thereby increasing the surface area of the nanowire channel and improving the performance of the detection chip.
[0005] In order to solve the above technical problems, the present invention provides a method for preparing a nanowire channel, comprising:
[0006] Providing a substrate, wherein a first dielectric layer is covered on the surface of the substrate;
[0007] Depositing a second dielectric layer, doping conductive particles and adding foaming components during the deposition of the second dielectric layer to form a porous conductive layer covering the second dielectric layer, wherein the material of the second dielectric layer is different from that of the first dielectric layer;
[0008] A patterning process is performed on the porous conductive layer to form a plurality of nanowire channels, wherein the outer walls of the nanowire channels are concave-convex.
[0009] Optionally, the second dielectric layer includes a low-K dielectric and / or an ultra-low-K dielectric.
[0010] Optionally, the first dielectric layer and the second dielectric layer are formed by a vapor deposition process, and the first dielectric layer and the second dielectric layer are formed in-situ in the same process chamber.
[0011] Optionally, the material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes one or any combination of silicon oxycarbide, silicon carbide hydroxide, or silicon oxycarbonitride.
[0012] Optionally, a process temperature for depositing the first dielectric layer is greater than or equal to a process temperature for depositing the second dielectric layer, and a gas pressure for depositing the second dielectric layer is greater than or equal to a gas pressure for depositing the first dielectric layer.
[0013] Optionally, the foaming component includes a silicon-containing precursor and a foaming agent.
[0014] Optionally, the silicon-containing precursor includes methyldiethoxysilane, the foaming agent includes α-terpinene, the process temperature for forming the porous conductive layer is 150° C. to 300° C., and the gas pressure is 5 Torr to 10 Torr.
[0015] Optionally, the conductive particles include metal organic matter.
[0016] Optionally, the step of patterning the porous conductive layer includes:
[0017] forming a patterned photoresist layer on the porous conductive layer;
[0018] The patterned photoresist layer is used to perform a dry etching process on the porous conductive layer with the first dielectric layer as an etching stop layer to form the nanowire channel.
[0019] According to another aspect of the present invention, a detection chip is also provided, comprising:
[0020] substrate;
[0021] A first dielectric layer covering the surface of the substrate;
[0022] A plurality of nanowire channels are arranged on the first dielectric layer and the outer walls of the nanowire channels are concave-convex. The nanowire channels are formed by a porous conductive layer formed by a second dielectric layer in situ doped with conductive particles and adding a foaming component, and the material of the second dielectric layer is different from that of the first dielectric layer.
[0023] In summary, the present invention forms a first dielectric layer on a substrate, and then deposits a second dielectric layer to cover the first dielectric layer, and dopes conductive particles and adds a foaming component during the deposition of the second dielectric layer to form a porous conductive layer, and then performs a patterning process on the porous conductive layer to form a number of nanowire channels, the outer wall of the nanowire channel is concave-convex, and the concave-convex outer surface of the nanowire channel is used to make the nanowire channel have a larger surface area than the relatively flat outer wall under the same size, and also by adding conductive particles and foaming components in situ during the deposition of the second dielectric layer, the process of forming the porous conductive layer has the advantages of simplicity and strong operability. The detection chip made of the nanowire channel can attach more sensitive probes by virtue of its higher specific surface area, thereby improving the performance of the detection chip, and the outer wall of the above-mentioned nanowire channel is relatively uneven, which is more conducive to the attachment of sensitive probes than the relatively flat outer wall. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.
[0025] Figure 1 is a flow chart of a method for preparing a nanowire channel provided in Example 1;
[0026] Figure 2a to Figure 2e This is a schematic structural diagram corresponding to the corresponding steps of the method for preparing the nanowire channel provided in Example 1.
[0027] In the attached figure:
[0028] 10 - substrate; 11 - first dielectric layer; 20 - porous conductive layer; 21 - holes; 22 - patterned photoresist layer; 23 - nanowire channel; 24 - pits. DETAILED DESCRIPTION
[0029] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0030] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0031] Embodiment 1
[0032] Embodiment 1 provides a method for preparing a nanowire channel.
[0033] Figure 1 This is a flow chart of the method for preparing a nanowire channel provided in Example 1.
[0034] like Figure 1 As shown, the method for preparing the nanowire channel provided in this embodiment includes:
[0035] S01: providing a substrate, wherein a first dielectric layer is covered on a surface of the substrate;
[0036] S02: depositing a second dielectric layer, doping conductive particles and adding foaming components during the deposition of the second dielectric layer to form a porous conductive layer covering the second dielectric layer, wherein the material of the second dielectric layer is different from that of the first dielectric layer;
[0037] S03: performing a patterning process on the porous conductive layer to form a plurality of nanowire channels, wherein the outer walls of the nanowire channels are concave-convex.
[0038] Figure 2a to Figure 2e The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the nanowire channel provided in Example 1 is shown below. Figure 2a to Figure 2e The preparation method of the nanowire channel is described in detail.
[0039] First, please refer to Figure 2a , perform step S01, provide a substrate, and a first dielectric layer is covered on the surface of the substrate.
[0040] The material of the substrate 10 may include any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, glass, quartz, and plastic, etc. The first dielectric layer 11 may include any suitable insulating material, such as silicon oxide or silicon nitride, etc., and may be formed on the surface of the substrate 10 using any suitable process.
[0041] Next, please refer to Figure 2b , executing step S02, depositing a second dielectric layer, doping conductive particles and adding foaming components during the deposition of the second dielectric layer to form a porous conductive layer 20 covering the second dielectric layer, the material of the second dielectric layer is different from that of the first dielectric layer 11.
[0042] The second dielectric layer may include a low-K dielectric (dielectric constant of 3.9 to 2.8) and / or an ultra-low-K dielectric (dielectric constant of 2.8 to 2.2) to provide a relatively loose substrate for forming the porous conductive layer 20, so as to facilitate the formation of a porous structure and facilitate the addition of conductive particles and foaming components. The material of the second dielectric layer is different from that of the first dielectric layer 11, so that the first dielectric layer 11 can be used as an etching stop layer when etching the second dielectric layer (porous conductive layer 20). In a preferred embodiment, the first dielectric layer 11 and the second dielectric layer can be formed by a vapor deposition process, and the second dielectric layer can be formed in situ on the first dielectric layer 11, that is, the first dielectric layer 11 and the second dielectric layer are formed in sequence in the same process chamber to simplify the process and improve the preparation efficiency. In addition, the process temperature for depositing the second dielectric layer can be less than or equal to the process temperature for depositing the first dielectric layer 11, and the gas pressure for depositing the second dielectric layer can be greater than or equal to the gas pressure for depositing the first dielectric layer 11, so as to improve the film density of the first dielectric layer 11 and reduce the film density of the second dielectric layer.
[0043] Conductive particles can be added in situ during the vapor deposition of the second dielectric layer, and may include conductive metal-based compounds, such as metal organics, in which the metal may be niobium, zinc, titanium or silver, etc. Similarly, foaming components can also be added in situ during the vapor deposition of the second dielectric layer, and may include two components input simultaneously, such as a silicon-containing precursor and a foaming agent, which react in the second dielectric layer (during the deposition process) to form pores 21 to achieve a foaming effect, thereby forming a porous structure.
[0044] Taking the material of the first dielectric layer 11 as an example, the material of the second dielectric layer may include one or any of silicon oxide, silicon hydroxide or silicon oxynitride. Specifically, in the present embodiment, the material of the first dielectric layer 11 may include silicon oxide, the material of the second dielectric layer may include silicon oxide, the process temperature for depositing the second dielectric layer may be 150° C. to 300° C., and the gas pressure may be 5 Torr to 10 Torr. The doped conductive particles may be metal organics, and their metal bases may include, for example, Nb-TiO2 or Zn-TiO2. The silicon-containing precursor of the foaming component may be DEMS (methyl diethoxysilane), and the foaming agent may be ATRP (α-terpinene). In this way, the second dielectric layer can be formed to be looser, porous (porous structure) and conductive, and used as the porous conductive layer 20. It should be understood that, compared with introducing conductive particles by ion implantation after forming the second dielectric layer, this embodiment introduces conductive particles by in-situ doping during the deposition of the second dielectric layer, which is not only conducive to uniform distribution of conductive particles in the second dielectric layer, but also avoids destroying the porous structure formed by the second dielectric layer.
[0045] Next, step S03 is performed to perform a patterning process on the porous conductive layer 20 to form a plurality of nanowire channels 23 , wherein the outer walls of the nanowire channels 23 are concave-convex.
[0046] For details, please refer to Figure 2c , a patterned photoresist layer 22 is formed on the porous conductive layer 20. The patterned photoresist layer 22 may include a plurality of photoresist lines arranged in parallel.
[0047] Please refer to Figure 2d and Figure 2e , using the patterned photoresist layer 22 as a mask and the first dielectric layer 11 as an etching stop layer, a dry etching process is performed on the porous conductive layer 20 to form a plurality of conductive lines, and the conductive lines are used as nanowire channels 23. Among them, the holes 21 on the outer walls (top walls and side walls) of the conductive lines formed after etching are partially etched and exposed to form a plurality of pits 24, so that the outer wall of the nanowire channel 23 is uneven. Compared with the conductive lines with relatively flat outer walls, the nanowire channel 23 with an uneven outer wall has a larger surface area. Among them, Figure 2d The cross-sectional schematic diagram of the porous conductive layer after etching provided in this embodiment, Figure 2e for Figure 2d Top view of the .
[0048] In addition, after dry etching, a dry cleaning process may be used to remove the patterned photoresist layer 22 remaining on the nanowire channel 23. The dry cleaning process may be, for example, an ashing process.
[0049] Embodiment 2
[0050] Embodiment 2 provides a detection chip.
[0051] The detection chip provided in this embodiment is used to detect a sample to be detected, and the sample to be detected may be a sample in the biological field or the environmental field, that is, the detection chip provided in this embodiment is used for biological detection or environmental detection. In this embodiment, the detection chip may include a substrate, a first dielectric layer and a nanowire channel. The first dielectric layer covers the surface of the substrate. A plurality of nanowire channels are arranged at intervals and are arranged on the second dielectric layer. In addition, a sensitive probe may be arranged on the exposed outer wall of the nanowire channel for combining with the sample to be detected to achieve the corresponding detection function.
[0052] The outer wall of the nanowire channel exposed on the second dielectric layer has a plurality of pits, and the above-mentioned pitted nanowire channel is formed by a porous conductive layer formed by in-situ doping of conductive particles and adding a foaming component to the second dielectric layer, so that the nanowire channel in the detection chip has a larger surface area than the conductive wire with a flatter outer wall, so that the detection chip of the same size can be modified (attached) with more sensitive probes, thereby improving the performance of the detection chip, including a higher detection limit and a higher detection sensitivity. Moreover, the outer wall of the above-mentioned nanowire channel is relatively uneven, which is more conducive to the attachment of sensitive probes than a flatter outer wall.
[0053] In summary, the present invention forms a first dielectric layer on a substrate, and then deposits a second dielectric layer to cover the first dielectric layer, and dopes conductive particles and adds a foaming component during the deposition of the second dielectric layer to form a porous conductive layer, and then performs a patterning process on the porous conductive layer to form a number of nanowire channels, the outer wall of the nanowire channel is concave-convex, and the concave-convex outer surface of the nanowire channel is used to make the nanowire channel have a larger surface area than the relatively flat outer wall under the same size, and also by adding conductive particles and foaming components in situ during the deposition of the second dielectric layer, the process of forming the porous conductive layer has the advantages of simplicity and strong operability. The detection chip made of the nanowire channel can attach more sensitive probes by virtue of its higher specific surface area, thereby improving the performance of the detection chip, and the outer wall of the above-mentioned nanowire channel is relatively uneven, which is more conducive to the attachment of sensitive probes than the relatively flat outer wall.
[0054] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for preparing a nanowire channel, characterized in that: include: Providing a substrate, wherein a first dielectric layer is covered on the surface of the substrate; Depositing a second dielectric layer, doping conductive particles and adding foaming components during the deposition of the second dielectric layer to form a porous conductive layer covering the second dielectric layer, wherein the material of the second dielectric layer is different from that of the first dielectric layer; A patterning process is performed on the porous conductive layer to form a plurality of nanowire channels, wherein the outer walls of the nanowire channels are concave-convex.
2. The method for preparing a nanowire channel according to claim 1, characterized in that: The second dielectric layer includes a low-K dielectric and / or an ultra-low-K dielectric.
3. The method for preparing a nanowire channel according to claim 1, characterized in that: The first dielectric layer and the second dielectric layer are formed by using a vapor deposition process, and the first dielectric layer and the second dielectric layer are formed in-situ in the same process chamber.
4. The method for preparing a nanowire channel according to claim 1, characterized in that: The material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes one or more of silicon oxycarbide, silicon carbide hydroxide, or silicon oxycarbonitride.
5. The method for preparing a nanowire channel according to claim 1, characterized in that: The process temperature for depositing the first dielectric layer is greater than or equal to the process temperature for depositing the second dielectric layer, and the gas pressure for depositing the second dielectric layer is greater than or equal to the gas pressure for depositing the first dielectric layer.
6. The method for preparing a nanowire channel according to claim 1, characterized in that: The foaming components include a silicon-containing precursor and a foaming agent.
7. The method for preparing a nanowire channel according to claim 6, characterized in that: The silicon-containing precursor includes methyldiethoxysilane, the foaming agent includes α-terpinene, the process temperature for forming the porous conductive layer is 150° C. to 300° C., and the gas pressure is 5 Torr to 10 Torr.
8. The method for preparing a nanowire channel according to claim 1, characterized in that: The conductive particles include metal organic matter.
9. The method for preparing a nanowire channel according to claim 1, characterized in that: The step of patterning the porous conductive layer comprises: forming a patterned photoresist layer on the porous conductive layer; The patterned photoresist layer is used to perform a dry etching process on the porous conductive layer with the first dielectric layer as an etching stop layer to form the nanowire channel.
10. A detection chip, characterized in that: include: substrate; A first dielectric layer covering the surface of the substrate; A plurality of nanowire channels are arranged on the first dielectric layer and the outer walls of the nanowire channels are concave-convex. The nanowire channels are formed by a porous conductive layer formed by a second dielectric layer in situ doped with conductive particles and adding a foaming component, and the material of the second dielectric layer is different from that of the first dielectric layer.