Programmable delay test circuit

Abstract

The invention relates to a programmable delay test circuit. An integrated circuit includes a test circuit, an analog delay circuit, and a sampler register, each configured to receive a signal. The delay circuit includes a configuration input and a phase having a final phase. The sampler register includes a result output and delayed inputs, each coupled to a respective delayed output of the phase. The sampler register is configured to output a sampled signal indicative of a relationship between the signal and at least a final one of the phases. The integrated circuit also includes a test circuit including a configuration output coupled to the configuration input of the delay circuit and including a result input coupled to the result output of the sampler register. The test circuit is configured to iterate the selected values to test the delay circuit and determine that the delay circuit passes the test when the relationship matches a predetermined criterion.

Description

Technical Field

[0001] The present invention generally relates to testing of integrated circuits, and in a specific embodiment, to the structure of a test circuit for testing a programmable delay circuit and a method of operating the same. Background Art

[0002] Integrated circuits (ICs) require testing to verify correct operation. ICs are becoming increasingly complex and contain a mix of digital and analog logic that requires rigorous defect assessment during characterization and testing in production. For example, many parts of the circuit, such as analog circuits of a system-on-chip (SoC), require specific test techniques and time-consuming setups. In addition, many ICs are used in critical applications, such as automotive, and require very high quality and safety levels.

[0003] During testing, the IC can be placed on a test bench, and the test engineer can use external test equipment (e.g., automatic test equipment (ATE)) to implement specific test techniques. The test process can include writing a test program to enhance some input controls and then measuring some outputs (e.g., outputs from a model). However, this arrangement can be time consuming. For example, each time an external test device is relied upon, there is setup time for the test engineer and additional delays, such as instrument stabilization time. In addition, external test equipment may introduce more variability to the test process, which may increase the possibility of errors during the test procedure.

[0004] Therefore, there may be a need for a faster method to test features of an IC (such as an analog block) while reducing the possibility of errors, reducing the complexity of the setup, and without the need to write a test program. Summary of the invention

[0005] According to one embodiment of the present invention, an integrated circuit includes an analog delay circuit, the analog delay circuit including a plurality of delay phases, a delay configuration input, and a signal input, the signal input being configured to receive a signal to be delayed. The plurality of delay phases include an initial delay phase and a final delay phase. The integrated circuit also includes a sampler register, the sampler register including a signal input configured to receive a signal to be delayed, a plurality of test result outputs, and a plurality of delay inputs, each of the plurality of delay inputs being coupled to a corresponding delay output of the plurality of delay phases. The sampler register is configured to output a sampled signal, the sampled signal indicating a relationship between the signal to be delayed and at least a final delay phase of the plurality of delay phases. The integrated circuit also includes a test circuit, the test circuit including a delay configuration output coupled to the delay configuration input of the analog delay circuit, and including a plurality of test result inputs coupled to a plurality of test result outputs of the sampler register. The test circuit is configured to test the analog delay circuit by iterating through a plurality of selected delay values ​​provided to the analog delay circuit at the delay configuration input, and in response to receiving the sampled signal at the plurality of test result inputs, determine that the analog delay circuit passes the test by determining that the relationship matches a predetermined criterion.

[0006] According to another embodiment of the present invention, a built-in self-test (BIST) circuit includes a sampler register, the sampler register includes a signal input configured to receive a signal to be delayed, a plurality of test result outputs, and a plurality of delay inputs, each of the plurality of delay inputs being configured to be coupled to a corresponding delay output of a plurality of delay phases of an analog delay circuit. The sampler register is configured to output a sampled signal, the sampled signal indicating a relationship between the signal to be delayed and at least a final delay phase of the plurality of delay phases. The BIST circuit also includes a finite state machine circuit, the finite state machine circuit including: a delay configuration output configured to be coupled to a delay configuration input of the analog delay circuit, a plurality of test result inputs coupled to the plurality of test result outputs of the sampler register, and a test data register coupled to the finite state machine circuit. The finite state machine circuit is configured to: iterate through a plurality of selected delay values ​​provided to the analog delay circuit at the delay configuration input to test the analog delay circuit; in response to receiving the sampled signal at the plurality of test result inputs, determine that the analog delay circuit passes the test by determining that the relationship matches a predetermined criterion; and output delay tuning data, the delay tuning data indicating a selected delay value among the plurality of selected delay values, the selected delay value being associated with matching the predetermined criterion. The test data register is configured to store a status flag of the finite state machine circuit and to store delay tuning data.

[0007] According to another embodiment of the present invention, a method for testing an analog delay circuit of an integrated circuit includes: receiving a signal to be delayed at a signal input of the analog delay circuit, and receiving the signal to be delayed at a signal input of a sampler register of the integrated circuit. The analog delay circuit includes a delay configuration input and a plurality of delay phases, the plurality of delay phases including an initial delay phase and a final delay phase. The sampler register includes a plurality of test result outputs and a plurality of delay inputs, the plurality of delay inputs each being coupled to a corresponding output of the plurality of delay phases. The method also includes: outputting a sampling signal from the sampler register, the sampling signal indicating a relationship between the signal to be delayed and at least the final delay phase of the plurality of delay phases; iterating through a plurality of selected delay values ​​provided to the analog delay circuit at the delay configuration input by the delay configuration output of the test circuit of the integrated circuit to test the analog delay circuit; and in response to receiving the sampling signal at the plurality of test result inputs, determining that the analog delay circuit passes the test by determining that the relationship matches a predetermined criterion. The test circuit includes a plurality of test result inputs, the plurality of test result inputs being coupled to the plurality of test result outputs of the sampler register. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 An example integrated circuit according to an embodiment of the present invention is illustrated, the integrated circuit comprising an analog delay circuit, a test circuit configured to test the analog delay circuit, and a sampler register configured to output a sampled signal indicating a relationship between a signal to be delayed and at least a final delayed phase of the analog delay circuit;

[0010] Figure 2 An example integrated circuit according to an embodiment of the present invention is illustrated, the integrated circuit including an analog delay circuit having a sampler register configured to output a sampling signal indicative of a relationship between a signal to be delayed and at least a final delayed phase of the analog delay circuit, and including a test circuit implemented as a built-in self-test finite state machine and configured to test the analog delay circuit;

[0011] Figure 3 illustrates a state diagram conceptually depicting the behavior of an example finite state machine configured to test an analog delay circuit in accordance with an embodiment of the present invention;

[0012] Figure 4 An example integrated circuit according to an embodiment of the present invention is illustrated, the integrated circuit comprising an analog delay circuit having a delay line of delay phases, the delay phases comprising an initial delay phase and a final delay phase and optional intermediate delay phases therebetween;

[0013] Figure 5 An example schematic timing diagram of a tuned delay signal and an example schematic timing diagram of an untuned delay signal according to an embodiment of the present invention are illustrated, wherein the delay signal includes N delay phases;

[0014] Figure 6 Another example schematic timing diagram of a tuned delay signal and an example schematic timing diagram of an untuned delay signal according to an embodiment of the present invention are illustrated, wherein the delay signal includes 12 delay phases;

[0015] Figure 7 illustrates another example schematic timing diagram of a tuned delay signal and an example schematic timing diagram of an untuned delay signal according to an embodiment of the present invention, wherein the delay signal includes 6 delay phases and bitmasking is used; and

[0016] Figure 8 An example method of testing an analog delay circuit of an integrated circuit according to an embodiment of the present invention is illustrated.

[0017] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the range of the features. DETAILED DESCRIPTION

[0018] The making and using of various embodiments are discussed in detail below. However, it should be understood that the various embodiments described herein can be applied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways to make and use the various embodiments, and should not be construed as limiting the scope. Unless otherwise specified, the expressions "approximately," "approximately," and "substantially" mean within 10% of a given value, and preferably within 5% of a given value, or, such as in the case of substantially zero, less than 10% of a comparable amount and preferably less than 5% of a comparable amount.

[0019] Today, integrated circuits (ICs), such as automotive ICs, are growing in complexity, requiring high levels of quality (e.g., with a 0 ppm undetected defect rate target) and safety (e.g., meeting a specific automotive safety integrity level (ASIL)). This results in a significant increase in automated test equipment (ATE) testing costs in terms of test time (e.g., due to the large number of tests to be performed) and resources (e.g., because complex systems on a chip (SoCs) are typically equipped with a large number of analog circuits, the functionality of which must be verified using a specialized design for test (DFT) architecture).

[0020] Conventional methods for DFT of analog circuits (such as programmable analog delay circuits) rely on ATE methods, in which each test step is configured by setting the circuit under test to test mode to access the configuration of the circuit through a test manager inside the device. However, the input is ultimately still provided from the SoC pins. Specifically, in conventional ATE methods for measuring programmable analog delay circuits, each step of the input-to-output delay generated by the delay circuit is configured through a Joint Test Action Group (JTAG) interface, such as by programming a dedicated test data register (TDR). The values ​​in the TDR can be used to override the function / control of the circuit. The phase between the input signal and the output signal is measured by driving the input signal and observing the output delay signal on a dedicated test pad or using some kind of signal timestamp / sampling.

[0021] Conventional ATE methods for input-to-output delay measurements have the disadvantage of being time consuming and cumbersome (looping JTAG programming combined with measurements at each delay step results in longer test times). Conventional ATE also has the limitation of not being able to observe high frequency (e.g., greater than about 80MHz-100MHz) signals on the test pads (e.g., due to parasitic capacitance). In addition, the propagation delays from the input pads to the circuit under test and from the circuit under test to the output pads must be evaluated to understand the impact on the phase shift measurement.

[0022] Another conventional approach to DFT of analog circuits (such as programmable analog delay circuits) is the functional approach, in which the circuit under test is tested while operating in a functional mode. In the functional approach, the circuit under test must be configured by writing to functional registers and then tested using an application-like setup. However, the functional approach provides less control and flexibility because the test is performed in a functional mode. In addition, functional configuration of the circuit under test is difficult in a test environment.

[0023] Due to these shortcomings of conventional methods, IC device testing is becoming a bottleneck of profitability. Therefore, the following DFT solution is being attempted to be designed, which reduces the required test time and / or required ATE resources. Built-in self-test (BIST) technology can help solve these problems. When the conventional ATE test procedure of the specific circuit of IC needs to repeat many measurements in a cycle, wherein the configuration is changed before each new measurement, the advantage of the BIST solution can be more obvious. An example of this situation is the test of a programmable analog delay circuit. This circuit can be configured to generate a programmable delay between a programmable delay signal such as an input (e.g., clock, synchronization, protocol, etc.) and a related output signal, until a specific phase shift condition is met.

[0024] The programmable delay of the programmable analog delay circuit can be generated by introducing a programmable skew amount. Testing this may be time-consuming because configuration code must be generated to produce a given delay on the output signal. From a practical point of view, these codes can be manually studied by a test programmer and written by a test engineer to sequentially configure the circuit in a desired manner so that the output can be measured relative to the input (e.g., measuring the delay). If the required conditions (e.g., specification conditions) are not met, the test can continue further. For example, another configuration code for generating another input-to-output delay can be determined, and so on, until the desired delay between the input and the output is met.

[0025] As described above, a common approach may be to program the configuration of JTAG, measure the phase shift between the input signal and the output signal, and observe the delayed output on a dedicated test pad. This approach requires access pads for both specific test purposes and specific test modes. The pad must be connected to the circuit under test in order to be stimulated by the test equipment (e.g., ATE).

[0026] In view of the above shortcomings, it is desirable to automate the testing process. Relying on internal logic for testing (e.g., including functional logic that can also be used for testing) can advantageously speed up testing time and reduce the amount of resources required for testing. Some or all of the above shortcomings are overcome by a custom test architecture that can be used to test any device (e.g., an integrated circuit) that includes analog circuits configured to produce programmable input-to-output delays.

[0027] In various embodiments, an integrated circuit includes an analog delay circuit, a sampler register, and a test circuit (e.g., a BIST circuit including a finite state machine (FSM)). The analog delay circuit has a delay configuration input, a signal input configured to receive a signal to be delayed, and a plurality of delay phases, the plurality of delay phases including at least an initial delay phase and a final delay phase. For example, the signal to be delayed can be delayed by a plurality of delay phases, and the degree of delay can be configured using the delay configuration input. The delay phases can be cascaded so that a portion of the total delay can be caused by each of the delay phases.

[0028] The sampler register has a signal input also configured to receive a signal to be delayed, a result output, and a plurality of delay inputs, each of which is coupled to a corresponding output of a plurality of delay phases. The sampler register is configured to output an indication of a relationship between the signal to be delayed and at least a final delay phase of the plurality of delay phases.

[0029] The test circuit has a delay configuration output coupled to a delay configuration input of the delay circuit, and has a test result input coupled to a result output of the sampler register. The test circuit is configured to determine whether the delay circuit passes a test criterion. For example, the test circuit can be configured to test the delay circuit by iterating through a plurality of selected delay values ​​provided to the delay circuit at the delay configuration input. The test circuit can then determine that the analog delay circuit passes the test in response to receiving an indication at the test result input by determining that the relationship matches a predetermined criterion. For example, the predetermined criterion can be a delay threshold, such as whether the signal and at least the final delayed phase indicate a delay of at least one cycle (e.g., a clock cycle).

[0030] Embodiment integrated circuits including analog delay circuits, sampler registers, and test circuits described herein can advantageously reduce or eliminate the undesirable properties of conventional methods for testing analog circuits in integrated circuits. For example, embodiment integrated circuits can advantageously enable easier and faster testing of circuits (e.g., chips, ICs, SoCs, etc.). Embodiments can provide the benefit of reducing or eliminating the need for test engineers to configure during testing. Another advantage of embodiments can be to reduce the possibility of errors during the testing process. Embodiment integrated circuits can also advantageously save testing time in production (e.g., by providing useful pass / fail test results, rather than, for example, results that require further analysis).

[0031] The embodiments provided below describe various integrated circuits, and specifically describe the following integrated circuit, which includes an analog delay circuit, a test circuit configured to test the analog delay circuit, and a sampler register configured to output a sampled signal to the test circuit. The following description describes the embodiments. Figure 1 Used to describe an example integrated circuit. Figure 2 Another example integrated circuit is described below. Figure 3 To describe the state diagram of the example finite state machine. Figure 4 Another example integrated circuit is described below. Figure 5-Figure 7 Three timing diagrams are shown to illustrate example delayed signals. Figure 8 Describes an example method for testing analog delay circuits.

[0032] Figure 1 An example integrated circuit according to an embodiment of the present invention is illustrated, which includes an analog delay circuit, a test circuit configured to test the analog delay circuit, and a sampler register configured to output a sampling signal, the sampling signal indicating the relationship between a signal to be delayed and at least a final delayed phase of the analog delay circuit.

[0033] refer to Figure 1, the integrated circuit 100 includes an analog delay circuit 110 (DLY), and includes a DFT circuit 106 configured to test the analog delay circuit 110. For example, the integrated circuit 100 can be any type of device including circuit elements (e.g., electronic, photonic) that are integrated into a monolithic substrate, such as a semiconductor substrate (e.g., silicon, germanium, gallium arsenide, silicon carbide, etc.). In various embodiments, the integrated circuit 100 is a SoC, and in one embodiment the integrated circuit 100 is an automotive SoC. Of course, the integrated circuit 100 can have any number of uses and applications, and can include a delay circuit and a test circuit configured to test the delay circuit.

[0034] The analog delay circuit 110 is configured to receive a signal 50 to be delayed (e.g., a clock signal 51, as shown) at a delay circuit signal input 116 and output a delayed signal 152 at a delay output 112 (also labeled DLY_OUT[N-1:0]). Alternatively, the signal 50 to be delayed can be provided as a separate signal at an optional separate delay circuit signal input 17, which separate signal (e.g., functionally) can be a different clock signal or even an arbitrary periodic signal. It should be noted that the clock signal can be used to test the analog delay circuit 110 in order to provide a defined period, while during normal operation, the analog delay circuit 110 can delay any signal. The duration of the delay (and any other delay configuration settings) can be provided at the delay configuration input 115. Although shown and described herein and below as an analog circuit, the analog delay circuit 110 can be a digital circuit or include digital components.

[0035] The signal 50 to be delayed can be provided internally (e.g., using a configurable phase-locked loop (PLL), which is typically already present in the device). For example, the integrated circuit 100 may include an optional test pad 62 that allows an external clock signal 63 to be provided to test the analog delay circuit 110. Alternatively, the integrated circuit 100 may include an optional PLL circuit 60 that generates an internal clock signal 61. The use of the internal clock signal 61 can advantageously allow the analog delay circuit 110 to be tested at system speed (while the frequency of the external clock signal 63 may be limited to some extent by parasitic capacitance, such as, for example, to about 100 MHz). The signal 50 to be delayed can have any periodicity, but is high frequency in some embodiments. In one embodiment, the frequency of the signal 50 to be delayed is greater than 100 MHz. In another embodiment, the frequency of the signal 50 to be delayed is greater than 250 MHz, but the frequency of the signal 50 to be delayed can still be higher, such as greater than 1 GHz and higher.

[0036] The analog delay circuit 110 is a multi-phase delay circuit including multiple delay phases (i.e., at least an initial phase and a final phase, and may include one or more intermediate phases). Although in some applications only the final delayed signal of the analog delay circuit 110 will be used, the delayed signal 152 output by the analog delay circuit 110 at the delay output 112 includes multiple delayed signals (e.g., N output clocks, where N>1). That is, the analog delay circuit 110 generates multiple delayed signals with incremental phase shifts relative to the signal 50 to be delayed. Each delayed signal can be shifted by a "delay cell" of the analog delay circuit 110 that is responsible for the "delay phase". Any number of delay phases greater than 1 may be included in the analog delay circuit 110. The delay introduced by the delay cell may be digitally programmable (e.g., through a common configuration).

[0037] The DFT circuit 106 may be a BIST circuit, or include a BIST circuit. The DFT circuit 106 includes a test circuit 120 (TEST) coupled to the analog delay circuit 110. In some embodiments, the test circuit 120 is a BIST circuit (e.g., a so-called programmable delay BIST), and the test circuit 120 is a BIST FSM in one embodiment. The test circuit 120 outputs a configuration signal 155 (also labeled DLY_CFG) at a delay configuration output 125, which is received at a delay configuration input 115 of the analog delay circuit 110. The DFT circuit 106 may test the analog delay circuit 110 by implementing a so-called "tuning" procedure. Such a procedure may be performed by a test user in other ways.

[0038] During the tuning procedure, the test circuit 120 sequentially increments a programmable code that is used to configure the delay (using the delay configuration input 115). The configuration signal 155 may specify a total delay duration, a delay duration for all delay phases, or an individual delay duration for each delay phase. The test circuit 120 may gradually increase the delay of the analog delay circuit 110 (e.g., iterating selected delay values ​​from a starting value (e.g., 0) up to a maximum delay value, which may be defined by specifications, hardware capabilities, etc.).

[0039] In response to determining that the relationship between the signal to be delayed 50 and the delay signal 152 matches a predetermined criterion, the test circuit 120 indicates that the analog delay circuit 110 passes the test. For example, the analog delay circuit 110 passes the test when (or if) the delay (e.g., phase shift) between the delay circuit signal input 116 and the Nth output (DLY_OUT[N-1], the maximum possible delay) of the delay output 112 is equal to or exceeds a threshold delay duration. In one embodiment, the predetermined criterion is a delay of at least one cycle, but other criteria are of course possible.

[0040] Test circuit 120 can determine whether a predetermined criterion is met by comparing a "signature" bit sequence (e.g., a signature N-bit value indicating that a delay threshold has been met) with a bit sequence of sampled signal 158 (e.g., an N-bit value corresponding to N delayed phases sampled at predetermined times relative to the signal to be delayed). In some embodiments, the signature sequence can be programmable. In addition, one or more bits of the signature sequence can be selectively masked (e.g., not considered when determining whether a relationship matches a predetermined criterion).

[0041] Integrated circuit 100 also includes sampler register 130 (SMP). Sampler register 130 receives delay signal 152 at delay input 132 and outputs sampled signal 158 (also labeled PHASE[N-1:0]) at test result output 138 coupled to corresponding test result input 128 of test circuit 120. Sampler register 130 may be included in DFT circuit 106 (as shown), or may be a functional circuit included in analog delay circuit 110 or in another portion of integrated circuit 100.

[0042] The sampler register 130 also includes a sampler register signal input 136 (e.g., a clock signal input) that receives the signal 50 to be delayed and uses it to generate a sampling signal 158. For example, the sampling signal 158 indicates a relationship between the signal 50 to be delayed and at least the total delay (e.g., the final delay phase of the plurality of delay phases) of the analog delay circuit 110. Of course, the sampling signal 158 may indicate additional information, such as the relationship of each delay phase to the signal 50 to be delayed.

[0043] Each of the analog delay circuit 110, the test circuit 120, and the sampler register 130 may receive a clock signal 51. As already mentioned, the clock signal 51 may be received as the signal 50 to be delayed (e.g., in the case of the analog delay circuit 110 and the sampler register 130), or may simply be received at a clock input (e.g., as shown, in order to operate the test circuit 120). The clock signal 51 may be generated by a PLL circuit (such as the optional PLL circuit 60). In some embodiments, one or more of the analog delay circuit 110, the test circuit 120, and the sampler register 130 may be clocked by a PLL circuit included in the integrated circuit 100, while the signal 50 to be delayed may be provided externally (e.g., via the optional test pad 62).

[0044] The integrated circuit 100 may also include a test data register 140 (TDR) configured to store test data. The test data register 140 receives a status signal 157 (also labeled TEST_STS) from the test circuit 120, the status signal 157 indicating the status of the test circuit 120. For example, the status signal 157 may include status flags tracking information such as whether a test procedure is running, whether the analog delay circuit 110 passes or fails, what state of the FSM the test circuit 120 is in, etc. The test data register 140 may also store delay tuning data (e.g., the selected delay value currently being tested, output by the test circuit 120 to the test data register 140). If / when the analog delay circuit 110 passes the test, the selected delay value stored in the test data register 140 as the delay tuning value may indicate a specific selected delay value associated with matching a predetermined criterion (e.g., resulting in a match to the predetermined criterion), which allows the analog delay circuit 110 to be tuned accordingly. That is, a user may input a delay tuning value (or the tuning value may be automatically set) so that the analog delay circuit 110 operates according to specifications.

[0045] The test data register 140 may also control the behavior of the test circuit 120 by outputting a control signal 156 (also labeled TEST_CTRL) to the test circuit 120. For example, the test circuit 120 may read various test data (such as flags from the test data register 140) to control the testing of the analog delay circuit 110 (e.g., to control the execution of a tuning procedure).

[0046] Figure 2 An example integrated circuit according to an embodiment of the present invention is illustrated, the integrated circuit including an analog delay circuit having a sampler register configured to output a sampling signal indicating a relationship between a signal to be delayed and at least a final delayed phase of the analog delay circuit, and including a test circuit implemented as a built-in self-test finite state machine and configured to test the analog delay circuit. For example, Figure 2 The integrated circuit may be any other integrated circuit described herein (such as Figure 1 Similar labeled elements may be as previously described.

[0047] refer to Figure 2, the integrated circuit 200 includes a circuit under test 208 (CUT) and a DFT circuit 206. The circuit under test 208 includes an analog delay circuit 210 coupled to a sampler register 230, and includes a PLL circuit 60, which provides an internal clock signal 61 to the analog delay circuit 210 at a delay circuit signal input 216 and provides the internal clock signal 61 to the sampler register 230 at a sampler register signal input 236. Here, the internal clock signal 61 is also the signal 50 to be delayed. The DFT circuit 206 includes a test circuit 220 coupled to a test data register 240. The test circuit 220 outputs a configuration signal 255 at a delay configuration output 225, which is received by the analog delay circuit 210 of the circuit under test 208 at a delay configuration input 215. The internal clock signal 61 is also provided to the test circuit 220 (e.g., for testing the operation of the circuit 220).

[0048] It should be noted that here and below, a convention has been adopted for the sake of brevity and clarity, where elements following the pattern [x20] (where 'x' is a figure number) may be related implementations of test circuits in various embodiments. For example, unless otherwise noted, test circuit 220 may be similar to test circuit 120. Similar conventions are adopted for other elements, as made clear by the use of similar terminology in conjunction with the above-mentioned numbering system.

[0049] In this specific example, the DFT circuit 206 is implemented as a BIST, and the test circuit 220 is implemented as a FSM (finite state machine) of the BIST. A start signal 44 (TEST_START) may be provided to the test circuit 220, the start signal 44 initiating the test procedure (e.g., the user may provide the signal). In addition, a reset signal 46 (TEST_RESET) may be similarly provided to reset the test circuit 220. Both the start signal 44 and the reset signal 46 may also be provided from the test data register 240. For example, the test circuit 220 may be configured to maintain an idle state when the BIST start flag (TEST_START) is disabled, and to start testing the analog delay circuit 210 in response to receiving the start signal 44 enabling the BIST start flag.

[0050] The test circuit 220 outputs a status signal 257 to the test data register 240, which may include various information indicating the status of the test circuit 220 (and the test procedure being executed), such as a status flag and delay configuration information. The data stored in the test data register 240 may be read by the test circuit 220 using a control signal 256 output from the test data register 240 to the test circuit 220.

[0051] For example, the status signal 257 may include: a run signal 42 (TEST_RUN) (which may indicate that a test procedure (e.g., a tuning procedure) is in progress), an end signal 43 (TEST_END) (which may indicate whether the test procedure has ended), a status signal 45 (TEST_OK) (which may indicate whether the analog delay circuit 210 of the circuit under test 208 has passed the test), and the like.

[0052] The status signal 257 may also include delay tuning data 41 (e.g., a sequence of M bits DLY_TUNE[M-1:0], such as 7 bits, the length of which may depend on the specific delay capabilities of the analog delay circuit 210). The delay tuning data 41 may correspond to a selected delay value that is being used or has been used in a test procedure. For example, when the test procedure is also a tuning procedure, the delay tuning data 41 may be stored as a delay tuning value for each iteration of the tuning procedure. If / when the analog delay circuit 210 passes the test, the stored delay tuning value indicates a delay configuration that matches the predetermined criteria of the test procedure (and may therefore be used as a tuning value to tune the analog delay circuit 210).

[0053] Configuration signals 255 may include various information, such as selecting a delay value 47 (e.g., a P-bit sequence DLY_SEL[P-1:0], such as 4 bits indicating the number of delay cells used in the delay path), a delay cell 48 (e.g., an M-bit sequence DLY_UNIT[M-1:0] indicating the duration of a unit delay (how much delay each delay cell introduces) during iterations of testing a range of delay values), a delay enable signal 53, a sampler enable signal 54, etc. The delay enable signal 53 (DLY_EN) may be used to enable the analog delay circuit 210, while the sampler enable signal 54 (SAMPLE_EN) may be used to enable the sampler register 230. Of course, in some implementations, one or more of the delay enable signal 53 and the sampler enable signal 54 may not be required.

[0054] The analog delay circuit 210 delays the signal 50 to be delayed received at the delay circuit signal input 216 according to the configuration signal 255, and outputs a delayed signal 252 at the delay output 212, which is received at the delay input 232 of the sampler register 230. The sampler register 230 receives the delayed signal 252 and outputs a sampled signal 258 at the test result output 238, which is received at the test result input 228 of the test circuit 220 of the DFT circuit 206.

[0055] The implementation of the test circuit 220 as a BIST FSM can have various advantages, such as requiring minimal external configuration. For example, a user can only provide an input clock signal (which can also be a clock signal input to the analog delay circuit 210, as shown), and trigger the BIST execution (e.g., release the FSM reset (TEST_RESET), and issue a start signal to execute the BIST routine (TEST_START)). The FSM provides the BIST execution status (execution status) as an output (usually a pass / fail result flag (TEST_OK) and a flag indicating the end of the BIST (TEST_END)), while another flag can indicate when the BIST is still running (TEST_RUN), but other interfaces can certainly be used. In addition, the DFT circuit 206 implemented as a BIST circuit can be configured to periodically test the analog delay circuit 210 in the field to confirm that the analog delay circuit 210 continues to pass the test.

[0056] Figure 3 A state diagram conceptually depicting the behavior of an example finite state machine configured to test an analog delay circuit in accordance with an embodiment of the present invention is illustrated. Figure 3 A state diagram can conceptually depict the behavior of a finite state machine described herein, such as one implemented as Figure 2 1. A test circuit for a finite state machine of FIG. 1. Similar labeled elements may be as previously described.

[0057] refer to Figure 3 , state diagram 300 shows five states of an example finite state machine for a test circuit for testing a delay circuit. State diagram 300 includes an idle state 71, which may be a default state in which the test circuit is when no test procedure is being executed. When in the idle state 71, the start flag TEST_START may be zero. The reset flag TEST_RESET may place the test circuit in the idle state 71 when it is set to zero, as shown.

[0058] When TEST_START is set to 1, the test circuit can start the test procedure by moving to the evaluation state 72. In the evaluation state 72, the test circuit can generate a run flag (TEST_RUN=1) to indicate that the test procedure is running, an end flag to indicate that the test procedure has not yet ended (TEST_END=0), and a status flag TEST_OK=1 to indicate that the delay circuit has passed the test (for example, these flags can be output by the test circuit to the test data register and read from the test data register to determine the behavior of the test circuit). After verifying the state of the test circuit, the test circuit can test the delay circuit using the currently selected delay configuration (for example, evaluating the identification signal received from the sampler register).

[0059] Optionally, a validity flag DLY_VALID may be used to indicate whether the delayed signal being sampled is stable and reliable. For example, the validity flag may be provided by the delay circuit itself or generated by the test circuit. The validity flag may be useful to allow a certain transition time for the delay circuit from one configuration to another (e.g., when it is an analog delay circuit). When DLY_VALID=0, the test circuit may remain in the evaluation state 72 (e.g., waiting for the signal to be delayed to become valid).

[0060] The test circuit can iterate a series of delay configurations by switching back and forth between the evaluation state 72 and the increment state 73. Specifically, when the sampling signal PHASE[N-1:0] is not equal to the identification sequence SIG[N-1:0] and the maximum delay configuration has not been reached (DLY_CFG is not equal to MAX_DLY), the test circuit can increment the delay configuration (DLY_CFG++). When using the validity flag, the test circuit can also ensure that DLY_VALID=1 before incrementing the delay configuration.

[0061] If the evaluation state 72 determines that the sampling signal PHASE[N-1:0] is equal to the identification sequence SIG[N-1:0] (and optionally, DLY_VALID=1), the test circuit can identify that the delay circuit has passed the test (TEST_OK=1) and move to the pass state 74. For example, as previously described, if the predetermined criteria of the identification sequence (e.g., a delay duration of at least one cycle) are met, the delay circuit passes the test. In the pass state 74, the test procedure has ended (TEST_END=1), so it is not running (TEST_RUN=0). In addition, when the test procedure is also a tuning procedure, delay tuning data (DLY_TUNE) can be stored. From the pass state 74, TEST_START can be set to 0 and the test circuit can enter the idle state 71.

[0062] On the other hand, if the delay configuration reaches the maximum delay configuration (DLY_CFG equals MAX_DLY), and the sampled signal is still not equal to the identification signal (PHASE[N-1:0] is not equal to SIG[N-1:0]) (and optionally, DLY_VALID=1), the test circuit can recognize that the delay circuit has failed and enter the failed state 75 (TEST_OK=0). Similarly, TEST_RUN is now 0 and TEST_END=1. The test circuit can recover from the failed state 75 to the idle state 71 (for example, when TEST_START=0).

[0063] Figure 4 An example integrated circuit according to an embodiment of the present invention is illustrated, the integrated circuit including an analog delay circuit having a delay line of delay phases including an initial delay phase and a final delay phase and optional intermediate delay phases therebetween. Figure 4 The integrated circuit may be any other integrated circuit described herein (e.g., such as Figure 1 For example, similarly labeled elements may be as previously described.

[0064] refer to Figure 4 , the integrated circuit 400 includes an analog delay circuit 410 implemented using a delay line 80. The delay line 80 has a plurality of delay phases 83. Each of the delay phases 83 is a delay phase 84 formed by a delay unit. The signal 50 to be delayed, received at the delay circuit signal input 416, propagates through the delay line 80, starting with an initial delay phase 88 and ending with a final delay phase 89, resulting in a delayed output 412. Optionally, one or more intermediate delay phases 82 may be included. An intermediate delayed signal is also output between each of the intermediate delay phases 82. The final delayed signal (PHASE[N-1]) is of the longest duration (e.g., has the largest shift relative to the signal 50 to be delayed).

[0065] Each of the intermediate delay phases 82 can be configured using the configuration signal 455 (e.g., the analog delay circuit 410 is programmable). The configuration can be common so that each delay introduces the same configured delay (e.g., 10 ns), but of course this is not necessarily the case. The configuration signal 455 can select one or more of the intermediate delay phases 82 to introduce a delay (e.g., the signal passes through the unselected intermediate delay phases 82 without being delayed).

[0066] The delayed output 412 may be output to a sampler register 430, which may be similar to the sampler registers already described. For example, the sampler register 430 may be Figure 1 The sampler register 430 receives the delayed output 412 and the signal 50 to be delayed as inputs (delay input 432 and sampler register signal input 436, respectively) and outputs a sampled signal 458, as shown.

[0067] Figure 5 An example schematic timing diagram of a tuned delay signal and an example schematic timing diagram of an untuned delay signal according to an embodiment of the present invention are illustrated, wherein the delay signal includes N delay phases. Figure 5 The delayed signal shown in the timing diagram of can be any delayed signal described herein (e.g., such as Figure 1 Similarly labeled elements may be as previously described.

[0068] refer to Figure 5 , the "untuned" timing diagram 501 includes a delayed signal 552 having at least two phases (DLY_OUT[0] and DLY_OUT[N-1]). One or more intermediate phases may also be included (i.e., N may be greater than 2). The signal to be delayed is input to the delay circuit (DLY_IN) and has a signal period 98. Here, the delay threshold 96 (predetermined standard) is equal to the signal period 98, but is not strictly required to be equal. As shown, the final phase DLY_OUT[N-1] is not shifted by the entire signal period. As a result, the delayed signal 552 is untuned.

[0069] The test circuit uses the sampling signal PHASE[N-1:0] and the identification signal SIG[N-1:0] to determine that the delayed signal 552 is not tuned. For example, the sampling signal and the identification signal both include a bit sequence 93. At a predetermined time 94 (here, corresponding to the rising edge of the DLY_IN pulse), the sampling signal PHASE[N-1:0] is output. Because in this example, the delayed signal 552 is not tuned (the test failed), PHASE[N-1:0] includes a failure bit sequence 591 (1...0), which does not match the identification sequence 590 (0...1) of the identification signal SIG[N-1:0]. In contrast, the "tuned" timing diagram 502 shows a delayed signal 559, which generates a sampling signal having a pass bit sequence 592 (0...1) that matches the identification sequence 590 (0...1).

[0070] Figure 6 Another example schematic timing diagram of a tuned delay signal and an example schematic timing diagram of an untuned delay signal according to an embodiment of the present invention are illustrated, wherein the delay signal includes 12 delay phases. Figure 6 The delayed signal shown in the timing diagram of can be any delayed signal described herein (e.g., such as Figure 1Similarly labeled elements may be as previously described.

[0071] refer to Figure 6 , the "untuned" timing diagram 601 includes a delayed signal 652 having 12 phases (DLY_OUT[0] to DLY_OUT

[11] ). The test circuit uses the sampling signal PHASE[11:0] and the identification signal SIG[11:0] to determine that the delayed signal 652 is not tuned. Because in this example, the delayed signal 652 is not tuned (the test failed), PHASE[11:0] includes a failed bit sequence 691 (1_111110_00000), which does not match the identification sequence 690 (0_111111_00000) of the identification signal SIG[11:0]. In contrast, the "tuned" timing diagram 602 shows a delayed signal 659, which generates a sampled signal having a passed bit sequence 692 (0_111111_00000) that matches the identification sequence 690 (0_111111_00000).

[0072] Reading more than just the last phase (e.g., reading the entire identification) can advantageously give additional information about the consistency of the delays of the phases. As shown, the identification sequence 690 can be substantially evenly divided, but this is not required. For example, even division can indicate consistency of the phases of the delay circuit, but it is expected that delayed phases with different delays can be used. If one of the delayed phases is inconsistent, the balance may be changed (e.g., shifted early or shifted later), and the identification sequence 690 may not be obtained.

[0073] Figure 7 A further example schematic timing diagram of a tuned delay signal and an example schematic timing diagram of an untuned delay signal according to an embodiment of the present invention are illustrated, wherein the delay signal comprises 6 delay phases and bit masking is used. Figure 7 The delayed signal shown in the timing diagram of can be any delayed signal described herein (e.g., such as Figure 1 Similarly labeled elements may be as previously described.

[0074] refer to Figure 7, the "untuned" timing diagram 701 includes a delayed signal 752 having 6 phases (DLY_OUT[0] to DLY_OUT[5]). The test circuit uses the sampling signal PHASE[5:0] and the identification signal SIG[5:0] to determine that the delayed signal 752 is untuned. The identification signal SIG[5:0] includes an identification sequence 790. In this example, the optional ability to program the identification sequence 790 is demonstrated. Specifically, the identification sequence 790 can include a masked bit 99 (or more than one masked bit 99). The masked bit 99 is shown as an "X" (e.g., don't care), indicating that the masked bit 99 is not considered when comparing the identification sequence 790 to the sampled signal.

[0075] Because in this example, the delayed signal 752 is not tuned (test failed), PHASE[5:0] includes a fail bit sequence 791 (1_110_00) that does not match the identification sequence 690 (0_11X_00) of the identification signal SIG[5:0] (even ignoring the masked bit 99). In contrast, the "tuned" timing diagram 702 shows the delayed signal 759, which generates a sampled signal having a pass bit sequence 792 (0_110_00) that matches the identification sequence 690 (0_11X_00).

[0076] It is worth noting that the delay phase is not consistent in this example. Without the masked bit 99, the passing bit sequence 792 would not pass the test (e.g., without masking, the identification sequence 790 could be 0_111_00). However, masking the bits can make the overall result of the test pass, even though the delay phase is not consistent enough to pass without masking (e.g., silicon is not precise enough). Therefore, masking can be advantageous for situations where total delay is more important than phase consistency, or for debugging purposes, or to cope with process variations in integrated circuit production.

[0077] Figure 8 An example method of testing an analog delay circuit of an integrated circuit according to an embodiment of the present invention is illustrated. Figure 8 The method can be combined with other methods and can be performed using the systems and devices described herein. For example, Figure 8 The method can be used with Figures 1 to 7 Although shown in a logical order, Figure 8 The arrangement and numbering of the steps are not intended to be limiting. Figure 8 The method steps may be performed in any suitable order, or concurrently with each other, as will be apparent to those skilled in the art.

[0078] refer to Figure 8, a method 800 for testing an analog delay circuit of an integrated circuit includes step 801: receiving a signal to be delayed at a signal input of the analog delay circuit. The analog delay circuit includes a delay configuration input and a plurality of delay phases, the plurality of delay phases including an initial delay phase and a final delay phase. In step 802, the signal to be delayed is received at a signal input of a sampler register of the integrated circuit. For example, step 801 and step 802 may be substantially simultaneous. The sampler register includes a plurality of test result outputs and a plurality of delay inputs, the plurality of delay inputs being each coupled to a corresponding output of the plurality of delay phases.

[0079] Step 803 includes outputting a sampled signal from a sampler register, the sampled signal indicating a relationship between a signal to be delayed and at least a final delayed phase in a plurality of delay phases. In step 804, method 800 iterates through a plurality of selected delay values. The plurality of selected delay values ​​are provided to the analog delay circuit at a delay configuration input by a delay configuration output of a test circuit of the integrated circuit to test the analog delay circuit. The test circuit includes a plurality of test result inputs, the plurality of test result inputs being coupled to a plurality of test result outputs of the sampler register. In step 805, in response to receiving the sampled signal at the plurality of test result inputs, it is determined that the analog delay circuit has passed the test. For example, passing can be determined by determining that the relationship matches a predetermined criterion.

[0080] Example embodiments of the present invention are summarized here. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0081] Example 1. An integrated circuit, comprising: an analog delay circuit, comprising a plurality of delay phases, a delay configuration input, and a signal input, the signal input being configured to receive a signal to be delayed, the plurality of delay phases comprising an initial delay phase and a final delay phase; a sampler register, comprising: a signal input configured to receive the signal to be delayed, a plurality of test result outputs, and a plurality of delay inputs, the plurality of delay inputs being each coupled to a corresponding delay output of the plurality of delay phases, the sampler register being configured to: output a sampling signal, the sampling signal indicating a relationship between the signal to be delayed and at least the final delay phase of the plurality of delay phases; and a test circuit, comprising a delay configuration output, the delay configuration output being coupled to the delay configuration input of the analog delay circuit, and comprising a plurality of test result inputs, the plurality of test result inputs being coupled to the plurality of test result outputs of the sampler register, the test circuit being configured to: test the analog delay circuit by iterating through a plurality of selected delay values ​​provided to the analog delay circuit at the delay configuration input, and in response to receiving the sampling signal at the plurality of test result inputs, determining that the analog delay circuit passes the test by determining that the relationship matches a predetermined criterion.

[0082] Example 2. An integrated circuit according to Example 1, wherein the sampling signal is a bit sequence corresponding to the delayed outputs of the multiple delayed phases sampled at predetermined times relative to the signal to be delayed, and wherein the predetermined criterion is an identification bit sequence indicating that a delay threshold has been met.

[0083] Example 3. The integrated circuit of Example 2, wherein the signal to be delayed is a clock signal, and wherein the delay threshold is one period of the clock signal.

[0084] Example 4. An integrated circuit according to any one of Examples 2 and 3, wherein the plurality of delay phases includes at least one intermediate delay phase, and wherein at least one bit in the bit sequence corresponding to the at least one intermediate delay phase is masked and not considered when determining whether the relationship matches the predetermined criterion.

[0085] Example 5. An integrated circuit according to any of Examples 1 to 4, wherein the signal to be delayed is a clock signal.

[0086] Example 6. The integrated circuit according to Example 5 further includes: a phase-locked loop (PLL) circuit configured to: generate a clock signal and provide the clock signal as the signal to be delayed to the analog delay circuit and the sampler register.

[0087] Example 7. The integrated circuit of Example 6, wherein the test circuit is configured to operate using the clock signal.

[0088] Example 8. The integrated circuit of Example 5 further includes: a test pad configured to receive the clock signal and coupled to both the signal input of the analog delay circuit and the signal input of the sampler register, the clock signal being an external clock signal.

[0089] Example 9. An integrated circuit according to any one of Examples 1 to 8, further comprising: a test data register coupled to the test circuit, the test data register being configured to store delay tuning data, wherein the test circuit is further configured to: output the delay tuning data, wherein the delay tuning data indicates a selected delay value among the multiple selected delay values, the selected delay value being associated with matching the predetermined criterion.

[0090] Example 10. The integrated circuit of any of Examples 1 to 9, wherein the signal to be delayed has a frequency greater than about 100 MHz.

[0091] Example 11. An integrated circuit according to any one of Examples 1 to 10, wherein the sampler register is implemented as a functional circuit of the analog delay circuit

[0092] Example 12. An integrated circuit according to any of Examples 1 to 11, wherein the sampler register is implemented as a dedicated design for test (DFT) circuit.

[0093] Example 13. An integrated circuit according to any of Examples 1 to 12, wherein the test circuit is a built-in self-test (BIST) circuit.

[0094] Example 14. The integrated circuit of any of Examples 1 to 13, wherein the integrated circuit is an automotive system on a chip (SoC).

[0095] Example 15. An integrated circuit according to any of Examples 1 to 14, wherein the plurality of delay phases includes more than two delay phases.

[0096] Example 16. The integrated circuit of Example 15, wherein the plurality of delay phases has 12 delay phases.

[0097] Example 17. A built-in self-test (BIST) circuit, comprising: a sampler register, comprising: a signal input configured to receive a signal to be delayed, a plurality of test result outputs, and a plurality of delay inputs, each of the plurality of delay inputs being configured to be coupled to a corresponding delay output of a plurality of delay phases of an analog delay circuit, the sampler register being configured to: output a sampling signal, the sampling signal indicating a relationship between the signal to be delayed and at least a final delay phase of the plurality of delay phases; a finite state machine circuit, comprising a delay configuration output, the delay configuration output being configured to be coupled to the delay configuration input of the analog delay circuit, and comprising a plurality of test result inputs, the plurality of test result inputs being coupled to the sampler register The multiple test result outputs, the finite state machine circuit is configured to: test the analog delay circuit by iterating through a plurality of selected delay values ​​provided to the analog delay circuit at the delay configuration input, in response to receiving the sampling signal at the multiple test result inputs, determine that the analog delay circuit passes the test by determining that the relationship matches a predetermined standard, and output delay tuning data, the delay tuning data indicating a selected delay value from the multiple selected delay values, the selected delay value being associated with matching the predetermined standard; a test data register, coupled to the finite state machine circuit, the test data register being configured to: store a state flag of the finite state machine circuit, and store the delay tuning data.

[0098] Example 18. The BIST circuit of Example 17, wherein the finite state machine circuit is further configured to: maintain an idle state when a BIST enable flag is disabled, and start testing the analog delay circuit in response to receiving an enable signal that enables the BIST enable flag.

[0099] Example 19. The BIST circuit of Example 18, wherein the BIST circuit is configured to periodically test the analog delay circuit in the field to confirm that the analog delay circuit continues to pass the test.

[0100] Example 20. A BIST circuit according to any one of Examples 17 to 19, wherein the status flag includes a pass / fail flag indicating whether the analog delay circuit passes the test, a BIST run flag indicating whether the test is running, and a BIST end flag indicating whether the test is ended.

[0101] Example 21. A BIST circuit according to any one of Examples 17 to 20, wherein the sampling signal is a bit sequence corresponding to the delayed outputs of the multiple delayed phases sampled at predetermined moments relative to the signal to be delayed, and wherein the predetermined criterion is an identification bit sequence indicating that a delay threshold has been met.

[0102] Example 22. The BIST circuit of Example 21, wherein the identification bit sequence is programmable.

[0103] Example 23. The BIST circuit of Example 22, wherein the plurality of delay phases includes at least one intermediate delay phase, and wherein at least one bit in the bit sequence corresponding to the at least one intermediate delay phase is masked and not considered when determining whether the relationship matches the predetermined criterion.

[0104] Example 24. A method for testing an analog delay circuit of an integrated circuit, the method comprising: receiving a signal to be delayed at a signal input of the analog delay circuit, the analog delay circuit comprising a delay configuration input and a plurality of delay phases, the plurality of delay phases comprising an initial delay phase and a final delay phase; receiving the signal to be delayed at a signal input of a sampler register of the integrated circuit, the sampler register comprising a plurality of test result outputs and a plurality of delay inputs, the plurality of delay inputs each being coupled to a corresponding output of the plurality of delay phases; outputting a sampling signal from the sampler register, the sampling signal indicating a relationship between the signal to be delayed and at least the final delay phase of the plurality of delay phases; testing the analog delay circuit by iterating through a plurality of selected delay values ​​provided to the analog delay circuit at the delay configuration input by a delay configuration output of a test circuit of the integrated circuit, the test circuit comprising a plurality of test result inputs, the plurality of test result inputs being coupled to the plurality of test result outputs of the sampler register; and determining that the analog delay circuit passes the test in response to receiving the sampling signal at the plurality of test result inputs by determining that the relationship matches a predetermined criterion.

[0105] Example 25. A method according to Example 24, wherein outputting the sampled signal includes outputting a bit sequence corresponding to the delayed outputs of the multiple delayed phases sampled at predetermined moments relative to the signal to be delayed, and the predetermined criterion is an identification bit sequence indicating that a delay threshold has been met.

[0106] Example 26. A method according to Example 25, wherein the multiple delay phases include at least one intermediate delay phase, and wherein at least one bit in the bit sequence corresponding to the at least one intermediate delay phase is masked and not considered when determining whether the relationship matches the predetermined criterion.

[0107] Example 27. A method according to any one of Examples 25 and 26, wherein the identification bit sequence is programmable.

[0108] Example 28. The method according to any one of Examples 24 to 27 further includes: maintaining the idle state of the test circuit when the start flag is disabled; and starting to iterate the multiple selected delay values ​​in response to receiving a start signal that enables the start flag to test the analog delay circuit.

[0109] Example 29. The method of Example 28 further includes: using the test circuit to periodically test the analog delay circuit in the field to confirm that the analog delay circuit continues to pass the test.

[0110] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. With reference to the description, various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An integrated circuit, comprising: an analog delay circuit comprising a plurality of delay phases, a delay configuration input, and a signal input, the signal input being configured to receive a signal to be delayed, the plurality of delay phases comprising an initial delay phase and a final delay phase; A sampler register, comprising: a signal input, a plurality of test result outputs, and a plurality of delay inputs, wherein the signal input is configured to receive the signal to be delayed, the plurality of delay inputs are each coupled to a corresponding delay output of the plurality of delay phases, and the sampler register is configured to: outputting a sampling signal, the sampling signal indicating a relationship between the signal to be delayed and at least the final delayed phase among the plurality of delayed phases; as well as a test circuit comprising a delay configuration output and a plurality of test result inputs, the delay configuration output being coupled to the delay configuration input of the analog delay circuit, the plurality of test result inputs being coupled to the plurality of test result outputs of the sampler register, the test circuit being configured to: iterating through a plurality of selected delay values ​​to test the analog delay circuit, the plurality of selected delay values ​​being provided to the analog delay circuit at the delay configuration input, and In response to receiving the sampled signals at the plurality of test result inputs, determining that the analog delay circuit passes the test is determined by determining that the relationship matches a predetermined criterion.

2. An integrated circuit according to claim 1, wherein the sampling signal is a bit sequence corresponding to the delayed outputs of the multiple delay phases, the multiple delay phases are sampled at predetermined times relative to the signal to be delayed, and wherein the predetermined criterion is a flag bit sequence, the flag bit sequence indicating that a delay threshold has been met.

3. The integrated circuit of claim 2 , wherein the plurality of delay phases include at least one intermediate delay phase, and wherein at least one bit in the bit sequence corresponding to the at least one intermediate delay phase is masked and not considered when determining that the relationship matches the predetermined criterion. The integrated circuit according to claim 1 , wherein the signal to be delayed is a clock signal.

5. The integrated circuit of claim 4, further comprising: The phase-locked loop (PLL) circuit is configured to generate a clock signal and provide the clock signal as the signal to be delayed to the analog delay circuit and the sampler register.

6. The integrated circuit of claim 1 , further comprising: a test data register coupled to the test circuit, the test data register being configured to store delay tuning data, The test circuit is further configured as follows: The delay tuning data is output, wherein the delay tuning data indicates a selected delay value from the plurality of selected delay values, the selected delay value being associated with matching the predetermined criterion.

7. The integrated circuit of claim 1, wherein the signal to be delayed has a frequency greater than about 100 MHz.

8. A built-in self-test (BIST) circuit, comprising: A sampler register, comprising: a signal input, a plurality of test result outputs, and a plurality of delay inputs, wherein the signal input is configured to receive a signal to be delayed, the plurality of delay inputs are each configured to be coupled to a corresponding delay output of a plurality of delay phases of an analog delay circuit, the sampler register being configured to: outputting a sampling signal, the sampling signal indicating a relationship between the signal to be delayed and at least a final delayed phase among the plurality of delayed phases; a finite state machine circuit comprising a delay configuration output and a plurality of test result inputs, the delay configuration output being configured to be coupled to the delay configuration input of the analog delay circuit, the plurality of test result inputs being coupled to the plurality of test result outputs of the sampler register, the finite state machine circuit being configured to: iterating through a plurality of selected delay values ​​to test the analog delay circuit, the plurality of selected delay values ​​being provided to the analog delay circuit at the delay configuration input, In response to receiving the sampled signals at the plurality of test result inputs, determining that the analog delay circuit passes the test by determining that the relationship matches a predetermined criterion, and outputting delay tuning data indicating a selected delay value from among the plurality of selected delay values, the selected delay value being associated with matching the predetermined criterion; A test data register is coupled to the finite state machine circuit, and is configured to store a state flag of the finite state machine circuit and the delay tuning data.

9. The BIST circuit of claim 8, wherein the finite state machine circuit is further configured to: When the BIST start flag is disabled, the idle state is maintained and In response to receiving an enable signal that enables the BIST enable flag, testing of the analog delay circuit is initiated.

10. The BIST circuit of claim 9, wherein the BIST circuit is configured to periodically test the analog delay circuit in the field to confirm that the analog delay circuit continues to pass the test.

11. The BIST circuit according to claim 8, wherein the status flag comprises a pass / fail flag, a BIST run flag, and a BIST end flag, the pass / fail flag indicating whether the analog delay circuit passes the test, the BIST run flag indicating whether the test is running, and the BIST end flag indicating whether the test is ended.

12. The BIST circuit of claim 8 , wherein the sampled signal is a bit sequence corresponding to delayed outputs of the plurality of delayed phases, the plurality of delayed phases being sampled at predetermined moments relative to the signal to be delayed, and wherein the predetermined criterion is a flag bit sequence indicating that a delay threshold has been met.

13. The BIST circuit of claim 12, wherein the identification bit sequence is programmable.

14. The BIST circuit of claim 13, wherein the plurality of delay phases includes at least one intermediate delay phase, and wherein at least one bit in the bit sequence corresponding to the at least one intermediate delay phase is masked and not considered when determining that the relationship matches the predetermined criterion.

15. A method for testing an analog delay circuit of an integrated circuit, the method comprising: receiving a signal to be delayed at a signal input of the analog delay circuit, the analog delay circuit comprising a delay configuration input and a plurality of delay phases, the plurality of delay phases comprising an initial delay phase and a final delay phase; receiving the signal to be delayed at a signal input of a sampler register of the integrated circuit, the sampler register comprising a plurality of test result outputs and a plurality of delay inputs, the plurality of delay inputs each being coupled to a respective output of the plurality of delay phases; outputting a sampling signal from the sampler register, the sampling signal indicating a relationship between the signal to be delayed and at least the final delayed phase of the plurality of delayed phases; iterating through a plurality of selected delay values ​​to test the analog delay circuit, the plurality of selected delay values ​​being provided to the analog delay circuit at the delay configuration input by a delay configuration output of a test circuit of the integrated circuit, the test circuit including a plurality of test result inputs coupled to the plurality of test result outputs of the sampler register; as well as In response to receiving the sampled signals at the plurality of test result inputs, determining that the analog delay circuit passes the test is determined by determining that the relationship matches a predetermined criterion.

16. A method according to claim 15, wherein outputting the sampling signal includes outputting a bit sequence corresponding to the delayed outputs of the multiple delayed phases, the multiple delayed phases are sampled at predetermined times relative to the signal to be delayed, and the predetermined standard is an identification bit sequence, which indicates that a delay threshold has been met.

17. The method of claim 16, wherein the plurality of delay phases includes at least one intermediate delay phase, and wherein at least one bit in the bit sequence corresponding to the at least one intermediate delay phase is masked and not considered when determining that the relationship matches the predetermined criterion. The method according to claim 16 , wherein the identification bit sequence is programmable.

19. The method according to claim 15, further comprising: When the start flag is disabled, maintaining the test circuit in an idle state; as well as In response to receiving an enable signal that enables the enable flag, iterating through the plurality of selected delay values ​​is initiated to test the analog delay circuit.

20. The method according to claim 19, further comprising: The analog delay circuit is periodically tested in the field using the test circuit to confirm that the analog delay circuit continues to pass the test.

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