System and method for testing circuit

Abstract

Embodiments of the present disclosure relate to systems and methods for testing a circuit. A system for testing a circuit includes a phase-locked loop, a test logic circuit, and a test controller. A test logic circuit is coupled to the phase-locked loop. The test logic circuit is configured to count a number of clock cycles of the phase-locked loop using the reference clock as a reference. A reference clock is coupled to the test logic circuit. A test controller is coupled to the phase-locked loop and the test logic circuit. The test controller is configured to measure a clock frequency of the phase-locked loop using the counted number of clock cycles received from the test logic circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 511,390, filed on June 30, 2023, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to circuits and, in particular embodiments, to systems and methods for testing circuits. Background Art

[0004] A phase-locked loop (PLL) is a control system that generates an output signal with a corresponding phase, which is related to the phase of a corresponding input signal. There are many types of PLLs, the simplest of which is a circuit with a variable frequency oscillator and a phase detector coupled together in a feedback loop. The applied voltage controls the frequency and phase of the variable frequency oscillator proportionally. Therefore, a variable frequency oscillator is also referred to as a voltage-controlled oscillator (VCO). The oscillator generates a periodic signal with a specific frequency, and the phase detector then compares the phase of the periodic signal with the corresponding phase of the input periodic signal. This allows the oscillator to be adjusted to maintain phase matching between the input periodic signal and the output periodic signal.

[0005] Keeping the input phase and output phase synchronized also means keeping the input frequency and output frequency the same. Therefore, in addition to the synchronization signal, the phase-locked loop can track the input frequency, or it can generate a frequency that is a multiple of the input frequency. These features are used in computer clock synchronization, demodulation, and frequency synthesis.

[0006] Phase-locked loops are widely used in radio, telecommunications, computers, and other electronic applications, such as systems-on-chip for automotive applications. They can be used to demodulate signals, recover signals from noisy communication channels, generate stable frequencies at multiples of the input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can now provide a complete phase-locked loop building block, the technology is widely used in modern electronic devices, where output frequencies range from a fraction of a hertz up to many gigahertz. Therefore, new solutions for testing phase-locked loops are desired. Summary of the invention

[0007] According to one embodiment, a system for testing a circuit includes: a phase-locked loop; a test logic circuit, the test logic circuit is coupled to the phase-locked loop, the test logic circuit is configured to count the number of clock cycles of the phase-locked loop using a reference clock as a reference, the reference clock is coupled to the test logic circuit; and a test controller, the test controller is coupled to the phase-locked loop and the test logic circuit, the test controller is configured to measure the clock frequency of the phase-locked loop using the counted number of clock cycles received from the test logic circuit.

[0008] According to another embodiment, a system for testing a circuit includes: a phase-locked loop; a test logic circuit, the test logic circuit is coupled to the phase-locked loop, the test logic circuit includes: a lock cycle counter, the lock cycle counter is configured to count the number of cycles of a reference clock between an activation time of the phase-locked loop and a lock state time of the phase-locked loop, the reference clock is coupled to the test logic circuit; and a fast cycle counter, the fast cycle counter is configured to count the number of fast clock cycles of the phase-locked loop using the reference clock as a reference; and a test controller, the test controller is coupled to the phase-locked loop and the test logic circuit, the test controller is configured to receive a lock cycle count signal from the lock cycle counter and to receive a fast cycle count signal from the fast cycle counter.

[0009] According to another embodiment, a method for testing a circuit includes: enabling a test logic circuit using a test controller, the test logic circuit being coupled to a phase-locked loop and the test controller; counting the number of clock cycles of the phase-locked loop using a reference clock as a reference using the test logic circuit, the reference clock being coupled to the test logic circuit; and determining the clock frequency of the phase-locked loop using the counted number of clock cycles using the test controller.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 illustrates a schematic diagram of a system for testing a phase locked loop according to some embodiments;

[0013] Figures 2 to 5 illustrates a schematic diagram of a phase-locked loop test block according to some embodiments; and

[0014] Figure 6 A flow chart of a method for testing a circuit according to some embodiments is illustrated.

[0015] Unless otherwise indicated, corresponding numbers and symbols in the different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the scope of the features. DETAILED DESCRIPTION

[0016] The making and use of various embodiments are discussed in detail below. However, it should be understood that the various embodiments described herein are applicable in a variety of specific contexts. The specific embodiments discussed only illustrate specific methods for making and using various embodiments and should not be interpreted in a limited scope.

[0017] Phase-locked loops (PLLs) are widely used in semiconductor devices to increase the external crystal oscillator frequency (which may be in the MHz domain) relative to the internal frequency (which may be in the GHz domain). It would be advantageous to test the performance of the PLL circuits during manufacturing, thereby improving the quality of the finished devices (in other words, avoiding shipping damaged or out-of-specification devices). Due to the growth in complexity of systems on chip (SoCs) and the continuous increase in the number of embedded PLLs, new test architectures are desired for PLL circuits.

[0018] According to one or more embodiments of the present disclosure, the present application relates to an electronic circuit for testing a phase-locked loop (PLL). Specific logic, also referred to as a test block or a test logic circuit, is added to directly monitor a lock signal and a PLL clock frequency using a PLL output signal. Since the signal does not need to be propagated through a device input / output (IO) pad by a backup function, this is advantageous. This may reduce signal monitoring accuracy because multiple signals need to be allocated to the same IO pad and the distance between the PLL and the IO pad that may require a pipeline stage increases (such as within the range of several millimeters). In addition, due to a divider and the logic between the PLL and the IO pad, signal monitoring on the IO pad may be inaccurate, which reduces the accuracy of measuring parameters such as frequency.

[0019] Specific logic (in other words, test blocks or test logic circuits) can be controlled and monitored using a suitable standard interface (e.g., IEEE 1149.1 interface, IEEE 1500 interface, or IEEE 1687 interface) using a test controller. Therefore, the classic IEEE standard interface pins are available on the test controller because the boundary scan standard is generally required to meet the IEEE standard (e.g., IEEE 1149.x). Embodiments of the present disclosure may provide advantages such as simplifying the PLL test architecture, allowing more accurate measurement of the PLL signal, reducing the test time for the PLL and thus allowing the parallel execution of the PLL, standardizing the PLL test architecture between different products, improving the accuracy of frequency testing (such as by adjusting the reference capture window), and simplifying the test process on the automatic test equipment (ATE), which can reduce the complexity on the board or device and thus allow lower cost testing. Embodiments may allow the application of PLL testing during the burn-in phase of the board, such as by using a standard interface (e.g., Joint Test Action Group (JTAG) 1149.1). Embodiments also provide the ability to run PLL tests in applications using an Advanced Peripheral Bus (APB) interface to monitor PLL frequency and wake-up time.Some embodiments include built-in self-test technology (BIST) frequency capability.

[0020] Embodiments of the present disclosure are described in the context of the accompanying drawings. Embodiments of a system for testing one or more phase-locked loops will use Figure 1 An embodiment of a test block for testing a phase locked loop will use Figures 2 to 5 An embodiment of a method for testing a circuit will use Figure 6 is described.

[0021] Figure 1 A block diagram of a system 100 for testing a phase-locked loop 200 is illustrated. The system 100 includes the phase-locked loop 200 and may be part of a larger device such as a system on a chip (SoC) or the like that may be used in automotive applications. However, the system 100 may be included in any suitable device or system. A test controller 300 and a test block 400 are coupled to the phase-locked loop 200. Although a phase-locked loop 200 and a test block 400 are composed of Figure 1, but any suitable number of phase locked loops 200 may be coupled to and tested by the test controller 300 and any suitable number of test blocks 400. In some embodiments, the system 100 includes a plurality of phase locked loops 200 and test blocks 400, and each phase locked loop 200 is coupled to and tested by a corresponding test block 400. In other embodiments, a plurality of phase locked loops 200 are coupled to and tested by a single test block 400, such as by multiplexing the outputs of a plurality of phase locked loops 200 that are close to each other to a single corresponding test block 400.

[0022] Due to the test block 400, the phase-locked loop signals do not need to be routed through, for example, the device IO pads, because these signals are connected to the test controller 300. This can reduce or avoid the need for complex routing monitoring of the signals on the device IO pads. One or more phase-locked loops 200, the test controller 300, and the test block 400 can be part of the same electronic device, such as one or more semiconductor chips (or, in the case of a chipset, one or more semiconductor dies) that can be mounted on a circuit board.

[0023] The example phase-locked loop 200 includes an input divider 202, a phase frequency detector (PFD) 204, a feedback divider 206, a voltage controlled oscillator (VCO) 208, an output divider 210, and a locking circuit 212. The input divider 202 receives a reference signal from a reference clock 130. In some embodiments, the reference clock 130 is an accurate and stable frequency source, such as a crystal (e.g., quartz) oscillator that provides good accuracy and stability. The input divider 202, the feedback divider 206, and the input divider 210 can be coupled to a phase-locked loop control register 304 of a test controller 300.

[0024] The phase frequency detector 204 is coupled to the input divider 202 and the feedback divider 206. The phase frequency detector 204 generates a signal output representing the phase difference between the inputs from the input divider 202 and the feedback divider 206. The signal output is coupled to the voltage controlled oscillator 208, thereby controlling the oscillation frequency of the voltage controlled oscillator 208. The output of the voltage controlled oscillator 208 is coupled to the feedback divider 206 to provide stability to the voltage controlled oscillator 208 along the feedback loop. The output of the voltage controlled oscillator 208 is also coupled to the output divider 210 to reduce the output frequency of the signal from the voltage controlled oscillator 208. The output from the output divider 210 is coupled to the test block 400 to provide a fast clock signal to be evaluated by the test block 400. The output from the output divider 210 is not coupled only to the test block 400, because it is also coupled to the functional logic that receives the fast clock signal from the phase locked loop 200, thereby acting functionally. The locking circuit 212 is coupled to the output from the phase frequency detector 204 to determine whether the phase locked loop 200 is in a locked state. The output signal from the locking circuit 212 indicating that the phase locked loop 200 is in a locked state is coupled to the test block 400. The output from the locking circuit 212 can also be coupled to any suitable input (e.g., an input of functional logic) to provide a signal indicating whether the phase locked loop 200 is in a locked state.

[0025] Phase locked loop 200 is included as a non-limiting example, and the test architecture (including test block 400) may be used to test any suitable phase locked loop circuit, and thus any and all such combinations of phase locked loops with the test architecture are within the scope of the disclosed embodiments.

[0026] The test controller 300 can be controlled (e.g., during manufacturing testing) using a suitable standard interface (e.g., IEEE 1149.1, IEEE 1500, or IEEE 1687). In some embodiments, the test controller 300 is controlled via a bridge 350 (e.g., an APB to IEEE bridge) using an advanced peripheral bus (APB) interface. This can be advantageous by enabling the test block 400 to be run during the runtime of an application (e.g., an automotive application or other application of a device including the system 100 that is run after manufacturing is complete), and allows monitoring of the phase-locked loop lock time and the phase-locked loop frequency. The application can monitor the phase-locked loop lock time when the phase-locked loop is awakened, and monitor the phase-locked loop lock frequency at any time during the life of the application. This may be useful for measuring frequency drift over time in an application (e.g., at different temperatures or across a device history timeline at different points to check for aging effects). This may be a critical feature for safety applications in particular (e.g., safety functions for automotive applications). The test controller 300 allows for testing of multiple phase-locked loops in nearly parallel (in other words, parameters are loaded serially into the phase-locked loops and the testing of the phase-locked loops is performed in parallel), which can save testing time during manufacturing. Thus, the system 100 including one or more phase-locked loops 200, the test controller 300, and the one or more test blocks 400 allows for testing the functional requirements of the phase-locked loops 200 together with the manufacturing requirements of testing the phase-locked loops 200. This can increase the testing performance for testing both functional requirements and manufacturing requirements.

[0027] The test controller 300 includes a control circuit 302, a phase-locked loop control register 304, a test block control register 306, and a test block status register 308. In some embodiments, the control circuit 302 includes a finite state machine, control logic, the like, or a combination thereof using an IEEE standard. However, any suitable control circuit 302 may be used. The control circuit 302 may control components of the phase-locked loop 200 (e.g., input divider 202, feedback divider 206, and output divider 210), and may control the test block 400 through the test block control register 306. The control circuit 302 also receives outputs from the test block 400 (e.g., data on the number of clock cycles counted by the test block 400) through the test block status register 308.

[0028] The test block 400 (also referred to as a test logic circuit) is used to test one or more phase-locked loops 200 by, for example, measuring the frequency of a fast clock signal from the phase-locked loop 200. The test block 400 receives inputs from the phase-locked loop 200 (e.g., a fast clock signal from the output divider 210 and a lock status signal from the lock circuit 212) and inputs from the test block control register 306 of the test controller 300 (e.g., a test enable signal, a reference clock period signal, and a delay signal).

[0029] The test block 400 also includes receiving a clock gating unit enable signal from the clock gating control circuit 110 and receiving an asynchronous reset signal from the reset providing circuit 120. The clock gating control circuit 110 is any suitable circuit that can provide the clock gating unit enable signal, and the reset providing circuit 120 is any suitable circuit that can provide the reset providing signal. In some embodiments, the clock gating unit enable signal and / or the asynchronous reset signal are provided from the test controller 300 or an APB interface coupled to the test controller 300. However, any suitable circuit can be used to provide the clock gating unit enable signal and the asynchronous reset signal to the test block 400.

[0030] An embodiment of the test block 400 is described below with respect to Figure 2 is described in more detail. Figure 1 The system 100 is shown to include a test block 400, but the system 100 may also include the following respectively with respect to Figure 3 , Figure 4 and Figure 5 The described test block 500 , test block 600 , or test block 700 , and any and all such combinations are within the scope of the disclosed embodiments.

[0031] Figure 2 FIG. 4 is a block diagram of a test block 400 for testing a phase-locked loop according to some embodiments. The test block 400 is associated with a phase-locked loop (eg, phase-locked loop 200; see above, Figure 1 ) and a test controller (e.g., test controller 300; see above, Figure 1) coupling. Test block 400 (also referred to as specific logic) is used to monitor the locking signal and the phase-locked loop clock frequency directly using the phase-locked loop output signal. This is advantageous because the phase-locked loop signal does not need to be propagated through other circuit devices (e.g., device IO pads). Test block 400 includes input terminal 402, input terminal 404, input terminal 406, input terminal 408, input terminal 410, input terminal 412, input terminal 414 and input terminal 416, output terminal 420, output terminal 422, output terminal 424 and output terminal 426, synchronizer 430, one or more clock gating units 440, lock cycle counter 450, delay reference counter 460, reference cycle counter 470, and fast cycle counter 480. Lock cycle counter 450, delay reference counter 460, reference cycle counter 470 and fast cycle counter 480 are circuits including suitable logic gates (combinatorial logic gates, sequential logic gates, or combinations thereof), other circuit components, similar components, or combinations thereof.

[0032] The input terminal 402 receives a signal (also referred to as a test enable signal) that enables the test block 400. The test enable signal may be provided from the test block control register 306 of the test controller 300. The input terminal 402 is coupled to the fast cycle counter 480 through the first synchronizer 430 and the first clock gating unit 440. When the signal received at the input terminal 402 is 0, the test block 400 is turned off. When the signal received at the input terminal 402 transitions from 0 to 1, the test block 400 starts operating, and when the signal received at the input terminal 402 transitions from 1 to 0, the test block 400 stops operating.

[0033] Input terminal 404 receives a signal (also referred to as a test gating clock signal) coupled to a corresponding input of one or more clock gating cells 440. The test gating clock signal may be provided by, for example, clock gating control circuit 110 (see above, Figure 1) is provided. The test gating clock signal is an enable signal for one or more clock gating cells 440. The test gating clock signal can be used to cover defects related to the clock gating cells 440 during an automatic test pattern generation (ATPG) step, which is advantageous because many current devices include a scan architecture. In various embodiments, the clock gating cell (e.g., clock gating cell 440) has a test enable (TE) pin (such as a lower input of an OR gate 442) that is at a high voltage when automatic test pattern generation is run (such as shifting into a scan chain) to prevent shift problems in the scan chain. The test pin can be kept at a low value (e.g., 0 compared to 1 while the automatic test pattern generation is run) during the capture cycle to increase coverage on the upper input of the OR gate 442, which can be coupled to the output of the synchronizer 430.

[0034] Input terminal 406 is connected from the output divider 210 (see above, Figure 1 ) receives a clock signal (also referred to as a fast clock signal). The fast clock signal is one of the inputs from the phase-locked loop 200 that is monitored and tested by the test block 400.

[0035] Input terminal 408 receives a reference clock expected period signal from a bus coupled to the test block control register 306 of the test controller 300. The reference clock expected period signal provides the number of reference clock periods to be used by the test block 400 to capture the number of clock periods of the fast clock signal. In some embodiments, the expected number of reference clock periods is in the range of 256 cycles to 65536 cycles.

[0036] Input terminal 410 provides an asynchronous reset signal to flip-flops included in test block 400, such as flip-flops in lock cycle counter 450, delay reference counter 460, reference cycle counter 470, and fast cycle counter 480. The asynchronous reset signal can be provided by, for example, reset providing circuit 120 (see above, Figure 1 The asynchronous reset signal enables the reset of sequential elements such as the locked cycle counter 450, the delayed reference counter 460, the reference cycle counter 470, and the fast cycle counter 480.

[0037] Input terminal 412 provides a delay time (measured in terms of reference clock cycles) between the switching of the test enable signal from 0 to 1 to enable the test block 400 and the start of the counting of fast clock cycles. The delay signal (also referred to as the clock delay signal) can be provided from a bus coupled to the test block control register 306 of the test controller 300. This is advantageous because when the phase-locked loop 200 is enabled, the phase-locked loop 200 may not be in a stable condition, such as to achieve a resolution on the order of parts per million (ppm) and / or lower jitter. Therefore, a certain amount of delay time (provided by the delay signal through input terminal 412) can be useful in order to have a stable and reliable measurement of the fast clock from the phase-locked loop 200.

[0038] Input terminal 414 provides a reference clock signal used as a time reference for counting fast clock cycles of phase-locked loop 200. The reference clock signal may be obtained from reference clock 130 (see above, Figure 1 ) is provided.

[0039] Input terminal 416 provides a lock signal indicating that the phase-locked loop 200 is in a locked condition, so that the fast clock signal generated by the phase-locked loop 200 (and delivered to input terminal 406) is set to the desired frequency. This may be useful because the measurement of the time between when the phase-locked loop 200 is set or enabled and when the phase-locked loop 200 is locked may be a phase-locked loop specification requirement that is desired to be checked. The lock signal may be obtained from the lock circuit 212 (see above, Figure 1 ) is provided.

[0040] The first synchronizer 430 receives a test enable signal from the input terminal 402 and receives a fast clock signal from the input terminal 406. In some embodiments, the synchronizer 430 is a circuit constructed using a plurality of pipeline trigger stages (e.g., two to three pipeline trigger stages). However, any suitable synchronization circuit can be used for the first synchronizer 430. The synchronizer 430 can be used in the test block 400 to reduce or prevent metastability problems, such as when the clock signal is asynchronous with respect to the data signal. For example, the test enable signal can be asynchronous with respect to the fast clock signal, so the first synchronizer 430 is conducive to reducing or preventing metastability problems.

[0041] The second synchronizer 430 receives the reference clock signal from the input terminal 414 and receives the locking signal from the input terminal 416. The second synchronizer 430 can be helpful to reduce or prevent the metastability problem that may occur when the locking signal is asynchronous with respect to the reference clock signal. The second synchronizer 430 can be substantially similar to the first synchronizer 430 as described above, and the details are not repeated in this article. However, any suitable synchronization circuit can be used for the second synchronizer 430.

[0042] The first clock gating unit 440 receives the synchronized input from the first synchronizer 430, receives the test gating clock signal from the input terminal 404, and receives the fast clock signal from the input terminal 406. A clock gating unit such as the first clock gating unit 440 is used to gate the fast clock and save power when the logic of the test block 400 is off (in other words, when the test enable signal is set to 0). Figure 2 In the illustrated example, the first clock gating cycle 440 includes an OR gate 442, a latch 444, and an AND gate 446. The OR gate 442 receives synchronized inputs from the test enable signal and the first synchronizer 430 of the fast clock signal and the test gating clock signal. The latch 444 receives the output of the OR gate 442 and the fast clock signal as inputs through an inverter. The AND gate 446 receives the fast clock signal and the output of the latch 444 as inputs. As the output of the first clock gating unit 440, the output of the AND gate 446 is a gated fast clock signal coupled to the input of the fast cycle counter 480. However, the first clock gating unit 440 can have any suitable structure and components.

[0043] In some embodiments, the third synchronizer 430 receives a test enable signal from the input terminal 402 and receives a reference clock signal from the input terminal 414. The third synchronizer 430 can be useful for reducing or preventing metastability problems that may occur when the test enable signal is asynchronous with respect to the reference clock signal. The third synchronizer 430 can be substantially the same as the first synchronizer 430 as described above, and the details are not repeated herein. However, any suitable synchronization circuit can be used for the third synchronizer 430. The third synchronizer 430 is illustrated with a dotted line because it is optional depending on whether the test enable signal is synchronized with the reference clock signal.

[0044] In some embodiments, the second clock gating unit 440 receives a synchronized input from the third synchronizer 430, receives a test gating clock signal from the input terminal 404, and receives a reference clock signal from the input terminal 414. The second clock gating unit 440 can be similar to the first clock gating unit 440 as described above, with a replacement of the reference clock signal for the fast clock signal, and the details are not repeated herein. However, any suitable clock gating unit can be used for the second clock gating unit 440. The second clock gating unit 440 is also illustrated with a dashed line because it can be optional, because, for example, in some cases the clock gating unit can be placed outside the test block 400, so that the reference clock signal is tied to a higher level in the hierarchy of the larger device. This can be beneficial to save power when the test block 400 is invalid, because it can avoid the second clock gating unit 440 being valid even when the test block 400 is not used. In these cases, the reference clock signal is propagated to the test block 400 only when it is needed (in other words, when the test block 400 is active), and the second clock gating unit 440 may not be needed.

[0045] The lock cycle counter 450 measures the activation to lock state time of the phase-locked loop 200. The lock cycle counter 450 receives the reference clock signal (the reference clock signal may be gated by the second clock gating unit 440 (if present)), the lock signal (synchronized with the reference clock signal) from the second synchronizer 430, and receives the test enable signal (the test enable signal may be synchronized with the reference clock signal by the third synchronizer 430 (if present)) and the asynchronous reset signal from the input terminal 410 as inputs. The lock cycle counter 450 uses the reference clock signal (with or without synchronization and / or clock gating) and is enabled when the test enable signal (with or without synchronization with the reference clock signal) changes from 0 to 1. This starts counting the clock cycles of the phase-locked loop 200 using the reference clock signal as a reference until the lock signal (with synchronization with the reference clock signal) also changes from 0 to 1.

[0046] The lock cycle counter 450 provides a lock cycle count signal as an output to the output terminal 424, which is the number of lock cycles measured between the assertion of the test enable signal and the time when the lock signal reaches its high value (e.g., 1). The lock cycle count signal can be multiplied by the period of the reference clock to provide the lock time of the phase-locked loop 200 (in other words, the time it takes for the phase-locked loop 200 to reach a locked state from its activation). The lock time can be used to check whether the phase-locked loop 200 is performing according to its specifications. The lock cycle counter 450 also provides a lock count end signal as an output to the output terminal 426, which becomes 1 when the count ends (in other words, when the lock cycle signal is at 1). This can be used to verify that the lock cycle count signal is reliable. The output terminal 424 and the output terminal 426 are coupled to the test controller 300 through the test block status register 308 to provide the lock cycle count signal and the lock count end signal to the test controller 300, respectively.

[0047] The delay reference counter 460 delays the initial count of the fast clock signal from the phase-locked loop 200 and the count of the reference cycle counter 470 by a specific time after the phase-locked loop 200 is started, when the phase-locked loop 200 is not in a stable condition, such as to achieve a resolution of the order of parts per million (ppm) and / or lower jitter. The delay reference counter 460 receives the delay signal from the input terminal 412, the reference clock signal (which can be gated by the second clock gating unit 440 (if present)), the lock signal (synchronized with the reference clock signal) from the second synchronizer 430, the test enable signal (which can be synchronized with the reference clock signal by the third synchronizer 430 (if present)) and the asynchronous reset signal from the input terminal 410 as input. The delay reference counter uses the reference clock signal (with or without synchronization and clock gating) as a reference and starts counting when the test enable signal (with or without synchronization) changes from 0 to 1 and the lock signal (after synchronization with the reference clock signal) reaches a high value of 1. The delayed reference counter 460 circuit then counts the number of cycles of the reference clock provided by the delayed signal before enabling the reference cycle counter 470 by sending an enable signal, such as a signal having a value of 1.

[0048] The reference cycle counter 470 provides an output that sets a window over which the fast cycle counter 480 performs its counting. The reference cycle counter 470 receives a reference clock expected period signal from the input terminal 408, a reference clock signal (which may be gated by the second clock gating unit 440 (if present)), a lock signal (synchronized with the reference clock signal) from the second synchronizer 430, a test enable signal (which may be synchronized with the reference clock signal by the third synchronizer 430 (if present)) and an enable signal from the delay reference counter 460, and an asynchronous reset signal from the input terminal 410 as input. When the reference cycle counter 470 receives the enable signal of 1 from the delay reference counter 460, and when the lock signal and the test enable signal (with or without synchronization) are also 1, the reference cycle counter 470 is enabled. The reference cycle counter 470 then starts counting the reference clock cycles from the reference clock signal (with or without synchronization and clock gating) as a reference. The output of the reference cycle counter 470 is coupled to the fast cycle counter 480 through the fourth synchronizer 430.

[0049] The fourth synchronizer 430 receives the counted reference clock cycle signal from the reference cycle counter 470 and receives the fast clock signal from the input terminal 406. The counted reference clock cycle signal from the reference cycle counter 470 becomes valid when the reference cycle counter 470 starts counting. The counted reference clock cycle signal from the reference cycle counter 470 remains valid until the reference counter 470 reaches its count end point as given by the value of the reference clock expected cycle signal from the input terminal 408. The fourth synchronizer 430 can be advantageous in synchronizing the counted reference clock cycle signal with the fast clock signal, thereby setting a window in which the fast cycle counter 480 performs its counting. The fourth synchronizer 430 can be substantially the same as the first synchronizer 430 as described above, and the details are not repeated herein. However, any suitable synchronization circuit can be used for the fourth synchronizer 430. In some embodiments, the counted reference clock cycle signal is synchronized with the fast clock signal by using the output from the first clock gating unit 440 instead of the clock of the fourth synchronizer 430.

[0050] The fast cycle counter 480 counts fast clock cycles from the phase-locked loop 200 to measure the performance of the phase-locked loop 200. The fast cycle counter 480 receives the gated fast clock signal from the first clock gating unit 440, receives the counted reference clock cycle signal (synchronized with the fast clock signal through the fourth synchronizer 430) from the reference cycle counter 470, and receives the asynchronous reset signal from the input terminal 410 as input. The fast cycle counter 480 receives the fast clock signal (after synchronization and clock gating) and counts cycles of the fast clock signal when the counted reference clock cycle signal is within the window set by the reference clock expected cycle signal, and also receives other constraints on the activation of the reference cycle counter 470 described above with respect to the reference cycle counter 470 (e.g., potential delays from the delay reference counter 460).

[0051] The counted number of cycles of the fast clock signal is provided as a fast cycle count signal to the output terminal 420. The fast cycle count signal provides the number of fast clock cycles counted in the expected number of reference clock cycles (with the expected number of cycles initially provided by the reference clock expected through the input terminal 408). This value provides a ratio between the rate of the fast clock of the phase-locked loop 200 and the reference clock, which is used (e.g., by the test controller 300) to determine the frequency of the fast clock. The fast cycle counter 480 marks the count as complete using the fast completion signal, which verifies the value of the fast cycle count signal when the fast completion signal is set to 1. The fast cycle counter 480 provides the fast completion signal as an output to the output terminal 422. The fast completion signal is used (e.g., by the test controller 300) to check when the fast cycle counter 480 has finished counting the fast clock cycles, thereby indicating that the fast cycle count signal is reliable. The output terminal 420 and the output terminal 422 are coupled to the test controller 300 through the test block status register 308 to provide the fast cycle count signal and the fast completion signal to the test controller 300, respectively.

[0052] The location and coupling of the synchronizer 430 and the one or more clock gating cells 440 with respect to the other components of the test block 400 are included as non-limiting examples. Any suitable location and coupling of the synchronizer 430 and the one or more clock gating cells 440 with respect to the other components of the test block 400 is within the scope of the disclosed embodiments.

[0053] Figure 3 FIG. 5 is a block diagram of a test block 500 (also referred to as a test logic circuit) for testing a phase-locked loop according to some embodiments. The test block 500 is similar to the test logic circuit described above. Figure 2The test block 400 described is similar with the addition of input terminals 502 and 504, fast cycle comparator 580, and output terminal 520. Test block 500 provides the functionality of evaluating whether the frequency of the fast clock is within an expected range.

[0054] Input terminal 502 receives the expected fast cycle signal from the output bus. The expected fast cycle signal is the expected number of fast clock cycles counted by fast cycle counter 480 (in other words, the expected number of fast cycle count signals; see above, Figure 2 ). In some embodiments, the expected number of fast clock cycles is in the range of 1000 cycles to 16000 cycles. In some embodiments, the output bus is coupled to the test block control register 306 of the test controller 300, and the test controller 300 provides the expected number of fast cycles. However, the output bus can be coupled to any suitable circuit to supply the expected fast cycle signal to the input terminal 502.

[0055] Input terminal 504 receives a fast cycle range signal from the output bus. The fast cycle range signal is a tolerance set between the expected fast cycle signal and the obtained number of the fast cycle count signal. In some embodiments, the output bus is coupled to the test block control register 306 of the test controller 300, and the test controller 300 provides the fast cycle range. However, the output bus can be coupled to any suitable circuit to supply the fast cycle range to the input terminal 504. In some embodiments, the value of the fast cycle range is between 2 and 16.

[0056] The fast cycle comparator 580 performs a comparison between the measured number of fast cycles and the expected number of fast cycles. The fast cycle comparator 580 can be a combinational logic circuit or a circuit using sequential logic. However, any suitable circuit can be used for the fast cycle comparator 580. The fast cycle comparator 580 receives the expected fast cycle signal from the input terminal 502, the fast cycle range signal from the input terminal 504 and the fast cycle count signal from the fast cycle counter 480 as inputs.

[0057] In some embodiments, the fast cycle comparator 580 evaluates the fast cycle range as the number of cycles, and the fast cycle count signal can be above or below the expected fast cycle signal. In other words, the fast cycle comparator 580 performs a comparison between the measured value of the fast cycle from the fast cycle counter 480 and the expected range of the expected value of the fast cycle. The expected range is the expected number of fast cycles minus the fast cycle range to the expected number of fast cycles plus the fast cycle range, or in other words, the expected range extends to the expected number of fast clock cycles above and below the fast cycle range. This can set the range of effective values ​​of the fast cycle counted. This tolerance is advantageous because the number of fast cycles counted for the expected number of reference clock cycles may not be a fixed value and can vary to a certain extent. This may be due to factors such as the fast clock of the phase-locked loop 200 being asynchronous with the reference clock and the possible jitter of the fast clock (related to the operation of the phase-locked loop 200). Therefore, it is desirable to monitor a narrow window of values ​​around the expected value of the fast cycle rather than the exact number of fast cycles.

[0058] The fast cycle comparator 580 provides a fast status signal as an output to the output terminal 520, which is coupled to the test controller 300 through the test block status register 308 to provide the fast status signal to the test controller 300. The fast status signal indicates whether the measured value of the fast cycle is within the expected range of the expected value of the fast cycle. For example, the fast status signal can be 1 when the measured value of the fast cycle is within the expected range, and 0 when the measured value of the fast cycle is outside the expected range. When the fast completion signal (see above, Figure 2 ) is set to 1, the value of the fast status signal will be valid.

[0059] The test block 500 allows setting an expected value of the fast cycle and setting an expected range to check if the frequency of the fast clock of the phase locked loop 200 is within the expected range. Adjusting the expected range of the expected value of the fast cycle allows checking the frequency of the fast clock by performing multiple measurements within the time range (in other words, sampling the fast cycle count in different time slices) and checking the frequency deviation or modulation of the fast frequency to the expected frequency, which can help identify the frequency offset or modulation. This can be performed during the manufacture of the device and during the operation of the completed device as part of an application (e.g., an automotive application), such as using a specific structure (e.g., an APB bridge) that is also used in the application.

[0060] Figure 4 FIG. 4 is a block diagram of a test block 600 (also referred to as a test logic circuit) for testing a phase-locked loop according to some embodiments. The test block 600 is similar to the test logic circuit described above. Figure 2The test block 400 described above is similar, with the addition of an input terminal 602, a lock comparator 650, and an output terminal 620. The test block 600 provides for evaluating the lock cycle counter 450 (see above, Figure 2 ) is below the expected maximum lock period provided from input terminal 602.

[0061] Input terminal 602 receives the expected maximum lock cycle signal from the output bus. The expected maximum lock cycle signal is the maximum expected number of lock cycles counted by the lock cycle counter 450 (in other words, the expected number of reference clock cycles from the activation of the phase-locked loop 200 until it reaches the locked state; see above, Figure 2 ). In some embodiments, the output bus is coupled to the test block control register 306 of the test controller 300, and the test controller 300 provides the expected maximum number of lock cycles. However, the output bus can be coupled to any suitable circuit to supply the expected maximum lock cycle signal to the input terminal 602.

[0062] The lock comparator 650 performs a comparison between the measured number of lock cycles from the lock cycle counter 450 and the expected maximum number of lock cycles. In some embodiments, the lock comparator 650 is a combinational logic circuit or a circuit using sequential logic. In an embodiment where the lock comparator 650 is a circuit using sequential logic, the lock comparator 650 receives a suitable clock signal from a suitable clock circuit as input. However, any suitable circuit can be used for the lock comparator 650. The lock comparator 650 receives the expected maximum lock cycle signal from the input terminal 602 and the lock cycle count signal from the lock cycle counter 450 as input.

[0063] The lock comparator 650 provides a lock status signal as an output to the output terminal 620, which is coupled to the test controller 300 through the test block status register 308 to provide the lock status signal to the test controller 300. The lock status signal is a single signal that indicates whether the measured number of lock cycles exceeds the expected maximum number of lock cycles. If the measured number of lock cycles does not exceed the expected maximum number of lock cycles, the phase-locked loop 200 lock time may be outside the expected range of its specifications. This may indicate that the phase-locked loop 200 may have internal damage. In this case, the lock status signal will remain at 0 to indicate that the phase-locked loop 200 lock time is outside the expected range. If the measured number of lock cycles does not exceed the expected maximum number of lock cycles, the phase-locked loop 200 lock time is within the expected range. In this case, the lock status signal will remain at 1 to indicate that the phase-locked loop 200 lock time is within the expected range. When the lock count end signal (see above, Figure 2) is set to 1, the value of the lock status signal will be valid.

[0064] In some embodiments of the system 100 having the test block 600, when the test enable signal from the input terminal 402 enables the test block 600, the fast clock signal from the input terminal 406 and the lock signal from the input terminal 416 (see above, Figure 2 In other embodiments, the check of the fast clock signal is separated from the check of the lock signal, so that only the frequency of the fast clock signal is monitored during the runtime of the application and the lock signal is only monitored during the wake-up period of the test block 600.

[0065] Figure 5 FIG. 1 is a block diagram of a test block 700 (also referred to as a test logic circuit) for testing a phase-locked loop according to some embodiments. The test block 700 is similar to the test logic circuit described above. Figure 2 The test block 400 described above is similar to the test block 400 described above, with the addition of the test block 500 (see above, Figure 3 ) in the input terminal 502 and the input terminal 504, the fast cycle comparator 580 and the output terminal 520, and adds the test block 600 (see above, Figure 4 ) in the input terminal 602, the locking comparator 650 and the output terminal 620. In other words, the embodiment of the test block 700 combines the above-mentioned Figure 3 and Figure 4 The embodiments of test block 500 and test block 600 are described, and the details are not repeated herein. Test block 700 provides an evaluation of whether the frequency of the fast clock is within the expected range and ... Figure 2 )'s lock cycle count is below the expected value.

[0066] As mentioned above, Figure 3 , Figure 4 and Figure 5 The described embodiments of test block 500, test block 600, and test block 700 allow for the addition of a test controller 300 (see above, Figure 1 ) can be run with a built-in self-test (BIST) because the test controller 300 can monitor the fast status signal and / or the locked status signal instead of monitoring the expected counter value for both the fast cycle count signal and the locked cycle count signal. This can increase the efficiency of the communication for the built-in self-test by reducing the amount of bandwidth used.

[0067] In some embodiments (e.g., embodiments of test block 500, test block 600, and test block 700), when the corresponding test block ends the check of the phase-locked loop 200, an interrupt signal can be added so that the pass / fail flag can be checked without using a polling mechanism (e.g., through an APB interface coupled to the test controller 300). In some embodiments, when the device is powered on, the APB is set to configure the expected control registers of the test controller 300. During the subsequent run time, the test controller 300 can directly control the start signal (e.g., the test enable signal) and monitor the fast cycle count signal and the fast completion signal for the fast clock of the phase-locked loop 200, and the lock cycle count signal and the lock count end signal for the lock time of the phase-locked loop 200. This is advantageous because it reduces the need to read or write to the test controller 300 through the APB during the application run time, because the interrupt signal allows data to be read at the end of the operation without polling the register content. In addition to the case where the phase-locked loop 200 is locked, the interrupt signal can also be generated at the end of the fast cycle count signal.

[0068] Although the above Figure 1 The system 100 is illustrated as including a test block 400 (described above with respect to Figure 2 ), but in some embodiments, system 100 includes test block 500 (described above with respect to Figure 3 Description), test block 600 (described above with respect to Figure 4 Description) or test block 700 (described above with respect to Figure 5 ) instead of the test block 400. In addition, in some embodiments, the system 100 includes a plurality of phase-locked loops, each of which is coupled to a corresponding test block. Each corresponding test block can be any one of the test block 400, the test block 500, the test block 600, or the test block 700, and any and all such combinations are within the scope of the disclosed embodiments. For example, the system may include a plurality of phase-locked loops 200 coupled to one of the test blocks 400, the test block 500, the test block 600, or the test block 700 and a test controller 300. In this example, the test controller 300 has registers that allow selection of an input terminal 406 for receiving a (multiple) fast clock signal and an input terminal 416 for receiving a (multiple) lock signal from the selected phase-locked loop 200. Appropriate phase-locked loop control registers 304 and test block status registers 308 can be programmed or checked depending on the phase-locked loop 200 being tested. This can be beneficial in saving silicon area.

[0069] Figure 68. A flow chart of a method 800 for testing a circuit according to some embodiments is illustrated. In step 802, a test logic circuit (eg, test block 400) is enabled using test controller 300, as described above with respect to Figure 1 and Figure 2 The test logic circuit is coupled to the phase locked loop 200 and is coupled to the test controller 300 .

[0070] In step 804, the test logic circuit counts the number of clock cycles of the phase locked loop 200 using the reference clock 130 as a reference, as described above with respect to Figure 2 The reference clock 130 is coupled to the test block 400 .

[0071] In step 806, the test controller 300 uses the counted number of clock cycles to determine the clock frequency of the phase locked loop 200, as described above with respect to Figure 2 described.

[0072] Example embodiments of the present disclosure are summarized herein. Other embodiments may also be understood from the entirety of the specification and claims filed herein.

[0073] Example 1. A system for testing a circuit, the system comprising: a phase-locked loop; a test logic circuit, the test logic circuit is coupled to the phase-locked loop, the test logic circuit is configured to count the number of clock cycles of the phase-locked loop using a reference clock as a reference, the reference clock is coupled to the test logic circuit; and a test controller, the test controller is coupled to the phase-locked loop and the test logic circuit, the test controller is configured to measure the clock frequency of the phase-locked loop using the counted number of clock cycles received from the test logic circuit.

[0074] Example 2. The system of Example 1, wherein the test logic circuit is further configured to count a number of cycles of the reference clock between an activation time of the phase-locked loop and a locked state time of the phase-locked loop.

[0075] Example 3. The system of Example 2, wherein the test logic circuit is further configured to provide a lock status signal to the test controller based on a counted number of reference clock cycles between an activation time of the phase-locked loop and a locked state time of the phase-locked loop.

[0076] Example 4. The system of any of Examples 2 or 3, wherein the test logic circuit includes a reference cycle counter configured to set a window over which a number of clock cycles of the phase-locked loop is counted.

[0077] Example 5. The system of Example 4, wherein the test logic circuit further comprises a delayed reference counter configured to enable the reference cycle counter after a delay time.

[0078] Example 6. The system of any one of Examples 1 to 5, wherein the test logic circuit includes a clock gating unit configured to gate a clock signal from a phase-locked loop.

[0079] Example 7. The system of any of Examples 1 to 6, wherein the test controller is controlled using an advanced peripheral device bus interface, the advanced peripheral device bus interface being coupled to the test controller via a bridge.

[0080] Example 8. The system of any of Examples 1 to 7, wherein the test controller is further configured to use an IEEE 1149.1, IEEE 1149.x, IEEE 1500, or IEEE 1687 interface.

[0081] Example 9. The system of any of Examples 1 to 8, wherein the test controller is further configured to run a built-in self test.

[0082] Example 10. A system for testing a circuit, the system comprising: a phase-locked loop; a test logic circuit, the test logic circuit being coupled to the phase-locked loop, the test logic circuit comprising: a lock cycle counter, the lock cycle counter being configured to count the number of cycles of a reference clock between an activation time of the phase-locked loop and a lock state time of the phase-locked loop, the reference clock being coupled to the test logic circuit; and a fast cycle counter, the fast cycle counter being configured to count the number of fast clock cycles of the phase-locked loop using the reference clock as a reference; and a test controller, the test controller being coupled to the phase-locked loop and the test logic circuit, the test controller being configured to receive a lock cycle count signal from the lock cycle counter and to receive a fast cycle count signal from the fast cycle counter.

[0083] Example 11. The system of Example 10, wherein the lock cycle counter is further configured to provide a lock condition signal to the test controller.

[0084] Example 12. The system of any of Examples 10 or 11, wherein the fast cycle counter is further configured to provide a fast status signal to the test controller.

[0085] Example 13. A system according to any of Examples 10 to 12, wherein the test logic circuit further includes a lock comparator configured to perform a comparison between a measured number of lock cycles from the lock cycle counter and an expected maximum number of lock cycles.

[0086] Example 14. The system of Example 13, wherein the expected maximum number of lockout cycles is provided from the test controller to the lockout comparator.

[0087] Example 15. A system according to any of Examples 10 to 14, wherein the test logic circuit further includes a fast cycle comparator configured to perform a comparison between a measured number of fast clock cycles from the fast cycle counter and an expected number of fast clock cycles.

[0088] Example 16. A system according to Example 15, wherein the fast cycle comparator is further configured to perform a comparison between the measured number of fast clock cycles from the fast cycle counter and the expected number of fast clock cycles using a range, the range extending above and below the expected number of fast clock cycles up to a fast clock range.

[0089] Example 17. The system of Example 16, wherein the expected number of fast clock cycles and the fast cycle range are provided from the test controller to the fast cycle comparator.

[0090] Example 18. A method for testing a circuit, the method comprising: enabling a test logic circuit using a test controller, the test logic circuit being coupled to a phase-locked loop and coupled to the test controller; counting the number of clock cycles of the phase-locked loop using a reference clock as a reference using the test logic circuit, the reference clock being coupled to the test logic circuit; and determining the clock frequency of the phase-locked loop using the counted number of clock cycles using the test controller.

[0091] Example 19. The method of Example 18, further comprising: counting, using the test logic circuit, a number of cycles of the reference clock between an activation time of the phase-locked loop and a locked state time of the phase-locked loop.

[0092] Example 20. A method according to any of Example 18 or Example 19, wherein determining the clock frequency of the phase-locked loop using the test controller occurs during the runtime of an application, the application is executed on a device, and the device includes a test logic circuit, a test controller and a phase-locked loop.

[0093] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art upon reference to this description. Therefore, the attached claims are intended to include any such modifications or embodiments.

Claims

1. A system for testing a circuit, the system comprising: Phase-locked loop; a test logic circuit coupled to the phase locked loop, the test logic circuit configured to count a number of clock cycles of the phase locked loop using a reference clock as a reference, the reference clock coupled to the test logic circuit; as well as A test controller is coupled to the phase locked loop and the test logic circuit, the test controller being configured to measure a clock frequency of the phase locked loop using the counted number of the clock cycles received from the test logic circuit. 2 . The system of claim 1 , wherein the test logic circuit is further configured to count the number of cycles of the reference clock between an activation time of the phase-locked loop and a locked state time of the phase-locked loop.

3. The system of claim 2 , wherein the test logic circuit is further configured to provide a lock status signal to the test controller based on the counted number of cycles of the reference clock between the activation time of the phase-locked loop and the locked state time of the phase-locked loop. 4 . The system of claim 2 , wherein the test logic circuit comprises a reference cycle counter configured to set a window over which the number of the clock cycles of the phase locked loop is counted. 5 . The system of claim 4 , wherein the test logic circuit further comprises a delayed reference counter configured to enable the reference cycle counter after a delay time. 6 . The system of claim 1 , wherein the test logic circuit comprises a clock gating unit configured to gate a clock signal from the phase locked loop.

7. The system of claim 1, wherein the test controller is controlled using an advanced peripheral device bus interface, the advanced peripheral device bus interface being coupled to the test controller through a bridge.

8. The system of claim 1, wherein the test controller is further configured to use an IEEE 1149.1, IEEE 1149.x, IEEE 1500, or IEEE 1687 interface.

9. The system of claim 1, wherein the test controller is further configured to run a built-in self test.

10. A system for testing a circuit, the system comprising: Phase-locked loop; a test logic circuit, the test logic circuit being coupled to the phase locked loop, the test logic circuit comprising: a lock cycle counter configured to count the number of cycles of a reference clock between an activation time of the phase locked loop and a lock state time of the phase locked loop, the reference clock being coupled to the test logic circuit; and a fast cycle counter configured to count a number of fast clock cycles of the phase locked loop using the reference clock as a reference; and A test controller is coupled to the phase locked loop and the test logic circuit, the test controller being configured to receive a locked cycle count signal from the locked cycle counter and a fast cycle count signal from the fast cycle counter. 11 . The system of claim 10 , wherein the lock cycle counter is further configured to provide a lock condition signal to the test controller.

12. The system of claim 10, wherein the fast cycle counter is further configured to provide a fast status signal to the test controller.

13. The system of claim 10, wherein the test logic circuit further comprises a lock comparator configured to perform a comparison between the measured number of lock cycles from the lock cycle counter and an expected maximum number of lock cycles.

14. The system of claim 13, wherein the expected maximum number of the lockout cycles is provided from the test controller to the lockout comparator.

15. The system of claim 10, wherein the test logic circuit further comprises a fast cycle comparator configured to perform a comparison between a measured number of fast clock cycles from the fast cycle counter and an expected number of fast clock cycles.

16. The system of claim 15, wherein the fast cycle comparator is further configured to perform a comparison between the measured number of fast clock cycles from the fast cycle counter and the expected number of fast clock cycles using a range, the range extending above and below the expected number of fast clock cycles up to a fast clock range.

17. The system of claim 16, wherein the expected number of the fast clock cycles and the fast cycle range are provided from the test controller to the fast cycle comparator.

18. A method for testing a circuit, the method comprising: enabling a test logic circuit with a test controller, the test logic circuit being coupled to a phase locked loop and the test controller; counting, with the test logic circuit, a number of clock cycles of the phase locked loop using a reference clock as a reference, the reference clock being coupled to the test logic circuit; as well as The counted number of clock cycles is used to determine, with the test controller, a clock frequency of the phase locked loop.

19. The method according to claim 18, further comprising: The test logic circuit is used to count the number of cycles of the reference clock between an activation time of the phase locked loop and a locked state time of the phase locked loop.

20. The method of claim 18, wherein determining the clock frequency of the phase-locked loop using the test controller occurs during runtime of an application, the application being executed on a device, the device including the test logic circuit, the test controller, and the phase-locked loop.

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