Integrated circuit fault detection system based on artificial intelligence

Abstract

The invention discloses an integrated circuit fault detection system based on artificial intelligence, particularly relates to the technical field of fault detection, and comprises a data acquisition module, a fault detection performance evaluation module, an algorithm optimization module and an improvement result evaluation module. On the basis of monitoring analysis of fault detection error information, cost consumption information and detection efficiency information in an integrated circuit fault detection system, the necessity of system performance and algorithm improvement is evaluated, when it is judged that the system performance is weak, a convolutional neural network-support vector machine algorithm model is constructed, and the system performance is improved. The system feature extraction and feature processing functions are improved, and the improved integrated circuit fault detection system combines system improvement information and comprehensive automation information to carry out practicability evaluation, so that the system is iterated for multiple times, and more reliable suggestions and data support are provided for subsequent construction of the integrated circuit fault detection system.

Description

Technical Field

[0001] The present invention relates to the technical field of fault detection, and more specifically, to an integrated circuit fault detection system based on artificial intelligence. Background Art

[0002] Integrated circuit fault detection systems have gradually evolved from manual detection since the 1960s. After the introduction of automated detection equipment and the integration of multiple testing technologies, they have achieved vigorous development. Today, with the popularization of machine learning and artificial intelligence, cloud computing and big data analysis, integrated circuit fault detection systems have entered the intelligent stage.

[0003] In the existing integrated circuit fault detection system, with the advantages of high-precision detection, diversified detection technology, comprehensive defect classification capabilities, improved automation and high adaptability, through high-resolution imaging technology and advanced algorithms, it can accurately detect tiny defects and anomalies while improving detection efficiency and consistency, thereby achieving the purpose of quickly locating and repairing problems.

[0004] However, the existing integrated circuit fault detection systems still have many problems that need to be solved, such as the imbalance between system costs and benefits achieved, the long processing time of high-resolution imaging and complex algorithms, which leads to slow detection speed and affects production efficiency, and the low efficiency when processing a large number of ICs, which makes it difficult to meet the needs of large-scale production. It may even result in high false alarm and missed alarm rates, affecting the reliability of detection. Summary of the invention

[0005] In order to overcome the above-mentioned defects of the prior art, an embodiment of the present invention provides monitoring and analysis of fault detection error information, cost information and detection efficiency information in an integrated circuit fault detection system, evaluates system performance and the necessity of algorithm improvement, and when it is judged that the system performance is weak, constructs a convolutional neural network-support vector machine algorithm model to improve the system feature extraction and feature processing functions. The improved integrated circuit fault detection system combines the system improvement information and comprehensive automation information to perform a practicality evaluation, thereby iterating the system multiple times and providing more reliable suggestions and data support for the subsequent construction of an integrated circuit fault detection system.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] The integrated circuit fault detection system based on artificial intelligence includes the following modules:

[0008] Data acquisition module, monitoring and collecting fault detection error information, cost information and detection efficiency information in the integrated circuit fault detection system, sample data required for the construction of the convolutional neural network-support vector machine algorithm model, and system improvement information and comprehensive automation information after the integrated circuit fault detection system is improved;

[0009] A fault detection performance evaluation module is used to build a fault detection performance evaluation model and evaluate the fault detection performance of the existing integrated circuit fault detection system;

[0010] Algorithm optimization module, for integrated circuit fault detection systems with weak fault detection, improves feature extraction and feature processing functions by building a convolutional neural network-support vector machine algorithm model;

[0011] Improve the results evaluation module, conduct a practical evaluation on the improved integrated circuit fault detection system based on system improvement information and comprehensive automation information, and iterate the convolutional neural network-support vector machine algorithm model based on the evaluation results.

[0012] Specifically, in the data acquisition module, the sample data of the integrated circuit is obtained by the joint operation of the test probe, oscilloscope, logic analyzer and automatic test equipment, and then designed and simulated by EDA software such as Cadence, Synopsys, MentorGraphics to generate test vectors to achieve the purpose of monitoring, analyzing, and processing the information related to the integrated circuit and the integrated circuit fault detection system. In actual use, due to factors such as equipment cost and complexity of real-time monitoring, the present invention is based on the premise of long-term operation of the integrated circuit fault detection system and relatively stable detection environment, and continuous monitoring of integrated circuit data, which may lead to the phenomenon of necessity change at a certain monitoring moment.

[0013] In the fault detection performance evaluation module, a fault detection performance evaluation model is constructed. The specific process is to collect the fault detection error information, cost information and detection efficiency information of the current integrated circuit fault detection system. The fault detection error information includes the fault detection error coefficient, which is calibrated as B gj , the cost information includes the cost coefficient, denoted as H cb , the detection efficiency information includes the detection efficiency coefficient, calibrated as X jc ;

[0014] Fault detection error coefficient B gj By collecting the data of the ten thousand integrated circuits recently detected by the current integrated circuit fault detection system, the number of integrated circuits that are actually not faulty but are detected as faulty by the system is calibrated as W jd , the number of ICs that were recently tested and returned for repair during the warranty period is marked as F jd, then the fault detection error coefficient B gj =W jd +F jd 2 ;

[0015] Cost consumption coefficient H cb By collecting the cost of establishing the current integrated circuit fault detection system, calibrated as J i1 , count the number of integrated circuits tested in a year, marked as S jc , then the cost consumption coefficient H cb =J j1 ÷S jc ;

[0016] Detection efficiency coefficient X jc By counting the number of integrated circuits detected by the current integrated circuit fault detection system within one hour, it is calibrated as T sl , collect the number of integrated circuits detected by other types of integrated circuit fault detection systems in the market within one hour, calibrated as T x , x is the number of other types of integrated circuit fault detection system, x=1,2,3...n, n is a positive integer, then the detection efficiency coefficient

[0017] The fault detection performance evaluation model is constructed by weighting the fault detection error information, cost information and detection efficiency information of the current integrated circuit fault detection system to generate the fault detection performance evaluation index XN pg , and the corresponding coefficients are respectively the fault detection error coefficient B gj , cost consumption coefficient H cb , Detection efficiency coefficient X jc , the formula is XN pg =α 1 ×B gj ×α 2 ×H cb +α 3 ×X jc ;

[0018] At the same time, α 1 , α 2 , α 3 All are greater than 0 and are set according to actual conditions. For example, the expert weighting method is adopted, that is, experts in related fields are invited to determine the weights of various indicators through professional opinion surveys and comprehensive evaluations to ensure that the weight coefficients can accurately reflect the importance of various indicators in the fault detection performance evaluation. In addition, the use of various methods such as hierarchical analysis method and fuzzy comprehensive evaluation method to determine the weight coefficients can ensure the objectivity and scientificity of the weight coefficients. I will not go into details here.

[0019] In the fault detection performance evaluation module, the fault detection performance evaluation index obtained from the fault detection performance evaluation model is used to reflect the performance strength of the integrated circuit fault detection system during the detection process. The larger its value is, the more frequent false alarms and missed alarms occur in the integrated circuit fault detection system, the higher the detection cost amortized to each integrated circuit, and the lower the detection efficiency is compared with other existing integrated circuit fault detection systems on the market.

[0020] In the fault detection performance evaluation module, when the fault detection performance evaluation index XN pg When it is greater than the set performance threshold, it indicates that the existing integrated circuit fault detection system cannot meet the production needs, and a signal of necessity for improvement is issued, and subsequent algorithm optimization is performed on the existing integrated circuit fault detection system;

[0021] When the fault detection performance evaluation index XN pg When it is less than or equal to the set performance threshold, it means that the existing integrated circuit fault detection system can meet the production needs, and no subsequent steps are performed, and the evaluation results are directly output.

[0022] In the algorithm optimization module, deep learning and traditional machine learning models are combined to achieve the purpose of optimizing the original algorithm. The deep learning algorithm uses the convolutional neural network algorithm. Through the powerful automatic feature extraction capability of the convolutional neural network algorithm, hierarchical high-level features are extracted from the original image data, so that the subsequent traditional machine learning model, that is, the selected support vector machine algorithm, can work efficiently in a smaller feature space, avoiding an overly complex model structure, thereby achieving the purpose of improving detection efficiency and reducing the number of false positives and missed negatives;

[0023] Furthermore, the method for constructing the convolutional neural network-support vector machine algorithm model of the present invention is as follows:

[0024] Step 3.1, data preparation and preprocessing, collect image data for integrated circuit fault detection, including normal and defective samples, and perform standardization, normalization, cropping, rotation and other processing on the images to improve the robustness of the model;

[0025] Step 3.2, Convolutional neural network feature extraction, build a convolutional neural network model, determine the input layer, input image, assume that the size of the input image is W×H×C, where W is the width, H is the height, and C is the number of channels (for example, grayscale image C=1, color image C=3), define the convolution layer, apply multiple convolution kernels (filters) on the input image, each convolution kernel will generate a feature map (Feature Map), the convolution operation formula is: Where σ is the activation function (such as ReLU), W (k) is the kth convolution kernel, X is the input image, b (k)is the bias of the kth convolution kernel, M and N are the height and width of the convolution kernel respectively, and the ReLU activation function is used: σ(x) = max(0, x), defining the pooling layer, applying the pooling operation on the output feature map of the convolution layer, usually the maximum pooling (Max Pooling) or the average pooling (Average Pooling), to reduce the size of the feature map, reduce the amount of calculation and the risk of overfitting, the maximum pooling is: Pooled Feature Map ij =max m，n (Feature Map (i+m)(j+n) ), where m and n are the sizes of the pooling windows (e.g. 2×2), convolution and pooling are performed layer by layer, and the output feature map of each layer is used as the input of the next layer, and the convolution and pooling operations are repeated;

[0026] Step 3.3, feature vector generation, through flattening operation and full connection operation, the output feature map of the last pooling layer is flattened into a one-dimensional feature vector and the flattened feature vector is input into the fully connected layer. Through a series of weight matrix transformations, further features are extracted. Flattening operation: v = Flatten (Pooled FeatureMaps), fully connected layer: y = σ (W v + b), where W is the weight matrix, v is the flattened feature vector, b is the bias vector, σ is the activation function (such as ReLU or softmax), and the output of the fully connected layer is used as the final feature vector, the final feature vector: f = y;

[0027] Step 3.4, support vector machine classification, build a vector machine model, transform the optimization problem into a constrained optimization problem, and solve it by the Lagrange multiplier method. The optimization problem formula is: The constraints are: i (w·f i +b)≥1-ξ i for i = 1, 2, ..., N and ξ i ≥0 for i=1,2,...,N,where w is the weight vector of the decision boundary, b is the bias term, ξ i is the slack variable, C is the regularization parameter, and f i is the feature vector extracted by the convolutional neural network, y i is a label (+1 or -1), introduce the Lagrange multiplier and solve: Among them, α iis the Lagrange multiplier, and the optimal w and b are obtained. The new feature vector is classified through the decision function. f is defined as the new feature vector, then f(f) = sign(w·f+b), and the result is output. If the result is positive, the predicted category is +1 (normal integrated circuit), and if the result is negative, the predicted category is -1 (defective integrated circuit).

[0028] In the improvement result evaluation module, after optimizing the existing integrated circuit fault detection system algorithm by constructing a convolutional neural network-support vector machine algorithm model, an improvement result evaluation model is constructed to evaluate the integrated circuit fault detection system after the algorithm improvement, and the evaluation results are recorded as the performance threshold reference value when the next integrated circuit fault detection system is constructed.

[0029] The practicality of the integrated circuit fault detection system after the algorithm improvement is evaluated. The specific process is to collect the system improvement information and comprehensive automation information of the integrated circuit fault detection system. The system improvement information of the integrated circuit fault detection system includes the detection coverage coefficient and the sales volume change coefficient, which are calibrated as J fg and X bh , the comprehensive automation information includes the comprehensive automation coefficient, denoted as Q zd ;

[0030] Detection coverage factor J fg The number of fault types that can be detected by the integrated circuit fault detection system is denoted as Z gz , count the number of fault types in the integrated circuit after-sales feedback, calibrated as S fk , then the detection coverage coefficient J fg =(Z g2 -S fk ) / Z gz ;

[0031] Sales volume variation coefficient X bh By collecting the sales volume of the original integrated circuit fault detection system within one year, calibrated as X yy , and then count the sales volume of the integrated circuit fault detection system after the algorithm is improved within one year, calibrated as X gj , then the sales volume change coefficient X bh =X gj ÷X yy ;

[0032] Comprehensive automation factor Q zd The total expenditure of the integrated circuit fault detection system after the acquisition algorithm is improved is calibrated as J gj , and then calculate the labor cost in the integrated circuit fault detection process, calibrated as R zc , then the comprehensive automation coefficient Q zd =(Jgj -R zc ) / J gj ;

[0033] The improvement result evaluation model is constructed by weighting the system improvement information and the comprehensive automation information to generate the improvement result evaluation index GJ pg , and the corresponding coefficients are the detection coverage coefficient J fg , sales volume change coefficient X bh , Comprehensive automation coefficient Q zd , the formula is GJ pg =β 1 ×J fg -β 2 ×X bh -β 3 ×Q zd , β 1 , β 2 , β 3 are the weight coefficients of the corresponding indicators, all of which are greater than 0.

[0034] In the improvement results evaluation module, when the improvement results evaluation index GJ pg When it is less than or equal to the practical threshold, it means that the integrated circuit fault detection system after the algorithm is improved can detect the faults encountered by the integrated circuit more comprehensively, and while increasing sales, it also has a high degree of automation and high practicality. The algorithm is no longer adjusted and the evaluation result is output;

[0035] When improving the outcome evaluation index GJ pg When it is greater than the practical threshold, it means that the integrated circuit fault detection system after the algorithm improvement does not detect the faults encountered by the integrated circuit comprehensively, fails to achieve the expected goals of increasing sales and high automation, and has low practicality. The evaluation results are fed back to the algorithm optimization module and used as parameters to iteratively adjust the algorithm.

[0036] Technical effects and advantages of the present invention:

[0037] The present invention is based on the monitoring and analysis of fault detection error information, cost information and detection efficiency information in the integrated circuit fault detection system, evaluates the system performance and the necessity of algorithm improvement, and when it is judged that the system performance is weak, constructs a convolutional neural network-support vector machine algorithm model to improve the system feature extraction and feature processing functions. The improved integrated circuit fault detection system combines the system improvement information and comprehensive automation information to evaluate the practicality, thereby iterating the system multiple times and providing more reliable suggestions and data support for the subsequent construction of the integrated circuit fault detection system. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1This is a flow chart of the integrated circuit fault detection system based on artificial intelligence of the present invention. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] The present invention is based on the monitoring and analysis of fault detection error information, cost information and detection efficiency information in the integrated circuit fault detection system, evaluates the system performance and the necessity of algorithm improvement, and when it is judged that the system performance is weak, constructs a convolutional neural network-support vector machine algorithm model to improve the system feature extraction and feature processing functions. The improved integrated circuit fault detection system combines the system improvement information and comprehensive automation information to evaluate the practicality, thereby iterating the system multiple times and providing more reliable suggestions and data support for the subsequent construction of the integrated circuit fault detection system.

[0041] Example

[0042] like Figure 1 As shown, the steps of the integrated circuit fault detection system based on artificial intelligence are as follows:

[0043] Data acquisition module, monitoring and collecting fault detection error information, cost information and detection efficiency information in the integrated circuit fault detection system, sample data required for the construction of the convolutional neural network-support vector machine algorithm model, and system improvement information and comprehensive automation information after the integrated circuit fault detection system is improved;

[0044] A fault detection performance evaluation module is used to build a fault detection performance evaluation model and evaluate the fault detection performance of the existing integrated circuit fault detection system;

[0045] Algorithm optimization module, for integrated circuit fault detection systems with weak fault detection, improves feature extraction and feature processing functions by building a convolutional neural network-support vector machine algorithm model;

[0046] Improve the results evaluation module, conduct a practical evaluation on the improved integrated circuit fault detection system based on system improvement information and comprehensive automation information, and iterate the convolutional neural network-support vector machine algorithm model based on the evaluation results.

[0047] Specifically, in the data acquisition module, the sample data of the integrated circuit is obtained by the joint operation of the test probe, oscilloscope, logic analyzer and automatic test equipment, and then designed and simulated by EDA software such as Cadence, Synopsys, MentorGraphics to generate test vectors to achieve the purpose of monitoring, analyzing, and processing the information related to the integrated circuit and the integrated circuit fault detection system. In actual use, due to factors such as equipment cost and complexity of real-time monitoring, the present invention is based on the premise of long-term operation of the integrated circuit fault detection system and relatively stable detection environment, and continuous monitoring of integrated circuit data, which may lead to the phenomenon of necessity change at a certain monitoring moment.

[0048] In the fault detection performance evaluation module, a fault detection performance evaluation model is constructed. The specific process is to collect the fault detection error information, cost information and detection efficiency information of the current integrated circuit fault detection system. The fault detection error information includes the fault detection error coefficient, which is calibrated as B gj , the cost information includes the cost coefficient, denoted as H cb , the detection efficiency information includes the detection efficiency coefficient, calibrated as X jc ;

[0049] Fault detection error coefficient B gj By collecting the data of the ten thousand integrated circuits recently detected by the current integrated circuit fault detection system, the number of integrated circuits that are actually not faulty but are detected as faulty by the system is calibrated as W jd , the number of ICs that were recently tested and returned for repair during the warranty period is marked as F jd , then the fault detection error coefficient B gj =W jd +F jd 2 ;

[0050] Cost consumption coefficient H cb By collecting the cost of establishing the current integrated circuit fault detection system, calibrated as J il , count the number of integrated circuits tested in a year, marked as S jc , then the cost consumption coefficient H cb =J il ÷S jc ;

[0051] Detection efficiency coefficient X jc By counting the number of integrated circuits detected by the current integrated circuit fault detection system within one hour, it is calibrated as T sl , collect the number of integrated circuits detected by other types of integrated circuit fault detection systems in the market within one hour, calibrated as T x, x is the number of other types of integrated circuit fault detection system, x=1,2,3...n, n is a positive integer, then the detection efficiency coefficient

[0052] The fault detection performance evaluation model is constructed by weighting the fault detection error information, cost information and detection efficiency information of the current integrated circuit fault detection system to generate the fault detection performance evaluation index XN pg , and the corresponding coefficients are respectively the fault detection error coefficient B gj , cost consumption coefficient H cb , Detection efficiency coefficient X jc , the formula is XN pg =α 1 ×B gj +α 2 ×H cb +α 3 ×X jc ;

[0053] At the same time, α 1 , α 2 , α 3 All are greater than 0 and are set according to actual conditions. For example, the expert weighting method is adopted, that is, experts in related fields are invited to determine the weights of various indicators through professional opinion surveys and comprehensive evaluations to ensure that the weight coefficients can accurately reflect the importance of various indicators in the fault detection performance evaluation. In addition, the use of various methods such as hierarchical analysis method and fuzzy comprehensive evaluation method to determine the weight coefficients can ensure the objectivity and scientificity of the weight coefficients. I will not go into details here.

[0054] In the fault detection performance evaluation module, the fault detection performance evaluation index obtained from the fault detection performance evaluation model is used to reflect the performance strength of the integrated circuit fault detection system during the detection process. The larger its value is, the more frequent false alarms and missed alarms occur in the integrated circuit fault detection system, the higher the detection cost amortized to each integrated circuit, and the lower the detection efficiency is compared with other existing integrated circuit fault detection systems on the market.

[0055] In the fault detection performance evaluation module, when the fault detection performance evaluation index XN pg When it is greater than the set performance threshold, it indicates that the existing integrated circuit fault detection system cannot meet the production needs, and a signal of necessity for improvement is issued, and subsequent algorithm optimization is performed on the existing integrated circuit fault detection system;

[0056] When the fault detection performance evaluation index XN pg When it is less than or equal to the set performance threshold, it means that the existing integrated circuit fault detection system can meet the production needs, and no subsequent steps are performed, and the evaluation results are directly output.

[0057] In the algorithm optimization module, deep learning and traditional machine learning models are combined to achieve the purpose of optimizing the original algorithm. The deep learning algorithm uses the convolutional neural network algorithm. Through the powerful automatic feature extraction capability of the convolutional neural network algorithm, hierarchical high-level features are extracted from the original image data, so that the subsequent traditional machine learning model, that is, the selected support vector machine algorithm, can work efficiently in a smaller feature space, avoiding an overly complex model structure, thereby achieving the purpose of improving detection efficiency and reducing the number of false positives and missed negatives;

[0058] Furthermore, the method for constructing the convolutional neural network-support vector machine algorithm model of the present invention is as follows:

[0059] Step 3.1, data preparation and preprocessing, collect image data for integrated circuit fault detection, including normal and defective samples, and perform standardization, normalization, cropping, rotation and other processing on the images to improve the robustness of the model;

[0060] Step 3.2, Convolutional neural network feature extraction, build a convolutional neural network model, determine the input layer, input image, assume that the size of the input image is W×H×C, where W is the width, H is the height, and C is the number of channels (for example, grayscale image C=1, color image C=3), define the convolution layer, apply multiple convolution kernels (filters) on the input image, each convolution kernel will generate a feature map (Feature Map), the convolution operation formula is: Where σ is the activation function (such as ReLU), W (k) is the kth convolution kernel, X is the input image, b (k) is the bias of the kth convolution kernel, M and N are the height and width of the convolution kernel respectively, and the ReLU activation function is used: σ(x) = max(0, x), defining the pooling layer, applying the pooling operation on the output feature map of the convolution layer, usually the maximum pooling (Max Pooling) or the average pooling (Average Pooling), to reduce the size of the feature map, reduce the amount of calculation and the risk of overfitting, the maximum pooling is: Pooled Feature Map ij =max m，n (Feature Map (i+m)(j+n) ), where m and n are the sizes of the pooling windows (e.g. 2×2), convolution and pooling are performed layer by layer, and the output feature map of each layer is used as the input of the next layer, and the convolution and pooling operations are repeated;

[0061] Step 3.3, feature vector generation, through flattening operation and full connection operation, the output feature map of the last pooling layer is flattened into a one-dimensional feature vector and the flattened feature vector is input into the fully connected layer. Through a series of weight matrix transformations, further features are extracted. Flattening operation: v = Flatten (Pooled FeatureMaps), fully connected layer: y = σ (W v + b), where W is the weight matrix, v is the flattened feature vector, b is the bias vector, σ is the activation function (such as ReLU or softmax), and the output of the fully connected layer is used as the final feature vector, the final feature vector: f = y;

[0062] Step 3.4, support vector machine classification, build a vector machine model, transform the optimization problem into a constrained optimization problem, and solve it by the Lagrange multiplier method. The optimization problem formula is: The constraints are: i (w·f i +b)≥1-ξ i for i = 1, 2, ..., N and ξ i ≥0 for i=1,2,...,N,where w is the weight vector of the decision boundary, b is the bias term, ξ i is the slack variable, C is the regularization parameter, and f i is the feature vector extracted by the convolutional neural network, y i is a label (+1 or -1), introduce the Lagrange multiplier and solve: Among them, α i is the Lagrange multiplier, and the optimal w and b are obtained. The new feature vector is classified through the decision function. f is defined as the new feature vector, then f(f) = sign(w·f+b), and the result is output. If the result is positive, the predicted category is +1 (normal integrated circuit), and if the result is negative, the predicted category is -1 (defective integrated circuit).

[0063] In the improvement result evaluation module, after optimizing the existing integrated circuit fault detection system algorithm by constructing a convolutional neural network-support vector machine algorithm model, an improvement result evaluation model is constructed to evaluate the integrated circuit fault detection system after the algorithm improvement, and the evaluation results are recorded as the performance threshold reference value when the next integrated circuit fault detection system is constructed.

[0064] The practicality of the integrated circuit fault detection system after the algorithm improvement is evaluated. The specific process is to collect the system improvement information and comprehensive automation information of the integrated circuit fault detection system. The system improvement information of the integrated circuit fault detection system includes the detection coverage coefficient and the sales volume change coefficient, which are calibrated as J fg and X bh, the comprehensive automation information includes the comprehensive automation coefficient, denoted as Q zd ;

[0065] Detection coverage factor J fg The number of fault types that can be detected by the integrated circuit fault detection system is denoted as Z gz , count the number of fault types in the integrated circuit after-sales feedback, calibrated as S fk , then the detection coverage coefficient J fg =(Z gz -S fk ) / Z gz ;

[0066] Sales volume variation coefficient X bh By collecting the sales volume of the original integrated circuit fault detection system within one year, calibrated as X yy , and then count the sales volume of the integrated circuit fault detection system after the algorithm is improved within one year, calibrated as X gj , then the sales volume change coefficient X bh =X gj ÷X yy ;

[0067] Comprehensive automation factor Q zd The total expenditure of the integrated circuit fault detection system after the acquisition algorithm is improved is calibrated as J gj , and then calculate the labor cost in the integrated circuit fault detection process, calibrated as R zc , then the comprehensive automation coefficient Q zd =(J gj -R zc ) / J gj ;

[0068] The improvement result evaluation model is constructed by weighting the system improvement information and the comprehensive automation information to generate the improvement result evaluation index GJ pg , and the corresponding coefficients are the detection coverage coefficient J fg , sales volume change coefficient X bh , Comprehensive automation coefficient Q zd , the formula is GJ pg =β 1 ×J fg -β 2 ×X bh -β 3 ×Q zd , β 1 , β 2 , β 3 are the weight coefficients of the corresponding indicators, all of which are greater than 0.

[0069] In the improvement results evaluation module, when the improvement results evaluation index GJ pg When it is less than or equal to the practical threshold, it means that the integrated circuit fault detection system after the algorithm is improved can detect the faults encountered by the integrated circuit more comprehensively, and while increasing sales, it also has a high degree of automation and high practicality. The algorithm is no longer adjusted and the evaluation result is output;

[0070] When improving the outcome evaluation index GJ pg When it is greater than the practical threshold, it means that the integrated circuit fault detection system after the algorithm improvement does not detect the faults encountered by the integrated circuit comprehensively, fails to achieve the expected goals of increasing sales and high automation, and has low practicality. The evaluation results are fed back to the algorithm optimization module and used as parameters to iteratively adjust the algorithm.

[0071] The above formulas are all dimensionless and calculated numerically. Specific dimension removal can be achieved by various means such as standardization, which will not be elaborated here. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0072] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, an ATA hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state ATA hard disk.

[0073] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0074] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0075] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0076] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0077] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0078] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile ATA hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other media that can store program codes.

[0079] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An integrated circuit fault detection system based on artificial intelligence, characterized in that: It includes the following: Data acquisition module, monitoring and collecting fault detection error information, cost information and detection efficiency information in the integrated circuit fault detection system, sample data required for the construction of the convolutional neural network-support vector machine algorithm model, and system improvement information and comprehensive automation information after the integrated circuit fault detection system is improved; A fault detection performance evaluation module is used to build a fault detection performance evaluation model and evaluate the fault detection performance of the existing integrated circuit fault detection system; Algorithm optimization module, for integrated circuit fault detection systems with weak fault detection, improves feature extraction and feature processing functions by building a convolutional neural network-support vector machine algorithm model; Improve the results evaluation module, conduct a practical evaluation on the improved integrated circuit fault detection system based on system improvement information and comprehensive automation information, and iterate the convolutional neural network-support vector machine algorithm model based on the evaluation results.

2. The integrated circuit fault detection system based on artificial intelligence according to claim 1, characterized in that: In the fault detection performance evaluation module, a fault detection performance evaluation model is constructed. The specific process is to collect the fault detection error information, cost information and detection efficiency information of the current integrated circuit fault detection system. The fault detection error information includes the fault detection error coefficient, which is calibrated as B gj , the cost information includes the cost coefficient, denoted as H cb , the detection efficiency information includes the detection efficiency coefficient, calibrated as X jc ; Fault detection error coefficient B gj By collecting the data of the ten thousand integrated circuits recently detected by the current integrated circuit fault detection system, the number of integrated circuits that are actually not faulty but are detected as faulty by the system is calibrated as W jd , the number of ICs that were recently tested and returned for repair during the warranty period is marked as F jd , then the fault detection error coefficient B gj =W jd +F jd 2 ; Cost consumption coefficient H cb By collecting the cost of establishing the current integrated circuit fault detection system, calibrated as J jl , the number of integrated circuits tested in one year is counted, marked as Sjc, then the cost coefficient H cb =J jl ÷S jc ; Detection efficiency coefficient X jc By counting the number of integrated circuits detected by the current integrated circuit fault detection system within one hour, it is calibrated as T sl , collect the number of integrated circuits detected by the existing integrated circuit fault detection system in the market within one hour, calibrated as T x , x is the number of the integrated circuit fault detection system, x=1,2,3...n, n is a positive integer, then the detection efficiency coefficient 3. The integrated circuit fault detection system based on artificial intelligence according to claim 2 is characterized in that: The fault detection performance evaluation model is constructed by weighting the fault detection error information, cost information and detection efficiency information of the current integrated circuit fault detection system to generate the fault detection performance evaluation index XN pg , and the corresponding coefficients are respectively the fault detection error coefficient B gj , cost consumption coefficient H cb , Detection efficiency coefficient X jc , the formula is XN pg =α1×B gj +α2×H cb +α3×X jc , α1, α2, and α3 are the weight coefficients of the corresponding indicators, all of which are greater than 0.

4. The integrated circuit fault detection system based on artificial intelligence according to claim 3 is characterized in that: In the fault detection performance evaluation module, when the fault detection performance evaluation index XN pg When the performance value is greater than a set performance threshold, a signal indicating the necessity of improvement is issued, and subsequent algorithm optimization is performed on the existing integrated circuit fault detection system; When the fault detection performance evaluation index XN pg When the value is less than or equal to the set performance threshold, no subsequent steps are performed and the evaluation result is directly output.

5. The integrated circuit fault detection system based on artificial intelligence according to claim 1, characterized in that: In the algorithm optimization module, deep learning and traditional machine learning models are combined to improve detection efficiency and reduce the number of false positives and missed negatives; Furthermore, the construction method of the convolutional neural network-support vector machine algorithm model is as follows: Step 3.1, data preparation and preprocessing, collect image data for integrated circuit fault detection, standardize, normalize, crop, and rotate the images to improve the robustness of the model; Step 3.2, Convolutional neural network feature extraction, build a convolutional neural network model, determine the input layer, input image, define the convolution layer and pooling layer, apply the pooling operation on the output feature map of the convolution layer, convolution and pooling layer by layer, the output feature map of each layer is used as the input of the next layer, and the convolution and pooling operations are repeated; Step 3.3, feature vector generation, through flattening operation and full connection operation, the output feature map of the last pooling layer is flattened into a one-dimensional feature vector and the flattened feature vector is input into the fully connected layer, and a series of weight matrix transformations are performed to further extract features; Step 3.4, support vector machine classification, build a vector machine model, transform the optimization problem into a constrained optimization problem, solve it through the Lagrange multiplier method, and output the result. If the result is positive, the prediction category is +1, indicating a normal integrated circuit. If the result is negative, the prediction category is -1, indicating a defective integrated circuit.

6. The integrated circuit fault detection system based on artificial intelligence according to claim 5, characterized in that: The practicality of the integrated circuit fault detection system after the algorithm improvement is evaluated. The specific process is to collect the system improvement information and comprehensive automation information of the integrated circuit fault detection system. The system improvement information of the integrated circuit fault detection system includes the detection coverage coefficient and the sales volume change coefficient, which are calibrated as J fg and X bh , the comprehensive automation information includes the comprehensive automation coefficient, denoted as Q zd ; Detection coverage factor J fg The number of fault types detected by the integrated circuit fault detection system is denoted as Z gz , count the number of fault types in the integrated circuit after-sales feedback, calibrated as S fk , then the detection coverage coefficient J fg =(Z gz -S fk ) / Z gz ; Sales volume variation coefficient X bh By collecting the sales volume of the original integrated circuit fault detection system within one year, calibrated as X yy , and then count the sales volume of the integrated circuit fault detection system after the algorithm is improved within one year, calibrated as X gj , then the sales volume change coefficient X bh =X gi ÷X yy ; Comprehensive automation factor Q zd The total expenditure of the integrated circuit fault detection system after the acquisition algorithm is improved is calibrated as J gj , and then calculate the labor cost in the integrated circuit fault detection process, calibrated as R zc , then the comprehensive automation coefficient Q zd =(J gi -R zc ) / J gj .

7. The integrated circuit fault detection system based on artificial intelligence according to claim 6, characterized in that: The improvement result evaluation model is constructed by weighting the system improvement information and the comprehensive automation information to generate the improvement result evaluation index GJ pg , and the corresponding coefficients are the detection coverage coefficient J fg , sales volume change coefficient X bh , Comprehensive automation coefficient Q zd , the formula is GJ pg =β1×J fg -β2×X bh -β3×Q zd , β1, β2, and β3 are the weight coefficients of the corresponding indicators, all of which are greater than 0.

8. The integrated circuit fault detection system based on artificial intelligence according to claim 7 is characterized in that: In the improvement results evaluation module, when the improvement results evaluation index GJ pg When it is less than or equal to the practical threshold, the algorithm is no longer adjusted and the evaluation result is output; When improving the outcome evaluation index GJ pg When it is greater than the practical threshold, the evaluation result is fed back to the algorithm optimization module and used as a parameter to iteratively adjust the algorithm.

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