Chip testing system and method, computer equipment, readable storage medium and program product
Through the split chip testing system, the combination of signal enhancement module and power module is used to solve the problems of large space occupation, low production capacity and high cost in the traditional chip aging test method, and efficient chip testing is achieved, extending equipment life and improving equipment Test capacity.
Patent Information
- Application Number
- CN202411412827.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2024-12-31
AI Technical Summary
Traditional chip aging testing methods take up a large space, low test capacity, short service life and high cost of testing devices.
A chip test system was designed, adopting a split architecture, the control module is not in the test environment, and the power module and signal conversion module are in the test environment, ensuring data transmission accuracy through the signal enhancement module, and using the power module as the intermediate bridge for data transmission , simplify circuit connection and realize isolation between the control module and the test environment.
It improves test production capacity, reduces maintenance costs, extends the service life of the control module, saves test environment space, and is suitable for more application scenarios.
Smart Images
Figure CN119224539A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of testing technology, and in particular to a chip testing system, method, computer equipment, computer-readable storage medium, and computer program product. Background Art
[0002] Normally, before a chip is put into use, it needs to be tested to ensure that all functions of the chip are normal. In order for the chip to maintain a stable and high-performance working state in different environments, in addition to routine functional testing, an aging test is also required.
[0003] In traditional technology, the test device and the chip are placed together in a high temperature and high humidity test environment to perform chip aging tests. However, this method takes up a lot of space, has low test capacity, and has a short service life of the test device, resulting in high test costs. Summary of the invention
[0004] Based on this, it is necessary to provide a chip testing system, method, computer equipment, computer-readable storage medium and computer program product that can improve test capacity and reduce test costs in response to the above technical problems.
[0005] In a first aspect, the present application provides a chip testing system, the system comprising: a control module, a power module and a signal conversion module, the power module and the signal conversion module are arranged in a test environment, and the control module is not arranged in the test environment, wherein:
[0006] A control module, electrically connected to the power module, for acquiring test parameter information and sending the information to the power module, wherein a signal enhancement module is provided between the control module and the power module;
[0007] A power module, used to generate test power parameter information according to the test parameter information;
[0008] The signal conversion module is electrically connected to the power module and the chip to be tested, respectively, and is used to receive the test power parameter data of the power module, and perform protocol conversion on the test power parameter data to obtain target power parameter data, and send the target power parameter data to the chip to be tested to drive the chip to be tested to work and obtain the test data of the chip to be tested.
[0009] In one embodiment, the signal conversion module is further used for:
[0010] Performing protocol conversion on the test data to obtain target test data;
[0011] Sending the target test data to the power module;
[0012] The power supply module is also used to send the target test data to the control module.
[0013] In one embodiment, the power module is further used for:
[0014] Obtaining the operating voltage of the chip to be tested;
[0015] In response to the operating voltage being greater than a preset threshold, the voltage output is turned off and an early warning message is sent.
[0016] In one embodiment, the control module includes:
[0017] A data receiving unit, used for acquiring initial parameter information and sending it to a data processing unit;
[0018] A data processing unit is used to parse the initial parameter information, generate test parameter information matching the initial parameter information, and send the test parameter information to the power module.
[0019] In one embodiment, the control module is electrically connected to the power module via a coaxial line.
[0020] In one embodiment, the signal conversion module is electrically connected to a plurality of chips to be tested, and the signal conversion module is further used for:
[0021] Determine a target chip to be tested corresponding to the target power parameter data from the multiple chips to be tested;
[0022] The target power parameter data is sent to the target chip to be tested.
[0023] In a second aspect, the present application further provides a chip testing method, which is applied to a signal conversion module of a chip testing system, comprising:
[0024] Receive test power parameter data;
[0025] Performing protocol conversion on the test power parameter data to obtain target power parameter data;
[0026] The target power parameter data is sent to the chip under test to drive the chip under test to operate and obtain test data of the chip under test.
[0027] In a third aspect, an embodiment of the present disclosure further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of any one of the methods in the embodiments of the present disclosure are implemented.
[0028] In a fourth aspect, the embodiments of the present disclosure further provide a computer-readable storage medium, wherein a computer program is stored thereon, and when the computer program is executed by a processor, the steps of any one of the methods in the embodiments of the present disclosure are implemented.
[0029] In a fifth aspect, the embodiments of the present disclosure further provide a computer program product, wherein the computer program product includes a computer program, and when the computer program is executed by a processor, the steps of any one of the methods in the embodiments of the present disclosure are implemented.
[0030] In the above-mentioned chip testing system, method, computer device, computer-readable storage medium and computer program product, when performing chip testing, the power module and the signal conversion module are set in the test environment, the control module is not set in the test environment, the control module is used to obtain test parameter information and send it to the power module, and a signal enhancement module is set between the control module and the power module, which can ensure the accuracy and effectiveness of data transmission when the control module and the power module are not in the same environment; through the setting of the split architecture of the chip testing system, each module can be independently developed, deployed and replaced, and flexibly combined and expanded according to needs, which is convenient for disassembly and maintenance, and reduces maintenance costs. Furthermore, the power module generates test power parameter information according to the received test parameter information, the signal conversion module receives the test power parameter data sent by the power module, and performs protocol conversion to obtain target power parameter data, and sends the target power parameter data to the chip to be tested, drives the chip to be tested to work, and obtains test data, so that the data can be converted into data that can be received and processed by the chip to be tested through the signal conversion module, and the power module is used as an intermediate bridge for data transmission. There is no need to set a connecting line between the control module and the chip to be tested based on the data transmission type of the chip to be tested, which simplifies the circuit connection of the chip testing system, thereby achieving isolation of the control module and the test environment during the test process, avoiding the influence of the high temperature and high humidity test environment on the control module, and effectively improving the service life of the control module; and saving space in the test environment, being able to simultaneously test more chips to be tested, greatly improving the test capacity, and being suitable for more application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0032] Figure 1 A structural block diagram of a chip testing system in one embodiment;
[0033] Figure 2 It is a structural block diagram of a chip testing system in another embodiment;
[0034] Figure 3 A schematic diagram of a chip testing method according to an embodiment of the present invention;
[0035] Figure 4 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION
[0036] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0037] In one embodiment, Figure 1 As shown, a chip testing system 100 is provided, the system comprising: a control module 110, a power module 120 and a signal conversion module 130, the power module 120 and the signal conversion module 130 are arranged in a test environment, and the control module 110 is not arranged in the test environment, wherein:
[0038] The control module 110 is electrically connected to the power module 120 and is used to obtain test parameter information and send it to the power module 120, wherein a signal enhancement module is provided between the control module 110 and the power module 120;
[0039] Exemplarily, the test environment can be determined according to the test requirements in the actual application scenario. For example, when performing an aging test on a chip, it is necessary to obtain the working status data of the chip in a high temperature and high humidity environment. At this time, the test environment can include a high temperature and high humidity test cavity.
[0040] The control module 110 is electrically connected to the power module 120. In one example, the control module 110 is connected to the power module 120 via a preset signal line, and the preset signal line may include a coaxial line. In one example, the control module 110 may include a ZYNQ chip.
[0041] A signal enhancement module is arranged between the control module 110 and the power module 120. The signal enhancement module may include but is not limited to gain elements such as amplifier chips. Since the control module 110 and the power module 120 are respectively arranged in different environments in this embodiment, the signal enhancement module is used to ensure the effectiveness of signal transmission and avoid problems such as data loss during transmission.
[0042] In a possible implementation, the control module 110 and the power module 120 communicate with each other bidirectionally, and therefore, a signal enhancement module is provided at two connection ends where the control module 110 and the power module 120 are electrically connected, respectively.
[0043] The test parameter information may be determined according to the actual application scenario. In some possible implementations, the test parameter information may be stored in advance at a preset storage location, and the control module 110 obtains the information from the preset storage location in response to the test instruction. The test parameter information may also be obtained in real time, that is, sent to the control module 110 through input operations, etc., and the control module 110 receives the test parameter information in response to the test instruction. In one example, the test parameter information may also be obtained after processing based on the initial parameter information, and the initial parameter information may be received from a preset storage location or through input operations, etc.
[0044] Exemplarily, the initial parameter information may include but is not limited to a voltage control threshold, a test cycle, a monitoring frequency, etc. The test parameter information may include but is not limited to a test sequence, etc.
[0045] A power module 120, configured to generate test power parameter information according to the test parameter information;
[0046] Exemplarily, the power module 120 generates test power parameter information according to the test parameter information, and the power module 120 is used to generate the test voltage required when the chip is working, and supply power according to the power-on timing corresponding to the test parameter information. In an example, the test power parameter information may include but is not limited to the test voltage, power-on timing, IO control data, etc.
[0047] The signal conversion module 130 is electrically connected to the power module 120 and the chip under test 140, respectively, and is used to receive the test power parameter data of the power module 120, and perform protocol conversion on the test power parameter data to obtain target power parameter data, and send the target power parameter data to the chip under test 140 to drive the chip under test 140 to work and obtain the test data of the chip under test 140.
[0048] The chip under test 140 may be determined in advance according to an actual application scenario. In an example, the chip under test 140 may include one or more chips.
[0049] Exemplarily, the chip under test 140 needs to receive data of an information type that matches it. In order to ensure data transmission efficiency, in this embodiment, the control module 110 and the chip under test 140 do not directly transmit data. The information type of the data sent by the control module 110 to the power module 120 is different from the data type corresponding to the chip under test 140.
[0050] The signal conversion module 130 performs protocol conversion on the test power parameter data to obtain target power parameter data, wherein the information type of the target power parameter data is the information type matched by the chip under test. The chip under test 140 receives the target power parameter data and works according to the target power parameter data. The signal conversion module 130 communicates with the chip under test 140, reads the working status information of the chip under test 140, and obtains the test data.
[0051] In one example, the information type corresponding to the chip under test 140 is data corresponding to the SPMI communication standard, the data sent by the control module 110 is data corresponding to the IIC communication standard, and the signal conversion module 130 is used to perform protocol conversion on the test power parameter data to obtain the target power parameter data under the SPMI communication standard. In one example, the chip under test 140 may include but is not limited to a VR chip.
[0052] In the embodiment of the present disclosure, when performing chip testing, the power module and the signal conversion module are arranged in the test environment, the control module is not arranged in the test environment, the control module is used to obtain test parameter information and send it to the power module, and a signal enhancement module is arranged between the control module and the power module, which can ensure the accuracy and effectiveness of data transmission when the control module and the power module are not in the same environment; through the setting of the split architecture of the chip testing system, each module can be independently developed, deployed and replaced, and flexibly combined and expanded according to needs, which is convenient for disassembly and maintenance, and reduces maintenance costs. Furthermore, the power module generates test power parameter information according to the received test parameter information, the signal conversion module receives the test power parameter data sent by the power module, and performs protocol conversion to obtain target power parameter data, and sends the target power parameter data to the chip to be tested, drives the chip to be tested to work, and obtains test data, so that the data can be converted into data that can be received and processed by the chip to be tested through the signal conversion module, and the power module is used as an intermediate bridge for data transmission. There is no need to set a connecting line between the control module and the chip to be tested based on the data transmission type of the chip to be tested, which simplifies the circuit connection of the chip testing system, thereby achieving isolation of the control module and the test environment during the test process, avoiding the influence of the high temperature and high humidity test environment on the control module, and effectively improving the service life of the control module; and saving space in the test environment, being able to simultaneously test more chips to be tested, greatly improving the test capacity, and being suitable for more application scenarios.
[0053] In one embodiment, the signal conversion module is further used for:
[0054] Performing protocol conversion on the test data to obtain target test data;
[0055] Sending the target test data to the power module;
[0056] The power supply module is also used to send the target test data to the control module.
[0057] Exemplarily, the signal conversion module is also used to send the test data to the control module. After the signal conversion module obtains the test data, it performs protocol conversion on the test data to obtain target test data, which is data of the information type that the control module can receive and process. In one example, the test data may include but is not limited to the serial number of the chip, the PMIC status data inside the chip, etc.
[0058] The power module receives the target test data and sends the target test data to the control module. Exemplarily, after receiving the target test data, the control module can analyze and process the target test data to obtain a test result.
[0059] In a possible implementation, the signal conversion module is also used to obtain abnormal status information of the chip and perform protocol conversion, and send the converted data to the power module, and the power module sends the converted data to the control module.
[0060] In the disclosed embodiment, the signal conversion module can also perform protocol conversion on the test data to obtain target test data, and send the target test data to the power module. The power module sends the target test data to the control module, thereby converting the test data into data that the control module can receive and process. Based on the power module and the signal conversion module, two-way transmission of data is achieved, and there is no need for a separate coaxial cable or other connecting line to connect the control module and the chip to be tested, which further simplifies the circuit connection of the chip testing system, realizes the isolation of the control environment and the test environment during the test process, and takes into account the accuracy and effectiveness of data transmission.
[0061] In one embodiment, the power module is further used for:
[0062] Obtaining the operating voltage of the chip to be tested;
[0063] In response to the operating voltage being greater than a preset threshold, the voltage output is turned off and an early warning message is sent.
[0064] Exemplarily, the power module is also electrically connected to the chip to be tested, and is used to obtain the operating voltage of the chip to be tested, wherein the operating voltage of the chip to be tested can be obtained by the signal conversion module and sent to the power module. In one example, a preset threshold can be set according to the actual application scenario. When the operating voltage of the chip to be tested is greater than the preset threshold, it can be considered that the voltage is too high and there is a risk of equipment damage. Therefore, the voltage output is turned off and an early warning message is sent. The early warning message can be sent to the control module, and the control module outputs early warning information according to the early warning message.
[0065] In a possible implementation, the power module is also used to monitor the voltages of various other modules in the chip detection system. When the voltage is greater than a preset threshold, the voltage data is shut down to protect the device from damage.
[0066] In one example, the chip testing system may further include a debug module, which provides network and serial communication interfaces for adjustment and analysis when a test is abnormal.
[0067] In the disclosed embodiment, an early warning function is also provided in the chip testing system. The power module can make judgments based on the operating voltage of the chip to be tested, shut down the output and send an early warning message when the voltage is too high, thereby ensuring the safety and reliability of the testing process, avoiding chip damage and test system damage caused by excessive voltage, and improving the service life of the chip testing system.
[0068] In one embodiment, the control module comprises:
[0069] A data receiving unit, used for acquiring initial parameter information and sending it to a data processing unit;
[0070] A data processing unit is used to parse the initial parameter information, generate test parameter information matching the initial parameter information, and send the test parameter information to the power module.
[0071] Exemplarily, the control module includes a data receiving unit and a data processing unit. The data receiving module is used to obtain initial parameter information and send it to the data processing unit. In one example, the initial parameter information can be determined by an external input operation or instruction.
[0072] In one example, the chip testing system may further include an input display module, and the user may operate through options such as start, stop, and test settings on the input display module. The input display module generates initial parameter information according to the user's operation and sends it to the data receiving unit of the control module.
[0073] Optionally, the data processing unit is used to parse the initial parameter information and generate test parameter information matching the initial parameter information. In one example, the test parameter information may include but is not limited to a functional test sequence, etc. In one example, the data processing unit is also used to complete the configuration of the real-time clock and the initialization of the control signal according to the initial parameter information.
[0074] In a possible implementation, the control module further includes a data recording unit for recording system startup information, test information, etc., including but not limited to system log information and test table data.
[0075] In the disclosed embodiment, the control module includes a data receiving unit and a data processing unit. The data receiving unit can obtain initial parameter information, and the data processing unit can parse the initial parameter information to generate test parameter information, thereby being able to quickly and accurately generate test parameter information based on the initial parameter information.
[0076] In one embodiment, the control module is electrically connected to the power module via a coaxial line.
[0077] For example, the coaxial line can be designed according to the signal transmission type of the control module and the signal transmission type of the power module in the actual application scenario, and the control module and the power module can be connected. Since in this embodiment, the control module is not set in the test environment, and the power module is set in the test environment, the length of the coaxial line can be set according to information such as the spatial distribution of the test environment in the actual test scenario, so that the control module is not affected by the test environment while ensuring the stability and reliability of data transmission.
[0078] In the disclosed embodiment, the control module and the power module are electrically connected via a coaxial cable, thereby achieving separation of the control module and the power module while ensuring the effectiveness and reliability of data transmission and avoiding damage to data transmission due to module isolation, which is suitable for more application scenarios.
[0079] In one embodiment, the signal conversion module is electrically connected to a plurality of chips to be tested, and the signal conversion module is further used for:
[0080] Determine a target chip to be tested corresponding to the target power parameter data from the multiple chips to be tested;
[0081] The target power parameter data is sent to the target chip to be tested.
[0082] Exemplarily, the signal conversion module can be electrically connected to a plurality of chips to be tested. In one example, the power module and the signal conversion module can both be arranged on the contact substrate, and the signal conversion module can include a plurality of interfaces that can be used to connect the chips to be tested, and the chips to be tested are electrically connected to the signal conversion module through the interfaces.
[0083] In one example, the number of chips to be tested and the interface of the signal conversion module can be set according to the test requirements in the actual application scenario.
[0084] The signal conversion module determines the corresponding target chip to be tested according to the target power parameter data, and sends the target power parameter data to the target chip to be tested. Optionally, the target power parameter data may include information such as chip identification, and the signal conversion module may determine the chip to be tested corresponding to the chip identification as the target chip to be tested.
[0085] In the disclosed embodiment, the signal conversion module is electrically connected to a plurality of chips to be tested. When sending target power parameters, the target chip to be tested is determined according to the target power parameter data, and the target power parameter data is sent to the target chip to be tested, thereby achieving simultaneous testing of the plurality of chips to be tested. Compared with traditional whole-machine testing equipment, the number of chips to be tested can be flexibly set according to the actual application scenario, thereby further improving the testing capacity and flexibility.
[0086] Figure 2 FIG. 1 is a schematic diagram showing a structure of a chip testing system according to an exemplary embodiment. Figure 2 As shown, the system includes an input display module, a control module, a debug module, a power module, and a signal conversion module. The control module includes a data receiving unit, a data processing unit, and a data recording unit. The signal conversion module is electrically connected to the chip to be tested.
[0087] The data receiving unit receives the initial parameter data and sends it to the data processing unit. The data processing unit performs parameter analysis to obtain test parameter information and sends the test parameter information to the power module. The power module generates test power parameter data. The power module simultaneously monitors the voltage of each channel of the system and the PMIC voltage of the chip, and shuts down the voltage output when the voltage is greater than the preset threshold.
[0088] In one example, the signal conversion module may include an IIC to SPMI module, which is connected to the power module through the IIC interface. The control module controls the input display module through the IIC (integrated circuit bus), and controls the debug module through the network cable and the serial communication interface. Instructions are sent through the network cable to debug the system and verify the chip function, and the debug output information is observed and monitored through the serial communication interface.
[0089] In one example, the input display module may be composed of a keypad of the start and stop device and a display screen, and the display screen may display abnormal information in a preset display mode.
[0090] Based on the same inventive concept, the embodiment of the present application also provides a chip testing method. The implementation scheme for solving the problem provided by the method is similar to the implementation scheme recorded in the above system, so the specific limitations in one or more chip testing method embodiments provided below can refer to the limitations on the chip testing system above, and will not be repeated here.
[0091] In an exemplary embodiment, Figure 3 As shown, a chip testing method is provided, which is applied to a signal conversion module of a chip testing system, including:
[0092] Step S310, receiving test power parameter data;
[0093] Step S320, performing protocol conversion on the test power parameter data to obtain target power parameter data;
[0094] Step S330: sending the target power parameter data to the chip under test to drive the chip under test to operate and obtain test data of the chip under test.
[0095] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0096] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 4 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store test parameter data and other data involved in the method described in this embodiment. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a chip testing method is implemented.
[0097] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.
[0098] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.
[0099] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.
[0100] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.
[0101] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.
[0102] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.
[0103] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0104] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A chip testing system, characterized in that: The system comprises: a control module, a power module and a signal conversion module, wherein the power module and the signal conversion module are arranged in a test environment, and the control module is not arranged in the test environment, wherein: A control module, electrically connected to the power module, for acquiring test parameter information and sending the information to the power module, wherein a signal enhancement module is provided between the control module and the power module; A power module, used to generate test power parameter information according to the test parameter information; The signal conversion module is electrically connected to the power module and the chip to be tested, respectively, and is used to receive the test power parameter data of the power module, and perform protocol conversion on the test power parameter data to obtain target power parameter data, and send the target power parameter data to the chip to be tested to drive the chip to be tested to work and obtain the test data of the chip to be tested.
2. The system according to claim 1, characterized in that The signal conversion module is also used for: Performing protocol conversion on the test data to obtain target test data; Sending the target test data to the power module; The power supply module is also used to send the target test data to the control module.
3. The system according to claim 1, characterized in that The power module is also used for: Obtaining the operating voltage of the chip to be tested; In response to the operating voltage being greater than a preset threshold, the voltage output is turned off and an early warning message is sent.
4. The system according to claim 1, characterized in that The control module comprises: A data receiving unit, used for acquiring initial parameter information and sending it to a data processing unit; A data processing unit is used to parse the initial parameter information, generate test parameter information matching the initial parameter information, and send the test parameter information to the power module.
5. The system according to claim 1, characterized in that The control module is electrically connected to the power module via a coaxial line.
6. The system according to claim 1, characterized in that The signal conversion module is electrically connected to a plurality of chips to be tested, and the signal conversion module is also used for: Determine a target chip to be tested corresponding to the target power parameter data from the multiple chips to be tested; The target power parameter data is sent to the target chip to be tested.
7. A chip testing method, characterized in that: The method is applied to a signal conversion module of a chip testing system according to any one of claims 1 to 6, and the method comprises: Receive test power parameter data; Performing protocol conversion on the test power parameter data to obtain target power parameter data; The target power parameter data is sent to the chip under test to drive the chip under test to operate and obtain test data of the chip under test.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to claim 7 are implemented.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 7 are implemented.
10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to claim 7 are implemented.