Data transmission system and method based on HSB bus

Abstract

The invention belongs to the technical field of data transmission, and particularly relates to a data transmission system and method based on an HSB bus. The system comprises an HSB bus, a central control PLC and a plurality of distributed PLCs, wherein the central control PLC and the plurality of distributed PLCs are connected with the HSB bus; the central control PLC and the distributed PLCs are each internally provided with a CPU and an FPGA, and each FPGA comprises a shared data RAM. The CPU is used for executing control logic, program and interaction with external equipment, managing main control tasks of the board and processing input and output signals; the FPGA is used for transmission and real-time control of data on a bus; the shared data RAM is used for storing data of the board and data received when the board communicates with other boards through an HSB bus; and the CPU reads and writes the shared data RAM through a memory mapping mechanism, so that data exchange and cooperation between the CPU and the FPGA are realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a data transmission system and method based on an HSB bus (High-Speed ​​Bus). Background Art

[0002] In the field of industrial control, refer to Figure 1 A typical industrial control device consists of a central control PLC (Programmable Logic Controller), multiple distributed PLCs and a PWR board (Power Amplifier Board). The central control PLC focuses on data acquisition and decision logic, while the distributed PLCs focus on executing specific control tasks, and the PWR board provides a stable power supply for the entire device. This distributed computing task allocation allows each PLC to work independently, improving the system's parallel processing capabilities.

[0003] IEC 61131-3 is a PLC programming standard developed by the International Electrotechnical Commission. It provides a variety of programming languages, among which Function Block Diagram (FBD) is a graphical programming method. FBD language represents control logic in a graphical way, allowing engineers to intuitively design and implement control logic by dragging and dropping function blocks and connecting inputs and outputs.

[0004] Take a cooling system control scenario based on a temperature sensor as an example. Figure 2 , using a central control PLC and two distributed PLCs to build. The central control PLC is responsible for temperature monitoring and decision logic. The central control PLC is connected to the temperature sensor to collect temperature data in real time, and decides whether to start or stop the cooling system according to the set temperature threshold. The distributed PLC is responsible for receiving instructions to start or stop the cooling system from the central control PLC, performing corresponding operations, and feeding back the status of the cooling system, such as running, stopped, faulty, etc., to the central control PLC for easy monitoring and management.

[0005] Reference Figure 3 From the functional block diagram of the central control PLC and the distributed PLC, we can see that in each cycle, data needs to be exchanged between the central control PLC and the distributed PLC. Therefore, it is particularly important to design an effective data interaction method between PLCs to ensure the efficiency and real-time performance of the entire industrial control device.

[0006] In the prior art, CAN bus, Ethernet, RS-485 and other methods can be used to exchange data between PLCs. However, each of these solutions has some obvious disadvantages. The standard data rate of the CAN bus is 125 kbps to 1Mbps. When a large amount of data needs to be transmitted or multiple nodes communicate at the same time, bandwidth will become a bottleneck. Ethernet communication requires the configuration of network devices such as switches, routers, and firewalls. The system architecture is relatively complex. In the case of high traffic or heavy network load, data packet conflicts and losses occur from time to time, which may cause communication interruptions or control command delays. The rate used by RS-485 in most occasions is between 9600bps and 115200bps. The number of nodes supported at the same time will be limited by the bus load and wiring electrical characteristics, and the expansion capability is relatively poor.

[0007] To address these issues, the HSB bus was designed to provide a more efficient and stable data interaction solution to meet the real-time and reliability requirements of industrial control systems, while also having the advantages of high speed and good scalability. Summary of the invention

[0008] In order to overcome the problems in the prior art, the present invention proposes a data transmission system and method based on the HSB bus.

[0009] The technical solution of the present invention to solve the above technical problems is as follows: In the first aspect, the present invention provides a data transmission system based on the HSB bus, including an HSB bus and a central control PLC and multiple distributed PLCs connected to the HSB bus; the central control PLC and the distributed PLCs are both provided with a CPU and an FPGA, and the FPGA includes a shared data RAM; the shared data RAM is used to store the board's own data and the data received when communicating with other boards through the HSB bus; the CPU reads and writes the shared data RAM through a memory mapping mechanism, thereby realizing data exchange and collaboration between the CPU and the FPGA.

[0010] Furthermore, the HSB bus adopts the LVDS bus transmission method, and its lines include: a clock CLK line, a control signal CTRL line and a data bus; wherein, the clock CLK line is used to provide a synchronous clock signal to ensure that all boards send and receive data at the same time point, the control signal CTRL line is used to control the access rights of the bus and the start or end of data transmission, and the data bus is used to transmit data.

[0011] Furthermore, the central control PLC is responsible for sending configuration requests and aggregating the data volume of each distributed PLC to calculate the total data transmission volume and allocate node information when the system is started or reconfigured; the distributed PLC is responsible for responding to the configuration request of the central control PLC, reporting its own data volume, and processing the occupied data nodes on its FPGA according to the received node information.

[0012] Furthermore, a sending module and a receiving module are provided on the FPGA; The sending module is used to send data to the bus in a predetermined format according to the relevant registers configured by the CPU when the FPGA timing interrupt comes; The receiving module is used to receive data on the bus in real time, parse the received data according to the register configuration and the situation of the board, and store the data in the corresponding position of the shared data RAM according to the control information in the data frame.

[0013] Furthermore, the data frame format includes a start address, a byte length, data content, a check code and an end flag.

[0014] Furthermore, the receiving module is also used to check the data frame to ensure the correctness of the data. If the check code is incorrect, it indicates that an error has occurred in the data transmission process, and a request is made to resend the data frame.

[0015] In a second aspect, the present invention further provides a data transmission method based on an HSB bus, comprising the following steps: Step 100: When the data transmission work starts, the sending module of one board sends the data frame in the board to the bus in a predetermined format according to the pre-configured information; After the data is sent, the sending module enters the waiting state, waiting for feedback from the receiving module; Step 200: The receiving modules of other boards monitor the data on the bus, and start receiving the data when data transmission is detected; the receiving modules write the data into the corresponding position of the RAM according to the content of the received data; The receiving module calculates the check code of the received data and compares it with the received check code. If the check codes are consistent, it continues to receive subsequent data or prepares to send data of this board; If they are inconsistent, the bus will be requested to retransmit; after receiving the retransmission signal, the sending module will resend the previous data; Step 300: When all boards have completed sending and receiving data once and no checksum error is detected, the data exchange of one HSB cycle is completed; Each board will determine whether the entire transmission process is completed based on the total number of nodes.

[0016] Furthermore, if the number of retransmissions exceeds a set value, the transmission is stopped and the CPU is notified.

[0017] Furthermore, before starting the data transmission work, the process includes: A central control PLC and multiple distributed PLCs are connected to the HSB bus, wherein each PLC is regarded as a board; the central control PLC and the distributed PLCs are both provided with a CPU and an FPGA; the FPGA includes a shared data RAM, the shared data RAM of each board is configured, and a partition is reserved for the data content of each board; when the central control PLC is initialized, the interrupt operation parameters are configured to the FPGA, and the interrupt mode is set.

[0018] Furthermore, before the data transmission work begins, it also includes data preparation and node division: the data size occupied by each board is pre-defined, that is, the central control PLC and distributed PLC have already known their respective data areas in the shared data RAM when the system starts.

[0019] Compared with the prior art, the present invention has the following technical effects: In the present invention, each board mounted on the bus has a shared data RAM. When one board sends data, other boards act as receiving ends to receive the data on the bus. The FPGA on the receiving board stores the received data in the corresponding position of the shared data RAM in the board according to the information in the data frame. According to the pre-assigned start address sending order, all boards send their own data in turn and receive data sent by other boards at the same time. Within an HSB interrupt cycle, all boards realize mutual data exchange, so that the data RAM in the board has the same data content, thereby achieving the purpose of data sharing, exchange and synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a typical schematic diagram of industrial control device; Figure 2 A control flow chart for a cooling system control scenario based on a temperature sensor as an example; Figure 3 Function block diagram for central control PLC and distributed PLC; Figure 4This is a schematic diagram of interrupt mode 0 of the present invention; Figure 5 This is a schematic diagram of interruption mode 1 of the present invention; Figure 6 This is a RAM memory allocation diagram of the present invention; Figure 7 A schematic diagram of memory allocation for each board of the present invention; Figure 8 This is a schematic diagram of the state machine of the sending module of the present invention; Fig. 9 This is a schematic diagram of a receiving module state machine of the present invention; Fig.10 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0022] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, the specific implementation methods, structures, features and effects of the technical solutions proposed by the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments. The specific features, structures or characteristics in one or more embodiments may be combined in any suitable form. Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those commonly understood by technicians in the technical field of the present invention.

[0023] In one embodiment of the present invention, a data transmission system based on an HSB bus is provided, the system comprising an HSB bus and a board connected to the HSB bus; the central control PLC and the distributed PLC are both provided with a CPU and an FPGA, the FPGA comprising a shared data RAM; the shared data RAM is used to store the board's own data and the data received when communicating with other boards via the HSB bus; the CPU reads and writes the shared data RAM through a memory mapping mechanism, thereby realizing data exchange and collaboration between the CPU and the FPGA.

[0024] In the present invention, each board mounted on the bus has a shared data RAM. When one board sends data, other boards act as receiving ends to receive the data on the bus. The FPGA on the receiving board stores the received data in the corresponding position of the shared data RAM in the board according to the information in the data frame. According to the pre-assigned start address sending order, all boards send their own data in turn and receive data sent by other boards at the same time. Within an HSB interrupt cycle, all boards realize mutual data exchange, so that the data RAM in the board has the same data content, thereby achieving the purpose of data sharing, exchange and synchronization.

[0025] In this embodiment, the transmission mode of the HSB bus adopts the LVDS (Low Voltage Differential Signaling) bus mode, which includes 6 lines: 1 clock CLK line, 1 control signal CTRL line and 4 data buses DATA0-3; among them, the clock CLK line is used to provide a synchronous clock signal to ensure that all boards send and receive data at the same time point; the control signal CTRL line is used to control the access rights of the bus and the start / end of data transmission; the data bus DATA0-3 includes 4 parallel data lines for transmitting 4-bit data. This bus design supports multiple boards to send and receive data frames in turn in a time-sharing manner to achieve data sharing, exchange and synchronization.

[0026] In this embodiment, the central control PLC and the distributed PLC are both provided with a CPU and an FPGA. The CPU is the core processing unit of the board, responsible for executing control logic, programs and interaction with external devices. It manages the main control tasks of the board and processes input / output signals. The FPGA is responsible for high-speed transmission and real-time control of data on the bus. It ensures fast data transmission and processing through hardware acceleration, especially in parallel tasks and applications with high real-time requirements. The shared data RAM is stored in the FPGA, but the CPU can directly read and write the shared data RAM through a memory mapping mechanism, thereby realizing data exchange and collaboration between the CPU and the FPGA.

[0027] Reference Figure 6 and Figure 7 , the shared data RAM is used to store the board's own data and the data received when communicating with other boards through the HSB bus. Each board has an independent shared data RAM, but the data RAM of all boards is logically shared, that is, they contain the same data content. It can be understood as follows: each board mounted on the bus has a RAM of the same size of 4096 bytes. The shared data RAM reserves partitions for the data content of different boards according to the configuration of the board. For example, bytes 0-64 store the content of the first board, bytes 65-127 store the content of the second board, and so on.

[0028] In addition to the shared data RAM that stores shared data, the FPGA also includes an independent register RAM, namely the configuration register, which is used to control and configure the hardware registers of the FPGA's internal functions. The CPU configures the FPGA's hardware functions by writing data into the register RAM. This process is essentially the CPU transferring data to the FPGA's register RAM through a write operation, thereby controlling the FPGA's behavior or configuring the FPGA's operating mode.

[0029] In a specific embodiment, in order to control the length of data transmitted at one time, the concept of node is introduced. The data of each board is divided into multiple nodes, and each node contains a specific range of data bytes. Each node contains up to 64 bytes of data, and each node will only contain the data of one board. For example, PLC1 has two nodes, the node starting sequence number is 0, node 0 is 0-63 bytes, and node 1 is 64 bytes; PLC2 has one node, the node starting sequence number is 2, and node 2 contains 65-127 bytes. The node starting number is used to identify the order of each node, thereby facilitating the organization and transmission of data. For example, the central control PLC with a starting address of 0 is the first board to send data because the central control PLC with a configuration starting address of 0.

[0030] Since all boards are synchronized using the same clock signal CLK, they can send and receive data at the same time point. This timing synchronization mechanism ensures the correct transmission and reception of data on the bus.

[0031] In this embodiment, the board includes a central control PLC and a distributed PLC.

[0032] The central control PLC is the core control unit in the system, used to send start signals and interrupt signals to ensure synchronization and coordination between all boards; it is also responsible for the overall configuration and management of the system, including configuring the starting address for each board, setting data transmission rules, etc.

[0033] Specifically, the CPU of the central control PLC is used to start the entire system, and when the system starts or is reconfigured, it sends a configuration request, summarizes the data volume of each distributed PLC, calculates the total data transmission volume, and distributes node information (including the starting node number, starting address, byte length, and total number of nodes); it is used to send start signals and interrupt signals to ensure synchronization and coordination between all boards; it is also responsible for the overall configuration and management of the system, including configuring the starting address for each board, setting data transmission rules, etc.; it executes control logic, programs and interactions with external devices, processes input / output signals, and makes decisions and controls based on the real-time data provided by the FPGA.

[0034] As other boards in the system, distributed PLCs perform corresponding data transmission and processing tasks according to the configuration and management information of the central control PLC. They receive or send data in a preset sending order to respond to the instructions of the central control PLC or communicate with other boards.

[0035] Specifically, the CPU of the distributed PLC responds to the configuration request of the central control PLC, reports its own data volume, and processes the occupied data nodes on the FPGA of the distributed PLC based on the received node information; receives data from other boards through the FPGA of the distributed PLC, and stores the data in the shared data RAM; at the same time, it is also used to process the data and perform corresponding data transmission and processing tasks; it is used to communicate with the central control PLC and other distributed PLCs, and receives or sends data in a preset sending order to respond to the instructions of the central control PLC or communicate with other boards.

[0036] The FPGA connected to the central control PLC is temporarily called the main FPGA. Compared with other FPGAs, it has the additional function of controlling the entire bus transmission.

[0037] In a specific embodiment, an interrupt mode is set in the CPU of the central control PLC, and the interrupt mode includes interrupt mode 0 and interrupt mode 1. Interrupt mode 0 is used to ensure real-time response and is suitable for applications that are sensitive to delays; interrupt mode 1 reduces the CPU burden through a fixed delay and is suitable for periodic data processing tasks.

[0038] The FPGA is provided with a register for identifying the interrupt mode currently to be used. During initialization, the CPU of the central control PLC configures the interrupt mode to the above register in the FPGA. When the value is 0, interrupt mode 0 is used; when the value is 1, interrupt mode 1 is used.

[0039] Specifically, refer to Figure 4 and Figure 5 , two interrupt modes: Interrupt mode 0 provides real-time response capability, ensuring that PLC (central control PLC and distributed PLC) can process data from FPGA in a timely manner, suitable for delay-sensitive applications such as real-time control or monitoring systems. When FPGA completes data exchange, it can notify PLC by triggering an interrupt, thus ensuring timely transmission and processing of data.

[0040] Interrupt mode 1 is suitable for scenarios where data processing is relatively stable. It can reduce the interrupt processing burden of the CPU and is suitable for tasks that require periodic data collection. Through fixed delays, time management can be better performed, which is suitable for scheduling periodic tasks. The fixed delay of the PLC interrupt is given.

[0041] Each time the FPGA's HSB interrupt comes, a data exchange is initiated, and the entire process is completed by the FPGA. During initialization, the CPU of the central control PLC configures the interrupt operation parameters, such as the interval between two interrupts, the HSB cycle, etc., to the FPGA. After completing a data exchange, the FPGA will generate an interrupt according to the configured interrupt mode. After receiving the interrupt, the CPU of the central control PLC performs corresponding read and write operations and other task operations.

[0042] In this embodiment, a sending module and a receiving module are provided on the FPGA.

[0043] The sending module is used to send data to the bus in a predetermined format according to the relevant registers configured by the CPU when the FPGA timing interrupt comes. When data transmission starts, it follows the pre-assigned sending order. The FPGA with node No. 1 sends a data frame to the bus, and the FPGAs on other boards will monitor the control signals on the bus and the data on the data bus. The format of the data frame includes the start flag, data length, data content, checksum, and end flag.

[0044] Referring to Table 1, the format of the entire data frame transmission is as follows: 2B (starting address) + 2B (byte length) + data + CRC (2 bytes).

[0045] Table 1 Data frame transmission format

[0046] The task of the receiving module is to receive the data on the bus in real time, parse the received data according to the relevant register configuration and the situation of the board, and store the data in the corresponding position of the shared data RAM according to the control information in the data frame. At the same time, the FPGA will also verify the data to ensure the correctness of the data. Since the data frame contains a check code, it is used to monitor errors that may occur during data transmission. If the FPGA on other boards detects that the check code does not match, it indicates that an error has occurred in the data transmission process. At this time, corresponding error handling measures can be taken, such as requesting the retransmission of the data frame. For example, the check code is a CRC check code. If the CRC values ​​are consistent, no operation is performed; if the CRC values ​​are inconsistent, a 0x55aa signal will be sent to the bus. After the FPGA with node No. 1 receives the signal, it will re-complete the data transmission in sequence and retransmit it up to 2 times.

[0047] When the data transmission of a node is completed and there is no retransmission signal on the bus, the FPGA with the second node sends data to the bus, and the above process is repeated until the FPGA with the last node completes sending data to the bus. It should be noted that if a board does not complete the sending or receiving of data within the predetermined time, other boards can consider that the board has a fault or timeout error, and take corresponding processing measures, such as skipping the data sending and receiving of the board.

[0048] If the receiving module on the board finds that the received data is the last node value sent by the previous board, and after receiving this node value, no other board sends a retransmission signal, then the receiving module will notify the sending module to start the sending function of this board.

[0049] In an HSB interrupt cycle, that is, the time period when all boards complete data transmission and reception, the data RAM of all boards will be updated to contain the same data content. In this way, each board can access the latest data, realizing data sharing, exchange and synchronization.

[0050] In a specific embodiment, the sending module is divided into three state machines: Figure 8 As shown in the state machine in T01 indicates that the CPU configuration starts and the board starts sending signals; T11 indicates that data sending is completed; T21 indicates that the fixed waiting time is completed.

[0051] The empty state is the state at power-on, reset or before starting to send. When the board is powered on or reset, the sending module of the FPGA is in the empty state by default, which is the initial state of the sending module. In the initial state, the FPGA will continuously monitor three signals: the first signal is the start-send signal, which only exists on the central control PLC. The CPU of the central control PLC will send a start instruction to the FPGA. Only when the CPU allows the FPGA to start the sending task can the FPGA send data according to the rules mentioned above; the second signal is the interrupt signal, which only exists on the central control PLC. Each time the FPGA starts data interaction, it will start once after detecting this signal, especially the central control PLC with a configuration start address of 0, because the central control PLC with a configuration start address of 0 is the first board to send data; the third signal is to monitor the data transmitted on the bus and monitor whether it is the turn of this board to start next time. If it is, then start the data sending in the next transmission. If not, continue to be in the receiving state.

[0052] The data sending state includes the starting address, length, and data. When the FPGA detects the relevant start sending signal and then jumps to the data sending state, it will first send the starting address according to the data format introduced above. The starting address sent by all boards for the first time is the starting address of the board configured by the CPU (CPU of the central PLC and distributed PLC). For example, board 1 has a starting address of 0 because the starting address of the RAM is 0. The FPGA will calculate the total number of nodes that need to be sent based on the starting address and data length register configured by the CPU. For example, if the starting address is configured to 0 and the data length is configured to 258 bytes, then after calculation inside the FPGA, it is concluded that 2 nodes need to be sent. The length of the data sent by the first node is 256 bytes, and the length of the data sent by the second node is 2 bytes. When board 1 is in this state for the first time, the starting address sent by the FPGA is 0 and the byte length is 256+2, that is, Bytes + 2 CRC values, followed by data and CRC; the second time the starting address is sent in this state is 256, the byte length is 2+2, that is, 2 bytes + 2 CRC values, followed by data and CRC.

[0053] The waiting state is used to wait for the response of the receiving board, and it is fixed to wait for 8 CLK cycles. If the data 0x55aa55aa is received in this state, it means that the transmission is wrong, jump to the empty state, and retransmit the last data. If the received data is not 0x55aa55aa, it means that the transmission is correct, jump to the empty state, and continue the subsequent transmission.

[0054] The receiving module is divided into 3 states, the specific state machine is as follows Fig. 9 As shown, T02 indicates that the enable signal is pulled high, T12 indicates that data reception is completed, and T22 indicates that the fixed waiting time is completed.

[0055] The receiving module jumps to the idle state when it is powered on or reset. In this state, the FPGA constantly monitors the changes of the control signal on the bus. If the control signal is pulled high, it means that data is sent to the bus. At this time, the receiving module state machine will jump to the receiving comparison state.

[0056] The receiving comparison state indicates that the state is the receiving data state and the comparing CRC state. In the receiving state, the FPGA will receive the data transmitted on the data bus, and determine the address to be written, the length of the data and other control signal contents in the transmission data message according to the content in the data, and calculate the CRC check according to the received data. After receiving the data, compare the received CRC data with the CRC data calculated by itself to see if they are consistent. If they are consistent, set the consistent flag signal high, if they are inconsistent, pull the consistent flag signal low, and then jump to the feedback state.

[0057] The feedback state has a total of 8 CLK cycles. The first two cycles are agreed to be idle cycles, that is, all boards do not perform any operations. In the 3rd to 6th cycles, if the data received by the board is problematic, it will send 0x55aa55aa to the bus, so that the board that sent the data previously will resend the previously sent data after receiving such data feedback. In the last two cycles, all boards do not process anything. Instead, after receiving the feedback information on the bus, it tells the board whether to prepare to receive data again, or to prepare to receive new data behind, or whether it is the board's turn to send data.

[0058] Based on the same inventive concept, an embodiment of the present invention further provides a method for data transmission based on an HSB bus for implementing the above-mentioned data transmission system based on an HSB bus. The implementation scheme for solving the problem provided by the system is similar to the implementation scheme recorded in the above-mentioned method, so the specific limitations in one or more system embodiments provided below can refer to the above-mentioned limitations on a data transmission system based on an HSB bus, and will not be repeated here.

[0059] In one embodiment, referring to Fig.10 , provides a data transmission method based on HSB bus, comprising the following steps: Step 100: When the data transmission work starts, the sending module of the board sends the data frame in the board to the bus in a predetermined format according to the pre-configured information; After the data is sent, the sending module enters the waiting state, waiting for feedback from the receiving module; Step 200: The receiving modules of other boards monitor the data on the bus, and start receiving the data when data transmission is detected; the receiving modules write the data into the corresponding position of the RAM according to the content of the received data; The receiving module calculates the CRC of the received data and compares it with the received CRC. If the CRCs are consistent, it continues to receive subsequent data or prepares to send data of this board; if they are inconsistent, it sends a 0x55aa signal to the bus to request retransmission.

[0060] After receiving the retransmission signal, the sending module will resend the previous data; if the number of retransmissions exceeds the set value, such as 2 times, the transmission will be stopped and the CPU will be notified.

[0061] Step 300: When all boards have completed sending and receiving data once and no CRC error is detected, the data exchange of one HSB cycle is completed; each board will determine whether the entire transmission process is completed based on the total number of nodes.

[0062] Before starting the data transmission work, it includes: connecting multiple boards to the HSB bus, setting FPGA and shared data RAM on each board, configuring the shared data RAM of each board, and reserving partitions for the data content of each board; when the central control PLC is initialized, the interrupt operation parameters are configured to the FPGA, and the interrupt mode is set; the FPGA is initialized according to the received configuration parameters and is ready to enter the data transmission state.

[0063] Before starting the data transmission work, it also includes data preparation and node division: setting up a visual configuration tool, and when using the tool to configure the PLC function, pre-dividing the data size occupied by each board, the central PLC and distributed PLC are aware of the area division when the system starts.

[0064] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A data transmission system based on HSB bus, characterized in that: It includes an HSB bus and a central control PLC and multiple distributed PLCs connected to the HSB bus, wherein each PLC is regarded as a board; the central control PLC and the distributed PLC are both provided with a CPU and an FPGA, the FPGA includes a shared data RAM, and the shared data RAM is used to store the data of the board itself and the data received when communicating with other boards through the HSB bus; The CPU reads and writes the shared data RAM through a memory mapping mechanism, thereby achieving data exchange and collaboration between the CPU and FPGA.

2. A data transmission system based on HSB bus according to claim 1, characterized in that: The HSB bus uses the LVDS bus transmission method, and its lines include: clock CLK line, control signal CTRL line and data bus; among them, the clock CLK line is used to provide a synchronous clock signal to ensure that all boards send and receive data at the same time point, the control signal CTRL line is used to control the access rights of the bus and the start or end of data transmission, and the data bus is used to transmit data.

3. A data transmission system based on HSB bus according to claim 1, characterized in that: The FPGA also includes a configuration register, and the CPU configures the FPGA through the configuration register.

4. A data transmission system based on HSB bus according to claim 1, characterized in that: The central control PLC is used to send configuration requests and summarize the data volume of each distributed PLC when the system is started or reconfigured, so as to calculate the total data transmission volume and allocate node information; the distributed PLC is used to respond to the configuration request of the central control PLC, report its own data volume, and process the occupied data nodes on its FPGA according to the received node information.

5. A data transmission system based on HSB bus according to claim 4, characterized in that: The FPGA is provided with a sending module and a receiving module; The sending module is used to send data to the bus in a predetermined format when the FPGA timing interrupt comes; The receiving module is used to receive data on the bus in real time, parse the received data according to the pre-configuration and the situation of the board, and store the data in the corresponding position of the shared data RAM according to the control information in the data frame.

6. A data transmission system based on HSB bus according to claim 5, characterized in that: The data frame format includes a start address, a byte length, data content, a check code and an end mark.

7. A data transmission system based on HSB bus according to claim 6, characterized in that: The receiving module is also used to check the data frame to ensure the correctness of the data; if the check code is incorrect, it indicates that an error has occurred in the data transmission process, and a request is made to resend the data frame.

8. A data transmission method based on HSB bus, used in a data transmission system based on HSB bus as claimed in any one of claims 1 to 7, characterized in that: The following steps are involved: Step 100: When the data transmission work starts, the sending module of one board sends the data frame in the board to the bus in a predetermined format according to the pre-configured information; After the data is sent, the sending module enters the waiting state, waiting for feedback from the receiving module; Step 200: The receiving modules of other boards monitor the data on the bus, and when data transmission is detected, they start receiving the data; The receiving module writes the data into the corresponding position of the RAM according to the content of the received data; The receiving module calculates the check code of the received data and compares it with the received check code. If the check codes are consistent, it continues to receive subsequent data or prepares to send data of this board; If they are inconsistent, a retransmission is requested from the bus; After receiving the retransmission signal, the sending module will resend the previous data; Step 300: When all boards have completed sending and receiving data once and no checksum error is detected, the data exchange of one HSB cycle is completed; Each board will determine whether the entire transmission process is completed based on the total number of nodes.

9. The data transmission method based on HSB bus according to claim 8, characterized in that: Before the data transmission work starts, it includes: A central control PLC and multiple distributed PLCs are connected to the HSB bus, wherein each PLC is regarded as a board; the central control PLC and the distributed PLCs are both provided with a CPU and an FPGA, wherein the FPGA includes a shared data RAM and a partition is reserved for the data content of each board; the central control PLC is set with an interrupt mode.

10. A data transmission method based on HSB bus according to claim 9, characterized in that: Before starting the data transmission work, it also includes data preparation and node division: the data size occupied by each board is pre-defined, that is, the central control PLC and the distributed PLC have already known their respective data areas in the shared data RAM when the system starts.

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