Transferable and low-power-consumption MCU (Microprogrammed Control Unit) device

Abstract

The invention discloses an MCU (Microprogrammed Control Unit) device with portability and low power consumption. The MCU device mainly comprises a kernel and a peripheral. In the kernel aspect, simplification of an instruction architecture, a storage architecture and a pipeline architecture is achieved. Meanwhile, in the aspect of peripherals, the system is designed according to the requirements in the current industrial scene, modules such as a UART, an SPI and a TMR0 are modularized, and implementation is carried out based on an SFR bus protocol. The method can be compatible with an MAPLAB integrated development environment, and has good transportability. In addition, an operation unit is improved in an operand isolation mode, and the dynamic power consumption of the MCU is effectively reduced.

Description

Technical Field

[0001] The invention relates to an MCU device with portability and low power consumption, and relates to the technical field of microcontrollers. Background Art

[0002] With the advancement of technology and the evolution of society, society has also been undergoing a profound change in surprising ways in recent years. Human society has undergone tremendous changes from the initial mechanical and electronic industry, the subsequent electronic information age, and the current intelligent age. With the continuous changes of the times, the development of electronic products has shown an increasingly obvious trend, playing a more important role in our daily lives. To a certain extent, electronic products have become an indispensable part of contemporary people's lives. Against the background of the rapid development of integrated circuits and Internet technology, various electronic products have emerged in an endless stream and have become an important product in today's society. At present, major companies in the world are developing their own microcontroller products to meet market demand. With the development of industries such as the Internet of Things, automotive electronics, and industrial control, the downstream application demand for microcontrollers (MCUs) will continue to rise, which provides broad space for the expansion of the MCU industry market.

[0003] MCU is a system computer that integrates peripheral devices such as memory, input and output ports, timers, serial communication ports, and digital-to-analog converters (DACs). Its core is the central processing unit (CPU). MCU can handle various complex and large instructions, and has powerful functional expansion capabilities. It can be classified according to the length of data that the processor participates in one operation, that is, the bit width, including 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit. According to the public information published on CISA in 2020, in the domestic MCU market, 8-bit and 32-bit MCUs account for 43% and 54% of the market share respectively, and these two types of MCUs are the most widely used. 8-bit MCUs are widely used in basic fields such as low-end and mid-range industrial control due to their safety, stability, simple and flexible structure, easy design, and low cost. Compared with 8-bit MCUs, 32-bit MCUs show better computing power and can handle a larger number of external devices at the same time. Therefore, they have been widely used in more high-end and complex scenarios such as smart homes and automotive electronics.

[0004] Initially, due to the constraints of commands and data of the processor core, the MCU's computing speed and operating efficiency were low in domestic and foreign research. However, with the in-depth research of researchers in system structure and chip technology, the MCU has been greatly improved in performance and operating speed. Although the single-chip microcomputer technology has developed rapidly, the low power consumption and low cost of MCU have attracted much attention. However, from the overall development situation at home and abroad, domestic research is still in the early stage and lacks in-depth and systematic research. Existing MCU devices also have certain limitations in portability, which restricts their wide application. Summary of the invention

[0005] Purpose of the invention: In view of the problems and shortcomings in the prior art, the present invention provides a MCU device with portability and low power consumption to make up for the shortcomings of the prior art and improve the computing speed and operating efficiency of the MCU.

[0006] Technical solution: A portable and low-power MCU device, including an instruction architecture, a storage architecture, a pipeline architecture, a processor core and peripheral IPs, a UART module, a SPI module, a TMR0 module, a GPIO module and a WDT module.

[0007] The instruction architecture includes byte operation instructions for operating file registers, bit operation instructions for operating file registers, immediate value operation instructions and fixed encoding format control instructions; each instruction has a corresponding code block or byte table; in all operation instructions, the operation code field is located in the highest bit segment, and the operation code field contains instruction type and function information.

[0008] The storage architecture includes an instruction storage area, a core (Core) and a data storage area; first, the instruction storage area stores instructions executed by the MCU, including flash memory or ROM implementation; second, the core (Core) reads instructions from the instruction storage area and executes them, and communicates with the instruction storage area and the data storage area through a bus; the data storage area is used to store data generated during the operation of the MCU.

[0009] The instruction storage area is allocated with different sizes and numbers of regions. The allocation process of the instruction storage area involves allocating appropriate storage areas for different types of instructions to ensure efficient instruction access and execution. First, the system designer divides the instruction storage area into multiple regions based on the size, number and characteristics of the instructions. The size of these regions is usually based on the specific needs of the instructions. For example, byte operation instructions, bit operation instructions and control instructions may require storage areas of different sizes. Next, the system allocates one or more storage areas for each type of instruction. The size and number of these areas are adjusted according to the expected size of the instruction set. Finally, the system ensures that each instruction can be efficiently stored and retrieved in its allocated area, avoiding waste of storage space and optimizing the speed and efficiency of instruction access. This process is usually managed by the compiler and the operating system, and efficient use of instruction storage is achieved through dynamic allocation and static allocation strategies. Through partitioning technology and address conversion technology, instruction storage has a wider range of applicability; the address conversion technology is a method for managing and accessing memory, mapping logical addresses to physical addresses; when the address of the instruction or data to be accessed in the memory exceeds the range of the current memory paging, a variety of different addressing methods are used to achieve a direct jump to the target address; because the instruction memory and the register have a certain mapping relationship, when the program is running, if there is no memory residue, the entire operating system needs to be reinitialized.

[0010] The data storage area is divided into 4 independent pages, which mainly include special function register area, general register area, and public mapping area. The special function register area is used to store registers with special functions. Low address units are installed on each page, including two types of configuration registers: kernel and peripherals. In a set time, the special function register area reads and writes data files according to the set rules. At the set time point, through the timer interrupt or scheduler trigger, the special function register mapped to the set memory address is read and written. According to the pre-defined rules and conditions, the hardware function is controlled and monitored. The general register stores the general data of the variables defined in the software and is stored in the high address unit of each page. The first page 70H to 7FH maps all the pages to the public storage area, so that the data can be shared arbitrarily in the storage units between the pages, realizing efficient data management.

[0011] The pipeline architecture adopts a double-layer shallow pipeline structure. The first pipeline is used for instruction fetching and the second pipeline is used for execution. In the second pipeline, each clock cycle is divided into four stages, each stage is triggered by a different edge of the clock: the first edge is used for instruction decoding, the second edge is used for operand fetching, the third edge is used for instruction execution, and the fourth edge is used for result writeback.

[0012] The processor core and the peripheral IP are divided into the following functional modules, namely, a dedicated register stack module, a program counter module, a controller module, an interrupt control module, a clock / reset management module and a stack module.

[0013] The main function of the dedicated register stack module is to set working information for the kernel and peripheral devices, and can record various important flag signals generated by the program in real time during execution. The module consists of six registers with special functions: INDF is an indirect addressing mode register, PCL is the lower eight bits of the program counter, STATUS is a status register, FSR is a file selection register, PCLATH is the upper five bits of the program counter, and WORK is a working register but without a unified address code. Each register has a corresponding reset value.

[0014] The main function of the program counter module is to analyze the decoding, operation results and external interrupts of the current instruction, so as to determine the address of the next instruction and ensure the normal operation of the system.

[0015] The program counter consists of three parts, namely the instruction decoding module, the operation unit module, and the register. The instruction decoding module is responsible for transmitting the instruction information read from the memory to the operation unit module in a serial manner, so as to calculate the corresponding data value and send it to the register for storage, which includes important information such as the operation code, operand address, immediate number and target address, so as to achieve high-precision control of the work of other modules.

[0016] The execution control code module can extract the key position from the operation sequence, then generate a new operation sequence based on the key position, and finally merge it with the original operation sequence to form a complete operation sequence. By performing 16 operations on the two input source operands and the operation code, the operation unit module can uniformly output the operation results and important flag information obtained after the operation, thereby achieving efficient data processing. The intermediate processing unit module is used to process the data generated by each operation and the control data obtained from multiple ports. The controller module is based on the interconnect bus and is responsible for controlling the read and write timing of special function registers, general registers and W registers, and outputs the corresponding read and write enable signals. The communication module is used to transmit control data and status reports, and interact with the communication protocol between external devices. The interrupt control module has the ability to synchronize and respond to interrupt request signals from multiple interrupt sources, so as to generate system interrupt signals. The storage unit module is responsible for storing data and the status of devices connected to the memory interface. The clock / reset management module receives the device status connected to the memory interface and the clock information of the external crystal oscillator, and generates multiple clock signals, such as the reference clock, four-phase clock and instruction cycle clock. These signals drive the normal operation of the entire system, manage the reset source, and generate the reset signal of the entire system. The data storage module is mainly used to save the data format and related parameters that must be used in the application. Although the stack module has the ability to save the instruction address before calling the subroutine and the corresponding interrupt, it should be noted that it cannot be directly read and written by the software.

[0017] The dedicated register stack module provides access to and operation of key registers in the system; the program counter module ensures the correct execution of instructions by analyzing the decoding results of instructions through the instruction decoding module, the operation unit module and the register; the controller module manages the read and write timing of the registers and coordinates the operations of each module; the intermediate processing unit module processes data and control signals and exchanges data with the communication module; the communication module is responsible for communication with external devices; the storage unit module stores data and works closely with the clock / reset management module to ensure the clock signal and reset function of the system; the stack module provides the ability to save data, but is limited by the fact that it cannot be directly operated by software.

[0018] As an asynchronous transmitter, the UART module can ensure that data is transmitted normally without using a clock line by setting the transmission format and rate of the receiving and transmitting ends. In order to realize the transceiver function of UART, two types of registers are configured: the first is the peripheral device register of UART, which can realize flexible configuration of UART working mode, including selecting communication mode (receiving, transmitting or full-duplex), setting baud rate, number of data bits, number of stop bits and verification mode, so as to adapt to different data transmission requirements; the other is the core interrupt register. When the kernel needs to respond to data changes or events of external devices in real time, the interrupt register can be configured to enable the system to access the peripheral register in an interrupt manner. This method allows the system to respond to external events immediately when needed, such as UART receiving new data or sending completion, so as to achieve efficient data exchange and processing, which meets the real-time requirements of kernel scheduling.

[0019] The UART module supports 8-bit and 9-bit data transmission modes, and provides optional check bits and 1-bit end bits. This module can also support the receive interrupt function. It includes multiple registers (such as RCSTA, RCREG, SPBRG, TXREG and TXSTA) connected to the SFR bus interface, the receive and transmit FIFO buffers, the bit rate generator, the receive state machine and the transmit state machine. These components are interconnected through internal access and interrupt signals to coordinate the processing of parallel data streams from RX reception to TX transmission. On this basis, a custom protocol interface is added to exchange data with other devices. The scalability and flexibility of this module have been significantly improved, thus providing more convenient conditions for system upgrades and changes. The use of this modular design scheme not only fully saves hardware resources, but also reduces the difficulty of development. The UART module is composed of two parts: the SFR bus control logic and the UART transceiver control logic, which are an indispensable core component of the present invention. The SFR bus control part is mainly used to realize data transmission between the CPU. According to the instruction configuration of the CPU, the working registers related to the UART module can be allocated, the corresponding status registers can be detected, and the transceiver registers can be read and written. By using the configuration information, the UART transceiver control logic can realize the functions of receiving, sending and caching data information at different baud rates, and can detect whether there is an error in the transmitted data frame, and output the result in the form of a flag bit, providing reliable protection for data transmission.

[0020] The SPI module supports two master-slave transmission modes and four communication modes, and has a receiving interrupt function. At the same time, the module also has the ability to exchange data with other peripheral devices. The design of the module is divided into two parts: SFR bus control logic and SPI transceiver control logic. The SPI transceiver control logic covers multiple modules, including REGCON transmission signal control module, TRIG trigger control module, BAUDGEN clock frequency division module, RX data receiving module and TX data sending module.

[0021] The TMR0 module can realize the timing function in two ways: timing and counting. Timing uses frequency division counting to realize the timing function. The counting is based on the pulse signal from the external input. When the pulse signal changes periodically, the timing function can be realized.

[0022] The timing counter module in the present invention has two driving modes to choose from: internal clock and external clock. Among them, the trigger edge can be selected independently by using the external clock drive. First, the timer is configured to receive an external clock source as a timing reference, and the type of trigger edge is selected by register setting, such as rising edge, falling edge or double edge. The timer contains an eight-bit pre-divider and a counting register. The eight-bit pre-divider can be programmed by software to set its frequency division coefficient to determine the number of times each clock pulse affects the counter, thereby adjusting the timing accuracy and overflow time interval. The counting register can be read and written by the CPU, and the CPU can read the current count value or write a new initial value to control the counting state of the timer. When the counting register overflows, the timer generates an interrupt request signal, and the system responds to the interrupt request and executes a predefined interrupt service routine (ISR) to handle specific interrupt events, such as resetting the counter, updating data or performing other related tasks, thereby realizing the precise timing function of the timer and timely interrupt processing.

[0023] As an interface for data communication between the microprocessor and the outside world, the pins of the GPIO module are used as data input and output, and can also be multiplexed with other functional modules to realize interrupts in different working modes.

[0024] Two groups of GPIOs consisting of 8 pins are used, and each pin is controlled by the corresponding bit on the TRIS register. The input signal is represented by a high level, while the output signal is presented by a low level. When setting the interrupt source, the enable signal must first be passed to the RBIE bit of the INTCON register to ensure that the interrupt request signal can be sent to the RBIF bit of the INTCON. In addition, if a register needs to be operated, different registers can be selected to execute separately. In the specific implementation process, the present invention adopts a method of mapping two registers to the same physical address to solve the logical conflict problem between the input and output directions.

[0025] In the WDT module, the watchdog timing method is used to detect the system. When the program runs abnormally, the overflow signal is sent to the divider, and a watchdog overflow signal is generated according to the frequency division ratio. This watchdog signal is then input to the kernel reset management module, which then triggers a global reset. When the program runs normally, no reset is triggered.

[0026] Low power consumption design and improvement: (1) Operand isolation design ALU is a computing unit composed of 16 types of operation circuits. When the input signal is reversed, it will inevitably generate considerable flip power. In order to reduce this flip power consumption, it is necessary to set corresponding operation identifiers for each register address in the dedicated register stack module, such as INDF, PCL, STATUS, FSR, PCLATH and WORK registers. When the ALU class instruction arrives, the opcode, SRC1 and SRC2 operands contained in each instruction will be transferred to the ALU unit after the calculation is completed. Before the SRC1 and SRC2 operands are input, an operand isolation register is introduced. The operand isolation circuit of ALU is used to effectively isolate and select different operands when performing operations to ensure correct data transmission and processing. This circuit selects appropriate operands from registers or immediate values ​​according to instruction requirements by using multiplexers and control signals, and sends them to ALU for operation.

[0027] (2) Sleep wake-up mode Once the system configuration is completed, the MCU may be in an idle state for the rest of the time. Only after the module of the peripheral device sends an interrupt request signal, the kernel will respond to it and execute the interrupt program to ensure the normal operation of the system. When the MCU is idle, a power-saving sleep mode, that is, standby mode or low-power mode, can be used to replace those mechanical and meaningless operation processes, so that the MCU can get a short rest during this period and maintain a low power consumption level. This sleep mode usually includes turning off some internal circuits or reducing the processor frequency to reduce power consumption while retaining sufficient functions to respond to external interrupt signals. In this process, if necessary, key data such as the current register state, temporary variables, and any intermediate calculation results will be stored so that it can be quickly restored to the state before sleep when it wakes up next time, and continue the unfinished task or perform new operations. When it is necessary to perform control tasks, the MCU system can be awakened by interrupt requests or watchdog timing. In sleep mode, if you want to resume work, you must first activate the sleep enable circuit before you can resume work. When the working mode is converted to the sleep mode, the kernel needs to execute the SLEEP instruction, and then the MCU will decode the sleep state to pull the high energy signal and turn off the four-phase clocks CLK_Q1, CLK_Q2, CLK_Q3, and CLK_Q4, while the registers in the MCU will keep the current state unchanged. After entering the sleep state, the present invention proposes two wake-up methods, one of which is to use the "watchdog" timing. Even if the system is in the sleep state, the watchdog can continue to work, but when the count overflows, it will trigger the system reset to achieve timed wake-up; the other is to use the sleep enable signal to initialize after the system enters sleep, and then start sleep through the interrupt mode, which can also achieve a certain degree of wake-up effect. The second method is to use an interrupt request to trigger the crystal oscillator to restart, so as to achieve wake-up. However, since it takes a period of time to change from the start-up state to the stable state, the interrupt request signal must always maintain a high level during this period of time, and can only be gradually reduced when the system resumes normal execution, otherwise it will cause wake-up failure. If there is a relatively high flag signal on the crystal oscillator at this time, it means that there is no fault or error information on the crystal oscillator, and no interrupt will occur. Only after the system is awakened and enters the interrupt program, the interrupt request flag signal will be pulled low. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of the MCU storage architecture of an embodiment of the present invention; Figure 2 is a timing diagram of a state machine architecture of an embodiment of the present invention; Figure 3 is a timing diagram of a multi-clock architecture according to an embodiment of the present invention; Figure 4 is a schematic diagram of a two-stage pipeline according to an embodiment of the present invention; Figure 5 It is a UART design structure diagram of an embodiment of the present invention; Figure 6 The invention discloses an operand isolation circuit of an ALU according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention is further explained below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0030] A portable and low-power MCU device comprising: (1) Instruction architecture The instruction architecture is compatible with the PIC16F8X series instruction system, including byte operation instructions for operating file registers, bit operation instructions for operating file registers, immediate operation instructions, and fixed encoding format control instructions, a total of 35 instructions; each instruction has a corresponding code block or byte table. In all operation instructions, the operation code field is located in the highest bit segment, and the operation code field contains instruction type and function information.

[0031] (2) Storage architecture like Figure 1 As shown in the figure, the storage architecture adopts the Harvard structure and successfully achieves the purpose of processor optimization through the internal micro-architecture design of the Core module. The MCU storage architecture includes the instruction storage area, the core (Core) and the data storage area. First, the instruction storage area stores the instructions executed by the MCU, including flash memory or ROM implementation. Secondly, the core (Core) reads instructions from the instruction storage area and executes them, and communicates with the instruction storage area and the data storage area through the bus; the data storage area is used to store data generated during the operation of the MCU, usually using RAM. The entire system is powered by the power module (POWER_SUPPLY) to ensure the normal operation of each component.

[0032] The depth of the instruction storage area is 8196 by designing a memory with sufficient address space and storage capacity. Specifically, the capacity of the storage area is designed to accommodate 8196 instructions, which usually involves assigning a unique address to each instruction and supporting this depth by increasing the bit width and number of storage units of the memory. For example, the address range of the memory and the number of storage units together determine the depth that the storage area can reach, thereby ensuring that the system can store and access the required number of instructions. The speed and reliability of instruction execution are improved by allocating different sizes and numbers of regions on each memory. First, the memory is divided into multiple regions according to the type and requirements of the instructions, such as allocating dedicated storage areas for byte operation instructions, bit operation instructions, and immediate operation instructions. The size and number of these regions are optimized based on the storage requirements and access frequency of each type of instruction. Then, through this division, the system can reduce the access time of each type of instruction, improve the efficiency of instruction acquisition, and avoid interference between different types of instructions, thereby improving the overall execution speed and system reliability. By accurately managing the storage and access of each region, efficient instruction execution and more stable system operation can be better supported. The use of partitioning technology and address conversion technology makes instruction storage more widely applicable. The address conversion technology is used in a method for managing and accessing memory, and improves the efficiency and flexibility of memory use by mapping logical addresses to physical addresses.

[0033] Hardware architecture based on memory management unit and instruction manager. In order to improve efficiency, the instruction storage area is divided into 4 pages, and the depth of each page is 2048. When encountering a wide-span addressing scenario, it means that the address range of the instruction or data to be accessed in the memory is very wide, far beyond the range of the current memory page. In this case, a variety of different addressing methods can be used to achieve direct jump to the target address without page-by-page traversal. For example, using segment page addressing, register-based indirect addressing, or using jump tables and other methods can quickly locate and jump to the required memory location, improving addressing efficiency and instruction execution speed. In addition, because there is a certain mapping relationship between the instruction memory and the register, when the program is running, if there is no memory residue, the entire operating system needs to be reinitialized. Usually, after the system reset is over, the program pointer will automatically point to the address of the reset vector, and then it will automatically jump to the entry of the main program, and then continue to execute the main program, and the compiler will automatically assign a value to the entry of the main program. After the main program fails, if new input or operation requests appear in the program, it is necessary to reprogram and compile to ensure the normal operation of the system. When the kernel is executing the main program, once an interrupt response occurs, the program pointer will automatically jump to the entry address of the interrupt program, thus ensuring the normal operation of the program.

[0034] The data storage area is divided into 4 independent pages. The pages mainly include 3 register areas with special functions, a general register area, and a public mapping area. A special function register area is set in each partition. In order to store registers with special functions, low-address units are installed on each page, which mainly include two types of configuration registers: kernel and peripherals. At a specific time, these special function register areas read and write data files according to certain rules. At the set time point, through the timer interrupt or scheduler trigger, the special function register mapped to the set memory address is read and written. According to the pre-defined rules and conditions, the control and monitoring of the hardware function is realized. The general register stores the general data of the variables defined in the software and is stored in the high address unit of each page. Thus, the data in different pages can be fully and independently processed. In addition, the first page 70H to 7FH maps all the paging public storage areas so that the data can be shared arbitrarily in the storage units between the pages to achieve efficient data management.

[0035] Figure 2 The timing diagram of a state machine is shown, where the clock signal (CLOCK) and the state (STATE) signal show the transition process of the state machine at different times. The states are ST0, ST1, ST2, etc., and they repeat in a cycle. Cycle1 and Cycle2 represent two complete state transition cycles respectively.

[0036] Figure 3 The timing diagram of a multi-clock system structure is shown, including the main clock (CLK) and four sub-clocks (CLK_Q1, CLK_Q2, CLK_Q3, CLK_Q4), as well as the state changes of the program counter (PC) and the next program counter (PC_NEXT) at different time points. In each clock cycle (Tcy1, Tcy2, Tcy3, Tcy4), PC and PC_NEXT execute and prefetch instructions respectively.

[0037] (3) Pipeline architecture In order to achieve the goals of reducing costs, saving area and reducing power consumption, a double-layer shallow pipeline structure is adopted. Among them, the first pipeline is used for instruction fetching, and the second pipeline is used for execution. In the second pipeline, each clock cycle (Tcy) is divided into four stages, and each stage is triggered by a different edge of the clock: the first edge is used for instruction decoding, the second edge is used for operand extraction, the third edge is used for instruction execution, and the fourth edge is used for result writeback. In this way, multiple operations can be completed in one clock cycle, thereby improving data processing efficiency. This design method can not only achieve the requirements of saving area and reducing power consumption, but also significantly improve the speed. More importantly, it effectively solves the various logical problems caused by deep pipelines while reducing circuit complexity. In addition, all of the above work is achieved using simple shift registers. See Figure 4 The pipeline is implemented using a dual level.

[0038] Processor core and peripheral IP design: The microprocessor core is the core part of the MCU system, responsible for the important tasks of input instruction decoding, execution, emulation and writing back, so as to accurately control the operation of the entire system. During the design process, the interrelationship and coordination between various functional areas should be fully considered to ensure that the entire chip can work normally and maximize its effectiveness. The invention is divided into 8 functional modules, namely, dedicated register stack module, program counter module, instruction decoding module, operation unit module, controller module, interrupt control module, clock / reset management module and stack module.

[0039] The main function of the dedicated register stack module is to set working information for the kernel and peripheral devices, and to record various important flag signals generated by the program during execution in real time. This module consists of six registers with special functions, as shown in Table 1. The table lists the special function registers related to the kernel, including their symbols, addresses, names and reset values. Specifically, INDF is the indirect addressing mode register, PCL is the lower eight bits of the program counter, STATUS is the status register, FSR is the file selection register, PCLATH is the upper five bits of the program counter, and WORK is a working register but without a unified address encoding. Each register has a corresponding reset value, such as most of them are 0x00, and the reset value of the STATUS register is 0x18.

[0040] Table 1 Core-related special function registers symbol address name Reset value INDF 00H / 80H / 100H / 180H Indirect Addressing Mode Register 0X00 PCL 02H / 82H / 102H / 182H The lower eight bits of the program counter 0X00 STATUS 03H / 83H / 103H / 183H Status Register 0X18 FSR 04H / 84H / 104H / 184H File selection register 0X00 PCLATH 0AH / 8AH / 10AH / 18AH The upper five bits of the program counter 0X00 WORK - Working register, no unified address code 0X00 The main function of the program counter module is to analyze the decoding, operation results and external interrupts of the current instruction, so as to determine the address of the next instruction and ensure the normal operation of the system. On this basis, other corresponding operations are completed to execute subsequent functions. The program counter consists of three parts, namely the instruction decoding module, the operation unit module and the register. The instruction decoding module is responsible for transmitting the instruction information read from the memory to the operation unit module in a serial manner, so as to calculate the corresponding data value and send it to the register for storage, which covers important information such as the operation code, operand address, immediate number and target address, so as to achieve high-precision control of the work of other modules. The execution control code module generates a new operation sequence by parsing and extracting the key positions in the operation sequence, and merges it with the original operation sequence to form a complete operation sequence to ensure the accuracy of instruction execution and the continuity of system operation. The intermediate processing unit module is used to process the data generated by each operation and the control data obtained from multiple ports. These data and control signals are transmitted through the interconnection bus to ensure the coordination between the internal and external systems. The controller module based on the interconnection bus realizes the control of the read and write timing of the special function register, general register and W register, and outputs the corresponding read and write enable signal. The communication module is responsible for exchanging data with external devices, transmitting control data and status reports, and processing communication protocols with external devices. The storage unit module is responsible for storing data in the system and the status of devices connected to the memory interface, ensuring stable storage and management of data. The data storage module is used to save the data format and related parameters required in the application, providing efficient data access and storage support. Although the stack module has the ability to save the address of the instruction before calling the subroutine and interruption, it should be noted that it cannot be directly read and written by the software.

[0041] UART module design: As an asynchronous transmitter, UART can ensure that data is transmitted normally without using a clock line by setting the transmission format and rate of the receiving and transmitting ends. This method can effectively reduce system overhead and improve system performance. In order to realize the transceiver function of UART, two types of registers are configured: the first is the peripheral device register of UART, which can realize flexible configuration of UART working mode, including selecting communication mode (receiving, transmitting or full-duplex), setting baud rate, number of data bits, number of stop bits and verification mode, so as to adapt to different data transmission requirements; the other is the core interrupt register. When the kernel needs to respond to data changes or events of external devices in real time, the interrupt register can be configured to enable the system to access the peripheral register in an interrupt manner. This method allows the system to respond to external events immediately when needed, such as UART receiving new data or sending completion, so as to achieve efficient data exchange and processing, which meets the real-time requirements of kernel scheduling.

[0042] On this basis, the UART module of the present invention is a configurable design based on hardware circuit software. In addition, this module can support 8-bit and 9-bit data transmission modes, and provides an optional check bit and 1 end bit. In addition, this module can also support a receive interrupt function. Figure 5 The design structure diagram of UART (Universal Asynchronous Receiver / Transmitter) is shown, including multiple registers (such as RCSTA, RCREG, SPBRG, TXREG and TXSTA) connected to the SFR bus interface. The receiving and transmitting FIFO buffers, bit rate generators, receiving state machines and transmitting state machines are shown in the figure. These components are interconnected through internal access and interrupt signals to coordinate the processing of parallel data streams from RX receiving to TX sending. On this basis, a custom protocol interface is added to exchange data with other devices. The scalability and flexibility of this module have been significantly improved, thus providing more convenient conditions for system upgrades and changes. The use of this modular design scheme not only fully saves hardware resources, but also reduces the difficulty of development. The UART module is composed of two parts: SFR bus control logic and UART transceiver control logic, which is an indispensable core component of the present invention. The SFR bus control part is mainly used to realize data transmission between the CPU. According to the instruction configuration of the CPU, the working registers related to the UART module can be allocated, the corresponding status registers can be detected, and the transceiver registers can be read and written. By using the configuration information, the UART transceiver control logic can realize the functions of receiving, sending and caching data information at different baud rates, and can detect whether there is an error in the transmitted data frame, and output the result in the form of a flag bit, providing reliable protection for data transmission.

[0043] SPI module design: The design of the SPI module realizes the configurability of software on the basis of the hardware circuit, supports two transmission modes of master and slave and four communication modes at the same time, and has the ability to receive interrupts. At the same time, the module also has the ability to exchange data with other peripheral devices, thereby providing more flexible and changeable application modes for the system. According to the operating principle of the SPI protocol, in combination with the processor core in the present invention, the design of this module is divided into two parts: SFR bus control logic and SPI transceiver control logic. By dividing these functional modules and combining them according to different logical relationships to form the structural framework of the whole system, the specific circuit design and analysis of each functional module on the chip are completed. The SPI transceiver control logic covers multiple modules, including REGCON transmission signal control module, TRIG trigger control module, BAUDGEN clock frequency division module, RX data receiving module and TX data sending module, and the detailed functions of these modules are shown in Table 2.

[0044] Table 2 SPI transceiver control logic module functions Module Name Functional Description REGCON Module Generate various control signals, detect status micro signals in real time, refresh status registers regularly to prevent mis-collection and mis-transmission of data, control the jump of state machines, and generate interrupt request signals. BAUDGEN module The system clock CLK is divided by 4, 16, or 64 in the host module, and the SCK signal is output as the serial synchronous clock for data transmission. TRIG module The system always detects the edge of SCK through CLK, and outputs the transmit signal and the receive signal according to the corresponding working mode. TX module The written parallel data is sent bit by bit. RX Module Convert serial data into parallel data, store it in registers, and wait for CPU access. TMR0 module design: There are two main ways to implement the timing function of TMR0: timing and counting, which can provide the MCU with precise time control. The principle of using the timing method to implement the timing function is frequency division counting, and the counting method is based on the pulse signal from the external input. When this pulse signal changes periodically, the timing function can be realized.

[0045] The timing counter module in the present invention has two driving modes to choose from: internal clock and external clock. Among them, the trigger edge can be selected independently by using the external clock drive. First, the timer is configured to receive an external clock source as a timing reference, and the type of trigger edge is selected by register setting, such as rising edge, falling edge or double edge. The timer contains an eight-bit pre-divider and a counting register. The eight-bit pre-divider can be programmed by software to set its frequency division coefficient to determine the number of times each clock pulse affects the counter, thereby adjusting the timing accuracy and overflow time interval. The counting register can be read and written by the CPU, and the CPU can read the current count value or write a new initial value to control the counting state of the timer. When the counting register overflows, the timer generates an interrupt request signal, and the system responds to the interrupt request and executes a predefined interrupt service routine (ISR) to handle specific interrupt events, such as resetting the counter, updating data or performing other related tasks, thereby realizing the precise timing function of the timer and timely interrupt processing.

[0046] GPIO module design: As an interface for microprocessor to communicate data with the outside world, GPIO pins can not only be used for data input and output, but can also be multiplexed with other functional modules to save hardware resources and even realize interrupts in different working modes.

[0047] In the present invention, two groups of GPIOs consisting of 8 pins are used, each pin is controlled by the corresponding bit on the TRIS register, the input signal is represented by a high level, and the output signal is presented by a low level. When setting the interrupt source, the enable signal must first be passed to the RBIE bit of the INTCON register to ensure that the interrupt request signal can be sent to the RBIF bit of the INTCON. In addition, if it is necessary to operate a register, different registers can be selected to execute respectively. In the specific implementation process, the present invention adopts a method of mapping two registers to the same physical address to solve the logical conflict problem between the input and output directions.

[0048] WDT module design: WDT is a module specially used to detect the running status of MCU programs to prevent the program from running away and causing deadlock. WDT performs its functions under the control of its reference clock. Here, the present invention proposes a method of using watchdog timing to detect the system. When the program runs abnormally, the overflow signal is sent to the frequency divider, and a watchdog overflow signal is generated according to the frequency division ratio. Then, this watchdog signal is input to the reset management module of the kernel, and then a global reset is triggered. When the program runs normally, a reset will not be triggered.

[0049] Low power consumption design and improvement: (1) Operand isolation design ALU is a computing unit composed of 16 types of operation circuits. When the input signal is reversed, it will inevitably generate considerable flip power. In order to reduce this flip power consumption, it is necessary to set corresponding operation identifiers for each address in these registers so that users can know their corresponding register values. Instructions will be translated into ALU instructions and non-ALU instructions, which is the responsibility of the decoding unit. If a certain type of instruction needs to be executed, the corresponding instruction can be selected from another type of instruction to achieve this purpose. When ALU instructions arrive, the opcode, SRC1 and SRC2 operands contained in each instruction will be transferred to the ALU unit after the calculation is completed. After the operation is completed, the ALU will output the result and write it to the target storage unit, and record three flag bits at the same time. If a reinitialization or renaming operation is required, it will return to execute the next instruction. When the kernel receives a non-ALU instruction, it will not focus on the current ALU operation status. However, the source operand and opcode port of the ALU will still access the data for calculation and output the result. Although this can increase the processing speed, it reduces the overall performance of the system. Unlike other ALU instructions, non-ALU instructions will not write the result and flag information into the storage unit, so as not to interfere with the normal operation of the kernel. Since this method can enable the processor to have a good understanding of the execution of instructions, the processing speed can be improved. Due to the existence of unused paths, the signal flip phenomenon always exists, so the dynamic power consumption of the system will increase. In addition, if an external memory is to be used, these operations need to be re-encoded, which not only wastes resources but also causes program errors. In order to reduce the flipping and dynamic power consumption of the system, the present invention introduces an operand isolation register before inputting the SRC1 and SRC2 operands, such as Figure 6As shown, the operand isolation circuit of the ALU is used to effectively isolate and select different operands when performing operations to ensure correct data transmission and processing. The circuit uses a multiplexer and control signals to select appropriate operands from registers or immediate numbers according to instruction requirements and sends them to the ALU for operation, thereby improving the efficiency and accuracy of data processing. The register can pre-compile the output according to the operation data input to the memory array and then transmit it to the decoding unit. Once the decoding unit detects that the current instruction is a non-ALU instruction, it will reset the two source operands to zero and correspond the operation code to the NOP instruction, thereby completely terminating the operation in the ALU.

[0050] (2) Sleep wake-up mode Once the system configuration is completed, the MCU may be in an idle state for the rest of the time. Only after the module of the peripheral device sends an interrupt request signal, the kernel will respond to it and execute the interrupt program to ensure the normal operation of the system. Since the kernel itself does not have the interrupt function, it must use other devices to assist in interrupt processing. When the system is in an idle state, the kernel usually performs a series of operations, such as running an infinite loop program, jumping, taking values, decoding and executing, etc. However, these operations do not bring any practical effects, but instead cause a large amount of dynamic power consumption. If you want to continue these complex and cumbersome operation steps, you will need to consume more power. Therefore, when the MCU is in an idle state, a power-saving sleep mode can be used to replace those mechanical and meaningless operation processes, so that the MCU can get a short rest during this period and maintain a low power consumption level. During this process, if necessary, these data are stored for the next use. When it is necessary to perform control tasks, the MCU system can be awakened by interrupt requests or watchdog timing. In sleep mode, if you want to resume work, you must first activate the sleep enable circuit before you can resume work. When the working mode is converted to the sleep mode, the kernel needs to execute the SLEEP instruction, and then the MCU will decode the sleep state to pull the high energy signal and turn off the four-phase clocks CLK_Q1, CLK_Q2, CLK_Q3, and CLK_Q4, while the registers in the MCU will keep the current state unchanged. After entering the sleep state, the present invention proposes two wake-up methods, one of which is to use the "watchdog" timing. Even if the system is in the sleep state, the watchdog can continue to work, but when the count overflows, it will trigger the system reset to achieve timed wake-up; the other is to use the sleep enable signal to initialize after the system enters sleep, and then start sleep through the interrupt mode, which can also achieve a certain degree of wake-up effect. The second method is to use an interrupt request to trigger the crystal oscillator to restart, so as to achieve wake-up. However, since it takes a period of time to change from the start-up state to the stable state, the interrupt request signal must always maintain a high level during this period of time, and can only be gradually reduced when the system resumes normal execution, otherwise it will cause wake-up failure. If there is a relatively high flag signal on the crystal oscillator at this time, it means that there is no fault or error information on the crystal oscillator, and no interrupt will occur. Only after the system is awakened and enters the interrupt program, the interrupt request flag signal will be pulled low.

Claims

1. A portable and low-power MCU device, characterized in that: Including instruction architecture, storage architecture, pipeline architecture, processor core and peripheral IP, UART module, SPI module, TMR0 module, GPIO module and WDT module; The instruction architecture includes byte operation instructions for operating file registers, bit operation instructions for operating file registers, immediate value operation instructions and fixed encoding format control instructions; in all operation instructions, the operation code field is located in the highest bit segment, and the operation code field contains instruction type and function information; The storage architecture includes an instruction storage area, a core and a data storage area; first, the instruction storage area stores instructions executed by the MCU; second, the core reads instructions from the instruction storage area and executes them, and communicates with the instruction storage area and the data storage area through a bus; the data storage area is used to store data generated during the operation of the MCU; The pipeline architecture adopts a double-layer shallow pipeline structure; wherein the first pipeline is used for instruction fetching and the second pipeline is used for execution; in the second pipeline, each clock cycle is divided into four stages, each stage is triggered by a different edge of the clock: the first edge is used for instruction decoding, the second edge is used for operand fetching, the third edge is used for instruction execution, and the fourth edge is used for result writing back; The processor core and the peripheral IP are divided into the following functional modules, namely, a dedicated register stack module, a program counter module, a controller module, an interrupt control module, a clock / reset management module and a stack module; As an asynchronous transmitter, the UART module can ensure that data is transmitted normally without using a clock line by setting the transmission format and rate of the receiving end and the transmitting end; in order to realize the UART receiving and transmitting functions, two types of registers are configured: the first is the UART peripheral device register, which is configured to realize flexible configuration of the UART working mode, including selecting receiving, sending or full-duplex communication mode, setting the baud rate, the number of data bits, the number of stop bits, and the check method, so as to adapt to different data transmission requirements; the other is the core interrupt register, when the kernel needs to respond to data changes or events of external devices in real time, the interrupt register is configured to enable the system to access the peripheral register in an interrupt manner; this method allows the system to respond to external events immediately when needed; The SPI module supports two transmission modes, master-slave and multiple communication modes, and has a receiving interrupt function; at the same time, the module also has the ability to exchange data with other peripheral devices; the module is divided into two parts: SFR bus control logic and SPI transceiver control logic; The TMR0 module is used for timing and counting; the timing function is realized by frequency division counting, and the counting is based on the pulse signal from the external input. When the pulse signal changes periodically, the timing function can be realized; as an interface for the microprocessor to communicate data with the outside, the pins of the GPIO module are used as data input and output, and are multiplexed with other functional modules to realize interrupts in different working modes; in the WDT module, the watchdog timing method is used to detect the system. When the program runs abnormally, the overflow signal is sent to the frequency divider, and a watchdog overflow signal is generated according to the frequency division ratio, and then the watchdog signal is input to the reset management module of the kernel, which then triggers a global reset.

2. The MCU device with portability and low power consumption according to claim 1, characterized in that: A corresponding operation identifier is set for each register address in the dedicated register stack module. When an ALU-type instruction arrives, the operation code, SRC1 and SRC2 operands contained in each instruction will be transmitted to the ALU unit after calculation. Before inputting the SRC1 and SRC2 operands, an operand isolation register is introduced. The operand isolation circuit of the ALU is used to effectively isolate and select different operands when performing operations. The circuit selects operands from registers or immediate numbers according to instruction requirements by using multiplexers and control signals, and sends them to the ALU for operation.

3. The MCU device with portability and low power consumption according to claim 1, characterized in that: The instruction storage area is equipped with areas of different sizes and numbers, and the instruction storage area is divided into multiple areas according to the size, number and characteristics of the instructions; then, one or more storage areas are allocated to each type of instruction, and the size and number of these areas are adjusted according to the expected size of the instruction set; finally, the instruction storage is utilized through dynamic allocation and static allocation strategies; the partitioning technology and address conversion technology are used to make the instruction storage have a wider range of applicability; the address conversion technology is a method for managing and accessing the memory, mapping the logical address to the physical address; when the address of the instruction or data to be accessed in the memory exceeds the range of the current memory paging, a variety of different addressing methods are used to directly jump to the target address; because the instruction memory has a certain mapping relationship with the register, when the program is running, if there is no memory residue, the entire operating system needs to be reinitialized.

4. The MCU device with portability and low power consumption according to claim 1, characterized in that: The data storage area is divided into 4 independent pages, and the pages mainly include a special function register area, a general register area, and a public mapping area; the special function register area is used to store registers with special functions, and low address units are installed on each page, including two types of configuration registers: kernel and peripherals; within a set time, the special function register area reads and writes data files according to set rules, and at a set time point, through a timer interrupt or a scheduler trigger, reads and writes the special function register mapped to the set memory address, and according to pre-defined rules and conditions, the control and monitoring of hardware functions are realized; the general register stores the general data of variables defined in the software and is stored in the high address units of each page.

5. The MCU device with portability and low power consumption according to claim 1, characterized in that: The dedicated register stack module sets working information for the kernel and peripheral devices, and can record various flag signals generated by the program during execution in real time; the module consists of six registers with special functions: INDF is the indirect addressing mode register, PCL is the lower eight bits of the program counter, STATUS is the status register, FSR is the file select register, PCLATH is the upper five bits of the program counter, and WORK is the working register but there is no unified address encoding; each register has a corresponding reset value.

6. The MCU device with portability and low power consumption according to claim 1, characterized in that: The program counter module analyzes the decoding, operation result and external interrupt of the current instruction to determine the address of the next instruction; The program counter consists of three parts, namely, the instruction decoding module, the operation unit module, and the register; The instruction decoding module is responsible for transmitting the instruction information read from the memory to the operation unit module in a serial manner, so that the corresponding data value is calculated and sent to the register for storage; The calculation unit module can uniformly output the calculation results and flag information obtained after the calculation, thereby realizing efficient data processing.

7. The MCU device with portability and low power consumption according to claim 1, characterized in that: When the MCU is in idle state, a power-saving sleep mode is adopted. The sleep mode includes shutting down some internal circuits or reducing the processor frequency, and retaining sufficient functions to respond to external interrupt signals; during the sleep process, the current register status, temporary variables and any intermediate calculation result data are stored so that they can be quickly restored to the state before sleep when woken up next time, and continue the unfinished task or execute new operations; when the control task needs to be executed, the MCU system is woken up by interrupt request or watchdog timing; in sleep mode, if you want to restart work, you must first activate the sleep enable circuit to resume work; when the working mode is converted to sleep mode, the kernel needs to execute the SLEEP instruction, and then the MCU will decode the sleep state to pull the high-energy signal and turn off the four-phase clocks CLK_Q1, CLK_Q2, CLK_Q3, and CLK_Q4, while the registers in the MCU will remain in the current state unchanged; after entering the sleep state, the There are two wake-up methods, one of which is to use the "watchdog" timing. Even if the system is in sleep mode, the watchdog can continue to work, but when the count overflows, it will trigger a system reset to achieve timed wake-up; the other is to use the sleep enable signal to initialize after the system enters sleep, and then start sleep through an interrupt, which can also achieve a certain degree of wake-up effect; the second method is to use an interrupt request to trigger the crystal oscillator to restart, thereby achieving wake-up; however, since it takes a while to change from the starting state to the stable state, the interrupt request signal must always remain at a high level during this period of time, and can only be gradually reduced when the system resumes normal execution, otherwise it will cause wake-up failure; if there is a relatively high flag signal on the crystal oscillator, it means that there is no fault on the crystal oscillator or there is no erroneous information, and no interrupt will occur at this time; only after the system is awakened and enters the interrupt program, the interrupt request flag signal will be pulled low.

8. The MCU device with portability and low power consumption according to claim 1, characterized in that: The timing counter module has two driving modes to choose from: internal clock and external clock. Among them, the external clock drive can independently select the trigger edge. First, configure the timer to receive the external clock source as the timing reference, and select the type of trigger edge through register settings. The timer contains an eight-bit prescaler and a counting register. The eight-bit prescaler is programmed by software to set its division coefficient to determine the number of times each clock pulse affects the counter, thereby adjusting the timing accuracy and overflow time interval. The counting register can be read and written by the CPU. The CPU reads the current count value or writes a new initial value to control the counting state of the timer. When the count register overflows, the timer generates an interrupt request signal, and the system responds to the interrupt request and executes a predefined interrupt service program to handle the interrupt event.

9. The MCU device with portability and low power consumption according to claim 1, characterized in that: Two groups of 8-pin GPIOs are used. Each pin is controlled by the corresponding bit on the TRIS register. The input signal is represented by a high level, while the output signal is represented by a low level. When setting the interrupt source, the enable signal must first be passed to the RBIE bit of the INTCON register to ensure that the interrupt request signal can be sent to the RBIF bit of INTCON. If a register needs to be operated, different registers can be selected for execution separately. The two registers are mapped to the same physical address to solve the logical conflict between the input and output directions.

Images