Method, device and equipment for testing equalization parameters of sending end of high-speed serial computer expansion bus and medium

Abstract

The invention discloses a sending end equalization parameter testing method, device and equipment for a high-speed serial computer expansion bus and a medium, relates to the technical field of computers, and is applied to a target device. The target device comprises a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on an acquisition component and an analysis component. The method comprises the following steps: configuring a current sending end equalization parameter in the uplink port or the downlink port; performing error code check according to the signal sent by the downlink port and the received signal; if the verification is passed, a signal sent by a downlink port is collected through a collection assembly; a target voltage is calculated according to an acquired signal through an analysis component, a de-emphasis parameter and a pre-emphasis parameter are calculated according to the target voltage, and a target sending end equalization parameter determined based on the de-emphasis parameter and the pre-emphasis parameter is compared with a current sending end equalization parameter. Therefore, the test cost is reduced and the test period is shortened.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, equipment and medium for testing equalization parameters of a high-speed serial computer expansion bus at the sending end. Background Art

[0002] With the gradual improvement of computer processing performance and the gradual increase in the amount of stored data, new challenges are constantly being raised to the data transmission rate and computer interface rate of computers. In order to meet the requirements of high link reliability, manufacturers are required to ensure that the PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus) interface meets the PCIe PHY (Physical, port physical layer) test specifications. The PCIe Tx Preset (transmitter equalization parameter) test is one of the key test items of compliance testing. This test requires the use of a high-speed oscilloscope to capture the PCIe Tx waveform binary file and use SigTest for analysis.

[0003] Due to the shortage of high-speed oscilloscope resources in China, the test cost of PCIe Tx equalization parameters increases accordingly. During the verification phase, the PCIe Sig compliance test of the PCIe interface needs to be repeated many times, which increases the test cost and the test cycle of a single lane is longer, corresponding to a longer test cycle.

[0004] Therefore, the above problems need to be solved by those skilled in the art urgently. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a method, device, equipment and medium for testing equalization parameters of a high-speed serial computer expansion bus, which reduces the test cost and shortens the test cycle. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses a method for testing equalization parameters of a high-speed serial computer expansion bus at the transmitting end, which is applied to a target device, wherein the target device includes a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on a collection component and an analysis component, and the method includes:

[0007] configuring a current transmitting end equalization parameter in the uplink port or the downlink port;

[0008] Performing error checking according to a first signal sent by the downlink port and a second signal received by the downlink port; wherein the first signal is transmitted to the uplink port through the first loop, and the second signal is output to the downlink port through the uplink port;

[0009] If the error check passes, after receiving the signal collection instruction, the third signal sent by the downlink port is collected by the collection component to obtain a collection signal;

[0010] The target voltage is calculated according to the acquired signal by the analysis component, and the de-emphasis parameters and the pre-emphasis parameters are calculated according to the target voltage, and then the target transmitting end equalization parameters determined based on the de-emphasis parameters and the pre-emphasis parameters are compared with the current transmitting end equalization parameters to obtain corresponding comparison test results.

[0011] Optionally, after receiving the signal collection instruction, collecting the third signal sent by the downlink port by the collection component to obtain the collection signal includes:

[0012] After receiving the signal collection instruction each time, the collection component collects the value of the preset bit in the third signal sent by the downlink port to obtain a first collection result;

[0013] Obtaining a first acquisition signal according to the plurality of first acquisition results;

[0014] Accordingly, calculating the target voltage according to the collected signal by the analysis component includes:

[0015] The first target voltage is calculated by the analysis component according to the average value of the first acquisition signal.

[0016] Optionally, after receiving the signal collection instruction, collecting the third signal sent by the downlink port by the collection component to obtain the collection signal includes:

[0017] Controlling the downlink port to send a fourth signal, and adjusting the current transmitting end equalization parameter to a transformed transmitting end equalization parameter; wherein the fourth signal includes a level signal corresponding to the second target voltage and a level signal corresponding to the third target voltage;

[0018] Based on the transformed transmitting-end equalization parameter, the downlink port is controlled to send the third signal, and after receiving the signal collection instruction each time, the collection component collects the value of the preset bit in the third signal sent by the downlink port to obtain a second collection result corresponding to the second target voltage and a third collection result corresponding to the third target voltage;

[0019] Obtaining a second acquisition signal according to the plurality of the second acquisition results, and obtaining a third acquisition signal according to the plurality of the third acquisition results;

[0020] Accordingly, calculating the target voltage according to the collected signal by the analysis component includes:

[0021] The second target voltage is calculated according to the average value of the second acquisition signal by the analysis component, and the third target voltage is calculated according to the average value of the third acquisition signal by the analysis component.

[0022] Optionally, calculating a de-emphasis parameter and a pre-emphasis parameter according to the target voltage includes:

[0023] The de-emphasis parameter is calculated according to the logarithm of the voltage ratio of the first target voltage to the second target voltage, and the pre-emphasis parameter is calculated according to the logarithm of the voltage ratio of the third target voltage to the first target voltage.

[0024] Optionally, after comparing the target transmitting end equalization parameter determined based on the de-emphasis parameter and the pre-emphasis parameter with the current transmitting end equalization parameter, the method further includes:

[0025] If the target transmitting end equalization parameter is consistent with the current transmitting end equalization parameter, it is determined that the transmitting end equalization parameter test passes;

[0026] If the target transmitting end equalization parameter is inconsistent with the current transmitting end equalization parameter, it is determined that the transmitting end equalization parameter test has failed.

[0027] Optionally, the current transmitting end equalization parameters are configured in the uplink port, then the first loop includes the downlink port, the uplink port, the power divider and the first signal enhancement component in sequence, and the second loop includes the uplink port, the power divider, the second signal enhancement component, the acquisition component and the analysis component in sequence; wherein the power divider is used to attenuate the power of the corresponding signal, and the first signal enhancement component and the second signal enhancement component are used to enhance the power of the corresponding signal.

[0028] Optionally, the current transmitting end equalization parameters are configured in the downlink port, then the first loop includes the downlink port, the power divider, the first signal enhancement component and the uplink port in sequence, and the second loop includes the downlink port, the power divider, the second signal enhancement component, the acquisition component and the analysis component in sequence; wherein the power divider is used to attenuate the power of the corresponding signal, and the first signal enhancement component and the second signal enhancement component are used to enhance the power of the corresponding signal.

[0029] In a second aspect, the present application discloses a transmitter equalization parameter test device for a high-speed serial computer expansion bus, which is applied to a target device, wherein the target device includes a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on an acquisition component and an analysis component, including:

[0030] A parameter configuration module, configured to configure current transmitting end equalization parameters in the uplink port or the downlink port;

[0031] an error checking module, configured to perform error checking according to a first signal sent by the downlink port and a second signal received by the downlink port; wherein the first signal is transmitted to the uplink port through the first loop, and the second signal is output to the downlink port through the uplink port;

[0032] A signal acquisition module, configured to acquire a third signal sent by the downlink port through the acquisition component after receiving a signal acquisition instruction if the error check passes, to obtain an acquisition signal;

[0033] A signal testing module is used to calculate a target voltage according to the collected signal through the analysis component, and calculate a de-emphasis parameter and a pre-emphasis parameter according to the target voltage, and then compare the target transmitting end equalization parameter determined based on the de-emphasis parameter and the pre-emphasis parameter with the current transmitting end equalization parameter to obtain a corresponding comparison test result.

[0034] In a third aspect, the present application discloses an electronic device, comprising:

[0035] Memory, used to store computer programs;

[0036] The processor is used to execute the computer program to implement the above-disclosed method for testing equalization parameters of the transmitter of the high-speed serial computer expansion bus.

[0037] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the transmitting-end equalization parameter testing method of the high-speed serial computer expansion bus disclosed above is implemented.

[0038] It can be seen that the present application proposes a method for testing transmitter equalization parameters of a high-speed serial computer expansion bus, which is applied to a target device, wherein the target device includes a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on an acquisition component and an analysis component, and the method includes: configuring the current transmitter equalization parameters in the uplink port or the downlink port; performing error checking according to the first signal sent by the downlink port and the second signal received by the downlink port; wherein the first signal is transmitted to the uplink port through the first loop, and the second signal is output to the downlink port through the uplink port; if the error checking passes, the third signal sent by the downlink port is collected by the acquisition component after receiving the signal collection instruction to obtain an acquisition signal; the target voltage is calculated according to the acquisition signal by the analysis component, and the de-emphasis parameter and the pre-emphasis parameter are calculated according to the target voltage, and then the target transmitter equalization parameter determined based on the de-emphasis parameter and the pre-emphasis parameter is compared with the current transmitter equalization parameter to obtain a corresponding comparison test result. It can be seen that the present application constructs a first loop based on the uplink port and the downlink port, and constructs a second loop based on the acquisition component and the analysis component, so that the transmitting end equalization parameter test process of the present application is closer to the actual application scenario. Further, the present application verifies the reliability of the link based on the first loop, improves the link reliability, and ensures that the test results are accurate. In addition, the present application completes the acquisition of the signal through the acquisition component, and realizes the analysis of the signal through the analysis component, so that automation and remote operation can be realized, with high reproducibility and scalability, easy to realize batch testing, reducing the test cost and shortening the test cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0040] Figure 1 A flow chart of a method for testing equalization parameters of a high-speed serial computer expansion bus transmitter disclosed in the present application;

[0041] Figure 2 A schematic diagram of the structure of a transmitter equalization parameter test of a USP link disclosed in the present application;

[0042] Figure 3 A schematic diagram of the structure of a DSP link transmitter equalization parameter test disclosed in the present application;

[0043] Figure 4 A schematic diagram of a target voltage disclosed in this application;

[0044] Figure 5 It is a schematic diagram of the comparison relationship between equalization parameters, de-emphasis parameters and pre-emphasis parameters;

[0045] Figure 6 A flow chart of a specific method for testing equalization parameters of a high-speed serial computer expansion bus transmitter disclosed in the present application;

[0046] Figure 7 A flow chart of a specific method for testing equalization parameters of a high-speed serial computer expansion bus transmitter disclosed in the present application;

[0047] Figure 8 This is a schematic diagram of the structure of a high-speed serial computer expansion bus transmitter equalization parameter testing device disclosed in the present application;

[0048] Fig. 9 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] Due to the shortage of high-speed oscilloscope resources in China, the test cost of PCIe Tx equalization parameters increases accordingly. During the verification phase, the PCIe Sig compliance test of the PCIe interface needs to be repeated many times, which increases the test cost and the test cycle of a single lane is longer, corresponding to a longer test cycle.

[0051] To this end, an embodiment of the present application proposes a transmitter equalization parameter testing solution for a high-speed serial computer expansion bus, which can reduce testing costs and shorten testing cycles.

[0052] The present application embodiment discloses a method for testing equalization parameters of a high-speed serial computer expansion bus transmitter, which is applied to a target device, wherein the device includes a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on a collection component and an analysis component, see Figure 1 As shown, including:

[0053] Step S11: configure the current transmitting end equalization parameters in the uplink port or the downlink port.

[0054] In this embodiment, the transmitting end parameters are divided into 11 coarse adjustment values ​​from P0 to P10, and the current transmitting end equalization parameters are configured in the uplink port (UpperStream Port, USP) or the downlink port (Down Stream Port, DSP). For example, P0 is configured first, and the P0 test of the uplink port or the downlink port is implemented through the subsequent steps of this embodiment, and then P1 is configured, and so on.

[0055] In a first specific implementation, the current transmitting end equalization parameter is configured in the uplink port, the first loop includes the downlink port, the uplink port, the power splitter and the first signal enhancement component in sequence, and the second loop includes the uplink port, the power splitter, the second signal enhancement component, the acquisition component and the analysis component in sequence; wherein the power splitter is used to attenuate the power of the corresponding signal, and the first signal enhancement component and the second signal enhancement component are used to enhance the power of the corresponding signal. Figure 2 As shown in the figure, USP is Slave (slave device) or Device Board (device board), the power divider meets the preset attenuation conditions, and the attenuation conditions can be set in different scenarios. There is no restriction here. Figure 2 It can realize the transmission end equalization parameter test of USP link.

[0056] In a second specific implementation, the current transmitting end equalization parameter is configured in the downlink port, the first loop includes the downlink port, the power splitter, the first signal enhancement component and the uplink port in sequence, and the second loop includes the downlink port, the power splitter, the second signal enhancement component, the acquisition component and the analysis component in sequence; wherein the power splitter is used to attenuate the power of the corresponding signal, and the first signal enhancement component and the second signal enhancement component are used to enhance the power of the corresponding signal. Figure 3 As shown, DSP is the Host or System Board, based on Figure 3 It can realize the transmission end equalization parameter test of DSP link.

[0057] Step S12: performing error checking based on a first signal sent by the downlink port and a second signal received by the downlink port; transmitting the first signal to the uplink port through the first loop, and outputting the second signal to the downlink port through the uplink port.

[0058] In this embodiment, before performing the transmitter equalization parameter test, it is necessary to perform a bit error stress test. Since the voltage amplitude of TxPreset P7 is the lowest, it is most likely to cause bit errors due to excessive link loss. Figure 2 and Figure 3After the verification system is built, USP fixes Tx Preset to P7 and completes link establishment with DSP. The downlink port sends a fixed code pattern of 1010 alternating. After loopback, the downlink port verifies whether the received code pattern is the alternating 1010 code pattern. If the error check passes, it means the link is stable. If there is an error, it is necessary to check each connection link to ensure that there is no error before performing the transmitter equalization parameter test.

[0059] Step S13: If the error check passes, the third signal sent by the downlink port is collected by the collection component after receiving the signal collection instruction to obtain a collection signal.

[0060] In this embodiment, the transmitting end equalization parameters include pre-emphasis parameters and de-emphasis parameters, and the calculation and Figure 4 The voltage shown is related to this embodiment. Figure 4 Wherein Vb is the first target voltage, Va is the second target voltage, and Vc is the third target voltage.

[0061] The following describes how to calculate the first target voltage:

[0062] After each signal acquisition instruction is received, the acquisition component acquires the value of the preset bit position in the third signal emitted by the downlink port to obtain a first acquisition result, and obtains a first acquisition signal based on multiple first acquisition results, so that the first target voltage can be calculated according to the average value of the first acquisition signal through the analysis component.

[0063] by Figure 2 Taking the system as an example, this embodiment configures a group of preset values ​​to be tested in the USP, so that the DSP and the USP negotiate according to the preset value specific to the USP during the initial power-on link negotiation. After the DSP and the USP complete the link establishment, the DSP sends a third signal of a specific code type at intervals according to the sampling requirements. The third signal consists of 64 consecutive 0s and 64 1s. After receiving the third signal, the USP sends it through the Tx link. When the USP sends the 10th 0 or 1, it notifies the analysis component through the Com (Communication) interface to start reading the sampled data from the acquisition component but does not save it. When the USP sends the 45th 0 or 1, it notifies the analysis component through the Com interface to start saving the sampled data read from the acquisition component. The sampling is completed before the USP sends the 62nd 0 or 1 to obtain the first acquisition result. Repeat the above steps, and obtain the first acquisition signal based on multiple first acquisition results, and then calculate the first target voltage based on the average value of the first acquisition signal.

[0064] by Figure 3Taking the system as an example, this embodiment configures a set of preset values ​​to be tested in the DSP, so that the DSP and USP negotiate according to the preset value specific to the DSP when they first power on the link. After the DSP and USP complete the link establishment, the DSP sends a third signal of a specific code type at intervals according to the sampling requirements. Similarly, when the DSP sends to the 10th 0 or 1, it notifies the analysis component to start reading data from the acquisition component. When the DSP sends to the 45th 0 or 1, it notifies the analysis component to complete a sampling and data storage. Before the DSP sends to the 62nd 0 or 1, the sampling and storage ends, and the first acquisition result is obtained. Repeat the above steps, and obtain the first acquisition signal based on multiple first acquisition results, and then calculate the first target voltage based on the average value of the first acquisition signal.

[0065] The calculation method of the second target voltage and the third target voltage is introduced below:

[0066] Control the downlink port to send a fourth signal, and adjust the current transmitter equalization parameter to the transformed transmitter equalization parameter; wherein the fourth signal includes a level signal corresponding to the second target voltage and a level signal corresponding to the third target voltage. Further, based on the transformed transmitter equalization parameter, control the downlink port to send a third signal, and after each signal acquisition instruction is received, collect the value of the preset bit position in the third signal sent by the downlink port through the acquisition component to obtain a second acquisition result corresponding to the second target voltage and a third acquisition result corresponding to the third target voltage. Further, obtain a second acquisition signal based on multiple second acquisition results, and obtain a third acquisition signal based on multiple third acquisition results, so that the second target voltage is calculated according to the average value of the second acquisition signal through the analysis component, and the third target voltage is calculated according to the average value of the third acquisition signal through the analysis component.

[0067] See also Figure 5 As shown, the de-emphasis parameter (De-emphasis) and pre-emphasis parameter (Preshoot) of P4 are both 0, so Va=Vb=Vc. In this way, to determine P1, it is only necessary to determine Va. It is known that Vc=Vb. When P1 has been configured, the DSP's transmitter Tx sends a Va level (the second target voltage), and then P1 is modified to P4 (that is, the transmitter equalization parameter after the transformation), and 64 consecutive 1s (assuming that the Va level is 1) are sent followed by 64 consecutive 0s. One sampling is completed between the 45th 1 and the 62nd 1. Since the P1 to P4 code type does not change, P4 Vb=P1 Va at this time, that is, a Va sampling is completed. Repeat the above process 500 times and complete 500 samplings. At this time, the P1 Vb collected in the early stage can be used to analyze P1, and then Va is obtained. The calculation of Vc refers to Va. In the calculation of Vc, the Vc level is the third target voltage.

[0068] Step S14: Calculate the target voltage according to the collected signal through the analysis component, and calculate the de-emphasis parameters and the pre-emphasis parameters according to the target voltage, and then compare the target transmitting end equalization parameters determined based on the de-emphasis parameters and the pre-emphasis parameters with the current transmitting end equalization parameters to obtain corresponding comparison test results.

[0069] From the above analysis, it can be known that the present embodiment calculates the first target voltage, the second target voltage and the third target voltage according to the collected signal. Further, the de-emphasis parameter is calculated according to the logarithm of the voltage ratio of the first target voltage to the second target voltage, and the pre-emphasis parameter is calculated according to the logarithm of the voltage ratio of the third target voltage to the first target voltage. Specifically, De-emphasis = 20log10 Vb / Va, Preshoot = 20log10 Vc / Vb. Further, the present embodiment compares the target transmitter equalization parameter determined based on the de-emphasis parameter and the pre-emphasis parameter with the current transmitter equalization parameter, and when the target transmitter equalization parameter is consistent with the current transmitter equalization parameter, it is determined that the transmitter equalization parameter test has passed, and when the target transmitter equalization parameter is inconsistent with the current transmitter equalization parameter, it is determined that the transmitter equalization parameter test has failed. It should be noted that the present embodiment can refer to Table 1 for comparison, which shows the corresponding relationship between P0~P10 and the pre-emphasis parameter and the de-emphasis parameter:

[0070] Table 1

[0071]

[0072] In this way, a test of the equalization parameters of the transmitter is completed. Further, the equalization parameter values ​​in the DSP or USP are modified and the above steps are repeated. After the voltages corresponding to the 11 equalization parameter values ​​are sampled, the equalization parameter values ​​are analyzed according to the corresponding relationship in Table 1 to complete a round of equalization parameter testing.

[0073] See also Figure 6 As shown, in the transmitter equalization parameter test of the USP link, P7 is configured in the USP, and the DSP is linked to the USP. Then, the DSP is controlled to send the alternating fixed code pattern of S1 to the USP. After receiving, the USP sends it to the power divider. Further, the power divider divides S1 into two. If the S1 received by the first signal enhancement component (Redriver1) is an alternating code pattern of 1010, it is restored and error checking is performed, otherwise it is discarded. Figure 7The same is true for the bit error test of the DSP link in the above. Furthermore, after the bit error test is passed, the DSP sends the third signal (that is, the 64 1s + 64 0s mentioned above). At this time, if the S1 received by the second signal enhancement component (Redriver2) is 64 1s + 64 0s, it will be restored and sampled and analyzed. Figure 7 The same is true for the transmitter equalization parameter test of the DSP link.

[0074] From the above, it can be seen that the present application reduces the high dependence on high-speed oscilloscopes and test fixtures, reduces the use of high-speed oscilloscopes, and saves test resources. Since the test verification system of the present application is controlled by an analysis component (such as a PC analyzer), automated testing and remote batch testing can be achieved. At the same time, multiple high-speed acquisition and analysis systems can be configured to improve test efficiency to achieve parallel testing. The present application forms a loop with DSP and USP that can normally perform link training and service stress testing. A fixed Tx Preset value is written to the DSP or USP end to be tested, so that the link is established according to this Tx Preset parameter. After that, the DSP sends a signal of a specific code type, and the power divider divides the signal into two, one for error verification, and the other for sampling analysis. The analyzed Tx Preset parameters are compared to see if they are consistent with the pre-configured equalization parameters. If they are consistent, the verification is passed, and if they are inconsistent, the verification fails.

[0075] Further, the present embodiment can calculate the value of the Boost parameter based on the above method to implement the test of the Boost parameter, Boost = 20log10 Vd / Vb, wherein Vb can be obtained by the above method, and the calculation of Vd is shown in Va. In the calculation of Vd, the Vc level is the fourth target voltage, and the value of the fourth target voltage is shown in Figure 4 shown.

[0076] It can be seen that the present application proposes a method for testing transmitter equalization parameters of a high-speed serial computer expansion bus, which is applied to a target device, wherein the target device includes a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on an acquisition component and an analysis component, and the method includes: configuring the current transmitter equalization parameters in the uplink port or the downlink port; performing error checking according to the first signal sent by the downlink port and the second signal received by the downlink port; wherein the first signal is transmitted to the uplink port through the first loop, and the second signal is output to the downlink port through the uplink port; if the error checking passes, the third signal sent by the downlink port is collected by the acquisition component after receiving the signal collection instruction to obtain an acquisition signal; the target voltage is calculated according to the acquisition signal by the analysis component, and the de-emphasis parameter and the pre-emphasis parameter are calculated according to the target voltage, and then the target transmitter equalization parameter determined based on the de-emphasis parameter and the pre-emphasis parameter is compared with the current transmitter equalization parameter to obtain a corresponding comparison test result. It can be seen that the present application constructs a first loop based on the uplink port and the downlink port, and constructs a second loop based on the acquisition component and the analysis component, so that the transmitting end equalization parameter test process of the present application is closer to the actual application scenario. Further, the present application verifies the reliability of the link based on the first loop, improves the link reliability, and ensures that the test results are accurate. In addition, the present application completes the acquisition of the signal through the acquisition component, and realizes the analysis of the signal through the analysis component, so that automation and remote operation can be realized, with high reproducibility and scalability, easy to realize batch testing, reducing the test cost and shortening the test cycle.

[0077] Correspondingly, the embodiment of the present application also discloses a transmitter equalization parameter test device for a high-speed serial computer expansion bus, which is applied to a target device, wherein the target device includes a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on a collection component and an analysis component, see Figure 8 As shown, including:

[0078] A parameter configuration module 11, configured to configure current transmitting end equalization parameters in the uplink port or the downlink port;

[0079] The error checking module 12 is used to perform error checking according to the first signal sent by the downlink port and the second signal received by the downlink port; wherein the first signal is transmitted to the uplink port through the first loop, and the second signal is output to the downlink port through the uplink port;

[0080] The signal acquisition module 13 is used for acquiring the third signal sent by the downlink port through the acquisition component after receiving the signal acquisition instruction if the error check passes, so as to obtain an acquisition signal;

[0081] The signal testing module 14 is used to calculate the target voltage according to the collected signal through the analysis component, and calculate the de-emphasis parameters and the pre-emphasis parameters according to the target voltage, and then compare the target transmitting end equalization parameters determined based on the de-emphasis parameters and the pre-emphasis parameters with the current transmitting end equalization parameters to obtain corresponding comparison test results.

[0082] Among them, for more specific working processes of the above-mentioned modules, please refer to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0083] It can be seen that the present application proposes a method for testing transmitter equalization parameters of a high-speed serial computer expansion bus, which is applied to a target device, wherein the target device includes a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on an acquisition component and an analysis component, and the method includes: configuring the current transmitter equalization parameters in the uplink port or the downlink port; performing error checking according to the first signal sent by the downlink port and the second signal received by the downlink port; wherein the first signal is transmitted to the uplink port through the first loop, and the second signal is output to the downlink port through the uplink port; if the error checking passes, the third signal sent by the downlink port is collected by the acquisition component after receiving the signal collection instruction to obtain an acquisition signal; the target voltage is calculated according to the acquisition signal by the analysis component, and the de-emphasis parameter and the pre-emphasis parameter are calculated according to the target voltage, and then the target transmitter equalization parameter determined based on the de-emphasis parameter and the pre-emphasis parameter is compared with the current transmitter equalization parameter to obtain a corresponding comparison test result. It can be seen that the present application constructs a first loop based on the uplink port and the downlink port, and constructs a second loop based on the acquisition component and the analysis component, so that the transmitting end equalization parameter test process of the present application is closer to the actual application scenario. Further, the present application verifies the reliability of the link based on the first loop, improves the link reliability, and ensures that the test results are accurate. In addition, the present application completes the acquisition of the signal through the acquisition component, and realizes the analysis of the signal through the analysis component, so that automation and remote operation can be realized, with high reproducibility and scalability, easy to realize batch testing, reducing the test cost and shortening the test cycle.

[0084] Furthermore, an embodiment of the present application also provides an electronic device. Fig. 9This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0085] Fig. 9 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the method for testing the equalization parameters of the transmitter of the high-speed serial computer expansion bus disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0086] In this embodiment, the power supply 26 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 24 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0087] In addition, the memory 22, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc., and the resources stored thereon may include a computer program 221, and the storage method may be a temporary storage or a permanent storage. Among them, the computer program 221 includes not only a computer program that can be used to complete the equalization parameter test method of the transmitter of the high-speed serial computer expansion bus executed by the electronic device 20 disclosed in any of the aforementioned embodiments, but also a computer program that can be used to complete other specific tasks.

[0088] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned disclosed method for testing equalization parameters of a transmitter of a high-speed serial computer expansion bus.

[0089] For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be described in detail here.

[0090] Furthermore, an embodiment of the present application also discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the transmitting end equalization parameter testing method of the high-speed serial computer expansion bus as disclosed above.

[0091] The various embodiments in this application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0092] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0093] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0094] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0095] The above is a detailed introduction to the transmitting end equalization parameter testing method, device, equipment, and storage medium of a high-speed serial computer expansion bus provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for testing equalization parameters of a high-speed serial computer expansion bus, characterized in that: Applied to a target device, the target device includes a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on a collection component and an analysis component, the method includes: configuring a current transmitting end equalization parameter in the uplink port or the downlink port; Performing error checking according to a first signal sent by the downlink port and a second signal received by the downlink port; wherein the first signal is transmitted to the uplink port through the first loop, and the second signal is output to the downlink port through the uplink port; If the error check passes, after receiving the signal collection instruction, the third signal sent by the downlink port is collected by the collection component to obtain a collection signal; The target voltage is calculated according to the acquired signal by the analysis component, and the de-emphasis parameters and the pre-emphasis parameters are calculated according to the target voltage, and then the target transmitting end equalization parameters determined based on the de-emphasis parameters and the pre-emphasis parameters are compared with the current transmitting end equalization parameters to obtain corresponding comparison test results.

2. The method for testing equalization parameters of a high-speed serial computer expansion bus at the transmitting end according to claim 1, characterized in that: After receiving the signal collection instruction, collecting the third signal sent by the downlink port through the collection component to obtain the collection signal includes: After receiving the signal collection instruction each time, the collection component collects the value of the preset bit in the third signal sent by the downlink port to obtain a first collection result; Obtaining a first acquisition signal according to the plurality of first acquisition results; Accordingly, calculating the target voltage according to the collected signal by the analysis component includes: The first target voltage is calculated by the analysis component according to the average value of the first acquisition signal.

3. The method for testing equalization parameters of a high-speed serial computer expansion bus at the transmitting end according to claim 2, characterized in that: After receiving the signal collection instruction, collecting the third signal sent by the downlink port through the collection component to obtain the collection signal includes: Controlling the downlink port to send a fourth signal, and adjusting the current transmitting end equalization parameter to a transformed transmitting end equalization parameter; wherein the fourth signal includes a level signal corresponding to the second target voltage and a level signal corresponding to the third target voltage; Based on the transformed transmitting-end equalization parameter, the downlink port is controlled to send the third signal, and after receiving the signal collection instruction each time, the collection component collects the value of the preset bit in the third signal sent by the downlink port to obtain a second collection result corresponding to the second target voltage and a third collection result corresponding to the third target voltage; Obtaining a second acquisition signal according to the plurality of the second acquisition results, and obtaining a third acquisition signal according to the plurality of the third acquisition results; Accordingly, calculating the target voltage according to the collected signal by the analysis component includes: The second target voltage is calculated according to the average value of the second acquisition signal by the analysis component, and the third target voltage is calculated according to the average value of the third acquisition signal by the analysis component.

4. The method for testing equalization parameters of a high-speed serial computer expansion bus at the transmitting end according to claim 3, characterized in that: The calculating the de-emphasis parameter and the pre-emphasis parameter according to the target voltage includes: The de-emphasis parameter is calculated according to the logarithm of the voltage ratio of the first target voltage to the second target voltage, and the pre-emphasis parameter is calculated according to the logarithm of the voltage ratio of the third target voltage to the first target voltage.

5. The method for testing equalization parameters of a high-speed serial computer expansion bus at the transmitting end according to claim 1, characterized in that: After comparing the target transmitting end equalization parameter determined based on the de-emphasis parameter and the pre-emphasis parameter with the current transmitting end equalization parameter, the method further includes: If the target transmitting end equalization parameter is consistent with the current transmitting end equalization parameter, it is determined that the transmitting end equalization parameter test passes; If the target transmitting end equalization parameter is inconsistent with the current transmitting end equalization parameter, it is determined that the transmitting end equalization parameter test has failed.

6. The method for testing equalization parameters of a high-speed serial computer expansion bus at the transmitting end according to any one of claims 1 to 5, characterized in that: The current transmitting end equalization parameters are configured in the uplink port, then the first loop includes the downlink port, the uplink port, the power divider and the first signal enhancement component in sequence, and the second loop includes the uplink port, the power divider, the second signal enhancement component, the acquisition component and the analysis component in sequence; wherein the power divider is used to attenuate the power of the corresponding signal, and the first signal enhancement component and the second signal enhancement component are used to enhance the power of the corresponding signal.

7. The method for testing equalization parameters of a high-speed serial computer expansion bus at the transmitting end according to any one of claims 1 to 5, characterized in that: The current transmitting end equalization parameters are configured in the downlink port, then the first loop includes the downlink port, the power divider, the first signal enhancement component and the uplink port in sequence, and the second loop includes the downlink port, the power divider, the second signal enhancement component, the acquisition component and the analysis component in sequence; wherein the power divider is used to attenuate the power of the corresponding signal, and the first signal enhancement component and the second signal enhancement component are used to enhance the power of the corresponding signal.

8. A device for testing equalization parameters of a high-speed serial computer expansion bus at the transmitting end, characterized in that: Applied to a target device, the target device includes a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on a collection component and an analysis component, including: A parameter configuration module, used to configure the current transmitting end equalization parameter in the uplink port or the downlink port; an error checking module, configured to perform error checking according to a first signal sent by the downlink port and a second signal received by the downlink port; wherein the first signal is transmitted to the uplink port through the first loop, and the second signal is output to the downlink port through the uplink port; A signal acquisition module, configured to acquire a third signal sent by the downlink port through the acquisition component after receiving a signal acquisition instruction if the error check passes, to obtain an acquisition signal; A signal testing module is used to calculate a target voltage according to the collected signal through the analysis component, and calculate a de-emphasis parameter and a pre-emphasis parameter according to the target voltage, and then compare the target transmitting end equalization parameter determined based on the de-emphasis parameter and the pre-emphasis parameter with the current transmitting end equalization parameter to obtain a corresponding comparison test result.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the transmitter equalization parameter testing method of a high-speed serial computer expansion bus as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the transmitting end equalization parameter testing method of a high-speed serial computer expansion bus as described in any one of claims 1 to 7 is implemented.

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