A method for reducing the instantaneous effect of current inside a chip

Abstract

The present invention relates to the field of integrated circuit technology, and discloses a method for reducing the instantaneous effect of internal current of a chip. The method includes: in the startup stage of the target chip, gradually turning on the clocks and resets of each functional system; in the shutdown stage of the target chip, gradually turning off the clocks and resets of each functional system; in the dynamic operation stage of the target chip, monitoring the first current of the first logic circuit; if the first current decreases and the decreased current value meets the first condition, turning on the second logic circuit to perform equivalent occupancy on the first current; if the first current increases and the increased current value meets the second condition, turning off the second logic circuit. The present invention aims at two stages of the chip working process, reduces the current change rate in the corresponding stages to reduce the influence of the instantaneous effect of current mutation, and improves the functional stability of the chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a method for reducing the instantaneous effect of internal current of a chip. Background Art

[0002] With the improvement of the scale, frequency, and performance of integrated circuits, the power consumption also increases correspondingly, resulting in increased difficulty in power supply system and signal integrity design. Especially in high-power load scenarios, the problems of voltage spikes or dips caused by a rapid current change rate (di / dt) are particularly prominent, which easily lead to chip function failures, such as power supply noise, crosstalk, electromagnetic interference (EMI), etc., and may even affect the service life of the chip, such as causing local overheating or overvoltage damage.

[0003] Traditional chip-level power supply solutions, such as simple linear voltage regulators and basic switching power supplies, often struggle to effectively handle voltage spikes or dips caused by a rapid current change rate, resulting in chip function failures (power supply noise, crosstalk, EMI, etc.), and even affecting the service life (such as local overheating, overvoltage damage, etc.). Similarly, in the chip design process, the current change rate (di / dt) also poses challenges to the related designs of the backend power network (PI, SI) and package design.

[0004] In view of this, a method for reducing the instantaneous effect of internal current of a chip is needed to reduce di / dt from the chip's own design, that is, to reduce current mutations, thereby reducing the impact of current mutation instantaneous effects. Summary of the Invention

[0005] In view of this, the present invention provides a method for reducing the instantaneous effect of internal current of a chip, which can reduce the current change rate to reduce the impact of current mutation instantaneous effects and improve the functional stability of the chip.

[0006] In a first aspect, the present invention provides a method for reducing the instantaneous effect of internal current of a chip. The method includes: in the startup stage of the target chip, gradually turning on the clocks and resets of each functional system; in the shutdown stage of the target chip, gradually turning off the clocks and resets of each functional system; in the dynamic operation stage of the target chip, monitoring the first current of the first logic circuit; if the first current decreases and the decreased current value meets the first condition, turning on the second logic circuit to perform equivalent occupancy on the first current; if the first current increases and the increased current value meets the second condition, turning off the second logic circuit.

[0007] In a possible implementation, the first condition is that the decreased current value is greater than the first threshold; the second condition is that the increased current value is greater than the second threshold.

[0008] In a possible implementation, the first condition is that the descending gradient of the first current is greater than a third threshold; the second condition is that the ascending gradient of the first current is greater than a fourth threshold.

[0009] In a second aspect, the present invention provides an integrated circuit chip, in which a soft start control system is deployed to execute a method for reducing the instantaneous effect of the internal current of the chip; the soft start control system includes a reset management module and a clock management module; the reset management module is used to control the sequence and time interval of the resets of each functional system; the clock management module is used to control the sequence and time interval of the clocks of each functional system.

[0010] In a possible implementation, the first logic circuit is a preset functional system circuit in the chip.

[0011] In a possible implementation, the integrated circuit chip further includes a power consumption backup system; the power consumption backup system includes a second logic circuit, and the second logic circuit includes a multiplexing logic circuit; the second logic circuit is a circuit of a functional system other than the preset functional system in the chip.

[0012] In a possible implementation, the multiplexing logic circuit is further used to multiplex existing logic; the existing logic includes DFX logic and non-operating circuits.

[0013] In a possible implementation, the second logic circuit includes at least one additional backup circuit; the additional backup circuit includes a D flip-flop logic circuit.

[0014] In a possible implementation, the power consumption backup system is further used to control the working states of the corresponding number of second logic circuits according to the change gradient of the first current.

[0015] In a third aspect, the present invention provides an electronic device, including: a memory and an integrated circuit chip, which are communicatively connected to each other, the memory stores instructions, and the integrated circuit chip executes the instructions to execute a method for reducing the instantaneous effect of the internal current of the chip according to the first aspect or any corresponding implementation manner thereof.

[0016] In a fourth aspect, the present invention provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to execute a method for reducing the instantaneous effect of the internal current of the chip according to the first aspect or any corresponding implementation manner thereof.

[0017] The technical solution provided by this application may include the following beneficial effects:

[0018] The method for reducing the instantaneous effect of the internal current of a chip in this application gradually turns on the clocks and resets of each functional system during the startup and shutdown phases of the chip. By staggering the time points, the current undergoes multiple small-amplitude gradual changes over a longer period, reducing the instantaneous load pressure faced by the power supply system. During the dynamic operation phase of the chip, the current change of the first logic circuit is monitored in real time. When it is detected that the current of the first logic circuit decreases to less than the first threshold, the second logic circuit is turned on to perform equivalent current occupancy, which can make up for the decrease in the total power consumption caused by the decrease in the current of the first logic circuit. When it is detected that the current of the first logic circuit increases to greater than the second threshold, the second logic circuit is turned off to avoid excessive power consumption by the second logic circuit. By turning on and off the second logic circuit, the overall current is relatively stabilized at a certain value. The above solution targets two phases of the chip's working process respectively, reducing the current change rate in the corresponding phases to reduce the impact of the instantaneous current mutation effect and improving the functional stability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a schematic structural diagram of a soft start control system according to an embodiment of the present invention;

[0021] Figure 2 It is a schematic flowchart of a method for reducing the instantaneous effect of the internal current of a chip according to an embodiment of the present invention;

[0022] Figure 3 It is a schematic structural diagram of a power consumption backup system according to an embodiment of the present invention;

[0023] Figure 4 It is a schematic hardware structure diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0025] An embodiment of the present invention provides a method for reducing the instantaneous effect of the internal current of a chip. By controlling the rate of change of the chip current during the startup, shutdown, and dynamic operation phases, the impact of the instantaneous effect of current mutation is reduced, and the functional stability of the chip is improved.

[0026] According to an embodiment of the present invention, an embodiment of a method for reducing the instantaneous effect of the internal current of a chip is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0027] In this embodiment, an integrated circuit chip is also provided. A soft start control system is deployed in the integrated circuit chip to execute a method for reducing the instantaneous effect of the internal current of the chip; the soft start control system is as Figure 1 shown, and includes:

[0028] A reset management module 101, which is used to control the sequence and time interval of the resets of each functional system;

[0029] A clock management module 102, which is used to control the sequence and time interval of the clocks of each functional system.

[0030] Among them, the main purpose of the soft start control system is to make the current change more slowly during the startup and shutdown processes of the chip by controlling the resets and clocks of each functional system, thereby reducing the instantaneous effect of the current.

[0031] The reset management module receives a reset request and controls the sequence and time interval of the resets of each functional system, including the assert (reset pull-down) and de-assert (reset cancellation pull-up) of the reset. By designing the reset sequence and time interval, the mutation of the current during the startup and shutdown phases can be reduced.

[0032] The clock management module controls the sequence and time interval of the clocks of each functional system through ICG (clock gating). By controlling the turn-on and turn-off of the clocks, it is ensured that each functional system can increase or decrease the power consumption orderly and slowly during startup and shutdown, thereby reducing di / dt.

[0033] For example Figure 1 shown, the reset management module receives reset requests from reset source O and reset source N, and the reset management module and the clock management module jointly control the sequence and time interval of the resets and clocks of functional system O and functional system N through path (0), path (1), and path (2).

[0034] Figure 2It is a flowchart of a method for reducing the instantaneous effect of internal current of a chip according to an embodiment of the present invention. The process includes the following steps:

[0035] Step S201, in the startup stage of the target chip, gradually turn on the clocks and resets of each functional system.

[0036] When the chip starts up, since all functional systems start simultaneously, it may cause a huge instantaneous current change (di / dt). Therefore, the present invention proposes to adopt a soft startup control system in the startup stage. Through the reset management module and the clock management module, gradually turn on the clocks and resets of each functional system. Specifically, in the stage of gradually starting up the functional system, the reset management module and the clock management module cooperate to sequentially turn on the clocks of the functional system and release the reset. In this stage, there are three controllable variables: the order between different functional systems, the time interval between different functional systems, and the clock and reset interval within a functional system. Specifically, gradually turning on can be to turn on the clocks and resets of each functional system at a certain time interval.

[0037] Optionally, in the embodiment of the present application, in the startup stage of the target chip, the time interval between each functional system corresponds to each functional system, that is, different functional systems correspond to different time intervals. This control of the order and time interval enables the current to change slowly in multiple small amplitudes over a long time, thus significantly reducing di / dt.

[0038] Step S202, in the shutdown stage of the target chip, gradually turn off the clocks and resets of each functional system.

[0039] Similar to the startup stage, if the clocks and resets of all functional systems are directly cut off in the shutdown stage, a large di / dt will also be generated. Adopt a soft startup control system to gradually turn off the clocks and resets of each functional system. Specifically, gradually turning off can be to turn off the clocks and resets of each functional system at a certain time interval.

[0040] Optionally, in the embodiment of the present application, in the shutdown stage of the target chip, the time interval between each functional system corresponds to each functional system, that is, different functional systems correspond to different time intervals; for example, for a functional system that needs a long time to complete data transmission, the time interval is set longer; for a functional system that needs a short time to complete data transmission, the time interval is set shorter. In the process of gradually turning off, the time interval can be adjusted according to the current change situation of the functional system. For example, in the stage where the current drops significantly, a longer time interval may be required; in the stage where the current drops slightly, a shorter time interval may be required. According to the characteristics and current situation of each functional system, the soft startup control system can flexibly adjust the time interval to more accurately control di / dt.

[0041] Step S203, during the dynamic operation phase of the target chip, monitor the first current of the first logic circuit; if the first current decreases and the decreased current value meets the first condition, turn on the second logic circuit to perform equivalent occupancy on the first current; if the first current increases and the increased current value meets the second condition, turn off the second logic circuit.

[0042] During the dynamic operation phase of the chip, by monitoring the current change of the first logic circuit and according to the preset conditions, turn on or off the second logic circuit to perform equivalent occupancy of power consumption.

[0043] Optionally, the first condition is that the decreased current value is greater than the first threshold; the second condition is that the increased current value is greater than the second threshold.

[0044] Alternatively, the first condition is that the falling gradient of the first current is greater than the third threshold; the second condition is that the rising gradient of the first current is greater than the fourth threshold.

[0045] To more precisely control the turning on and off of the power consumption backup circuit system, multiple optional conditions are set to determine whether the current change of the first logic circuit requires equivalent occupancy by the second logic circuit.

[0046] Specifically, there are two setting methods for the first condition and the second condition.

[0047] In the first setting method, the first condition is that when the current of the first logic circuit decreases and the decreased current value is greater than the preset first threshold, turn on the second logic circuit to perform equivalent occupancy of power consumption. The second condition is that when the current of the first logic circuit increases and the increased current value is greater than the preset second threshold, it is considered that the power consumption of the first logic circuit has been restored at this time, and turn off the second logic circuit. This setting method is based on the absolute value of the current change and is used to judge whether the power consumption of the first logic circuit is sufficient or excessive.

[0048] In the second setting method, the first condition is that when the falling gradient of the current of the first logic circuit is greater than the preset third threshold, that is, the current drops rapidly in a short time, it is considered that this rapid current change may cause a large impact on the power supply system, so it is necessary to immediately turn on the second logic circuit to perform equivalent occupancy of power consumption. The second condition is that when the rising gradient of the current of the first logic circuit is greater than the preset fourth threshold, that is, the current rises rapidly in a short time, it is considered that the power consumption of the original circuit is sufficient at this time, so turn off the second logic circuit. This setting method is based on the rate of current change and can respond more timely to current fluctuations.

[0049] The threshold value in the present invention refers to the critical value of current or the critical value of current gradient. For example, the first threshold value can be 0.5A. When the decreased current value of the first logic circuit is greater than 0.5A, the second logic circuit is turned on; the second threshold value can be 1A. When the increased current value of the first logic circuit is greater than 1A, the second logic circuit is turned off; the third threshold value can be 1A / us. When the current decrease gradient of the first logic circuit is greater than 1A / us, the second logic circuit is turned on; the fourth threshold value can be 2A / us. When the current increase gradient of the first logic circuit is greater than 2A / us, the second logic circuit is turned off. Configuring the first threshold value, the second threshold value, the third threshold value and the fourth threshold value according to the actual situation can more flexibly control the turning on and off of the second logic circuit.

[0050] In some alternative embodiments, the first logic circuit is a pre-set functional system circuit in the chip. In the embodiments of the present invention, the first logic circuit is a pre-set functional system circuit in the chip. During the operation of the chip, the current change of the first logic circuit directly reflects the fluctuation of its power consumption.

[0051] In some alternative embodiments, the above integrated circuit chip further includes a power consumption backup system; the power consumption backup system includes a second logic circuit; the second logic circuit is a circuit of a functional system in the chip other than the pre-set functional system.

[0052] The second logic circuit includes a multiplexing logic circuit; the multiplexing logic circuit is further used to multiplex existing logic; the existing logic includes DFX logic and non-working circuits.

[0053] Optionally, the second logic circuit includes at least one additional backup circuit; the additional backup circuit includes a D flip-flop logic circuit.

[0054] Specifically, the power consumption backup system is composed of the second logic circuit. The second logic circuit refers to other functional system circuits in the chip except for the pre-set main functional system circuit, which can be turned on or off under specific conditions to realize the adjustment of the instantaneous effect of the current inside the chip, and the second logic circuit includes two implementation methods:

[0055] The first implementation method is that the multiplexing logic circuit is the main component of the power consumption backup system. The multiplexing logic circuit uses the existing logic in the chip that is not currently in the working state (such as DFX logic, non-working circuits, etc.) to perform equivalent occupancy of power consumption. This method does not require adding too many additional logic circuits, and only needs to add some monitoring and control logic on the basis of the existing logic to achieve.

[0056] The second implementation method is that the additional backup circuit is used as an alternative to the power consumption backup system. The additional backup circuit includes newly added logic components such as D flip-flop logic circuits. These circuits have no actual functional role and only serve as power consumption backups. Although there may be some redundancy in the functional logic in this way, it provides higher flexibility, allowing the size and scope of power consumption backup to be adjusted according to actual needs.

[0057] Among them, the structure of the power consumption backup system is as Figure 3 shown. The multiplexing logic circuit mainly includes DFX logic B, control unit C, and monitoring unit D. DFX logic B is the main component bearing power consumption and participates in or exits the main operation logic according to requirements. Control unit C is the core of the entire multiplexing logic. It processes the signals from logic circuit A, which are used as the original function signals to guide the behavior of DFX logic B. When the system starts, control unit C is responsible for initializing all DFX logic B to the default state, and can drive DFX logic B to run at full speed when needed, as well as switch to the functional mode to cooperate with logic circuit A. Monitoring unit D is responsible for detecting the operating state of logic circuit A, directly receiving upstream interface signals or parsing local protocol layer status information.

[0058] The additional backup circuit part includes control unit E and power consumption backup circuit F. Control unit E is similar to control unit C, but provides more diverse control methods, such as clock enable (clken*), reset operation (rst*), frequency adjustment (Div*), etc., to meet the system's requirements in different scenarios. Power consumption backup circuit F is an important part of the system's power consumption management and is composed of storage elements such as DFFs or MEMs. Power consumption backup circuit F supports grouped management of the circuit, enabling separate turning on and off of different components, as well as adjustment of the operating frequency.

[0059] As Figure 3 shown, the power consumption backup system structure has the following execution logic:

[0060] 1. Monitoring unit D receives upstream interface signals;

[0061] 2. Monitoring unit D monitors or processes signals by parsing local protocol layer status information;

[0062] 3. Control unit C processes the signals from monitoring unit D;

[0063] 4. Control unit C processes the signals from logic circuit A;

[0064] 5. DFX logic B is guided by control unit C;

[0065] 6. Control unit E processes the signals from monitoring unit D;

[0066] 7. The control unit E provides signals such as clock enable, reset operation, and frequency adjustment to the power consumption backup circuit.

[0067] In summary, the multiplexing logic circuit of the first implementation manner of the second logic circuit is the main solution of the power consumption backup system. The additional power consumption backup circuit of the second implementation manner of the second logic circuit is an optional solution, which is only used in scenarios where the number of logics and DIE size are not sensitive, and the power consumption of the logic multiplexing part is too small to meet the power consumption balance requirement, as an alternative solution.

[0068] In some alternative embodiments, the power consumption backup system is also used to control the operating states of the corresponding number of second logic circuits according to the change gradient of the first current.

[0069] The current change gradient is a physical quantity that describes how fast the current changes over time and reflects the degree of current change. In the embodiments of the present invention, by monitoring the current change gradient of the first logic circuit, the power consumption backup system can judge the trend and intensity of the current chip power consumption change, and thus make a response. When the current change gradient of the first logic circuit is large, it means that the power consumption change intensity is large. At this time, the power consumption backup system will control to turn on more second logic circuits to provide more power consumption equivalent occupancy, so as to more effectively balance the change of the overall current and reduce the current instantaneous effect. On the contrary, when the current change gradient of the first logic circuit is small, the power consumption backup system will correspondingly reduce the number of second logic circuits turned on to avoid wasting resources.

[0070] In summary, the embodiments of the present invention introduce a soft start control system and a power consumption backup system, respectively for the start-up and shutdown phases and the dynamic operation phase of the chip working process, to reduce the current change rate in the corresponding phases to reduce the impact of the current mutation instantaneous effect and improve the chip function stability.

[0071] The embodiments of the present invention also provide an electronic device, in which an integrated circuit chip including a soft start control system as shown in Figure 1 and a power consumption backup system as shown in Figure 3 is provided to implement the method as shown in Figure 2 .

[0072] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of an electronic device provided by an alternative embodiment of the present invention. As shown in Figure 4As shown, the electronic device includes: one or more integrated circuit chips 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Each component communicates with each other using different buses and can be installed on a common motherboard or in other ways as needed. The integrated circuit chip can process instructions executed within the electronic device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if needed, multiple integrated circuit chips and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a set of blade servers). Figure 4 In this, an integrated circuit chip 10 is taken as an example.

[0073] The integrated circuit chip 10 can be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above programmable logic device can be a complex programmable logic device, a field programmable gate array, a generic array logic, or any combination thereof.

[0074] Among them, the memory 20 stores instructions executable by at least one integrated circuit chip 10, so that at least one integrated circuit chip 10 executes the method shown in the above embodiments.

[0075] The memory 20 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device, etc. In addition, the memory 20 can include high-speed random access memory and can also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 can optionally include a memory remotely set relative to the integrated circuit chip 10, and these remote memories can be connected to the computer device through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0076] The memory 20 can include volatile memory, such as random access memory; the memory can also include non-volatile memory, such as flash memory, a hard disk, or a solid-state drive; the memory 20 can also include a combination of the above types of memory.

[0077] The computer device further includes an input device 30 and an output device 40. The integrated circuit chip 10, the memory 20, the input device 30, and the output device 40 can be connected through a bus or other means, Figure 4 In this, the connection through a bus is taken as an example.

[0078] The input device 30 can receive input numerical or character information and generate key signal inputs related to the user settings and function controls of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), and a haptic feedback device (e.g., a vibration motor), etc. The above display device includes but is not limited to a liquid crystal display, a light-emitting diode, a display, and a plasma display. In some alternative embodiments, the display device can be a touch screen.

[0079] The embodiments of the present invention also provide a computer-readable storage medium. The method according to the embodiments of the present invention can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented by downloading via a network the original computer code stored in a remote storage medium or a non-transitory machine-readable storage medium and to be stored in a local storage medium, so that the method described herein can be stored as such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0080] A part of the present invention can be applied as a computer program product, such as computer program instructions, which when executed by a computer, can call or provide the methods and / or technical solutions according to the present invention through the operation of the computer. Those skilled in the art should be able to understand that the forms in which computer program instructions exist in a computer-readable medium include but are not limited to source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include but are not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible by the computer.

[0081] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for reducing the transient effect of internal current of a chip, characterized in that: The method includes: In the startup phase of the target chip, gradually turn on the clocks and resets of each functional system; In the shutdown phase of the target chip, gradually turn off the clocks and resets of each functional system; In the dynamic operation phase of the target chip, monitor the first current of the first logic circuit; if the first current decreases and the decreased current value meets the first condition, turn on the second logic circuit to perform equivalent occupancy on the first current; if the first current increases and the increased current value meets the second condition, turn off the second logic circuit; the second logic circuit includes a multiplexing logic circuit; the multiplexing logic circuit is used to perform equivalent occupancy of power consumption through the logic circuits that already exist in the chip and are not currently in the working state; The first condition is that the decreased current value is greater than the first threshold; the second condition is that the increased current value is greater than the second threshold; alternatively, the first condition is that the descending gradient of the first current is greater than the third threshold; the second condition is that the ascending gradient of the first current is greater than the fourth threshold.

2. An integrated circuit chip, characterized in that: A soft start control system is deployed in the integrated circuit chip to execute the method according to claim 1; the soft start control system includes a reset management module and a clock management module; The reset management module is used to control the sequence and time interval of the resets of each functional system; The clock management module is used to control the sequence and time interval of the clocks of each functional system.

3. The chip according to claim 2, wherein The first logic circuit is a preset functional system circuit in the chip.

4. The chip according to claim 3, characterized in that The integrated circuit chip further includes a power consumption backup system; the power consumption backup system includes the second logic circuit; The second logic circuit is a circuit of a functional system in the chip other than the preset functional system.

5. The chip according to claim 4, characterized in that, The multiplexing logic circuit is further used to multiplex existing logic circuits; the existing logic circuits include DFX logic circuits and non-working circuits.

6. The chip according to claim 3, wherein The second logic circuit includes at least one additional backup circuit; the additional backup circuit includes D flip-flop logic circuits.

7. The chip according to claim 4, characterized in that The power consumption backup system is further used to control the working states of the corresponding number of second logic circuits according to the change gradient of the first current.

8. A computer-readable storage medium, characterized in that, Computer instructions are stored on the computer-readable storage medium, and the computer instructions are used to cause a computer to execute the method according to claim 1.

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