Method for optimizing ion implantation process parameters of integrated circuit

Abstract

The invention discloses a method for optimizing ion implantation process parameters of an integrated circuit, which comprises the following steps of: simulating a front-end process of a CMOS (Complementary Metal Oxide Semiconductor) device by utilizing Sensor Process of Sensor TCAD (Technology Computer Aided Design) software, and changing process parameters in a Halo ion implantation step to obtain a simulated CMOS device; then, carrying out numerical solution on the electrical property of the simulation CMOS device by utilizing a Sensor Device in the software, so as to obtain electrical data; and training, verifying and testing the residual neural network model by using the process parameters and the electrical data, optimizing parameters of the residual neural network model, and finally obtaining optimized process parameters. The method not only improves the optimization efficiency and precision of the ion implantation process parameters, but also realizes the automation and intelligence of process optimization through the combination of the deep learning algorithm and the TCAD simulation technology.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a method for optimizing integrated circuit ion implantation process parameters. Background Art

[0002] Ion implantation is a semiconductor doping process that began to develop in the 1960s. In the production and manufacturing of integrated circuits, many doping processes use ion implantation technology. For example, in the preparation process of silicon-on-insulator (SOI) materials, a buried oxide layer is usually formed by high-energy, high-concentration oxygen ion implantation; in the isolation process of integrated circuit manufacturing, in order to prevent parasitic channels, channel interception technology is used; when adjusting the threshold voltage, channel doping is used; ion implantation is also used to form the wells and source and drain regions of N-type and P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices, thereby forming CMOS (Complementary Metal Oxide Semiconductor) devices; as well as doping of shallow junctions, etc. This series of key processes all rely on ion implantation technology.

[0003] However, the traditional CMOS ion implantation process has many limitations. The adjustment and optimization of process parameters usually require a long experimental cycle and high testing costs, and the establishment of the ion implantation process recipe (i.e., process parameters) is highly dependent on the experience of engineers and physical theory formulas. As integrated circuits develop towards higher integration, smaller size, and more complex structures, these traditional methods are difficult to meet increasingly stringent manufacturing standards. For example, as the size of the doped region decreases, the channeling and scattering phenomena in the ion implantation process become more complex, and the requirements for the precision of process control are getting higher and higher.

[0004] Therefore, a method that can achieve more precise process control is urgently needed. Summary of the invention

[0005] The first purpose of the present invention is to provide a method for optimizing integrated circuit ion implantation process parameters in view of the deficiencies in the prior art. By using Sentaurus TCAD software to perform structural modeling, simulation and electrical parameter extraction on MOSFET logic devices, a large-scale data set of the relationship between ion implantation and device electrical property parameters is constructed. Combined with a neural network algorithm model, rapid iterative optimization of ion implantation process recipes is achieved, which helps to improve the functional performance, yield and stability of the device, accelerate the speed of device research and development, and promote the application and development of intelligent manufacturing technology in the field of integrated circuit manufacturing.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] Step S1, using the process simulation module (Sentaurus Process) of Sentaurus TCAD software to simulate the front-end process of the CMOS device, the front-end process includes the following steps: substrate initialization, shallow trench isolation formation, P / N type well implantation, gate oxide and polysilicon gate growth, first layer sidewall growth, LDD (Lightly Doped Drain, lightly doped drain) ion implantation, Halo (halo) ion implantation, second layer sidewall growth and source and drain ion implantation, metal silicide to form source and drain contact; changing the process parameters in the Halo ion implantation step to obtain a simulated CMOS device;

[0008] Step S2, using the device simulation module (Sentaurus Device) of Sentaurus TCAD software to solve the electrical properties of the simulated CMOS device obtained in step S1 to obtain electrical data;

[0009] Step S3, preprocessing the process parameters and electrical data and constructing a data set, which is then divided into a training set, a validation set, and a test set;

[0010] Step S4: construct a residual neural network model, use the data set to train, verify and test the residual neural network model, and output the optimized process parameters.

[0011] Furthermore, the process parameters include implantation angle, implantation energy and implantation dose.

[0012] Furthermore, the electrical data includes the device threshold voltage (V th ), subthreshold voltage swing (SS), saturation current (I dsat ), leakage current (I off ), maximum transconductance (G m ), linear region resistance (R lin ) and saturation resistance (R sat ).

[0013] Furthermore, the residual neural network model adopts a ResNet18 model.

[0014] Furthermore, step S2 solves the electrical properties based on physical models, and the physical models include carrier transport model, density gradient model, drift-diffusion model, mobility models, inversion and accumulation layer mobility models, high-field saturation models, SRH (Shockley-Read-Hall) composite model and avalanche breakdown model.

[0015] A second object of the present invention is to provide an integrated circuit ion implantation process parameter optimization system for implementing the above method, comprising the following modules:

[0016] Data simulation module, used to simulate the manufacturing process of CMOS devices and obtain electrical data and process parameters;

[0017] Data preprocessing module, used to preprocess electrical data and process parameters;

[0018] The process parameter optimization module inputs the preprocessed electrical data and process parameters into the optimized residual neural network model to obtain the optimized process parameters.

[0019] A third object of the present invention is to provide an electronic device, comprising a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement the above method.

[0020] A fourth object of the present invention is to provide a machine-readable storage medium storing machine-executable instructions, which, when called and executed by a processor, prompt the processor to implement the above method.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The present invention uses TCAD simulation to iteratively optimize process parameters quickly and automatically in a virtual environment, greatly reducing experimental cycles and testing costs. Combined with a deep learning model, it can perform high-precision optimization of process parameters under complex conditions, achieve refined requirements for process control, and quickly complete multiple optimization iterations, greatly accelerating device development and shortening product time to market.

[0023] The method of the present invention can improve the functional performance, yield and stability of the device by optimizing the process recipe through a deep learning model. By learning and analyzing a large amount of simulation data, the neural network model can identify the optimal combination of process parameters and avoid errors caused by insufficient human experience or inaccurate physical theoretical formulas.

[0024] The method of the present invention not only improves the optimization efficiency and accuracy of the ion implantation process, but also promotes the application of intelligent manufacturing technology in the field of integrated circuit manufacturing. Through the combination of deep learning algorithm and TCAD simulation technology, the automation and intelligence of process optimization are realized, providing a new technical means for integrated circuit intelligent manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a flow chart of the present invention.

[0026] Figure 2 (a) to (f) are schematic diagrams of NMOS process flow simulation device process.

[0027] Figure 3 (a) to (f) are schematic diagrams of the PMOS process flow simulation device process.

[0028] Figure 4 It is a structural diagram of the residual neural network model of the present invention.

[0029] Figure 5 This is the accuracy result of the model training process of the present invention. DETAILED DESCRIPTION

[0030] The present invention is further described below in conjunction with embodiments and drawings.

[0031] like Figure 1 As shown, the present invention provides a method for optimizing integrated circuit ion implantation process parameters, comprising the following steps:

[0032] Step S1, using the process module (Sentaurus Process) of Sentaurus TCAD software to simulate the front-end process of the CMOS device, the CMOS device includes NMOS (N-type metal oxide semiconductor) and PMOS (P-type metal oxide semiconductor), the simulation steps are as follows:

[0033] (1) Substrate initialization

[0034] choose <100> The silicon substrate is crystalline <100> The silicon with the lowest interface defect density is conducive to the growth of a good quality oxide layer on its surface. The doping concentration is 1.0×10 15 cm -3The boron ion impurities form a P-type bare chip with a resistivity of about 10.0Ω·cm. The initial substrate thickness is defined as 4μm and the width is defined as 0.5μm.

[0035] (2) Forming Shallow Trench Isolation (STI)

[0036] A layer of silicon dioxide (SiO2) film is grown on the surface of the substrate by dry oxygen oxidation at 1050°C as a pre-oxidation layer (Pad-Oxide Layer) to relieve the stress between the subsequently deposited silicon nitride (Si3N4) hard mask and the substrate. Then an anisotropically deposited layer Si3N4 is used as a hard mask (blocking layer) for etching the active area.

[0037] In the STI region, Si3N4 and SiO2 are anisotropically overetched. Then the trapezoidal etching depth is The trench angle is 85° for silicon, forming a shallow trench. To ensure a high-quality surface and reduce the number of trap states, the substrate is wet-oxidized at 1050°C. Then isotropic deposition is performed SiO2 is etched to -0.02μm using CMP. Finally, the surface Si3N4 is removed to form an STI structure. The structural schematic diagrams of the NMOS device and the PMOS device are shown in the figure below. Figure 2 (a) and Figure 3 (a) shown.

[0038] (3) P / N-type well injection

[0039] Before ion implantation in the well region, a thin oxide layer needs to be deposited as a sacrificial oxide layer to prevent the channel effect of ion implantation in the well region. For NMOS devices, the P well region is first implanted with an energy of 7.5keV and a dose of 6.00×10 12 cm -2 Boron is used to adjust the threshold voltage of NMOS devices; the re-implantation energy is 110keV and the dose is 7.0×10 12 cm -2 Boron is used to adjust the doping concentration in the channel to prevent leakage from the source and drain of the device; finally, the injection energy is 215keV and the dose is 3.1×10 13 cm -2 Boron is used to adjust the P-well concentration, reduce the P-well resistance, and prevent latch-up. For PMOS devices, the N-well region is first implanted with an energy of 34keV and a dose of 1.00×10 12 cm -2Phosphorus is used to adjust the threshold voltage of the PMOS device; the re-injection energy is 200keV and the dose is 5.9×10 12 cm -2 Phosphorus is used to adjust the doping concentration in the channel region to make the depletion region narrower when the device is working; finally, the injection energy is 370keV and the dose is 3.6×10 13 cm -2 Phosphorus to change the N-well concentration, reduce the N-well resistance and weaken the latch-up effect.

[0040] Finally, annealing is performed at 1000°C in an inert gas for 10 seconds to push the doped ions to a suitable depth. At the same time, annealing can activate the doped ions and repair the lattice damage caused by ion implantation. Finally, the isolation oxide layer is removed. The device structure after annealing of P-well and N-well implantation is as follows: Figure 2 (b) and Figure 3 (b) as shown.

[0041] (4) Growth of gate oxide and polysilicon gate

[0042] In an atmosphere of N2O and H2, a layer of oxide film is grown at 1000°C as a gate oxide layer, and then isotropically deposited at 500°C. For NMOS, the injection energy is 5keV and the dose is 2.9×10 15 cm -2 Phosphorus precisely dopes polysilicon. Anisotropic etching outside the Poly region The polysilicon is then anisotropically etched away. Finally, the polysilicon is thermally oxidized in a low-oxygen environment at 900°C to form a thin oxide layer as a buffer layer for Si3N4. At the same time, the polysilicon doping can be activated, surface etching damage can be repaired, and stress can be relieved.

[0043] (5) Growth of the first offset spacer

[0044] A layer of Si3N4 isotropically deposited as the isolation layer of the first layer of sidewall, and then anisotropically etched to remove the Si3N4 on the gate surface and active area to form the first layer of thin gate sidewall to reduce the overlap between the gate and the source and drain active areas, and also determine the effective length of the channel. The device structure of NMOS and PMOS devices after polysilicon growth is shown in Figure 1. Figure 2 (c) and Figure 3 (c) as shown.

[0045] (6) LDD ion implantation

[0046] For NMOS devices, the implantation dose in the active region is 3.0×10 14 cm -2 , Germanium ions with an energy of 12keV to amorphize the surface and avoid channeling. Then the implantation dose is 8.2×10 14 cm -2 Arsenic ions with an energy of 3 keV can effectively improve the drain barrier lowering effect and hot carrier injection effect. For PMOS devices, the active region is first injected with an energy of 4 keV and a dose of 3.87×10 14 cm -2 Germanium, then the dose is 6.0×10 14 cm -2 , BF2 with an injection energy of 3.5keV.

[0047] (7)Halo ion implantation

[0048] First, the active area was rotated horizontally four times with an implant energy of 6.5 keV and a dose of 6.0×10 13 cm -2 , a Boron with a tilt angle of 30° and a rotation angle of 45°, and then rotated horizontally in the active area for 4 times with an injection energy of 45 keV and a dose of 1.9×10 13 cm -2 , indium ions with an inclination angle of 30° and a rotation angle of 45° form the Halo structure of NMOS. The Halo structure of PMOS is similar, but the doping recipe is different. The Halo structure can effectively prevent the source and drain depletion regions from extending into the channel region, thereby eliminating the charge sharing effect, inhibiting the source and drain crosstalk phenomenon, reducing leakage current, enhancing gate control performance, and reducing threshold voltage.

[0049] Finally, a spike thermal annealing is performed at 1000°C to repair the lattice damage and activate the implanted ions. The device structures of NMOS and PMOS devices after LDD ion implantation and Halo ion implantation are shown in Figure 1. Figure 2 (d) and Figure 3 (d) as shown.

[0050] (8) Growth of the second layer of sidewalls and source and drain ion implantation

[0051] First, a layer of isotropically deposited Si3N4, then anisotropically etched Si3N4 is used to form thick gate sidewalls to block the injection of heavily doped source and drain ions, protect the LDD structure, and then the SiO2 on the surface is anisotropically etched away.

[0052] Isotropically deposit a layer SiO2 is used as a protective layer for source and drain ion implantation. First, a dose of 2.0×10 13 cm -2 , Phosphorus with energy of 25 keV, and then implanted with a dose of 3.8×10 15 cm -2 , Arsenic with energy of 35keV, and finally the injection dose of 8.9×10 14 cm -2 , Phosphorus with energy of 7keV to form heavily doped NMOS source and drain. The process of forming PMOS source and drain is similar to the above, except that the oxide layer before source and drain ion implantation is thinner to dope the polysilicon at the same time. Finally, spike thermal annealing is performed at 1000℃. The device structures of NMOS and PMOS devices after source and drain ion implantation are shown in the figure. Figure 2 (e) and Figure 3 (e) as shown.

[0053] (9) Metal silicide forms source-drain contacts

[0054] The SiO2 on the surface is removed by isotropic etching and anisotropic etching, and then selective isotropic etching is performed. of silicon, and then isotropically deposit a layer of NickelSilicide, and finally annealing to relieve stress. The final NMOS and PMOS device structures are as follows Figure 2 (f) and Figure 3 (f) as shown.

[0055] In the above step (7), key process parameters such as implantation dose, implantation energy and implantation angle are adjusted respectively to perform process modeling to obtain different simulation devices.

[0056] Step S2: using the device module (Sentaurus Device) of the Sentaurus TCAD software to perform numerical solution on the simulated CMOS device obtained in step S1.

[0057] Solving a simulated device can be considered as a virtual measurement of its electrical properties. During this process, the device is meshed into a finite element structure, and each mesh point contains data such as material type and doping concentration.

[0058] In the Sdevice tool, when solving the NMOS device, the substrate and source voltages are set to 0V, the drain voltage is 1.2V, and the gate voltage V gs=0.05V and 1.2V, the device is numerically solved for quasi-static conditions to obtain the voltage transfer characteristics when it works in the linear region and the saturation region, respectively. The unit of the implanted dose is cm -2 , the unit of injection energy is keV, the unit of injection angle (tilt) is °, the same as below. For the PMOS device, the substrate and source voltages are set to 0V, the drain voltage is -1.2V, and when the gate voltage V gs =-0.05V and -1.2V, the device is numerically solved to obtain its voltage transfer characteristics in the linear region and saturation region. Finally, all the solved simulation device data results are exported as cvs files for the construction of training data sets.

[0059] Step S3: preprocessing the process parameters and electrical data and constructing a data set:

[0060] Use statistical methods or rule-based algorithms to detect and remove outliers and noise in the data set to improve the accuracy of the model. For missing data, use the mean filling method or the interpolation method based on similar samples. During the training process of the neural network model, the loss function is optimized by the gradient descent method. Unstandardized data may have different dimensions and ranges, which will lead to inconsistent step sizes when updating weights, thereby affecting the convergence speed of the model. The standardized data have the same dimensions and range, which can make the gradient descent method converge faster and more stably. The method of the present invention performs Z-score standardization on the data set and converts it into a standard normal distribution with a mean of 0 and a standard deviation of 1.

[0061] Finally, the dataset is divided into training set, validation set, and test set in a ratio of 5:3:2 to evaluate model performance and prevent overfitting.

[0062] Step S4: construct a residual neural network model, use the data set to train, verify and test the residual neural network model, and optimize the residual neural network model parameters; the input of the model is energy, tilt, dose, V th , SS, I dsat ,I off , G m , R lin and R sat , the output is energy, tilt, and dose.

[0063] The present invention adopts the ResNet18 model, whose structure is as follows Figure 4 As shown in Figure 2, the ResNet18 model consists of five sequentially connected modules, including 17 convolutional layers and 1 fully connected layer.

[0064] Module 1 contains a 7x7 convolutional layer for extracting preliminary features. This is followed by a batch normalization layer to speed up the training process and improve the stability of the model. This is followed by a 3x3 max pooling layer with a step size of 2 to reduce the size of the feature map, thereby reducing the amount of computation and extracting more abstract features.

[0065] Module 2 consists of two residual blocks, each of which contains two 3x3 convolutional layers and a batch normalization layer, and uses the ReLU activation function. These residual blocks do not contain 1x1 convolutional layers, and directly add the input and output through skip connections to form residual connections.

[0066] Module 3: Contains a residual block with a 1x1 convolutional layer and a residual block without a 1x1 convolutional layer connected in series. The 1x1 convolutional layer of the first residual block is used to adjust the number of channels so that the input matches the output, ensuring the feasibility of the skip connection.

[0067] Module 4: The structure is the same as module 3, which contains a residual block with a 1x1 convolution layer and a residual block without a 1x1 convolution layer connected in series. This design further enhances the expressiveness of the model while maintaining the efficiency of gradient transfer through the residual connection.

[0068] Module 5: It also contains a residual block with a 1x1 convolution layer and a residual block without a 1x1 convolution layer connected in series. This configuration enables the model to extract high-level features at deeper levels and continue to alleviate the gradient vanishing problem through residual connections.

[0069] In the last part, the Global Average Pooling Layer performs global average pooling on each feature map, shrinking each feature map to a size of 1x1, thereby aggregating all features. This pooling method effectively reduces the number of parameters, avoids overfitting, and retains important information in the feature map. Then, through a fully connected layer, the pooled features are input into the classifier or regressor to output the final prediction result.

[0070] The hyperparameter settings in model training are shown in Table 1.

[0071] Table 1 Model training hyperparameter settings

[0072] batch_size learning_rate epoch k_fold weight_decay 128 1e-4 30 5 1e-3

[0073] In the model training process, K-fold cross validation is used by th , SS, I dsat ,I off , G m , R lin and R sat The entire parameter data set is divided into K equal-sized subsets (folds), and each subset is used cyclically as a validation set, and the remaining K-1 subsets are used as training sets to ensure that each data point is used once in the training set and the validation set, reducing the deviation caused by data division. Finally, the results of all K validations are averaged to obtain a comprehensive performance evaluation of the model.

[0074] The optimization algorithm uses Adam (Adaptive Moment Estimation), which can dynamically adjust the learning rate for each parameter, making parameter updates more efficient. In addition, compared with other optimization algorithms, such as SGD (stochastic gradient descent), Adam is insensitive to the choice of hyperparameters, is more robust, and can achieve fast and robust convergence when training deep neural networks. The Adam optimization algorithm calculates the first-order moment (mean) and second-order moment (variance) of the gradient and uses these moment estimates to update the parameters. Its update algorithm is shown in the following formula (1):

[0075]

[0076] Among them, g t is the gradient, α is the learning rate, β1 and β2 are the exponential decay rates of the first and second order moments, respectively. and They represent the decay degree of momentum of β1 and β2 after the tth iteration, ∈ is a small constant used to prevent division by zero error; m t and v t are the first-order and second-order moment estimates, and They are m t and v t Bias correction, θ t represents the model parameters after the tth iteration, θ t+1 Represents the model parameters after the t+1th iteration.

[0077] The loss function uses the cross entropy loss function (CrossEntropyLoss), as shown in formula (2), to measure the difference between the model prediction and the true label, that is, first perform a Softmax transformation on the input, and then calculate the negative log-likelihood loss.

[0078]

[0079] Among them, N is the number of training samples, y i is the one-hot encoding of the true label, is the model’s predicted probability for the i-th class.

[0080] Through the above method, the model continuously adjusts parameters in each iteration and gradually approaches the optimal solution. The accuracy results of the training process are as follows: Figure 5 As shown in the figure, the training accuracy is as high as 95%, and the test set accuracy exceeds 90%. After multiple rounds of K-fold cross-validation and parameter optimization, the model can stably output the optimal ion implantation energy, tilt, dose and other process recipes under the expected electrical parameters, thereby accelerating the process development process and improving device performance and manufacturing yield.

Claims

1. A method for optimizing integrated circuit ion implantation process parameters, characterized in that: The method comprises the following steps: Step S1, using the process simulation module of Sentaurus TCAD software to simulate the front-end process of the CMOS device, the front-end process includes the following steps: substrate initialization, shallow trench isolation formation, P / N type well implantation, gate oxide and polysilicon gate growth, first layer sidewall growth, LDD ion implantation, Halo ion implantation, second layer sidewall growth and source and drain ion implantation, metal silicide forming source and drain contact; changing the process parameters in the Halo ion implantation step to obtain a simulated CMOS device; Step S2, using the device simulation module of Sentaurus TCAD software to obtain the electrical data of the simulated CMOS device obtained in step S1; Step S3, preprocessing the process parameters and electrical data and constructing a data set, which is then divided into a training set, a validation set, and a test set; Step S4: construct a residual neural network model, use the data set to train, verify and test the residual neural network model, and output the optimized process parameters.

2. The method for optimizing integrated circuit ion implantation process parameters according to claim 1, characterized in that: The process parameters include implantation angle, implantation energy and implantation dose.

3. The method for optimizing integrated circuit ion implantation process parameters according to claim 1, characterized in that: The electrical data includes the device threshold voltage V th , subthreshold voltage swing SS, saturation current I dsat , leakage current I off , Maximum transconductance G m , linear region resistance R lin And the saturation resistance R sat .

4. The method for optimizing integrated circuit ion implantation process parameters according to claim 1, characterized in that: The residual neural network model adopts the ResNet18 model.

5. The method for optimizing integrated circuit ion implantation process parameters according to claim 1, characterized in that: Step S2 specifically obtains electrical data by solving the electrical properties of the simulated CMOS device based on a physical model, wherein the physical model includes a carrier transport model, a density gradient model, a drift-diffusion model, a mobility model, an inversion layer and accumulation layer mobility model, a high field velocity saturation model, a Shockley-Read-Hall composite model, and an avalanche breakdown model.

6. An integrated circuit ion implantation process parameter optimization system for implementing the method according to any one of claims 1 to 5, characterized in that: Includes the following modules: Data simulation module, used to simulate the manufacturing process of CMOS devices and obtain electrical data and process parameters; Data preprocessing module, used to preprocess electrical data and process parameters; The parameter optimization module inputs the preprocessed electrical data and process parameters into the optimized residual neural network model to obtain the optimized process parameters.

7. An electronic device, characterized in that: The invention comprises a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement the method according to any one of claims 1 to 5.

8. A machine-readable storage medium, characterized in that: The machine-readable storage medium stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the method described in any one of claims 1 to 5.

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