A method for optimizing ion implantation process parameters for integrated circuits

Abstract

The application discloses a method for optimizing ion implantation process parameters of integrated circuits, comprising the following steps: simulating the front-end process of a CMOS device by using Sentaurus Process of Sentaurus TCAD software, changing the process parameters in the Halo ion implantation step, and obtaining a simulation CMOS device; then numerically solving the electrical properties of the simulation CMOS device by using Sentaurus Device in the software, and obtaining electrical data; training, verifying and testing a residual neural network model by using the process parameters and the electrical data, optimizing the residual neural network model parameters, and finally obtaining optimized process parameters. The method not only improves the optimization efficiency and precision of ion implantation process parameters, but also realizes the automation and intelligentization of process optimization through the combination of deep learning algorithm and TCAD simulation technology.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor technology, and particularly relates to a method for optimizing ion implantation process parameters of integrated circuits. BACKGROUND

[0002] Ion implantation technology is a semiconductor doping process that began to develop in the 1960s. In the production and manufacturing process of integrated circuits, many doping processes use ion implantation technology. For example, in the preparation process of Silicon-On-Insulator (SOI) material, a buried oxide layer is usually formed by high-energy and high-concentration oxygen ion implantation; in the isolation process of integrated circuits, channel stop technology is used to prevent parasitic channels; channel doping is used to adjust the threshold voltage; ion implantation is also used to form the well and source-drain regions of N-type and P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices, thereby forming CMOS (Complementary Metal Oxide Semiconductor) devices; and doping of shallow junctions, etc. This series of key processes all rely on ion implantation technology.

[0003] However, the traditional CMOS ion implantation process has many limitations. The adjustment and optimization of process parameters usually require a long experimental period and high testing costs, and the establishment of ion implantation process recipe (i.e. process parameters) highly depends on the experience of engineers and physical theoretical formulas. With the development of integrated circuits towards higher integration, smaller size and more complex structure, these traditional methods are difficult to meet the increasingly strict manufacturing standards. For example, as the size of the doped region decreases, the channel effect and scattering phenomenon in the ion implantation process become more complex, and the requirement for the precision of process control is higher and higher.

[0004] Therefore, there is an urgent need for a method that can achieve more precise process control. SUMMARY

[0005] The first object of the present application is to provide a method for optimizing ion implantation process parameters of integrated circuits to overcome the shortcomings of the prior art. By using Sentaurus TCAD software to model, simulate and extract electrical parameters of MOSFET logic devices, a large-scale ion implantation and device electrical property parameter dataset is constructed, and a neural network algorithm model is combined to realize the rapid iterative optimization of ion implantation process recipe, which helps to improve the functional performance, yield and stability of the device, speeds up the device development speed, and promotes the application and development of intelligent manufacturing technology in the field of integrated circuit manufacturing.

[0006] To achieve the above object, the present application adopts the following technical solutions:

[0007] Step S1, simulating the front-end process of the CMOS device by using the process simulation module (Sentaurus Process) of the Sentaurus TCAD software, the front-end process including the following steps: substrate initialization, forming shallow trench isolation, P / N type well implantation, growing gate oxide and polysilicon gate, growing the first layer of side wall, LDD (Lightly Doped Drain) ion implantation, Halo ion implantation, growing the second layer of side wall and source-drain ion implantation, metal silicide forming source-drain contact; changing the process parameters in the Halo ion implantation step to obtain a simulation CMOS device;

[0008] Step S2, solving the electrical properties of the simulation CMOS device obtained in step S1 by using the device simulation module (Sentaurus Device) of the Sentaurus TCAD software to obtain electrical data;

[0009] Step S3, preprocessing the process parameters and electrical data and constructing a data set, and then dividing it into a training set, a validation set and a test set;

[0010] Step S4, constructing a residual neural network model, training, validating and testing the residual neural network model by using the data set, and outputting the optimized process parameters.

[0011] Further, the process parameters include implantation angle, implantation energy and implantation dose.

[0012] Further, the electrical data includes device threshold voltage (V th ), sub-threshold voltage swing (SS), saturation current (I dsat ), leakage current (I off ), maximum transconductance (G m ), linear region resistance (R lin ) and saturation region resistance (R sat ).

[0013] Further, the residual neural network model adopts a ResNet18 model.

[0014] Further, the step S2 solves the electrical property based on a physical model, the physical model including a carrier transport model, a density gradient model, a drift-diffusion model, mobility models, inversion and accumulation layer mobility models, high-field saturation models, a SRH (Shockley-Read-Hall) recombination model, and an avalanche model.

[0015] A second object of the present application is to provide an integrated circuit ion implantation process parameter optimization system implementing the above method, comprising the following modules:

[0016] A data simulation module is configured to simulate a manufacturing process of a CMOS device to obtain electrical data and process parameters.

[0017] A data preprocessing module is configured to preprocess the electrical data and the process parameters.

[0018] A process parameter optimization module is configured to input the preprocessed electrical data and the process parameters into an optimized residual neural network model to obtain optimized process parameters.

[0019] A third object of the present application is to provide an electronic device comprising a processor and a memory, wherein the memory stores machine executable instructions capable of being executed by the processor, and the processor executes the machine executable instructions to implement the above method.

[0020] A fourth object of the present application is to provide a machine readable storage medium storing machine executable instructions, wherein the machine executable instructions, when invoked and executed by a processor, cause the processor to implement the above method.

[0021] Compared with the prior art, the present application has the following advantages:

[0022] The present application can quickly and automatically optimize process parameters in a virtual environment through TCAD simulation, greatly reducing the experimental cycle and test cost, and combining a deep learning model, the process parameters can be optimized with high precision under complex conditions, the fine requirements of process control can be realized, and multiple optimization iterations can be quickly completed, greatly accelerating the device development speed and shortening the product market time.

[0023] The method of the present application can improve the functional performance, yield and stability of devices through the optimization of process recipe by a deep learning model. Through learning and analysis of a large amount of simulation data, the neural network model can identify the optimal combination of process parameters, avoiding errors caused by insufficient human experience or inaccurate physical theory formulas.

[0024] The method of the present application not only improves the optimization efficiency and accuracy of ion implantation process, but also promotes the application of intelligent manufacturing technology in the field of integrated circuit manufacturing. Through the combination of deep learning algorithm and TCAD simulation technology, the automation and intelligentization of process optimization are realized, providing a new technical means for integrated circuit intelligent manufacturing. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 The flowchart of the present application.

[0026] Figure 2 (a) to (f) are respectively the process simulation device process schematic diagram of NMOS process flow.

[0027] Figure 3 (a) to (f) are respectively the process simulation device process schematic diagram of PMOS process flow.

[0028] Figure 4 The structure diagram of the residual neural network model of the present application.

[0029] Figure 5 The model training process precision result of the present application. DETAILED DESCRIPTION

[0030] The present application will be further described below in combination with examples and drawings.

[0031] As shown in the figure, the present application provides a method for optimizing ion implantation process parameters of integrated circuits, comprising the following steps: Figure 1

[0032] Step S1, using the process module (Sentaurus Process) of Sentaurus TCAD software to simulate the front-end process of CMOS device, the CMOS device includes NMOS (N-type metal oxide semiconductor) and PMOS (P-type metal oxide semiconductor), the simulation steps are as follows:

[0033] (1) Substrate initialization

[0034] Silicon with <100> crystal orientation is selected as the substrate, because silicon with <100> crystal orientation has the smallest interface defect density, which is beneficial to grow a good quality oxide layer on its surface. The doping concentration is 1.0×10 15 cm -3 ​Boron ion impurities form a P-type die with a resistivity of approximately 10.0 Ω·cm. The initial substrate thickness is defined as 4 μm and the width as 0.5 μm.

[0035] (2) Shallow Trench Isolation (STI)

[0036] A silicon dioxide (SiO2) film is grown on the substrate surface at 1050℃ using dry oxidation as a pad-oxide layer to alleviate stress between the subsequently deposited silicon nitride (Si3N4) hard mask and the substrate. Then, an anisotropic layer is deposited. Si3N4 is used as a hard mask (barrier layer) for etching the active region.

[0037] Anisotropic overetching of Si3N4 and SiO2 was performed in the STI region, respectively. Then, a trapezoidal etching depth of [insert depth here]. Silicon with a trench angle of 85° is used to form shallow trenches. To ensure high-quality surface growth and reduce the number of trapped states, the substrate is subjected to wet oxygen oxidation at 1050°C. Then, isotropic deposition is performed. The SiO2 was etched to a depth of -0.02 μm using CMP. Finally, the surface Si3N4 was removed to form an STI structure. Schematic diagrams of the NMOS and PMOS devices are shown below. Figure 2 (a) and Figure 3 As shown in (a).

[0038] (3) P / N type trap injection

[0039] Before ion implantation in the well region, a thin oxide layer needs to be deposited as a sacrificial oxide layer to prevent channeling effects during well ion implantation. For NMOS devices, an implantation energy of 7.5 keV and a dose of 6.00 × 10⁻⁶ are first performed in the P-well region. 12 cm -2 Boron was used to adjust the threshold voltage of the NMOS device; the re-injection energy was 110 keV and the dose was 7.0 × 10⁻⁶. 12 cm -2 Boron is used to adjust the doping concentration in the channel to prevent source-drain punch-through and leakage current in the device; finally, four horizontal rotations are performed with an injection energy of 215 keV and a dose of 3.1 × 10⁻⁶. 13 cm -2 Boron is used to adjust the P-well concentration, reduce the P-well resistance, and prevent latch-up. For PMOS devices, an energy of 34 keV and a dose of 1.00 × 10⁻⁶ are first implanted into the N-well region. 12 cm -2Phosphorus to adjust the threshold voltage of the PMOS device; the last implantation is 370 keV, 3.6 x 10 12 cm -2 of Phosphorus to adjust the channel doping concentration, to make the device work with a narrower depletion region; the last implantation is 370 keV, 3.6 x 10 13 cm -2 of Phosphorus to change the N-well concentration, to reduce the N-well resistance and to weaken the latch-up effect.

[0040] Finally, annealing at 1000°C for 10 seconds in an inert gas to drive the dopant ions to the proper depth, and to activate the dopant ions and to repair the lattice damage caused by the ion implantation. The isolation oxide layer is removed. The device structure after the P-well and N-well implantation and annealing is shown in Figure 2 (b) and Figure 3 (b).

[0041] (4) Growth of Gate Oxide and Polysilicon Gate

[0042] Growth of a thin oxide film as the gate oxide layer at 1000°C in a gas atmosphere of N2O and H2, followed by isotropic deposition of Polysilicon at 500°C. For NMOS, an implantation of 5 keV, 2.9 x 10 15 cm -2 of Phosphorus is needed to precisely dope the polysilicon. The polysilicon outside the poly region is etched anisotropically , and the surface oxide layer is etched anisotropically. Finally, the polysilicon is thermally oxidized at 900°C in a low-oxygen environment to form a thin oxide layer as a buffer layer for Si3N4, and to activate the polysilicon doping, to repair the surface etching damage and to relieve the stress.

[0043] (5) Growth of the First Offset Spacer

[0044] Isotropic deposition of a layer of Si3N4 as the isolation layer of the first offset spacer, followed by anisotropic etching to remove the Si3N4 on the surface of the gate and the active region to form the first thin gate offset spacer, to reduce the overlap between the gate and the source / drain active region, and to determine the effective length of the channel. The device structure after the growth of the polysilicon for NMOS and PMOS devices is shown in Figure 2 (c) and Figure 3 (c).

[0045] (6) LDD Ion Implantation

[0046] For NMOS devices, the implantation dose in the active region is 3.0 × 10⁻⁶. 14 cm -2 Germanium ions with an energy of 12 keV are introduced to amorphize the surface and avoid channeling effects. Then, a dose of 8.2 × 10⁻⁶ is implanted. 14 cm -2 Arsenic ions with an energy of 3 keV can effectively improve the leakage-induced barrier reduction effect and the hot carrier injection effect. For PMOS devices, arsenic ions with an energy of 4 keV and a dose of 3.87 × 10⁻⁶ are first injected into the active region. 14 cm -2 Germanium, then at a dose of 6.0 × 10 14 cm -2 BF2 with an injection energy of 3.5 keV was injected.

[0047] (7) Halo ion implantation

[0048] First, the active region was horizontally rotated four times, with an injection energy of 6.5 keV and a dose of 6.0 × 10⁻⁶. 13 cm -2 A Boron with a tilt angle of 30° and a rotation angle of 45° was then horizontally rotated four times in the active region, injecting an energy of 45 keV and a dose of 1.9 × 10⁻⁶. 13 cm -2 Indium ions with a tilt angle of 30° and a rotation angle of 45° form the Halo structure of NMOS. The Halo structure of PMOS is similar, but the doping recipe is different. The Halo structure can effectively prevent the extension of the source-drain depletion region into the channel region, thereby eliminating the charge sharing effect, suppressing source-drain crosstalk, reducing leakage current, enhancing gate control performance, and lowering the threshold voltage.

[0049] Finally, peak thermal annealing at 1000℃ was performed to repair lattice damage and activate the implanted ions. The device structures after LDD ion implantation and Halo ion implantation for NMOS and PMOS devices are shown below. Figure 2 (d) and Figure 3 As shown in (d).

[0050] (8) Growth of the second sidewall and source / drain ion implantation

[0051] First, an isotropic layer is deposited. Si3N4, then anisotropically etched Si3N4 is used to form thick sidewalls for the gate to block the implantation of heavily doped ions from the source and drain, thus protecting the LDD structure. Then, the SiO2 on the surface is anisotropically etched away.

[0052] An isotropic layer is deposited SiO2 was used as a protective layer for source and drain ion implantation. First, an implantation dose of 2.0 × 10⁻⁶ was applied to the active region. 13 cm -2 Phosphorus with an energy of 25 keV, followed by an injection of a dose of 3.8 × 10⁻⁶. 15 cm -2 Arsenic with an energy of 35 keV was injected, followed by a final dose of 8.9 × 10⁻⁶. 14 cm -2 A 7keV Phosphorus is used to form heavily doped NMOS source / drain devices. The PMOS source / drain formation process is similar, except that the oxide layer is thinner before source / drain ion implantation to simultaneously dope the polysilicon. Finally, a peak thermal annealing at 1000℃ is performed. The device structures of the NMOS and PMOS devices after source / drain ion implantation are as follows. Figure 2 (e) and Figure 3 As shown in (e).

[0053] (9) Metal silicide formation source and drain contacts

[0054] The SiO2 on the surface is completely removed by isotropic and anisotropic etching, followed by selective isotropic etching. Silicon, then an isotropic layer is deposited. Nickel Silicide was applied, followed by stress relief through annealing. The final NMOS and PMOS device structures are as follows: Figure 2 (f) and Figure 3 As shown in (f).

[0055] In step (7) above, the key process parameters such as injection dose, injection energy and injection angle are adjusted respectively to obtain different simulation devices through process modeling.

[0056] Step S2: Use the Sentaurus Device module of the Sentaurus TCAD software to perform numerical solutions on the simulated CMOS device obtained in Step S1.

[0057] Solving for a simulated device can be regarded as a virtual measurement of its electrical properties. In this process, the device is meshed into a finite element structure, and each mesh point contains data such as material type and doping concentration.

[0058] In the Sdevice tool, when solving for an NMOS device, the substrate and source voltages are set to 0V, and the drain voltage is 1.2V. When the gate voltage V... gs= 0.05V and 1.2V, respectively, the device is subjected to quasi-static numerical solution to obtain the voltage transfer characteristics when it works in the linear region and the saturation region, wherein the unit of the injection dose is cm -2 , the unit of the injection energy is keV, and the unit of the injection angle is °, as follows. The substrate and the source voltage of the PMOS device are set to 0V, and the drain voltage is -1.2V. When the gate voltage V gs = -0.05V and -1.2V, respectively, the device is subjected to numerical solution to obtain the voltage transfer characteristics when it works in the linear region and the saturation region. Finally, all the simulation device data results are exported as a cvs file for the construction of a data set.

[0059] Step S3, preprocessing the process parameters and electrical data and constructing a data set:

[0060] The statistical method or rule-based algorithm is used to detect and remove outliers and noise in the data set, so as to improve the accuracy of the model. For missing data, the mean filling method or the interpolation method based on similar samples is used. In the training process of the neural network model, the gradient descent method is used to optimize the loss function. The data that has not been standardized may have different dimensions and ranges, which may cause the step length of weight update to be inconsistent, thereby affecting the convergence speed of the model. The standardized data has the same dimension and range, which can make the gradient descent method converge faster and more stably. The method of the application performs Z-score standardization on the data set, and converts it to a standard normal distribution with a mean of 0 and a standard deviation of 1.

[0061] Finally, the data set is divided into a training set, a validation set and a test set in a ratio of 5:3:2, so as to evaluate the model performance and prevent overfitting.

[0062] Step S4, constructing a residual neural network model, training, verifying and testing the residual neural network model by using the data set, and optimizing the parameters of the residual neural network model; the input of the model is energy, tilt, dose, V th , SS, I dsat , I off , G m , R lin and R sat , and the output is energy, tilt and dose.

[0063] The application adopts a ResNet18 model, and the structure thereof is shown in Figure 4 The ResNet18 model is composed of five sequentially connected modules, including 17 convolutional layers and one fully connected layer.

[0064] Module 1 contains a 7x7 convolutional layer to extract initial features. This is followed by a batch normalization layer to speed up the training process and improve the stability of the model. Then there is a 3x3 max pooling layer with a stride of 2 to reduce the size of the feature maps, thereby reducing the computational load and extracting more abstract features.

[0065] Module 2 consists of two residual blocks, each containing two 3x3 convolutional layers and batch normalization layers, with ReLU activation functions. These residual blocks do not contain 1x1 convolutional layers, but directly add the input and output through a skip connection, forming a residual connection.

[0066] Module 3: Contains a residual block with a 1x1 convolutional layer and a residual block without a 1x1 convolutional layer connected in series. The 1x1 convolutional layer of the first residual block is used to adjust the number of channels, so that the input and output are matched to ensure the feasibility of the skip connection.

[0067] Module 4: The structure is the same as module 3, containing a residual block with a 1x1 convolutional layer and a residual block without a 1x1 convolutional layer connected in series. This design further enhances the expressive power of the model, while maintaining the efficiency of gradient transmission through residual connections.

[0068] Module 5: Also contains a residual block with a 1x1 convolutional layer and a residual block without a 1x1 convolutional layer connected in series. This configuration allows the model to extract high-level features at a deeper level and continues to alleviate the gradient vanishing problem through residual connections.

[0069] The final part first uses a global average pooling layer to perform global average pooling on each feature map, reducing each feature map to 1x1 size, thereby aggregating all features. This pooling method effectively reduces the number of parameters, avoids overfitting, and preserves important information in the feature map. Then a fully connected layer is used to input the pooled features into a classifier or regressor, outputting the final prediction result.

[0070] The hyperparameter settings in model training are shown in Table 1.

[0071] Table 1 Model training hyperparameter settings

[0072] batch_size learning_rate epoch k_fold weight_decay 128 1e-4 30 5 1e-3

[0073] During the model training process, K-fold cross-validation is used, by dividing the entire dataset containing energy, tilt, dose, V th , SS, I dsat , I off , G m , R lin and R sat parameters into K equal size subsets (folds), each subset is used as the validation set cyclically, and the remaining K-1 subsets are used as the training set, ensuring that each data point is used once in the training set and the validation set, reducing the bias caused by data division. Finally, the results of all K validations are averaged to get the comprehensive performance evaluation of the model.

[0074] The optimization algorithm uses Adam (Adaptive Moment Estimation), which can dynamically adjust the learning rate for each parameter, making parameter updates more efficient. In addition, compared with other optimization algorithms such as SGD (Stochastic Gradient Descent), Adam is not sensitive to the selection of hyperparameters, and performs more stably, enabling fast and stable convergence when training deep neural networks. Adam optimization algorithm calculates the first moment (mean) and second moment (variance) of the gradient, and uses these moment estimates to update the parameters. Its update algorithm is shown in the following formula (1):

[0075]

[0076] where g t is the gradient, α is the learning rate, β1 and β2 are the exponential decay rates of the first and second moments, and respectively represent the degree of momentum decay of β1 and β2 after the tth iteration, ∈ is a small constant to prevent division by zero error; m t and v t are the first and second moment estimates, and are the bias corrections of m t and v t , θ t represents the model parameters after the tth iteration, and θ t+1 represents the model parameters after the (t+1)th iteration.

[0077] The loss function uses the cross-entropy loss function (CrossEntropyLoss) as shown in formula (2) to measure the difference between the model prediction and the true label, that is, first perform Softmax transformation on the input, then calculate the negative log-likelihood loss.

[0078]

[0079] where N is the number of training samples, y i is the one-hot encoding of the true label, is the predicted probability of the model for the i-th class.

[0080] Through the above method, the model continuously adjusts the parameters in each iteration, gradually approaching the optimal solution. The training process accuracy results are shown in Figure 5 , with a training accuracy of up to 95% and a test set accuracy of over 90%. After multiple rounds of K-fold cross-validation and parameter optimization, the model can stably output the optimal ion implantation energy, tilt, and dose, etc. process recipe under the expected electrical parameters, thereby speeding up the process development process and improving device performance and manufacturing yield.

Claims

1. A method of optimizing ion implantation process parameters for integrated circuits, characterized by, The method comprises the following steps: Step S1, simulating the front-end process of the CMOS device by using the process simulation module of the Sentaurus TCAD software, the front-end process comprising the following steps: substrate initialization, shallow trench isolation formation, P / N type well implantation, gate oxide and polysilicon gate growth, first layer side wall growth, LDD ion implantation, Halo ion implantation, second layer side wall growth and source-drain ion implantation, and metal silicide formation source-drain contact; changing the process parameters in the Halo ion implantation step to obtain a simulation CMOS device; the process parameters are implantation angle, implantation energy and implantation dose; Step S2, obtaining electrical data of the simulated CMOS device obtained in step S1 by using a device simulation module of Sentaurus TCAD software; the electrical data are device threshold voltage V th , subthreshold voltage swing SS, saturation current I dsat , leakage current I off , maximum transconductance G m , linear region resistance R lin and saturation region resistance R sat ; Step S3, preprocessing the process parameters and electrical data and constructing a data set, Z-score standardizing the data set to convert it into a standard normal distribution with a mean of 0 and a standard deviation of 1, and then dividing it into a training set, a validation set and a test set; Step S4, constructing a residual neural network model, training, validating and testing the residual neural network model using the data set, and outputting the optimized process parameters in the Halo ion implantation step; the residual neural network model uses a ResNet18 model, the input is electrical data, and the output is the process parameters in the Halo ion implantation step.

2. The method of optimizing integrated circuit ion implant process parameters according to claim 1, wherein, Step S2 is specifically based on a physical model to solve the electrical properties of the simulation CMOS device to obtain electrical data, the physical model including a carrier transport model, a density gradient model, a drift-diffusion model, a mobility model, a inversion layer and accumulation layer mobility model, a high field velocity saturation model, a Shockley-Read-Hall recombination model and an avalanche breakdown model.

3. An integrated circuit ion implantation process parameter optimization system implementing the method of any of claims 1-2, wherein, It comprises the following modules: A data simulation module for simulating the manufacturing process of the CMOS device to obtain electrical data and process parameters; A data preprocessing module for preprocessing the electrical data and process parameters; A parameter optimization module for inputting the preprocessed electrical data and process parameters into the optimized residual neural network model to obtain the optimized process parameters.

4. An electronic device, comprising: It comprises a processor and a memory, the memory storing machine executable instructions executable by the processor, and the processor executing the machine executable instructions to implement the method of any one of claims 1-2.

5. A machine-readable storage medium, characterized in that, The machine readable storage medium stores machine executable instructions, which when called and executed by the processor, cause the processor to implement the method of any one of claims 1-2.

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