Timing sequence analysis method of chip circuit and related device

Abstract

The invention discloses a chip circuit time sequence analysis method and a related device, and relates to the technical field of electronic chips, and the method comprises the steps: sorting path sets from large to small according to the difficulty meeting a time sequence condition based on the correlation between the delay value of each path set and the difficulty meeting the time sequence condition, and obtaining a path set sequence, according to the sequence in the path set sequence corresponding to the time sequence condition from small to large, whether each path in the path set meets the time sequence condition or not is judged until no path which does not meet the time sequence condition exists in the path set. In the path set sequence, the difficulty that the paths in the path set with small order in the path set sequence meet the time sequence condition is greater than that of the paths in the path set with large order, and the time sequence analysis result of the chip circuit can be obtained without performing time sequence analysis on the paths in all the path sets. Therefore, according to the time sequence analysis method of the chip circuit provided by the embodiment of the invention, the path number of time sequence analysis is reduced, and the time sequence analysis speed of the chip circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of electronic chip technology, and in particular to a timing analysis method for a chip circuit and a related device. Background Art

[0002] Chip circuits are widely used in various electronic devices, such as mobile phones, computers, tablet computers, televisions, automotive electronics, smart homes, etc. With the continuous advancement and development of science and technology, the performance and integration of chip circuits are constantly improving, and the difficulty and time cost of timing analysis of chip circuits are significantly increased. How to accelerate the timing analysis of chip circuits is a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0003] In view of the above problems, the present application provides a timing analysis method and related device for a chip circuit to achieve the purpose of improving the timing analysis speed of the chip circuit. The specific scheme is as follows:

[0004] The first aspect of the present application provides a timing analysis method for a chip circuit, comprising:

[0005] Extracting isomorphic paths from a circuit netlist of a chip circuit to be analyzed to obtain multiple path sets;

[0006] For each of the path sets, obtaining a delay value of the path set based on a delay value of a target path in the path set, the target path including at least one path;

[0007] Based on the correlation between the delay value and the difficulty of satisfying the preset timing condition, the path set is sorted from the greatest difficulty to the smallest difficulty of satisfying the timing condition to obtain a path set sequence;

[0008] According to the sequence of paths corresponding to the timing condition from small to large, whether each path in the path set meets the timing condition is judged until there is no path that does not meet the timing condition in the path set, and the timing analysis result of the chip circuit is output, and the timing analysis result of the chip circuit includes all paths that do not meet the timing condition.

[0009] In a possible implementation, the timing condition includes a hold time condition and a setup time condition;

[0010] Based on the correlation between the delay value and the difficulty of satisfying the preset timing condition, the path set is sorted from large to small according to the difficulty of satisfying the timing condition to obtain a path set sequence, including:

[0011] For the holding time condition, the path sets are sorted in ascending order according to the delay value to obtain a first path set sequence;

[0012] For the establishment time condition, each of the path sets is sorted from large to small according to the delay value to obtain a second path set sequence.

[0013] In a possible implementation, acquiring the delay value of the path set based on the delay value of the target path in the path set includes:

[0014] Selecting at least one path from the path set as a target path;

[0015] estimating the delay value of each of the target paths;

[0016] The average value of the delay values ​​of the target paths is used as the delay value of the path set.

[0017] In a possible implementation, the delay value of the path set includes a minimum delay value and a maximum delay value, and acquiring the delay value of the path set based on the delay value of the target path in the path set includes:

[0018] Selecting at least one path from the path set as a target path;

[0019] Estimating the maximum and minimum delay values ​​of each target path;

[0020] Taking the minimum value of the delay value of the first target path as the minimum delay value of the path set, wherein the first target path is a path with the smallest minimum delay value among the target paths;

[0021] The maximum value of the delay value of the second target path is used as the maximum delay value of the path set, and the second target path is a path with the largest maximum delay value among the target paths.

[0022] In a possible implementation, for the holding time condition, each of the path sets is sorted in ascending order according to the delay value to obtain a first path set sequence, including:

[0023] For the holding time condition, the path sets are sorted in ascending order according to the minimum delay value to obtain a first path set sequence;

[0024] For the establishment time condition, sorting the path sets from large to small according to the delay value to obtain a second path set sequence includes:

[0025] For the establishment time condition, each of the path sets is sorted from large to small according to the maximum delay value to obtain a second path set sequence.

[0026] In a possible implementation, judging whether each path in the path set meets the timing condition according to the sequence of the path set corresponding to the timing condition from small to large, until there is no path in the path set that does not meet the timing condition, and outputting the timing analysis result of the chip circuit, includes:

[0027] According to the order from small to large in the first path set sequence, judging whether each path in each path set meets the hold time condition, until it is determined that there is no path that does not meet the hold time condition in the path sets of a continuous preset number of sets, obtaining a hold time analysis result of the chip circuit, the hold time analysis result including the path that does not meet the hold time condition;

[0028] According to the order of the second path set sequence from small to large, judging whether each path in each path set meets the setup time condition, until it is determined that there is no path that does not meet the setup time condition in the path sets of a continuous preset number of sets, obtaining a setup time analysis result of the chip circuit, wherein the setup time analysis result includes the path that does not meet the setup time condition;

[0029] A timing analysis result of the chip circuit is obtained, wherein the timing analysis result includes the hold time analysis result and the setup time analysis result.

[0030] A second aspect of the present application provides a timing analysis device for a chip circuit, comprising:

[0031] A path set partitioning unit extracts isomorphic paths from a circuit netlist of a chip circuit to be analyzed to obtain a plurality of path sets;

[0032] A delay characteristic calculation unit, configured to obtain, for each of the path sets, a delay value of the path set based on a delay value of a target path in the path set, wherein the target path includes at least one path;

[0033] A set sorting unit, configured to sort the path sets from greatest to least difficulty in satisfying the timing conditions based on the correlation between the delay values ​​of the path sets and the difficulty in satisfying the preset timing conditions, to obtain a path set sequence;

[0034] A timing analysis unit is used to determine whether each path in the path set meets the timing condition according to the sequence of path sets corresponding to the timing condition from small to large, until there is no path that does not meet the timing condition in the path set, and output the timing analysis result of the chip circuit, wherein the timing analysis result of the chip circuit includes all paths that do not meet the timing condition.

[0035] The third aspect of the present application provides a computer program product, including computer-readable instructions. When the computer-readable instructions are executed on an electronic device, the electronic device implements the timing analysis method of the chip circuit of the above-mentioned first aspect or any implementation method of the first aspect.

[0036] A fourth aspect of the present application provides an electronic device, comprising at least one processor and a memory connected to the processor, wherein:

[0037] The memory is used to store computer programs;

[0038] The processor is used to execute the computer program so that the electronic device can implement the timing analysis method of the chip circuit of the above-mentioned first aspect or any implementation manner of the first aspect.

[0039] A fifth aspect of the present application provides a computer storage medium, which carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can use the timing analysis method of the chip circuit of the above-mentioned first aspect or any implementation method of the first aspect.

[0040] By means of the above technical scheme, the present application provides a timing analysis method and related devices for a chip circuit, extracts isomorphic paths from a circuit netlist of a chip circuit to be analyzed, obtains multiple path sets, for each path set, obtains the delay value of the path set based on the delay value of the target path in the path set, sorts the path sets from large to small according to the difficulty of meeting the timing conditions based on the correlation between the delay values ​​of each path set and the difficulty of meeting the timing conditions, obtains a path set sequence, judges whether each path in the path set meets the timing conditions according to the sequence in the path set sequence corresponding to the timing conditions from small to large, until there is no path that does not meet the timing conditions in the path set, outputs the timing analysis result of the chip circuit, and the timing analysis result of the chip circuit includes the path that does not meet the timing conditions. Because, The calculation complexity of the path delay value that is correlated with the difficulty of meeting the timing conditions is lower than the complexity of the timing condition analysis, and the proportion of paths that do not meet the timing conditions in the chip circuit is very small. Therefore, based on the delay value, the path set can be sorted from high to low according to the difficulty of meeting the timing conditions. The difficulty of meeting the timing conditions for the paths in the path set with a smaller sequence in the path set sequence is greater than that for the paths in the path set with a larger sequence. Therefore, the timing condition analysis is performed from high to low in difficulty until there are no paths in the path set that do not meet the timing conditions and the timing analysis is stopped. The timing analysis result of the chip circuit can be obtained without performing timing analysis on the paths in all path sets. Therefore, the timing analysis method of the chip circuit provided in the embodiment of the present application reduces the number of paths for timing analysis and improves the speed of timing analysis of the chip circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0042] Figure 1 A schematic diagram of a system architecture provided for this application;

[0043] Figure 2 An optional hardware structure diagram of the terminal 100 is shown;

[0044] Figure 3 An optional structural diagram of the server 200 is shown;

[0045] Figure 4 A schematic diagram of a flow chart of a timing analysis method for a chip circuit provided in an embodiment of the present application;

[0046] Figure 5 An example of a schematic diagram of the structure of a circuit netlist of a chip circuit is provided;

[0047] Figure 6 It is a schematic diagram of the path set partitioning result of the circuit netlist D;

[0048] Figure 7 A schematic diagram illustrating a path set sequence is shown;

[0049] Figure 8 An example of a timing analysis sequence diagram is shown;

[0050] Fig. 9 A flowchart of a specific implementation method of a timing analysis method for a chip circuit provided in an embodiment of the present application;

[0051] Fig.10 The delay value diagram of the path set is illustrated;

[0052] Fig.11 A schematic diagram illustrating a path set sequence is shown;

[0053] Fig.12 A schematic diagram illustrating a timing analysis result;

[0054] Fig.13 A schematic diagram of the structure of a timing analysis device for a chip circuit provided in an embodiment of the present application;

[0055] Fig.14 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] The following describes the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0057] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0058] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0059] This application can be applied to the field of electronic chip technology. With the advancement of integrated circuit technology and the continuous improvement of chip computing power requirements, the chip scale continues to increase. At present, the number of transistors on a single chip has reached more than 30 billion, and the scale of SoC (System on Chip) chips will be further improved in the future. In addition, the chip circuit process feature size continues to shrink, the operating voltage is reduced, and the impact of process-voltage-temperature (PVT) fluctuations on circuit performance has shifted from the traditional concentrated Gaussian distribution to a flattened non-Gaussian distribution. In this context, on the one hand, the number of paths required for timing circuit analysis of the chip has doubled, resulting in a significant increase in the difficulty and time overhead of timing analysis. On the other hand, the accuracy requirements for timing analysis are getting higher and higher.

[0060] As described above, the timing analysis of chip circuits is one of the keys to shortening the design cycle of high-computing power chips. Therefore, a timing analysis method for a chip circuit provided in an embodiment of the present application aims to improve the timing analysis speed of the chip circuit, reduce the time overhead of the timing analysis of the chip circuit, and thus significantly shorten the chip development cycle.

[0061] This application can be applied to, but is not limited to, applications with timing analysis functions or cloud services provided by cloud-side servers, etc., which are introduced below:

[0062] See also Figure 1 , Figure 1A schematic diagram of a system architecture is shown. The system may include a terminal 100 and a server 200. The server 200 may include one or more servers ( Figure 1 In the example, a server is included, and the server 200 can provide the method provided in the embodiment of the present application for one or more terminals.

[0063] Among them, a timing analysis application can be installed on the terminal 100. The above application and web page can provide an interface. The terminal 100 can receive relevant parameters entered by the user on the timing analysis interface and send the above parameters to the server 200. The server 200 can obtain processing results based on the received parameters and return the processing results to the terminal 100.

[0064] It should be understood that in some optional implementations, the terminal 100 can also complete the action of obtaining the processing result based on the received parameters by itself without the cooperation of the server, and the embodiments of the present application are not limited to this.

[0065] Next describe Figure 1 The product form of the mid-terminal 100;

[0066] The terminal 100 in the embodiment of the present application can be a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (AR) / virtual reality (VR) device, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), etc., and the embodiment of the present application does not impose any limitation on this.

[0067] Figure 2 An optional hardware structure diagram of the terminal 100 is shown.

[0068] refer to Figure 2 As shown, the terminal 100 may include a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), an earphone jack 163 (optional), a processor 170, an external interface 180, a power supply 190 and other components. Those skilled in the art will appreciate that Figure 2 These are merely examples of terminals or multi-function devices and do not constitute limitations on the terminals or multi-function devices, which may include more or fewer components than those shown in the figures, or combinations of certain components, or different components.

[0069] The input unit 130 can be used to receive input digital or character information, and generate key signal input related to the user settings and function control of the portable multifunctional device. Specifically, the input unit 130 may include a touch screen 131 (optional) and / or other input devices 132. The touch screen 131 can collect the user's touch operations on or near it (such as the user's operation on or near the touch screen using any suitable object such as fingers, joints, stylus, etc.), and drive the corresponding connection device according to a pre-set program. The touch screen can detect the user's touch action on the touch screen, convert the touch action into a touch signal and send it to the processor 170, and can receive and execute the command sent by the processor 170; the touch signal at least includes the touch point coordinate information. The touch screen 131 can provide an input interface and an output interface between the terminal 100 and the user. In addition, the touch screen can be implemented using multiple types such as resistive, capacitive, infrared and surface acoustic wave. In addition to the touch screen 131, the input unit 130 can also include other input devices. Specifically, other input devices 132 may include, but are not limited to, one or more of a physical keyboard, function keys (such as a volume control key, a switch key, etc.), a trackball, a mouse, a joystick, and the like.

[0070] Among them, the input device 132 can receive input data and the like.

[0071] The display unit 140 may be used to display information input by the user or provided to the user, various menus of the terminal 100, interactive interfaces, file display, and / or playback of any multimedia file. In the embodiment of the present application, the display unit 140 may be used to display an interface for timing analysis of a chip circuit, processing results, and the like.

[0072] The memory 120 can be used to store instructions and data. The memory 120 can mainly include an instruction storage area and a data storage area. The data storage area can store various data, such as multimedia files, texts, etc.; the instruction storage area can store software units such as operating systems, applications, instructions required for at least one function, or their subsets and extensions. It can also include a non-volatile random access memory; provide the processor 170 with hardware, software and data resources including management of computing and processing equipment, and support control software and applications. It is also used for the storage of multimedia files, and the storage of running programs and applications.

[0073] The processor 170 is the control center of the terminal 100. It uses various interfaces and lines to connect various parts of the entire terminal 100. By running or executing instructions stored in the memory 120 and calling data stored in the memory 120, it executes various functions of the terminal 100 and processes data, thereby controlling the terminal device as a whole. Optionally, the processor 170 may include one or more processing units; preferably, the processor 170 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface and application program, and the modem processor mainly processes wireless communication. It is understandable that the above-mentioned modem processor may not be integrated into the processor 170. In some embodiments, the processor and the memory may be implemented on a single chip, and in some embodiments, they may also be implemented separately on separate chips. The processor 170 may also be used to generate corresponding operation control signals, send them to corresponding components of the computing and processing device, read and process data in the software, especially read and process data and programs in the memory 120, so that each functional module therein performs corresponding functions, thereby controlling the corresponding components to act according to the requirements of the instructions.

[0074] Among them, the memory 120 can be used to store software codes related to the timing analysis method of the chip circuit, the processor 170 can execute the steps of the timing analysis method of the chip circuit, and can also schedule other units (such as the above-mentioned input unit 130 and display unit 140) to realize corresponding functions.

[0075] The radio frequency unit 110 (optional) can be used for receiving and sending information or receiving and sending signals during a call, for example, after receiving the downlink information of the base station, it is sent to the processor 170 for processing; in addition, the designed uplink data is sent to the base station. Generally, the RF circuit includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (Low Noise Amplifier, LNA), a duplexer, etc. In addition, the radio frequency unit 110 can also communicate with network devices and other devices through wireless communication. The wireless communication can use any communication standard or protocol, including but not limited to Global System of Mobile communication (Global System of Mobile communication, GSM), General Packet Radio Service (General Packet Radio Service, GPRS), Code Division Multiple Access (Code Division Multiple Access, CDMA), Wideband Code Division Multiple Access (Wideband Code Division Multiple Access, WCDMA), Long Term Evolution (Long Term Evolution, LTE), email, Short Messaging Service (SMS), etc.

[0076] In this embodiment of the present application, the RF unit 110 can send data to the server 200 and receive processing results sent by the server 200.

[0077] It should be understood that the radio frequency unit 110 is optional and can be replaced by other communication interfaces, such as a network port.

[0078] The terminal 100 also includes a power supply 190 (such as a battery) for supplying power to various components. Preferably, the power supply can be logically connected to the processor 170 through a power management system, so that the power management system can manage functions such as charging, discharging, and power consumption.

[0079] The terminal 100 further includes an external interface 180 , which may be a standard Micro USB interface or a multi-pin connector, and may be used to connect the terminal 100 to communicate with other devices, or to connect a charger to charge the terminal 100 .

[0080] Although not shown, the terminal 100 may also include a flashlight, a wireless fidelity (WiFi) module, a Bluetooth module, sensors with different functions, etc., which are not described in detail here. Some or all of the methods described below may be applied in the following embodiments. Figure 2 In the terminal 100 shown.

[0081] Next describe Figure 1 The product form of the server 200;

[0082] Figure 3 An optional structural diagram of the server 200 is shown. Figure 3 As shown, the server 200 includes a bus 201, a processor 202, a communication interface 203, and a memory 204. The processor 202, the memory 204, and the communication interface 203 communicate with each other via the bus 201.

[0083] The bus 201 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0084] The processor 202 may be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0085] The memory 204 may include a volatile memory, such as a random access memory (RAM). The memory 204 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0086] The memory 204 may be used to store software codes related to the timing analysis method of the chip circuit, and the processor 202 may execute the steps of the timing analysis method of the chip circuit of the chip, and may also schedule other units to implement corresponding functions.

[0087] It should be understood that the above-mentioned terminal 100 and server 200 can be centralized or distributed devices, and the processors in the above-mentioned terminal 100 and server 200 (such as processor 170 and processor 202) can be hardware circuits (such as application specific integrated circuit (ASIC), field-programmable gate array (FPGA), general-purpose processor, digital signal processor (DSP), microprocessor or microcontroller, etc.), or a combination of these hardware circuits. For example, the processor can be a hardware system with an instruction execution function, such as a CPU, DSP, etc., or a hardware system without an instruction execution function, such as an ASIC, FPGA, etc., or a combination of the above-mentioned hardware systems without an instruction execution function and hardware systems with an instruction execution function.

[0088] The timing analysis of the chip circuit specifically refers to analyzing each path in the chip circuit to determine whether the chip circuit meets the corresponding timing conditions. For example, the timing analysis includes but is not limited to path hold time analysis and path setup time analysis, wherein the path hold time analysis refers to analyzing whether the path hold time meets the preset hold time condition, and the path setup time analysis refers to analyzing whether the path setup time meets the preset setup time condition. In the prior art, timing analysis is usually performed on each path traversally according to the circuit netlist of the chip circuit. Obviously, in the scenario of large-scale chip circuits, the traversal analysis needs to analyze all paths to obtain a complete timing analysis result, resulting in a long time-consuming and low efficiency of the timing analysis.

[0089] Based on this, an embodiment of the present application provides a timing analysis method for a chip circuit. The timing analysis method for a chip circuit of an embodiment of the present application is described in detail below in conjunction with the accompanying drawings.

[0090] Reference Figure 4 , Figure 4 The process diagram of a timing analysis method for a chip circuit provided in an embodiment of the present application is as follows: Figure 4 As shown, a data processing method provided in an embodiment of the present application may include steps S401 to S404, and these steps are described in detail below.

[0091] S401 . Extract isomorphic paths from a circuit netlist of a chip circuit to be analyzed to obtain multiple path sets.

[0092] In this embodiment, the circuit netlist includes a transistor-level circuit netlist or a gate-level circuit netlist, wherein the circuit netlist is composed of multiple paths.

[0093] See also Figure 5 , Figure 5 The schematic diagram of the circuit netlist of a chip circuit is shown as an example. Figure 5 As shown, the circuit netlist D is composed of multiple combinational logic gates and bistable flip-flops (DFF, D Flip-Flop) circuits connected in series, where the DFF circuit controls the output state through a clock signal (CLK) and is a synchronous sequential logic circuit.

[0094] by Figure 5 Taking the circuit netlist D shown as an example, the chip circuit is divided into multiple paths, namely path P1 to path P14 marked with dotted boxes, wherein each path includes multiple combinational logic gates connected in series, for example, P1 includes 1 combinational logic gate, and P12 includes 6 combinational logic gates connected in series.

[0095] In this embodiment, a path set includes a group of isomorphic paths formed by connecting logic units of the same type with the same connection relationship. It can be understood that the circuit connection structure of the isomorphic paths is the same.

[0096] by Figure 5 Taking the circuit netlist D shown in the figure as an example, the paths in the circuit netlist D are divided into multiple path sets W according to the number of combinational logic gates connected in series. Figure 6 , Figure 6 Schematic diagram of the path set partitioning result of the circuit netlist D, the path set of the circuit netlist D includes path sets G1 to G7, wherein the paths in each path set include at least one isomorphic path with the same number of combinational logic gates. For example, G1 includes P1 and P2, and P1 and P2 are isomorphic paths.

[0097] S402: For each path set, based on the delay value of the target path in the path set, obtain the delay value of the path set.

[0098] In this embodiment, the target path includes at least one path. Optionally, the target path includes a preset number of isomorphic paths, where the preset number is a positive integer less than the total number of paths in the path set.

[0099] Optionally, the target path includes a path randomly selected from the path set, a delay value of the target path is calculated, and the delay value is used as the delay value of the path set.

[0100] In this embodiment, the delay value of the path refers to the total time delay experienced by the signal from the input end to the output end, and the delay value is obtained by adding up the delays of each combinational logic gate that constitutes the path. Specifically, each combinational logic gate has a fixed delay time, which represents the time required from input to output, and the delay value of the path is obtained by accumulating the delay times of all combinational logic gates in the path.

[0101] Still taking the circuit netlist D as an example, select P1, P3, P5, P7, P9, P11 and P13 as the target paths of G1~G7 respectively, and calculate the delay value td of P1 to be 1ns, the delay value td of P3 to be 2ns, the delay value td of P5 to be 3ns, the delay value td of P7 to be 4ns, the delay value td of P9 to be 5ns, the delay value td of P11 to be 6ns, and the delay value td of P13 to be 7ns. Then take the delay value of the target path as the delay value of the path set, as shown in Figure 6 As shown, the delay values ​​td of G1~G7 are 1ns, 2ns, 3ns, 4ns, 5ns and 6ns respectively.

[0102] It should be noted that there are multiple methods for calculating the delay value of a path, and the details can be found in the prior art.

[0103] S403 , based on the correlation between the delay value and the difficulty of satisfying the preset timing condition, sort the path set from the greatest difficulty to the smallest difficulty of satisfying the timing condition to obtain a path set sequence.

[0104] In this embodiment, the delay value of the path is a key feature for the path to meet the timing condition. Optionally, the delay value of the path is positively correlated or negatively correlated with the difficulty of meeting the timing condition.

[0105] Specifically, based on the correlation between the delay value and the difficulty of satisfying the timing condition, the path set is sorted from large to small according to the difficulty of satisfying the timing condition, and the method for obtaining the path set sequence includes:

[0106] If the delay value of the path is positively correlated with the difficulty of meeting the timing conditions, the path set sequence is obtained by sorting the delay value from large to small. If the delay value of the path is negatively correlated with the difficulty of meeting the timing conditions, the path set sequence is obtained by sorting the delay value from small to large.

[0107] In this embodiment, the timing condition is a condition for judging whether each timing parameter meets the timing requirements. Optionally, the timing parameters include but are not limited to hold time and setup time, wherein the hold time refers to the minimum time that the data signal must remain stable after the rising edge (or falling edge) of the trigger clock signal. The setup time refers to the minimum time that the data signal must remain stable before the rising edge (or falling edge) of the trigger clock signal. Correspondingly, the timing conditions include but are not limited to hold time conditions and setup time conditions. The hold time condition is that the hold time is greater than a preset hold time threshold, and the setup time condition includes that the setup time is less than a preset setup time threshold.

[0108] Based on the principles of timing analysis and historical data, it can be concluded that the larger the delay value, the easier it is to meet the hold time condition, and the smaller the delay value of the path, the easier it is to meet the setup time condition.

[0109] Therefore, the delay value of the path is inversely correlated with the difficulty of satisfying the hold time condition, that is, the larger the delay value of the path, the smaller the difficulty of satisfying the hold time condition. For example, when the delay value of the first path is greater than the delay value of the second path, the first path is easier to satisfy the hold time condition than the second path.

[0110] The delay value of the path is positively correlated with the difficulty of meeting the establishment time condition, that is, the smaller the delay value, the smaller the difficulty of meeting the establishment time condition. For example, when the delay value of the third path is smaller than the delay value of the second path, the third path is easier to meet the establishment time condition than the fourth path.

[0111] Figure 7 A schematic diagram illustrating a sequence of path collections is shown below. Figure 7 As shown, for the holding time condition, the path set is sorted from large to small according to the difficulty of satisfying the holding time condition, that is, the path set is sorted from small to large according to the delay value to obtain a first path set sequence, and for the establishment time condition, the path set is sorted from large to small according to the difficulty of satisfying the establishment time condition, and the path set is sorted from large to small according to the delay value to obtain a second path set sequence.

[0112] S404, judging whether each path in the path set meets the timing condition according to the sequence of the path set corresponding to the timing condition from small to large, until there is no path in the path set that does not meet the timing condition, and outputting the timing analysis result of the chip circuit.

[0113] In this embodiment, the timing analysis result of the chip circuit includes paths that do not meet the timing conditions.

[0114] In this embodiment, a path set in which no path fails to meet the timing condition is called a target path set, and each path in a post-order set of the target path set is determined to meet the timing condition. The post-order set of the target path set refers to a path set that is located after the target path set in the order indicated by the timing condition.

[0115] Next, we take the timing conditions including hold time conditions and setup time conditions as an example:

[0116] In this embodiment, in the first path set sequence corresponding to the hold time condition, the smaller the rank, the smaller the delay value, and the greater the difficulty of satisfying the hold time condition, that is, the greater the probability of not satisfying the hold time condition. Therefore, according to the rank from small to large in the first path set sequence, it is judged whether each path in the path set satisfies the hold time condition, until there is no path in the path set that does not satisfy the hold time condition, the hold time condition analysis is stopped, and the hold time analysis results of each path in the unanalyzed path set are directly determined to be satisfied, and the hold time analysis results of the chip circuit are output, and the hold time analysis results include the paths that do not satisfy the hold time condition.

[0117] In this embodiment, in the second path set sequence corresponding to the setup time condition, the smaller the rank, the larger the delay value, and the greater the difficulty in meeting the setup time condition, that is, the greater the probability of not meeting the setup time condition. Therefore, according to the rank from small to large in the second path set sequence, it is judged whether each path in the path set meets the setup time condition, until there is no path that does not meet the setup time condition in the path set, the setup time condition analysis is stopped, and the setup time analysis results of each path in the unanalyzed path set are directly determined to be satisfied, and the setup time analysis results of the chip circuit are output, and the setup time analysis results include the paths that do not meet the setup time condition.

[0118] In summary, the timing analysis results include hold time analysis results and setup time analysis results.

[0119] Figure 8 An example of a timing analysis sequence diagram is provided. Specifically, when analyzing whether each path in the circuit netlist D meets the hold time condition, the order of the hold time condition indication is the first timing analysis order, that is, the order in the first path set sequence is from small to large. When analyzing whether each path in the circuit netlist D meets the setup time condition, the order of the setup time condition indication is the second timing analysis order, that is, the order in the second path set sequence is from small to large.

[0120] It can be seen from the above technical scheme that the timing analysis method of the chip circuit provided in the embodiment of the present application extracts isomorphic paths from the circuit netlist of the chip circuit to obtain multiple path sets. For each path set, based on the delay value of the target path in the path set, the delay value of the path set is obtained. Based on the correlation between the delay value of each path set and the difficulty of meeting the timing conditions, the path sets are sorted from large to small according to the difficulty of meeting the timing conditions to obtain a path set sequence. According to the sequence in the path set sequence corresponding to the timing conditions, it is judged from small to large whether each path in the path set meets the timing conditions until there is no path that does not meet the timing conditions in the path set, and the timing analysis result of the chip circuit is output. The timing analysis result of the chip circuit Including paths that do not meet the timing conditions, since the calculation complexity of the delay value that is correlated with the difficulty of meeting the timing conditions is lower than the complexity of the timing condition analysis, and the paths that do not meet the timing analysis conditions in the chip circuit are much smaller than the paths that meet the timing analysis conditions, the path set can be sorted from large to small according to the difficulty of meeting the timing conditions by sorting the delay values, since the difficulty of meeting the timing conditions for the paths in the path set with a small rank in the path set sequence is greater than that for the paths in the path set with a large rank, therefore, when all the paths in the path set meet the timing conditions, it can be determined that all the paths in the subsequent path set meet the timing conditions, and the timing analysis results of the chip circuit can be obtained without performing timing analysis on the paths in all the path sets. Therefore, the timing analysis method of the chip circuit provided in the embodiment of the present application reduces the number of paths for timing analysis and improves the speed of timing analysis of the chip circuit.

[0121] Furthermore, this scheme first divides the chip circuit into multiple path sets, which include multiple isomorphic paths. The delay values ​​of the isomorphic paths are the same. Therefore, there is no need to calculate the delay values ​​of all paths to determine the delay values ​​of a group of isomorphic paths. The paths are analyzed in timing according to the path set, further improving the efficiency of the timing analysis.

[0122] It should be noted that there are multiple specific implementations of the timing analysis method for a chip circuit provided in the embodiments of the present application.

[0123] For example, timing analysis is not limited to hold time analysis based on hold time conditions and setup time analysis based on setup time conditions, but may also include other types of timing analysis. If other types of timing analysis are performed, it is determined that the difficulty of satisfying the corresponding timing conditions is correlated with the delay value (positively correlated or inversely correlated). Based on the correlation, the path set can be sorted with reference to the delay value, and timing analysis is performed preferentially on paths that are more difficult to satisfy the timing relationship, thereby reducing the number of analysis paths.

[0124] For another example, when sorting a path set, a quick sort algorithm can be used to improve the sorting speed.

[0125] Next, we will take timing analysis including hold time analysis and setup time analysis as an example to introduce the specific implementation method of an optional chip circuit timing analysis method. Fig. 9 A flowchart of a specific implementation method of a timing analysis method for a chip circuit provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, this method specifically includes:

[0126] S901. Extract isomorphic paths from a circuit netlist of a chip circuit to be analyzed to obtain multiple path sets.

[0127] In this embodiment, the circuit netlist of the chip circuit is composed of multiple circuit paths, and one path is composed of at least one logic unit or component, wherein the logic unit includes a combinational logic gate.

[0128] In this embodiment, isomorphic paths refer to multiple paths in which the logical units or components are exactly the same and the connection relationships between the logical units or components are the same. If the logical units or components constituting path A are exactly the same as the logical units or components constituting path B, and the connection relationship between the logical units or components constituting path A is exactly the same as the connection relationship between the logical units or components constituting path B, then path A and path B are isomorphic paths.

[0129] In a possible implementation, a subgraph isomorphism algorithm is used to extract isomorphic paths in a circuit netlist, and the isomorphic paths are divided into the same path set, wherein the method of extracting isomorphic paths in a circuit netlist using the subgraph isomorphism algorithm includes:

[0130] After adopting the device connection relationship coding, the hash value is calculated according to the device connection relationship coding, and the hash value matching of the two paths is used as the basis for judging whether the two paths are isomorphic paths, thereby realizing the extraction of isomorphic paths using the subgraph isomorphism algorithm.

[0131] It should be noted that the specific method of extracting isomorphic paths in a circuit netlist using a subgraph isomorphism algorithm can be found in the prior art.

[0132] S902: Select at least one path from the path set as a target path, and estimate the maximum and minimum delay values ​​of each target path.

[0133] In this embodiment, at least one path is selected from the path set as the target path. Specifically, the path set includes N paths, and n paths are randomly selected from the path set as the target paths, where n∈[1,N].

[0134] S903: Taking the minimum value of the delay value of the first target path as the minimum delay value of the path set, and taking the maximum value of the delay value of the second target path as the maximum delay value of the path set.

[0135] In this embodiment, the first target path is a path with the smallest minimum delay value among all target paths, and the second target path is a path with the largest maximum delay value among all target paths.

[0136] Taking the path set G5 in the circuit netlist D as an example, the target path includes P9 and P10. The maximum and minimum delay values ​​of P9 and P10 are estimated, and the minimum and maximum delay values ​​of P9 are 4.5ns and 5ns respectively, and the minimum and maximum delay values ​​of P10 are 5ns and 5.5ns respectively.

[0137] Then, the path with the smallest minimum delay value in the path set G5, that is, the first target path, is P9, and the path with the largest maximum delay value, that is, the second target path, is P10. The minimum delay value of P9 is taken as the minimum delay value of the path set, and the maximum delay value of P10 is taken as the maximum delay value of the path set, so that the delay value td of the path set includes a minimum delay value tdmin=4.5ns and a maximum value tdmax=5.5ns.

[0138] See also Fig.10 , Fig.10 The delay value diagram of the path set is shown as an example. Fig.10 In the example, (td = (tdmin, tdmax)) represents the delay value of each path set. For example, G5 (td = (4.5ns, 5.5ns)).

[0139] It should be noted that when there is only one target path, the minimum delay value of the target path is directly selected as the minimum delay value of the path set, and the maximum delay value is selected as the maximum delay value of the path set.

[0140] S904: Determine that the correlation between the delay value and the difficulty of satisfying the retention time condition is an inverse correlation.

[0141] In this embodiment, the correlation between the delay value and the difficulty of satisfying the holding time condition is an inverse correlation, that is, the larger the delay value, the smaller the difficulty of satisfying the holding time condition.

[0142] It should be noted that the correlation between the delay value and the difficulty of satisfying the hold time condition is obtained based on data analysis of various chip circuit parameters and historical analysis results. The data analysis method can refer to the prior art.

[0143] S905 . For the maintenance time condition, sort each path set from small to large according to the minimum delay value to obtain a first path set sequence.

[0144] See also Fig.11 , Fig.11A schematic diagram of a path set sequence is illustrated. Taking circuit netlist D as an example, each path set is sorted from small to large according to the minimum delay value to obtain a first path set sequence [G1, G2, G3, G4, G5, G6, G7].

[0145] S906. Determine whether each path in each path set meets the hold time condition according to the order from small to large in the first path set sequence, until it is determined that there is no path that does not meet the hold time condition in the path sets of a preset number of consecutive sets, and obtain the hold time analysis result of the chip circuit.

[0146] In this embodiment, the hold time analysis result includes paths that do not meet the hold time condition. The preset number of sets can be pre-configured to a value greater than 1 based on the timing analysis accuracy requirement and the total number of path sets.

[0147] See also Fig.11 Taking the circuit netlist D as an example, the hold time condition analysis is performed on each path in each path set according to the first path set sequence from small to large, and the hold time condition analysis result of each path is obtained, that is, whether each path meets the hold time condition is determined.

[0148] Taking the case where the number of consecutive preset sets is 1 as an example, paths P1~P4 in G1 and G2 do not meet the hold time condition, and paths P5 and P6 in G3 meet the hold time condition. Since the delay values ​​of paths P5 and P6 in G3 are smaller than those of G4~G7, that is, it is more difficult for paths P5 and P6 in G3 to meet the hold time condition than G4~G7, therefore, when paths P5 and P6 in G3 meet the hold time condition, it is determined that paths in G4~G7 meet the hold time condition.

[0149] S907. Determine that the correlation between the delay value and the difficulty of satisfying the establishment time condition is a positive correlation.

[0150] In this embodiment, the correlation between the delay value and the difficulty of satisfying the establishment time condition is a positive correlation, that is, the smaller the delay value, the smaller the difficulty of satisfying the establishment time condition.

[0151] It should be noted that the correlation between the delay value and the difficulty of satisfying the establishment time condition is obtained based on data analysis of various chip circuit parameters and historical analysis results. The data analysis method can refer to the prior art.

[0152] S908 . For the establishment time condition, sort each path set from large to small according to the maximum delay value to obtain a second path set sequence.

[0153] See also Fig.11, sort each path set from large to small according to the maximum delay value to obtain the first path set sequence [G7, G6, G5, G4, G3, G2, G1].

[0154] S909, judging whether each path in each path set meets the setup time condition according to the sequence from small to large in the second path set sequence, until it is determined that there is no path that does not meet the setup time condition in the path sets of a preset number of consecutive sets, thereby obtaining a setup time analysis result of the chip circuit.

[0155] In this embodiment, the setup time analysis result includes paths that do not meet the setup time condition. The preset number of sets can be pre-configured to a value greater than 1 based on the timing analysis accuracy requirement and the total number of path sets.

[0156] See also Fig.11 , perform establishment time condition analysis on each path in each path set from small to large according to the sequence of the second path set, and obtain the establishment time condition analysis result of each path, that is, determine whether each path meets the establishment time condition.

[0157] Taking the case where the number of consecutive preset sets is 1 as an example, paths P11~P14 in G7 and G6 do not meet the establishment time condition, and paths P9 and P10 in G5 meet the establishment time condition. Since the delay values ​​of P9 and P10 in G5 are greater than those of G1~G4, that is, it is more difficult for the paths in G5 to meet the establishment time condition than G1~G4, therefore, when paths P9 and P10 in G5 meet the establishment time condition, it is determined that the paths in G1~G4 meet the establishment time condition.

[0158] S910, obtaining a timing analysis result of a chip circuit.

[0159] In this embodiment, the timing analysis result includes a hold time analysis result and a setup time analysis result.

[0160] See also Fig.12 , Fig.12 A schematic diagram of a timing analysis result is shown below. Fig.12 As shown, the timing analysis results include hold time analysis results and setup time analysis results. The hold time analysis results include paths that do not meet the hold time conditions, that is, all paths in G1 and G2. The setup time analysis results include paths that do not meet the setup time conditions, that is, all paths in G7 and G6.

[0161] It can be seen from the above technical solution that an embodiment of the present application provides a timing analysis method for a chip circuit. For the hold time condition, each path set is sorted from small to large according to the minimum delay value to obtain a first path set sequence. For the establishment time condition, each path set is sorted from large to small according to the maximum delay value to obtain a second path set sequence, thereby reducing analysis errors caused by unstable delay values ​​and improving the accuracy of timing analysis results.

[0162] Furthermore, the present solution may adopt a distributed structure for timing analysis. Specifically, the analysis process of each timing condition may be executed in parallel. For example, the hold time condition analysis shown in S904 to S906 and the setup time condition analysis shown in S907 to S909 may be executed in parallel to improve the speed of timing analysis.

[0163] Furthermore, increasing the number of preset sets can improve the accuracy of timing analysis results, and reducing the number of preset sets can improve the efficiency of timing analysis. This solution can dynamically adjust the number of preset sets to improve both the efficiency of timing analysis and the accuracy of timing analysis results, thereby avoiding misjudgments caused by delay value errors.

[0164] Furthermore, the present solution may also include performing a secondary timing analysis on a third target path. Specifically, the third target path is a path in a target path set that satisfies the timing condition, wherein the target path set is a path set having at least one path that does not satisfy the timing condition. For example, if P3 in G2 satisfies the hold time condition and P4 does not satisfy the hold time condition, a secondary hold time condition analysis is performed on P3 to verify the timing analysis result of P3 and improve the accuracy of the timing analysis result.

[0165] A timing analysis method for a chip circuit provided in an embodiment of the present application is introduced above, and a device for executing the timing analysis method for the chip circuit is introduced below.

[0166] See also Fig.13 , Fig.13 This is a schematic diagram of the structure of a timing analysis device for a chip circuit provided in an embodiment of the present application. Fig.13 As shown, the timing analysis device of the chip circuit includes:

[0167] A path set partitioning unit 1301 extracts isomorphic paths from a circuit netlist of a chip circuit to be analyzed to obtain multiple path sets;

[0168] The delay characteristic calculation unit 1302 is used to obtain the delay value of the path set for each of the path sets based on the delay value of the target path in the path set, where the target path includes at least one path;

[0169] A set sorting unit 1303 is used to sort the path sets from greatest to least difficulty in satisfying the timing conditions based on the correlation between the delay values ​​of the path sets and the difficulty in satisfying the preset timing conditions, so as to obtain a path set sequence;

[0170] The timing analysis unit 1304 is used to determine whether each path in the path set meets the timing condition according to the sequence of the path set corresponding to the timing condition from small to large, until there is no path that does not meet the timing condition in the path set, and output the timing analysis result of the chip circuit, and the timing analysis result of the chip circuit includes all paths that do not meet the timing condition.

[0171] In a possible implementation, the timing condition includes a hold time condition and a setup time condition;

[0172] The set sorting unit is used to sort the path set from the greatest difficulty to the least difficulty in satisfying the preset timing condition based on the correlation between the delay value and the difficulty in satisfying the preset timing condition, and when obtaining the path set sequence, specifically to:

[0173] For the holding time condition, the path sets are sorted in ascending order according to the delay value to obtain a first path set sequence;

[0174] For the establishment time condition, each of the path sets is sorted from large to small according to the delay value to obtain a second path set sequence.

[0175] In a possible implementation, the delay characteristic calculation unit is used to obtain the delay value of the path set based on the delay value of the target path in the path set, specifically to:

[0176] Selecting at least one path from the path set as a target path;

[0177] estimating the delay value of each of the target paths;

[0178] The average value of the delay values ​​of the target paths is used as the delay value of the path set.

[0179] In a possible implementation, the delay characteristic calculation unit is used to obtain the delay value of the path set based on the delay value of the target path in the path set, specifically to:

[0180] Selecting at least one path from the path set as a target path;

[0181] Estimating the maximum and minimum delay values ​​of each target path;

[0182] Taking the minimum value of the delay value of the first target path as the minimum delay value of the path set, wherein the first target path is a path with the smallest minimum delay value among the target paths;

[0183] The maximum value of the delay value of the second target path is used as the maximum delay value of the path set, and the second target path is a path with the largest maximum delay value among the target paths.

[0184] In a possible implementation, the set sorting unit is used to sort the path sets in ascending order according to the delay value for the holding time condition to obtain a first path set sequence, specifically to:

[0185] For the holding time condition, each of the path sets is sorted from small to large according to the minimum delay value to obtain a first path set sequence; a set sorting unit is used for, for the establishment time condition, when each of the path sets is sorted from large to small according to the delay value to obtain a second path set sequence, specifically for:

[0186] For the establishment time condition, each of the path sets is sorted from large to small according to the maximum delay value to obtain a second path set sequence.

[0187] In a possible implementation, the timing analysis unit is used to determine whether each path in the path set meets the timing condition according to the sequence of the path set corresponding to the timing condition from small to large, until there is no path in the path set that does not meet the timing condition, and output the timing analysis result of the chip circuit, specifically for:

[0188] According to the order from small to large in the first path set sequence, judging whether each path in each path set meets the hold time condition, until it is determined that there is no path that does not meet the hold time condition in the path sets of a continuous preset number of sets, obtaining a hold time analysis result of the chip circuit, the hold time analysis result including the path that does not meet the hold time condition;

[0189] According to the order of the second path set sequence from small to large, judging whether each path in each path set meets the setup time condition, until it is determined that there is no path that does not meet the setup time condition in the path sets of a continuous preset number of sets, obtaining a setup time analysis result of the chip circuit, wherein the setup time analysis result includes the path that does not meet the setup time condition;

[0190] A timing analysis result of the chip circuit is obtained, wherein the timing analysis result includes the hold time analysis result and the setup time analysis result.

[0191] The present application also provides an electronic device in an embodiment. Fig.14 As shown, it shows a schematic diagram of the structure of an electronic device suitable for implementing the embodiment of the present application. The electronic device in the embodiment of the present application may include but is not limited to fixed terminals such as mobile phones, laptops, PDAs (personal digital assistants), PADs (tablet computers), desktop computers, etc. Fig.14 The electronic device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0192] like Fig.14 As shown, the electronic device may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1401, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1402 or a program loaded from a storage device 1408 to a random access memory (RAM) 1403. When the electronic device is powered on, various programs and data required for the operation of the electronic device are also stored in the RAM 1403. The processing device 1401, the ROM 1402, and the RAM 1403 are connected to each other via a bus 1404. An input / output (I / O) interface 1405 is also connected to the bus 1404.

[0193] Typically, the following devices may be connected to the I / O interface 1405: an input device 1406 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1407 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1408 including, for example, a memory card, a hard disk, etc.; and a communication device 1409. The communication device 1409 may allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. Although Fig.14 An electronic device having various devices is shown, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0194] An embodiment of the present application also provides a computer program product including computer-readable instructions. When the computer-readable instructions are executed on an electronic device, the electronic device implements a timing analysis method for any chip circuit provided in the embodiment of the present application.

[0195] A computer-readable storage medium is also provided in an embodiment of the present application. The storage medium carries one or more computer programs. When one or more computer programs are executed by an electronic device, the electronic device can implement a timing analysis method for any chip circuit provided in an embodiment of the present application.

[0196] It should also be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the device embodiments provided by the present application, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.

[0197] Through the description of the above implementation mode, the technicians in the field can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course, it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. In general, all functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better implementation mode in more cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, a U disk, a mobile hard disk, a ROM, a RAM, a disk or an optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, a training device, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0198] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0199] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a training device, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, training device, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device, a data center, etc. that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

Claims

1. A timing analysis method for a chip circuit, characterized in that: include: Extracting isomorphic paths from a circuit netlist of a chip circuit to be analyzed to obtain multiple path sets; For each of the path sets, obtaining a delay value of the path set based on a delay value of a target path in the path set, the target path including at least one path; Based on the correlation between the delay value and the difficulty of satisfying the preset timing condition, the path set is sorted from the greatest difficulty to the smallest difficulty of satisfying the timing condition to obtain a path set sequence; According to the sequence of paths corresponding to the timing condition from small to large, whether each path in the path set meets the timing condition is judged until there is no path that does not meet the timing condition in the path set, and the timing analysis result of the chip circuit is output, and the timing analysis result of the chip circuit includes all paths that do not meet the timing condition.

2. The timing analysis method of a chip circuit according to claim 1, characterized in that: The timing conditions include a hold time condition and a setup time condition; Based on the correlation between the delay value and the difficulty of satisfying the preset timing condition, the path set is sorted from large to small according to the difficulty of satisfying the timing condition to obtain a path set sequence, including: For the holding time condition, the path sets are sorted in ascending order according to the delay value to obtain a first path set sequence; For the establishment time condition, each of the path sets is sorted from large to small according to the delay value to obtain a second path set sequence.

3. The timing analysis method of a chip circuit according to claim 2, characterized in that: The acquiring the delay value of the path set based on the delay value of the target path in the path set includes: Selecting at least one path from the path set as a target path; estimating the delay value of each of the target paths; The average value of the delay values ​​of the target paths is used as the delay value of the path set.

4. The timing analysis method of a chip circuit according to claim 2, characterized in that: The delay value of the path set includes a minimum delay value and a maximum delay value, and acquiring the delay value of the path set based on the delay value of the target path in the path set includes: Selecting at least one path from the path set as a target path; Estimating the maximum and minimum delay values ​​of each target path; Taking the minimum value of the delay value of the first target path as the minimum delay value of the path set, wherein the first target path is a path with the smallest minimum delay value among the target paths; The maximum value of the delay value of the second target path is used as the maximum delay value of the path set, and the second target path is a path with the largest maximum delay value among the target paths.

5. The timing analysis method of a chip circuit according to claim 4, characterized in that: For the holding time condition, the path sets are sorted in ascending order according to the delay value to obtain a first path set sequence, including: For the holding time condition, the path sets are sorted in ascending order according to the minimum delay value to obtain a first path set sequence; For the establishment time condition, sorting the path sets from large to small according to the delay value to obtain a second path set sequence includes: For the establishment time condition, each of the path sets is sorted from large to small according to the maximum delay value to obtain a second path set sequence.

6. The timing analysis method of a chip circuit according to claim 3 or 5, characterized in that: The step of judging whether each path in the path set meets the timing condition according to the order of the path set sequence corresponding to the timing condition from small to large, until there is no path in the path set that does not meet the timing condition, and outputting the timing analysis result of the chip circuit includes: According to the order from small to large in the first path set sequence, judging whether each path in each path set meets the hold time condition, until it is determined that there is no path that does not meet the hold time condition in the path sets of a continuous preset number of sets, obtaining a hold time analysis result of the chip circuit, the hold time analysis result including the path that does not meet the hold time condition; According to the order of the second path set sequence from small to large, judging whether each path in each path set meets the setup time condition, until it is determined that there is no path that does not meet the setup time condition in the path sets of a continuous preset number of sets, obtaining a setup time analysis result of the chip circuit, wherein the setup time analysis result includes the path that does not meet the setup time condition; A timing analysis result of the chip circuit is obtained, wherein the timing analysis result includes the hold time analysis result and the setup time analysis result.

7. A timing analysis device for a chip circuit, characterized in that: include: A path set partitioning unit extracts isomorphic paths from a circuit netlist of a chip circuit to be analyzed to obtain a plurality of path sets; A delay characteristic calculation unit, configured to obtain, for each of the path sets, a delay value of the path set based on a delay value of a target path in the path set, wherein the target path includes at least one path; A set sorting unit, configured to sort the path sets from greatest to least difficulty in satisfying the timing conditions based on the correlation between the delay values ​​of the path sets and the difficulty in satisfying the preset timing conditions, to obtain a path set sequence; A timing analysis unit is used to determine whether each path in the path set meets the timing condition according to the sequence of path sets corresponding to the timing condition from small to large, until there is no path that does not meet the timing condition in the path set, and output the timing analysis result of the chip circuit, wherein the timing analysis result of the chip circuit includes all paths that do not meet the timing condition.

8. A computer program product, characterized in that It comprises computer-readable instructions, and when the computer-readable instructions are executed on an electronic device, the electronic device implements the timing analysis method for a chip circuit as claimed in any one of claims 1 to 6.

9. An electronic device, characterized in that: The method comprises at least one processor and a memory connected to the processor, wherein: The memory is used to store computer programs; The processor is used to execute the computer program so that the electronic device can implement the timing analysis method of the chip circuit as described in any one of claims 1 to 6.

10. A computer storage medium, characterized in that: The storage medium carries one or more computer programs, and when the one or more computer programs are executed by an electronic device, the electronic device can implement the timing analysis method for a chip circuit as described in any one of claims 1 to 6.

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