Analog circuit performance index acquisition method and device based on convolutional neural network

Abstract

The invention discloses an analog circuit performance index obtaining method and device based on a convolutional neural network, and relates to the technical field of integrated circuits, and the method comprises the steps: obtaining a to-be-recognized analog circuit, and determining the design parameters of the to-be-recognized analog circuit; according to the structure of the analog circuit to be identified, mapping the design parameters into the two-dimensional space matrix to obtain a two-dimensional sparse matrix corresponding to the design parameters; inputting the two-dimensional sparse matrix into a trained convolutional neural network model for processing to obtain a performance index corresponding to the design parameter; wherein the trained convolutional neural network model takes data of a preset category as a training data set, the initial convolutional neural network model is trained to obtain the trained convolutional neural network model, and the data of the preset category comprises design parameters and calibration performance indexes of the analog circuit of which the type is the same as that of the analog circuit to be identified; the design parameters are in one-to-one correspondence with the calibration performance indexes. The design efficiency of the integrated circuit can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a method and a device for acquiring analog circuit performance indicators based on a convolutional neural network. Background Art

[0002] With the development of science and technology, analog integrated circuits are applied to all aspects of life, which has a profound impact on human technological development and daily life.

[0003] In the design of analog integrated circuits, the optimal design solution is determined by repeatedly running simulation software and comparing performance indicators. This design process is highly dependent on experience. However, the simulation time of the current general analog integrated circuit simulation software is long, resulting in low design efficiency. In addition, with the continuous improvement of the process, the size of the device is also shrinking, which may introduce parasitic parameters and non-ideal factors to the analog integrated circuit, which will cause the traditional circuit equations to not be able to describe the analog integrated circuit well, thereby affecting the accuracy of the design. Therefore, it is very necessary to propose an efficient analog integrated circuit modeling method to improve the design efficiency of analog integrated circuits. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a method and device for obtaining analog circuit performance indicators based on convolutional neural network. The technical problem to be solved by the present invention is achieved through the following technical solutions: In a first aspect, the present invention provides a method for acquiring performance indicators of analog circuits based on a convolutional neural network, comprising: Acquire an analog circuit to be identified, and determine design parameters of the analog circuit to be identified; According to the structure of the analog circuit to be identified, the design parameters are mapped into a two-dimensional space matrix to obtain a two-dimensional sparse matrix corresponding to the design parameters; The two-dimensional sparse matrix is ​​input into the trained convolutional neural network model for processing to obtain the performance indicators corresponding to the design parameters; Among them, the trained convolutional neural network model is obtained by training the initial convolutional neural network model with preset category data as the training data set. The preset category data includes design parameters and calibrated performance indicators of analog circuits of the same type as the analog circuit to be identified, and the design parameters and the calibrated performance indicators correspond one to one.

[0005] In a second aspect, the present invention further provides a device for acquiring performance indicators of analog circuits based on a convolutional neural network, comprising: A design parameter determination device, used to obtain an analog circuit to be identified and determine design parameters of the analog circuit to be identified; A design parameter processing device, used for mapping the design parameters into a two-dimensional space matrix according to the structure of the analog circuit to be identified, and obtaining a two-dimensional sparse matrix corresponding to the design parameters; A performance index acquisition device is used to input the two-dimensional sparse matrix into the trained convolutional neural network model for processing to obtain the performance index corresponding to the design parameters; Among them, the trained convolutional neural network model is obtained by training the initial convolutional neural network model with preset category data as the training data set. The preset category data includes design parameters and calibrated performance indicators of analog circuits of the same type as the analog circuit to be identified, and the design parameters and performance indicators correspond one to one.

[0006] Beneficial effects of the present invention: The present invention provides a method and device for obtaining analog circuit performance indicators based on convolutional neural networks, which maps the design parameters of the analog circuit into a two-dimensional space through sparse topological mapping, and uses a trained convolutional neural network model to process a two-dimensional sparse matrix to obtain performance indicators corresponding to the design parameters. The present invention can better describe the spatial and basic component-level characteristics of analog integrated circuits, has higher modeling accuracy, can replace simulation software and circuit equations for the design of analog integrated circuits, is conducive to improving the efficiency of integrated circuit design, has strong scalability, and has practical value in the automated design of analog integrated circuits.

[0007] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a flow chart of a method for obtaining analog circuit performance indicators based on a convolutional neural network provided by an embodiment of the present invention; Figure 2 is a schematic diagram of sparse topological mapping provided by an embodiment of the present invention; Figure 3 It is a schematic diagram of training a convolutional neural network model provided by an embodiment of the present invention; Figure 4 is a schematic diagram of feature extraction provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of a two-stage Miller compensation operational amplifier circuit in the prior art; Figure 6 It is a schematic diagram of a two-dimensional sparse matrix provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0009] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0010] See also Figure 1 , Figure 1 The present invention provides a flowchart of a method for obtaining analog circuit performance indicators based on a convolutional neural network according to an embodiment of the present invention. The method for obtaining analog circuit performance indicators based on a convolutional neural network provided by the present invention includes: S101 . Obtain an analog circuit to be identified, and determine design parameters of the analog circuit to be identified.

[0011] Specifically, in this embodiment, an analog circuit to be identified of a preset category is selected, and design parameters of the analog circuit to be identified are determined, specifically, basic elements of the analog circuit to be identified are determined, and parameters of the basic elements are used as design parameters. Optionally, the basic elements may be transistors, capacitors or resistors.

[0012] S102 . Mapping the design parameters into a two-dimensional space matrix according to the structure of the analog circuit to be identified, and obtaining a two-dimensional sparse matrix corresponding to the design parameters.

[0013] Specifically, in this embodiment, see Figure 2 , Figure 2 : is a schematic diagram of sparse topological mapping provided by an embodiment of the present invention. The two-dimensional sparse matrix corresponding to the design parameters is obtained through the following process: Determining the spatial position of each basic element of the analog circuit to be identified according to the structure of the analog circuit to be identified; The spatial positions of the basic elements are mapped into a two-dimensional space matrix, the design parameters of the basic elements are filled into the corresponding two-dimensional space matrix, and the positions in the two-dimensional space matrix that do not correspond to the basic elements are filled with 0.

[0014] It should be noted that Figure 2 The embodiment shown schematically shows only a schematic diagram of sparse topological mapping, mapping the analog circuit diagram into a two-dimensional space matrix, dividing the positions of transistors in the analog circuit diagram according to rows and columns, and filling the parameters of the transistors in the analog circuit diagram into the two-dimensional space matrix accordingly. For example, the design parameters of transistor M3 are length He Kuan , transistor M1 and transistor M3 are located in the same column, then the design parameter length of transistor M1 is He Kuan The positions below the design parameters of the transistor M3 in the two-dimensional space matrix are filled with 0s. Positions without corresponding design parameters in the two-dimensional space matrix are filled with 0s.

[0015] S103, inputting the two-dimensional sparse matrix into the trained convolutional neural network model for processing to obtain performance indicators corresponding to the design parameters; Among them, the trained convolutional neural network model is obtained by training the initial convolutional neural network model with preset category data as the training data set. The preset category data includes design parameters and calibrated performance indicators of analog circuits of the same type as the analog circuit to be identified, and the design parameters and the calibrated performance indicators correspond one to one.

[0016] Specifically, in this embodiment, before training the initial convolutional neural network model, the following steps are included: Build a convolutional neural network model; Among them, the convolutional neural network model includes multiple layers of convolutional layers, multiple layers of pooling layers and multiple layers of fully connected layers, the convolutional layers include the first convolutional layer, the second convolutional layer and the third convolutional layer, the pooling layers include the first pooling layer, the second pooling layer and the third pooling layer, and the fully connected layers include the first fully connected layer, the second fully connected layer and the third fully connected layer; the output of the first convolutional layer is connected to the input of the first pooling layer, the output of the first pooling layer is connected to the input of the second convolutional layer, the output of the second convolutional layer is connected to the input of the second pooling layer, the output of the second pooling layer is connected to the input of the third convolutional layer, the output of the third convolutional layer is connected to the input of the third pooling layer, the output of the third pooling layer is connected to the input of the first fully connected layer, the output of the first fully connected layer is connected to the input of the second fully connected layer, the output of the second fully connected layer is connected to the input of the third fully connected layer, and the third fully connected layer outputs the processed one-dimensional vector.

[0017] It should be noted that, in this embodiment, in order to avoid overfitting of the constructed convolutional neural network model and accelerate the training process, a pooling layer is added after each convolution layer; in order to better describe the nonlinear relationship between the characteristics and performance indicators of the integrated circuit, a fully connected layer is used to expand the feature matrix into a one-dimensional vector and fully connected to the neurons in the fully connected layer to improve the performance of the proposed convolutional neural network model.

[0018] In this embodiment, see Figure 3 , Figure 3 It is a schematic diagram of training a convolutional neural network model provided by an embodiment of the present invention. Training the initial convolutional neural network model includes: Obtain a training data set, the training data set includes a plurality of training samples, each training sample includes a two-dimensional sparse matrix corresponding to the design parameters of a preset type of analog circuit and a calibration performance index corresponding to the design parameters; wherein the analog circuit to be identified belongs to the preset type of analog circuit; optionally, in this embodiment, the design parameters and the calibration performance index corresponding to the design parameters are obtained using simulation software; In the In the first iteration, the training data set is input into the convolutional neural network model, and is processed by the first convolutional layer, the first pooling layer, the second convolutional layer, the second pooling layer, the third convolutional layer and the third pooling layer in sequence, and the feature matrix is ​​output. The feature matrix is ​​processed by the first fully connected layer, the second fully connected layer and the third fully connected layer in sequence, and the prediction performance index corresponding to the design parameters is output. The prediction performance index corresponding to the design parameters is compared with the calibration performance index corresponding to the design parameters to update the first iteration. In the iterative process, the weight parameters of the first convolutional layer, the second convolutional layer, and the third convolutional layer are updated until the convergence condition is reached. The trained convolutional neural network model is constructed according to the updated weight parameters of the first convolutional layer, the second convolutional layer, and the third convolutional layer.

[0019] In this embodiment, the traditional machine learning method usually inputs the design parameters in the form of a vector structure, and the processing method for the design parameter data structure is too simple and cannot capture the spatial position information of the analog integrated circuit. In view of this, this embodiment proposes a sparse topological mapping method for the input data structure, that is, extracting the analog integrated circuit design parameters and mapping them to a sparse matrix containing the spatial characteristics of the analog integrated circuit and the characteristics of the basic components. According to the circuit structure, the design parameters of each basic component are filled into the corresponding two-dimensional space, and the remaining space is filled with zeros. The sparse mapping process is as follows: Figure 2 Through this method, the spatial information of the analog integrated circuit and the basic component parameter information can be well reflected in the constructed sparse matrix. Compared with the traditional input vector form, it can more comprehensively reflect the analog integrated circuit information and facilitate the subsequent training and learning of the convolutional neural network.

[0020] It should be noted that, in this embodiment, the design parameters and the calibration performance indicators corresponding to the design parameters are obtained by using Cadence software, and then the design parameters are converted into a two-dimensional sparse matrix.

[0021] In this embodiment, see Figure 4 , Figure 4 is a schematic diagram of feature extraction provided by an embodiment of the present invention. The iteration process also includes: The first convolutional layer extracts the basic component-level features in the training data set through a movable window with weights to obtain the first feature; The second convolutional layer extracts the circuit module level features in the first feature through a movable window with weights to obtain the second feature; The third convolutional layer extracts the integrated circuit level features in the second features through a movable window with weights to obtain the third features.

[0022] It is understandable that the performance indicators of analog integrated circuits are closely related to the parameters of basic components. However, due to the influence of external factors, parasitic effects and non-ideal factors may exist in analog integrated circuits. The relationship between design indicators and performance indicators is very complex, and traditional circuit equations can no longer describe the nonlinear mapping relationship between the two. Therefore, it is necessary to decompose analog integrated circuits in layers and extract their key features to accurately describe the relationship between their design parameters and performance indicators. The feature extraction process of analog integrated circuits is similar to the natural language understanding process. Through simulation analysis of analog integrated circuits, the characteristics of analog integrated circuits can be divided into three levels, namely basic component level features, circuit module level features, and integrated circuit level features, such as Figure 4 As shown in the figure, the basic component level features are used as the basic units of analog integrated circuits to describe the impact of each basic unit on the performance indicators. The circuit module level features are used as the basic functional units to describe the impact of specific circuit modules (such as amplifiers, inverters, and NAND gates) composed of basic components on the overall circuit performance indicators. The integrated circuit level features are used to comprehensively describe the impact of the circuit level characteristic performance indicators of the overall integrated circuit composed of circuit modules. Through the above analysis, the analog integrated circuit can be described from local to global, thereby improving the modeling accuracy.

[0023] It should be noted that if Figure 3 As shown, convolution layer 1 is the first convolution layer, pooling layer 1 is the first pooling layer, convolution layer 2 is the second convolution layer, pooling layer 2 is the second pooling layer, convolution layer 3 is the third convolution layer, pooling layer 3 is the third pooling layer, the input features are processed by convolution layer 1 and pooling layer 1 to output transistor-level features, the transistor-level features are processed by convolution layer 2 and pooling layer 2 to output circuit module-level features, the circuit module-level features are processed by convolution layer 3 and pooling layer 3 to output integrated circuit-level features, and the integrated circuit-level features are processed by 3 layers of fully connected layers to output performance indicators corresponding to the design parameters, as shown in FIG. Figure 3 The output performance indicators shown can be gain, gain bandwidth product (GBW), slew rate (SR), power consumption (P), etc.; transistor-level characteristics, circuit module-level characteristics, and integrated circuit-level characteristics such as Figure 4 shown.

[0024] In this embodiment, the size of the convolution kernel in the convolution layer determines the effectiveness of feature extraction. A convolution kernel that is too small will miss some overall information, resulting in poor overall feature extraction capability, while a convolution kernel that is too large may miss some local information and cause too long training time due to too many parameters. Therefore, the appropriate convolution kernel size should be determined based on the input two-dimensional sparse matrix of the analog integrated circuit. In the iteration process, the expression of the size of the convolution kernel of the convolution layer is: ; in, represents the convolution kernel order, represents the ceiling function, represents the number of design parameters, represents the number of rows of the two-dimensional sparse matrix corresponding to the design parameters, Represents the number of columns of the two-dimensional sparse matrix corresponding to the design parameters. The sizes of the convolution kernels of the first convolution layer, the second convolution layer, and the third convolution layer are the same.

[0025] In this embodiment, In the iteration process, the expressions of the convolution operations of the first convolution layer, the second convolution layer and the third convolution layer are: ; in, Indicates Line The result of the column operation, Represents the total number of rows in the matrix, Represents the total number of columns of the matrix, represents the number of rows of the matrix, represents the number of columns of the matrix, Indicates Line The weight value of the column, Indicates Line Column input.

[0026] In this embodiment, the features extracted from the analog integrated circuit often contain a lot of redundant information. By periodically adding pooling layers, the spatial dimension of the features can be reduced, thereby reducing the number of training parameters and computational cost of the constructed convolutional neural network model. In order to avoid overfitting of the constructed convolutional neural network model and accelerate the training process, a pooling layer is added after each convolution layer, and the maximum pooling method is selected, that is, 2 2 maximum value in the range; During the iteration, the operation expressions of the first pooling layer, the second pooling layer and the third pooling layer are: ; in, Represents the result of the maximum pooling operation, Represents the input of the pooling layer.

[0027] Optionally, the setting of the pooling layer stride should be determined according to the scale of the analog integrated circuit. For smaller circuit scales, the stride is selected as 1, while for larger circuits, the stride can be set to 2. By performing the maximum pooling operation on each convolutional layer, the data can be effectively simplified and the training speed of the constructed convolutional neural network model can be improved.

[0028] In order to better describe the nonlinear relationship between the analog integrated circuit features extracted by convolution and the performance indicators, the feature matrix is ​​expanded into a one-dimensional vector and fully connected to the neurons in the fully connected layer to improve the performance of the constructed convolutional neural network model; experiments have shown that the convolutional neural network model with 3 fully connected layers has the best accuracy.

[0029] In summary, the present invention provides a method for obtaining analog circuit performance indicators based on convolutional neural networks. The design parameters of the analog circuit are mapped into a two-dimensional space through sparse topological mapping, and three convolutional layers are used to respectively extract the basic component-level features, circuit module-level features and integrated circuit-level features in the analog circuit. Compared with the traditional analog circuit modeling method, the present invention can better describe the analog integrated circuit space and basic component-level features, has higher modeling accuracy, can replace simulation software and circuit equations for the design of analog integrated circuits, is conducive to improving the efficiency of integrated circuit design, has strong scalability, and has practical value in the automated design of analog integrated circuits.

[0030] In an optional embodiment of the present invention, in order to verify the effectiveness of the method provided in the above embodiment, a two-stage Miller compensation operational amplifier circuit (TSMCOA) is used as an example for verification. The circuit schematic diagram is shown in FIG. Figure 5 As shown. The high-precision and comprehensive Cadence software is selected to simulate the circuit. The first stage of TSMCOA is a differential amplifier, which consists of NMOS input tubes (M1, M2) and PMOS current mirror load tubes (M3, M4). Transistors M5 and M8 that provide bias current are used for the first-stage bias. The second stage is a common-source amplifier composed of PMOS input tube M6 and NMOS current source load tube M7. In TSMCOA, M1, M3, and M5 are matched with M2, M4, and M8 respectively; among them, the gain (Av) of TSMCOA is the core indicator to measure the performance of the circuit. At the same time, a higher unit gain bandwidth (UGB) can expand the operating frequency range of TSMCOA and improve the circuit speed. The phase margin can ensure the stability of TSMCOA, and the power consumption can determine the cost of the entire circuit. Therefore, in order to fully describe TSMCOA, select , , , , , , , , , , , , , As the design parameters of TSMCOA, the value ranges of all circuit design parameters are listed in Table 1. AV, UGB, phase margin and power consumption are used as performance indicators to measure the quality of TSMCOA.

[0031] Table 1 Design parameters and performance indicators

[0032] For the selected performance indicators, the traditional circuit equations are derived. Among them, the size of the transistor ( , ) determines the transconductance parameter of the transistor , which can be expressed as: ; in, represents the transistor source-drain current, represents the mobility of carriers in the transistor, Multiplying together gives the total capacitance per unit length, Represents the gate length of the transistor; the circuit equations of Av, UGB, phase margin and power consumption are derived based on the transconductance of the relevant transistor, and the expressions are: ; ; ; ; , , ; in, represents the total gain, represents the gain of the first stage of TSMCOA, represents the gain of the second stage of TSMCOA, represents the internal resistance of the transistor itself, represents the transconductance parameter of the transistor, represents the TSMCOA first-stage output resistance, represents the TSMCOA second-stage output resistance, represents the Miller capacitance, represents the load capacitance of TSMCOA, Indicates the power supply voltage, is the total current in the circuit, Indicates power.

[0033] Through the derivation of the equations of various performance parameters of TSMCOA through the above content, it can be found that there is a nonlinear mapping relationship between the gain (Av) and the size of transistors M1, M2, and M6, while the unit gain bandwidth (UGB) is related to the size of transistor M1. However, the traditional approximate equation only considers ideal conditions, without considering parasitic effects and non-ideal factors. The current replication accuracy of the load tube and the current mirror will also affect these performance indicators; at the same time, the traditional machine learning method will list these design parameters as a one-dimensional vector for input, so that the network constructed later cannot learn the spatial information of TSMCOA. Therefore, it is necessary to use the input parameter sparse topological mapping method provided by the present invention and the convolutional neural network model constructed for extracting circuit features to effectively describe TSMCOA. According to the TSMCOA schematic diagram, the selected design parameters are transformed into a 6-dimensional vector through the sparse topological mapping method. 4 matrix to reflect the characteristics of transistors and circuit space, such as Figure 6 As shown, Figure 6 It is a schematic diagram of a two-dimensional sparse matrix provided by an embodiment of the present invention.

[0034] According to the proposed convolution kernel calculation formula, the convolution kernel size for the convolution layer of TSMCOA is calculated to be 3 3, to ensure that the minimum features in the circuit can be learned, the transistor-level features, circuit module-level features, and integrated circuit-level features are extracted step by step through three layers of convolutional layers. At the same time, in order to simplify the number of features and speed up the training process, 2 convolutional layers are placed after each convolutional layer. 2 maximum pooling layer, and finally flatten the extracted features into a one-dimensional vector and connect three fully connected layers, so as to establish a nonlinear mapping relationship between TSMCOA design parameters and related performance indicators. Through Cadence simulation, 59049 sets of data corresponding to the design parameters of Av, UGB, PM, and P were obtained. Among them, 58,000 sets of data were selected as training sets and 1049 sets of data were selected as test sets. In order to improve the convergence speed and convergence effect of the regression process, the "sgdm" optimizer was used, and the learning rate was selected based on experience. According to the constructed data set, the convolutional neural network model of TSMCOA was trained. In order to evaluate the performance of the constructed convolutional neural network model, the The coefficient of determination is an indicator. The coefficient of determination is an evaluation index of the model. Its maximum value is 1 and its minimum value is 0. The closer the value is to 1, the better the model is. The formula for calculating the coefficient of determination is: ; in, Indicates the calibration performance index, represents the prediction performance indicator, Indicates the average value of the calibration performance index.

[0035] After calculation, the fitting accuracy values ​​of the constructed convolutional neural network model for each performance index are all above 0.999, which proves the effectiveness of the proposed method.

[0036] Based on the same inventive concept, the present invention also provides a device for acquiring analog circuit performance indicators based on a convolutional neural network, which is used to implement the method provided in the above embodiment. Please refer to the above for the method embodiment, which will not be repeated here. The device includes: A design parameter determination device, used to obtain an analog circuit to be identified and determine design parameters of the analog circuit to be identified; A design parameter processing device, used for mapping the design parameters into a two-dimensional space matrix according to the structure of the analog circuit to be identified, and obtaining a two-dimensional sparse matrix corresponding to the design parameters; A performance index acquisition device is used to input the two-dimensional sparse matrix into the trained convolutional neural network model for processing to obtain the performance index corresponding to the design parameters; Among them, the trained convolutional neural network model is obtained by training the initial convolutional neural network model with preset category data as the training data set. The preset category data includes design parameters and calibrated performance indicators of analog circuits of the same type as the analog circuit to be identified, and the design parameters and the calibrated performance indicators correspond one to one.

[0037] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0038] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0039] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for obtaining performance indicators of analog circuits based on convolutional neural networks, characterized in that: include: Acquire an analog circuit to be identified, and determine design parameters of the analog circuit to be identified; According to the structure of the analog circuit to be identified, the design parameters are mapped into a two-dimensional space matrix to obtain a two-dimensional sparse matrix corresponding to the design parameters; Inputting the two-dimensional sparse matrix into a trained convolutional neural network model for processing to obtain performance indicators corresponding to the design parameters; Among them, the trained convolutional neural network model is obtained by training the initial convolutional neural network model with preset category data as the training data set, and the preset category data includes design parameters and calibration performance indicators of analog circuits of the same type as the analog circuit to be identified, and the design parameters and the calibration performance indicators correspond one to one.

2. The method for acquiring analog circuit performance indicators based on convolutional neural network according to claim 1, characterized in that: According to the structure of the analog circuit to be identified, the design parameters are mapped into a two-dimensional space matrix to obtain a two-dimensional sparse matrix corresponding to the design parameters, including: Determining the spatial position of each basic element of the analog circuit to be identified according to the structure of the analog circuit to be identified; The spatial positions of the basic elements are mapped into a two-dimensional spatial matrix, the design parameters of the basic elements are filled into the corresponding two-dimensional spatial matrix, and the positions in the two-dimensional spatial matrix that do not correspond to the basic elements are filled with 0.

3. The method for acquiring analog circuit performance indicators based on convolutional neural network according to claim 1, characterized in that: The basic elements include transistors, capacitors or resistors.

4. The method for acquiring analog circuit performance indicators based on convolutional neural network according to claim 1, characterized in that: Before training the initial convolutional neural network model, including: Build a convolutional neural network model; Among them, the convolutional neural network model includes multiple layers of convolutional layers, multiple layers of pooling layers and multiple layers of fully connected layers, the convolutional layers include the first convolutional layer, the second convolutional layer and the third convolutional layer, the pooling layers include the first pooling layer, the second pooling layer and the third pooling layer, and the fully connected layers include the first fully connected layer, the second fully connected layer and the third fully connected layer; the output of the first convolutional layer is connected to the input of the first pooling layer, the output of the first pooling layer is connected to the input of the second convolutional layer, the output of the second convolutional layer is connected to the input of the second pooling layer, the output of the second pooling layer is connected to the input of the third convolutional layer, the output of the third convolutional layer is connected to the input of the third pooling layer, the output of the third pooling layer is connected to the input of the first fully connected layer, the output of the first fully connected layer is connected to the input of the second fully connected layer, the output of the second fully connected layer is connected to the input of the third fully connected layer, and the third fully connected layer outputs the processed one-dimensional vector.

5. The method for acquiring analog circuit performance indicators based on convolutional neural network according to claim 4, characterized in that: Training the initial convolutional neural network model includes: Acquire a training data set, the training data set comprising a plurality of training samples, each training sample comprising a two-dimensional sparse matrix corresponding to design parameters of a preset type of analog circuit and a calibration performance index corresponding to the design parameters; wherein the analog circuit to be identified belongs to the preset type of analog circuit; In the In the first iteration process, the training data set is input into the convolutional neural network model, and is processed by the first convolution layer, the first pooling layer, the second convolution layer, the second pooling layer, the third convolution layer and the third pooling layer in sequence, and a feature matrix is ​​output. The feature matrix is ​​processed by the first fully connected layer, the second fully connected layer and the third fully connected layer in sequence, and the prediction performance index corresponding to the design parameter is output. The prediction performance index corresponding to the design parameter is compared with the calibration performance index corresponding to the design parameter to update the first iteration process. During the iteration process, the weight parameters of the first convolutional layer, the second convolutional layer and the third convolutional layer are updated until the convergence condition is reached, and a trained convolutional neural network model is constructed according to the updated weight parameters of the first convolutional layer, the second convolutional layer and the third convolutional layer.

6. The method for acquiring analog circuit performance indicators based on convolutional neural network according to claim 5, characterized in that: In the The iteration process also includes: The first convolutional layer extracts basic component-level features in the training data set through a movable window with a weight to obtain a first feature; The second convolutional layer extracts the circuit module level feature in the first feature through a movable window with a weight to obtain a second feature; The third convolutional layer extracts the integrated circuit level features in the second features through a movable window with weights to obtain the third features.

7. The method for acquiring analog circuit performance indicators based on convolutional neural network according to claim 5, characterized in that: In the In the iteration process, the expression of the size of the convolution kernel of the convolution layer is: ； in, represents the convolution kernel order, represents the ceiling function, represents the number of design parameters, represents the number of rows of the two-dimensional sparse matrix corresponding to the design parameters, The number of columns of the two-dimensional sparse matrix corresponding to the design parameters is represented, and the sizes of the convolution kernels of the first convolution layer, the second convolution layer, and the third convolution layer are the same.

8. The method for acquiring analog circuit performance indicators based on convolutional neural network according to claim 5, characterized in that: In the In the iteration process, the expressions of the convolution operations of the first convolution layer, the second convolution layer and the third convolution layer are: ； in, Indicates Line The result of the column operation, Represents the total number of rows in the matrix, Represents the total number of columns of the matrix, represents the number of rows of the matrix, represents the number of columns of the matrix, Indicates Line The weight value of the column, Indicates Line Column input.

9. The method for acquiring analog circuit performance indicators based on convolutional neural network according to claim 5, characterized in that: In the During the iteration, the expressions of the pooling operations of the first pooling layer, the second pooling layer and the third pooling layer are: ； in, Represents the result of the maximum pooling operation, Represents the input of the pooling layer.

10. A device for acquiring analog circuit performance indicators based on convolutional neural network, characterized in that: include: A design parameter determination device, used to obtain an analog circuit to be identified and determine design parameters of the analog circuit to be identified; A design parameter processing device, used for mapping the design parameters into a two-dimensional space matrix according to the structure of the analog circuit to be identified, so as to obtain a two-dimensional sparse matrix corresponding to the design parameters; A performance indicator acquisition device, used for inputting the two-dimensional sparse matrix into a trained convolutional neural network model for processing to obtain performance indicators corresponding to the design parameters; Among them, the trained convolutional neural network model is obtained by training the initial convolutional neural network model with preset category data as the training data set, and the preset category data includes design parameters and calibration performance indicators of analog circuits of the same type as the analog circuit to be identified, and the design parameters and the calibration performance indicators correspond one to one.

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