Thermoelectric coupling simulation method for early integrated circuit design stage

Abstract

The present invention discloses a thermoelectric coupling simulation method for the early design stage of integrated circuits, which relates to the field of integrated circuit analysis technology. The method comprises: characterizing all standard cells in a process library at different temperatures and obtaining lib files; synthesizing and analyzing the power consumption of the circuit under these lib files, and establishing a temperature-module power consumption table for the circuit; inputting the power consumption of each module of the circuit into a thermal simulation tool HotSpot at an initial temperature to perform thermoelectric coupling simulation and obtain the initial simulation temperature of each module; obtaining the power consumption of each module in the table according to the last simulation temperature, and performing simulation again to obtain the current simulation temperature; iterating the above steps and calculating the difference in simulation temperatures obtained by two adjacent simulations; redesigning the circuit, the layout of each module, and the boundary conditions of the chip package according to whether the iteration converges and the temperature difference. The present invention is used to obtain reliable chip temperature distribution and layout optimization in early circuit design.

Description

Technical Field

[0001] The present invention belongs to the technical field of early design analysis of integrated circuits, and in particular relates to a thermoelectric coupling simulation method for the early design stage of integrated circuits. Background Art

[0002] As semiconductor process nodes shrink, power density increases. This rapid increase in power consumption poses challenges to overall system temperature, making managing the heat generated by the system a critical issue in circuit design. The rising heat in such systems can result in expensive packaging and cooling costs, and significantly reduce the performance, lifespan, and reliability of computing systems. Therefore, thermal analysis is essential in chip design. Traditional thermal analysis relies on multi-physics simulation tools based on the finite element method (FEM), such as COMSOL and ANSYS. However, these commercial simulation tools have high computational costs and long solution times. These limitations make commercial simulation tools unsuitable for evaluating early-stage circuit designs (i.e., RTL-level circuits), circuit design schemes, and numerous operational scenarios. Therefore, fast and accurate thermal analysis is crucial for chip design and thermal optimization.

[0003] Static or leakage power is the power consumed by a circuit when it is not operating under any load. The primary source of leakage power is subthreshold leakage current, which occurs when a small amount of current flows. This occurs when the gate-source voltage (Vgs) of a MOS device is below the threshold voltage (Vth). Subthreshold leakage current increases exponentially with increasing temperature. In large-scale circuits operating at high temperatures, the impact of leakage power cannot be ignored to accurately obtain operating temperatures. When researching thermal-aware and power-aware simulation techniques, because rising circuit temperature increases leakage power, and rising power consumption in turn increases circuit temperature, this feedback loop between temperature and leakage power needs to be addressed to ensure their effectiveness in chip-level or system-level designs. Several studies have explored the challenges of leakage power in thermal simulation, primarily using linear or piecewise-linear leakage power models and leakage-aware thermal simulation methods based on Green's functions. Other approaches describe the relationship between leakage power and temperature as an empirical formula to provide temperature-power feedback. However, these methods fail to accurately consider the impact of different process and circuit functions on the overall circuit power consumption and operating temperature, a pressing issue in circuit thermal simulation. Summary of the Invention

[0004] In view of the above, the present invention provides a thermoelectric coupling simulation method for the early design stage of integrated circuits, which is used to obtain reliable chip temperature distribution and layout optimization in early circuit design.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention discloses a thermoelectric coupling simulation method for the early design stage of integrated circuits, comprising the following steps:

[0007] 1) Perform unit characterization on all standard units in the process library at different temperatures, and the unit characterization results at one temperature constitute a lib file;

[0008] 2) Perform logic synthesis and power consumption analysis on the RTL netlist corresponding to the chip to be simulated for thermoelectric coupling and the lib file at each temperature, obtain the power consumption of each module in the RTL netlist at each temperature, and establish a temperature-module power consumption table;

[0009] 3) Perform a thermoelectric coupling simulation of the power consumption of each module. For the first simulation, select an initial temperature at random. Input the power consumption of each module at that temperature from the temperature-module power consumption table into the thermal simulation tool HotSpot for simulation to obtain the initial simulation temperature of each module.

[0010] In the next simulation, find the power consumption of each module corresponding to the previous simulation temperature in the temperature-module power consumption table, input the power consumption into the thermal simulation tool HotSpot for simulation, obtain the current simulation temperature of each module, and calculate the difference between the simulation temperatures obtained in two adjacent thermal simulations;

[0011] When the difference in the simulated temperatures is less than a preset standard value, the thermoelectric coupling simulation operation is terminated, the simulated temperature of each module during the last simulation is obtained, and the layout planning of each module in the chip is optimized based on the obtained simulated temperature.

[0012] Furthermore, in step 2), before performing logic synthesis and power consumption analysis, the library compiler tool is used to convert the lib file into a db file.

[0013] Furthermore, in step 2), the logic synthesis and power consumption analysis are implemented by Design Compiler; when using Design Compiler for logic synthesis and power consumption analysis, the input of the Design Compiler also includes timing constraints, and the timing constraints include clock period, clock offset, clock delay, input delay and output delay.

[0014] Furthermore, in step 2), the initial temperature is 25°C.

[0015] Furthermore, in step 3), if the last simulation temperature falls between two adjacent temperature values ​​in the table, linear interpolation is used to obtain the power consumption value of each module at the simulation temperature.

[0016] Furthermore, in step 3), when the temperature difference between two adjacent simulations increases continuously in successive thermoelectric coupling simulations, resulting in thermal runaway, the RTL level circuit design and the boundary conditions of the chip package are modified.

[0017] In a second aspect, the present invention discloses a thermoelectric coupling simulation system for implementing the method, comprising:

[0018] The lib file acquisition module is used to perform unit characterization on all standard units in the process library at different temperatures. The unit characterization results at one temperature constitute a lib file.

[0019] The temperature-module power consumption table acquisition module is used to perform logic synthesis and power consumption analysis on the RTL-level netlist corresponding to the chip to be simulated for thermoelectric coupling and the lib file at each temperature, obtain the power consumption of each module in the RTL-level netlist at each temperature, and establish a temperature-module power consumption table;

[0020] Thermoelectric coupling simulation module is used to perform successive thermoelectric coupling simulations on the power consumption of each module. During the first simulation, an initial temperature is selected, and the power consumption of each module at that temperature from the temperature-module power consumption table is input into the thermal simulation tool HotSpot for thermal simulation to obtain the initial simulation temperature of each module.

[0021] In the next simulation, find the power consumption of each module corresponding to the previous simulation temperature in the temperature-module power consumption table, input the power consumption into the thermal simulation tool HotSpot for simulation, obtain the current simulation temperature of each module, and calculate the difference between the simulation temperatures obtained in two adjacent simulations;

[0022] The optimization module is used to compare the difference in simulation temperature with a preset standard value. When the difference in simulation temperature is less than the preset standard value, the thermal simulation operation is terminated, the simulation temperature of each module during the last thermal simulation is obtained, and the layout planning of each module in the chip is optimized based on the obtained simulation temperature. When the temperature difference between two adjacent simulations continues to increase in successive thermoelectric coupling simulations, resulting in thermal runaway, the RTL-level circuit design and the boundary conditions of the chip package are modified.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The present invention adopts technical methods such as standard cell characterization, circuit logic synthesis and power consumption analysis. From the power consumption analysis of each module of the RTL-level code circuit to the feedback considering the manufacturing process, leakage power consumption and temperature, a chip-level thermoelectric coupling simulation method is proposed. This method overcomes the defects of the simulation methods in existing thermoelectric coupling technology, which do not consider leakage power consumption or consider leakage power consumption but not the manufacturing process. Thus, a thermal simulation method with smaller error than the method of using empirical formulas to process leakage power consumption in the open source thermal simulation tool HotSpot is achieved (based on the commercial thermal simulation tool Icepak). Based on the difference in simulation temperature obtained from two adjacent thermal simulations, the layout planning of each module in the chip is optimized, and the optimal module layout planning is finally obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the framework of the detailed thermal simulation method of the entire invention;

[0026] Figure 2 This is a schematic diagram of how the power consumption of a pulsating array circuit changes with increasing temperature;

[0027] Figure 3 This is a schematic diagram of chip layering during thermal simulation. DETAILED DESCRIPTION

[0028] The present invention will be further described and illustrated below in conjunction with specific embodiments. The embodiments are merely illustrative of the present disclosure and do not limit its scope. The technical features of the various embodiments of the present invention may be combined accordingly, provided that there is no conflict between them.

[0029] The present invention provides a thermoelectric coupling simulation method for the early design stage of integrated circuits, the method comprising the following steps:

[0030] 1) Use the Cadence Liberate tool to characterize all standard cells in the process library at different temperatures. Perform a complete characterization process for each temperature and ultimately obtain the lib files at these temperatures.

[0031] 2) Perform logic synthesis and power analysis on the RTL (Register Transfer Level) netlist to be analyzed and the lib files at each temperature to obtain the power consumption of each module in the RTL netlist at each temperature. At this time, a temperature-module power consumption table is created, corresponding to the block0 power, block1 power, ...blockn power at temperatures T0, T1 ... Tm. One variable in this table is temperature, and the other variable is the module in the circuit. The table contains the different power consumption of each module at different temperatures.

[0032] Logic synthesis is the process of converting a digital circuit design described in a high-level abstract form such as a hardware description language (HDL) into a gate-level netlist. A gate-level netlist is a form of representing a circuit structure using logic gates (such as AND gates, OR gates, and NOT gates) and their connections. Power consumption analysis refers to obtaining the dynamic power consumption and leakage power consumption consumed by an electronic device or circuit during operation.

[0033] 3) The table lookup process is based on a compact thermal model, HotSpot, which uses inputs such as the power consumption of each module, the layout of all modules, and the characteristics of the packaging materials. During the first iteration, the power consumption of each module at 25°C is read and used as input to the HotSpot thermal simulation method. The first thermal simulation process completes, yielding the temperatures of all modules or the entire chip temperature distribution.

[0034] At the beginning of the second iteration, the previous temperature result is used to look up the power consumption of each module at the previous simulation temperature in the created table. The power consumption obtained from the table lookup is used as the input of the thermal simulation to simulate the temperature of each module or the temperature distribution of the entire chip. The temperature difference between the simulated temperatures obtained from two adjacent thermal simulations is also calculated.

[0035] Thermal simulation is performed repeatedly and iteratively. If the temperature difference is less than a preset standard value, the temperature is considered to have converged and the thermal simulation operation is terminated. The simulation temperature of each module during the last thermal simulation is obtained, and the layout plan of each module is optimized based on the obtained module simulation temperature. When the temperature difference between two adjacent simulations continues to increase in successive thermoelectric coupling simulations, resulting in thermal runaway, the RTL-level circuit design and the boundary conditions of the chip package are modified. Optimizing the layout plan of each module includes separating two or more adjacent modules with higher temperatures and preventing them from continuing to be close together. Modifying the RTL-level circuit and modifying the boundary condition design of the chip package is to avoid thermal runaway.

[0036] After application, the present invention considers the impact of leakage power consumption on chip temperature according to actual conditions and creates a table related to power consumption and temperature. This table can be used for thermal simulation of the present invention on the HotSpot architecture, and can also be used in the commercial software ANSYS icepak to modify the power consumption of the heat source to temperature-dependent power consumption, and fill the table relationship into its power consumption setting to complete the thermal simulation of the commercial tool considering leakage power consumption.

[0037] The power consumption input by the thermal simulation method includes dynamic power consumption and leakage power consumption. The main source of leakage power consumption is subthreshold leakage current, which occurs when a small amount of current flows. When the gate-source voltage Vgs in the MOS device is lower than the threshold voltage Vth, the leakage current is affected by temperature. The subthreshold leakage current increases exponentially with increasing temperature, as shown in the formula:

[0038]

[0039] Among them, I subthreshold is the subthreshold leakage current; A s is a process-related constant; V th is the threshold voltage; L and W are the effective device channel length and width; V GS is the gate-source voltage; n is the subthreshold swing coefficient of the transistor; V DS is the drain-source voltage; v T is the thermal voltage k is the Boltzmann constant, T is the temperature in Kelvin, and q is the charge of the electron.

[0040] In large-scale circuits operating at high temperatures, the impact of leakage power consumption cannot be ignored to accurately obtain operating temperatures. When researching thermal- and power-aware simulation technologies, since rising circuit temperature increases leakage power consumption, and rising power consumption in turn increases circuit temperature, this temperature and leakage power feedback loop must be resolved to ensure their effectiveness in chip- or system-level designs.

[0041] In order to create an accurate power consumption model related to temperature fluctuations, the present invention uses the Cadence Liberate tool to characterize standard cells using SPICE (Simulation Program with Integrated Circuit Emphasis, a simulation program focusing on integrated circuits). The standard cells include AND / OR gates, multipliers, etc. The purpose of standard cell characterization is to create a set of high-quality standard cell libraries to accurately and efficiently simulate the behavior of standard cells in actual circuits. These model sets are used for different purposes by a variety of different digital design tools. The cell characterization output uses an industry standard format (such as the Synopsys Liberty (.lib) format). The lib file includes information such as timing and power consumption of the standard cell under different inputs.

[0042] Table 1 Schematic diagram of input files required for Liberate characterization

[0043]

[0044]

[0045] As shown in Table 1, in the MODELS folder, files with the .scs extension contain device models with process corners. In the NETLIST folder, netlists contains the SPICE-formatted layout netlist. In the TEMPLATE folder, the template.tcl file contains all input signal conversion times and output capacitance loads, pin lists, cell names, and cell definitions (including delay templates, power templates, and constraint templates). Standard cell definitions can be obtained from existing lib files in the process library. The userdata.lib file contains all standard cell areas and pins. The char.tcl file contains all environmental variables such as voltage and temperature; sub-standard cell settings include NMOS, PMOS, and diode configurations to accurately reflect the transistor configuration of the process being characterized; then, write the NLDM, CCS, or ECSM model in the .lib file and name the lib file according to the PVT (process, voltage, temperature) conditions and the different models used.

[0046] See Figure 1 As shown, it is a framework diagram of the thermal simulation method in the entire invention.

[0047] At the beginning of cell characterization, each standard cell is characterized at different temperatures. In the setup.tcl script, a specific embodiment of the present invention defines temperature conditions from 25°C to 125°C, with a temperature gradient of 5°C, for a total of 21 different temperature settings. This range covers the operating temperature range of the chip under non-special circumstances. For each temperature, a complete characterization process is performed, and other input information remains unchanged, corresponding to the TSMC 28nm process library. It is worth noting that under the same input conditions, the leakage power consumption of the same standard cell will increase with increasing temperature.

[0048] Logic synthesis and power analysis are crucial components of the circuit design process. Logic synthesis inputs include not only RTL code and constraint files (such as SDCs defining clock and timing constraints), but also a process-specific standard cell target library in db format. This db file is converted from a lib file using the Library Compiler tool (i.e., the lib file is converted to a db file using the Library Compiler tool before performing logic synthesis and power analysis). The synthesis tool uses the information in the db file to select appropriate standard cells to implement the design, meeting performance requirements while optimizing cost. To prevent the logic synthesis tool from performing different optimizations on the RTL netlist under different temperature conditions, resulting in variations in the final mapped netlist, a specific embodiment of the present invention uniformly uses a gate-level netlist synthesized at 25°C (i.e., a mapped netlist output at 25°C) as input for power analysis across the entire temperature range. Subsequently, power analysis is performed using the lib files corresponding to different temperatures, outputting the total power consumption of the RTL circuit at the specific temperature for each file. This ensures that power analysis at different temperatures is performed on the same mapped netlist, thereby improving the reliability of experimental results.

[0049] After logic synthesis, the mapped gate-level netlist, the characterized and converted db file, and the timing constraints (including clock period, clock offset, clock delay, input delay, output delay, etc.) are input into Design Compiler, which can also be used for early design power consumption analysis. The present invention uses vectorless power analysis to define the switching rate of the node to perform power consumption estimation. Then, "report power" is used to obtain the dynamic power consumption and leakage power consumption of the RTL circuit under a specific process and temperature. This process of outputting power consumption requires repeatedly reading the lib files of T0, T1, ... Tm, and finally obtaining block0 power, block1 power, ... blockn power at temperatures of T0, T1, ... Tm, and establishing a temperature-module power consumption table for a specific process and circuit.

[0050] After the table is created, the thermal simulation process begins, taking into account iterative feedback on temperature and power consumption through table lookup. This table lookup process is based on the thermal simulation method of a compact thermal model called HotSpot. The inputs to the thermal simulation include the power consumption of each module, the layout plan of all modules (i.e., the position of each module in the circuit, the length and width of each module), and the packaging material properties (i.e., the thermal conductivity of the material, the length, width, and thickness of the material, the ambient temperature, and the boundary conditions of the chip package, such as the thermal resistance between the chip's outermost heat sink fins and the air).

[0051] See Figure 3Figure 1 shows the chip's layered structure during the thermal simulation process. The present invention uses only upward heat dissipation in thermal simulations. Therefore, the circuit package boundary conditions only consider the thermal resistance between the topmost heat sink fins and the air, ignoring the thermal resistance between the printed circuit board (PCB) and the air during downward heat dissipation.

[0052] In the first iteration, a specific embodiment of the present invention reads the power consumption of each module at 25°C in the table, completes the first thermal simulation process, and obtains the temperature of all modules. Starting from the second iteration, the previous temperature results will be used to find the power consumption of each module at that temperature from the created table, and the power consumption obtained from the table is subjected to thermal simulation to obtain the temperature of each module. The above is the simulation process of the block model. In the grid model, it is first necessary to complete the mapping from the chip temperature distribution map obtained by simulation to the module temperature, and then look up the table to obtain the power consumption of each module at that temperature, and then input it into the thermal simulation tool to solve the chip temperature distribution map, and then map it to the block temperature again. Iterate in this way until the power consumption and temperature converge. In this process, since the temperature variables in the table are discrete variables with an interval of 5°C, when the simulation temperature falls between the temperature variables in the table, linear interpolation will be used between adjacent temperatures to obtain a more accurate power consumption value. Within the range of every 5°C, the temperature power consumption curve can be considered linear.

[0053] The entire process is repeated until the temperature difference between two iterations meets the convergence criterion (i.e., the temperature difference is less than a preset standard value. In one embodiment of the present invention, the preset standard value is 0.1°C). Alternatively, the iterations may cause the temperature difference to continue to increase, leading to thermal runaway. In this case, it is necessary to reconsider the boundary conditions of the RTL-level circuit design, module layout planning, and circuit packaging.

[0054] If the table building process starts from 25°C to 125°C with an interval of 5°C, then it will take 21 times to read the mapped netlist, add timing constraints and output power consumption. Since the research focus of the present invention is the impact of leakage power consumption and temperature feedback on the final temperature, a larger circuit scale accompanied by a higher operating temperature can better highlight the effectiveness of our method and make the simulation temperature closer to the actual operating temperature. Therefore, the present invention requires a larger circuit scale to verify the proposed method. Unfortunately, a larger circuit scale will lead to an increase in the synthesis time and the time to read the netlist, and power consumption analysis at 21 temperatures is particularly time-consuming. Therefore, the present invention proposes a method to simplify this process. The present invention builds tables for small-scale circuits because their synthesis time or the time to read the mapped netlist is shorter, which facilitates the analysis of the results. Based on the power consumption temperature curve of the small-scale circuit, the present invention observed consistent results.

[0055] See Figure 2As shown in the figure, the power consumption of a pulsating array circuit changes with increasing temperature. As the temperature increases, the dynamic power consumption maintains a slow linear growth, while the leakage power consumption increases exponentially. This observation is almost consistent with the theoretical expectations mentioned above. Therefore, in order to reduce the table building time, a specific embodiment of the present invention only uses the lib files at 25°C and 125°C for synthesis and power consumption analysis. From this curve, the present invention reads the power consumption value at every 5°C interval, builds a complete table, and completes the power consumption analysis at two temperatures, which can greatly reduce the table building time and improve the efficiency of the thermal simulation method of power consumption temperature feedback.

[0056] This embodiment also provides a thermoelectric coupling simulation system for implementing the method, including:

[0057] The lib file acquisition module is used to perform unit characterization on all standard units in the process library at different temperatures. The unit characterization results at one temperature constitute a lib file.

[0058] The temperature-module power consumption table acquisition module is used to perform logic synthesis and power consumption analysis on the RTL-level netlist corresponding to the chip to be thermally simulated and the lib file at each temperature, obtain the power consumption of each module in the RTL-level netlist at each temperature, and establish a temperature-module power consumption table;

[0059] Thermoelectric coupling simulation module is used to input the power consumption of each module at an initial temperature into the thermal simulation tool HotSpot for thermal simulation to obtain the initial simulation temperature of each module;

[0060] The power consumption of each module corresponding to the previous simulation temperature is searched in the table, and the power consumption corresponding to all the modules found is input into the thermal simulation tool HotSpot for thermal simulation to obtain the current simulation temperature of each module. The difference between the simulation temperatures obtained in two adjacent thermal simulations is calculated; among them, the previous simulation temperature during the second thermal simulation is the initial simulation temperature;

[0061] The optimization module is used to compare the difference in simulated temperatures with a preset standard value. When the difference in simulated temperatures is less than the preset standard value, the thermal simulation operation is terminated, the simulated temperature of each module during the last thermal simulation is obtained, and the layout planning of each module in the chip is optimized based on the obtained simulated temperature. If the temperature difference continues to increase and leads to thermal runaway, the RTL-level circuit design and the boundary conditions of the chip package are modified.

[0062] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can be referred to the partial description of the method embodiment, and the implementation methods of the remaining modules will not be repeated here. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present invention. Ordinary technicians in this field can understand and implement it without paying any creative work.

[0063] Embodiments of the system of the present invention can be applied to any device with data processing capabilities, such as a computer or other device. System embodiments can be implemented through software, hardware, or a combination of software and hardware. For example, a software implementation, as a logical device, is implemented by a processor of any device with data processing capabilities, reading corresponding computer program instructions from non-volatile memory into internal memory and executing them.

[0064] Obviously, the above-described embodiments and drawings are only some examples of the present application. For those of ordinary skill in the art, the present application can also be applied to other similar situations based on these drawings without the need for creative work. In addition, it is understandable that although the work done in this development process may be complex and lengthy, for those of ordinary skill in the art, certain changes in design, manufacturing or production based on the technical content disclosed in this application are merely conventional technical means and should not be regarded as insufficient disclosure of the present application. Without departing from the concept of the present application, several variations and improvements can also be made, which all fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be based on the appended claims.

Claims

1. A thermoelectric coupling simulation method for the early design stage of integrated circuits, characterized in that: The following steps are involved: 1) Perform unit characterization on all standard units in the process library at different temperatures, and the unit characterization results at one temperature constitute a lib file; 2) Perform logic synthesis and power consumption analysis on the RTL netlist corresponding to the chip to be simulated for thermoelectric coupling and the lib file at each temperature, obtain the power consumption of each module in the RTL netlist at each temperature, and establish a temperature-module power consumption table; 3) Perform a thermoelectric coupling simulation of the power consumption of each module. For the first simulation, select an initial temperature and input the power consumption of each module at that temperature from the temperature-module power consumption table into the thermal simulation tool HotSpot for simulation to obtain the initial simulation temperature of each module. In the next simulation, find the power consumption of each module corresponding to the previous simulation temperature in the temperature-module power consumption table, input the power consumption into the thermal simulation tool HotSpot for simulation, obtain the current simulation temperature of each module, and calculate the difference between the simulation temperatures obtained in two adjacent thermal simulations; When the difference in the simulated temperatures is less than a preset standard value, the thermoelectric coupling simulation operation is terminated, the simulated temperature of each module during the last simulation is obtained, and the layout planning of each module in the chip is optimized based on the obtained simulated temperature.

2. The method according to claim 1, characterized in that In step 1), the Cadence Liberate tool is used to perform cell characterization on all standard cells in the process library at different temperatures.

3. The method according to claim 1, characterized in that In step 1), the lib file includes timing and power consumption information of the standard cell under different input states.

4. The method according to claim 1, wherein In the step 2), before performing logic synthesis and power consumption analysis, the library compiler tool is used to convert the lib file into a db file.

5. The method according to claim 1, wherein In step 2), the logic synthesis and power consumption analysis are implemented by Design Compiler; when using Design Compiler for logic synthesis and power consumption analysis, the input of Design Compiler also includes timing constraints, and the timing constraints include clock period, clock offset, clock delay, input delay and output delay.

6. The method according to claim 1, characterized in that In step 3), the initial temperature is 25°C.

7. The method according to claim 1, characterized in that In step 3), if the last simulation temperature falls between two adjacent temperature values ​​in the table, linear interpolation is used to obtain the power consumption value of each module at the simulation temperature.

8. The method according to claim 1, characterized in that In step 3), when the temperature difference between two adjacent simulations increases continuously in successive thermoelectric coupling simulations, resulting in thermal runaway, the RTL level circuit design and the boundary conditions of the chip package are modified.

9. The method according to claim 8, characterized in that The boundary conditions of the chip package include the thermal resistance between the outermost heat dissipation fins of the chip and the air.

10. A thermoelectric coupling simulation system for implementing the method according to claim 8, characterized in that: include: The lib file acquisition module is used to perform unit characterization on all standard units in the process library at different temperatures. The unit characterization results at one temperature constitute a lib file. The temperature-module power consumption table acquisition module is used to perform logic synthesis and power consumption analysis on the RTL-level netlist corresponding to the chip to be simulated for thermoelectric coupling and the lib file at each temperature, obtain the power consumption of each module in the RTL-level netlist at each temperature, and establish a temperature-module power consumption table; Thermoelectric coupling simulation module is used to perform successive thermoelectric coupling simulations on the power consumption of each module. During the first simulation, an initial temperature is selected, and the power consumption of each module at that temperature from the temperature-module power consumption table is input into the thermal simulation tool HotSpot for thermal simulation to obtain the initial simulation temperature of each module. In the next simulation, find the power consumption of each module corresponding to the previous simulation temperature in the temperature-module power consumption table, input the power consumption into the thermal simulation tool HotSpot for simulation, obtain the current simulation temperature of each module, and calculate the difference between the simulation temperatures obtained in two adjacent simulations; The optimization module is used to compare the difference in simulation temperature with a preset standard value. When the difference in simulation temperature is less than the preset standard value, the thermal simulation operation is terminated, the simulation temperature of each module during the last thermal simulation is obtained, and the layout planning of each module in the chip is optimized based on the obtained simulation temperature. When the temperature difference between two adjacent simulations continues to increase in successive thermoelectric coupling simulations, resulting in thermal runaway, the RTL-level circuit design and the boundary conditions of the chip package are modified.

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