Column gate drive circuit, pixel circuit, display control circuit and display panel

Abstract

The invention relates to a column gate driving circuit, a pixel circuit, a display control circuit and a display panel, and the column gate driving circuit comprises a first driving sub-circuit which is used for receiving a data signal and outputting the received data signal to the pixel circuit; the second driving sub-circuit is used for receiving the data signal, a first gate control signal and a first enable control signal, generating a column scanning signal according to the data signal, the first gate control signal and the first enable control signal, and outputting the column scanning signal to a first target transistor of the pixel circuit; wherein the first target transistor is located on a data signal write-in path between the second electrode and the grid electrode of the driving transistor. According to the column gate driving circuit, the writing process of the data signal can be controlled through the target column scanning signal, and then the data refreshing process of the pixel circuit is controlled, so that local refreshing of the display panel is realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a column gate driving circuit, a pixel circuit, a display control circuit and a display panel. Background Art

[0002] With the continuous development of science and technology, people have higher and higher requirements for electronic devices, for example, they have higher requirements for the refresh rate of display screens.

[0003] However, the current screen refresh frequency is a fixed frequency. The refresh frequency of the display panel refers to the frequency at which the display panel updates the displayed image. In applications, some areas of the display panel may display static images, while the rest of the area may display dynamic images normally. These areas with different display requirements can only be refreshed at a fixed frequency, which results in higher power consumption of the display panel. Summary of the invention

[0004] Based on this, it is necessary to provide a column gate driving circuit, a pixel circuit, a display control circuit and a display panel that can partially refresh the display panel to reduce power consumption in order to address the above technical problems.

[0005] In a first aspect, the present application provides a column gate driving circuit, comprising:

[0006] A first driving sub-circuit, configured to receive a data signal and output the received data signal to a pixel circuit;

[0007] The second driving subcircuit is used to receive the data signal, the first gate control signal and the first enable control signal, generate a column scan signal according to the data signal, the first gate control signal and the first enable control signal, and output it to the first target transistor of the pixel circuit; wherein the first target transistor is located on the data signal writing path between the second electrode and the gate of the driving transistor.

[0008] The column gate driving circuit includes a first driving subcircuit and a second driving subcircuit. The first driving subcircuit can transmit a data signal to a pixel circuit to control the pixel circuit to drive a light-emitting element; the second driving subcircuit outputs a target column scanning signal to the gate of the second target transistor according to the data signal, the second gate control signal and the first enable control signal to realize the multiplexing of the data signal, and at the same time, the on-off of the first target transistor can be controlled by the target column scanning signal. Since the first target transistor is located in the data signal writing path between the second pole and the gate of the driving transistor, the writing process of the data signal can be controlled by the target column scanning signal, thereby controlling the data refresh process of the pixel circuit. On this basis, the data refresh process of the pixel circuit in each display area can be controlled based on the column gate driving circuit, thereby realizing the partial refresh of the display panel and reducing the power consumption of the display panel.

[0009] In a second aspect, the present application provides a pixel circuit, the pixel circuit comprising:

[0010] A driving transistor, used for providing a driving current to the light emitting element;

[0011] A data writing module, wherein a first end of the data writing module is used to receive a data signal, a second end of the data writing module is connected to a first electrode of the driving transistor, and a control end of the data writing module is used to receive a first row scanning signal, so as to turn on the first electrode and the second electrode of the data writing transistor in response to the first row scanning signal, and output the data signal to the first electrode of the driving transistor;

[0012] A storage module, wherein a first terminal of the storage module is used to receive a first power supply voltage, and a second terminal of the storage module is connected to the gate of the driving transistor;

[0013] A first target transistor, wherein the first target transistor is located on a data signal writing path between the second electrode and the gate of the driving transistor, and the gate of the first target transistor is used to receive a target column scanning signal to turn on the first electrode and the second electrode of the first target transistor in response to the target column scanning signal.

[0014] In the above pixel circuit, since the first target transistor is located in the data signal writing path between the second electrode and the gate of the driving transistor, the on-off of the first target transistor will affect the on-off of the data signal writing path. Therefore, by controlling the on-off of the first target transistor through the target column scanning signal, the writing process of the data signal can be controlled, and then the data refresh process of the pixel circuit can be controlled. On this basis, the data refresh process of the pixel circuit in each display area can be controlled by controlling the target column scanning signal output to each pixel circuit, thereby realizing partial refresh of the display panel and reducing the power consumption of the display panel.

[0015] In a third aspect, the present application provides a display control circuit, the display control circuit comprising:

[0016] A column gate drive circuit as described above;

[0017] A pixel circuit as described above.

[0018] The column gate driving circuit outputs the target column scanning signal to the first target transistor of the pixel circuit to control the on and off of the first target transistor. Since the first target transistor is located in the data signal writing path between the second electrode and the gate of the driving transistor, the data refresh process of the pixel circuit can be controlled. On this basis, the data refresh process of the pixel circuit in each display area can be controlled based on the column gate driving circuit, thereby realizing partial refresh of the display panel and reducing the power consumption of the display panel.

[0019] In a fourth aspect, the present application provides a display panel, the display panel comprising:

[0020] The display control circuit as described above;

[0021] A controller is connected to the column gate driving circuit and is used to provide the data signal, the first gate control signal and the first enable control signal.

[0022] In the above-mentioned display panel, the controller is connected to the column gate drive circuit, and provides a data signal, a first gate control signal and a first enable control signal to the column gate drive circuit. The column gate drive circuit outputs a target column scan signal to the gate of the second target transistor according to the data signal, the second gate control signal and the first enable control signal, and the on and off of the first target transistor can be controlled by the target column scan signal. Since the first target transistor is located in the data signal writing path between the second pole and the gate of the driving transistor, the controller can control the writing process of the data signal by controlling the provided signal, and then control the data refresh process of the pixel circuit. On this basis, the data refresh process of the pixel circuit in each display area can be controlled based on the column gate drive circuit, thereby realizing partial refresh of the display panel and reducing the power consumption of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A circuit diagram of a pixel circuit of a 7T1C architecture in the related art;

[0025] Figure 2 A circuit diagram of a pixel circuit of an 8T1C architecture;

[0026] Figure 3 A circuit diagram of a GOA circuit for generating a scan signal for a P-type transistor;

[0027] Figure 4 for Figure 3 A signal timing diagram of the GOA circuit of the embodiment;

[0028] Figure 5 A circuit diagram of a GOA circuit for generating a scanning signal of an N-type transistor;

[0029] Figure 6 for Figure 5 A signal timing diagram of the GOA circuit of the embodiment;

[0030] Figure 7 This is a schematic diagram of the structure of a gate drive circuit in one embodiment of the present application;

[0031] Figure 8 A schematic diagram of the refresh area division of a display panel in one embodiment of the present application;

[0032] Fig. 9 is a schematic structural diagram of a column gate driving circuit in another embodiment of the present application;

[0033] Fig.10 is a structural schematic diagram of a gate drive circuit in yet another embodiment of the present application;

[0034] Fig.11 This is a signal timing diagram of a gate driving circuit in one embodiment of the present application;

[0035] Fig.12 is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0036] Fig.13 is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0037] Fig.14 is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0038] Fig.15 is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0039] Fig.16 is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0040] Fig.17is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0041] Fig.18 is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0042] Fig.19 is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0043] Fig. 20 is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0044] Fig.21 is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0045] Fig. 22 is a structural schematic diagram of a column gate driving circuit in another embodiment of the present application;

[0046] Fig.23 is a schematic structural diagram of a pixel circuit in one embodiment of the present application;

[0047] Fig.24 is a schematic structural diagram of a pixel circuit in another embodiment of the present application;

[0048] Fig.25 A schematic diagram of refreshing area division of a display panel in another embodiment of the present application;

[0049] Fig.26 is a structural schematic diagram of a pixel circuit in yet another embodiment of the present application;

[0050] Fig. 27 is a structural schematic diagram of a pixel circuit in another embodiment of the present application;

[0051] Fig.28 is a structural schematic diagram of a pixel circuit in another embodiment of the present application;

[0052] Fig.29 is a structural schematic diagram of a pixel circuit in another embodiment of the present application;

[0053] Fig.30 is a structural schematic diagram of a pixel circuit in another embodiment of the present application;

[0054] Fig.31 is a structural schematic diagram of a pixel circuit in another embodiment of the present application;

[0055] Fig.32 is a schematic diagram of the structure of a display control circuit in one embodiment of the present application;

[0056] Fig.33is a schematic diagram of the structure of a display control circuit in another embodiment of the present application;

[0057] Fig.34 is a schematic diagram of the structure of a display panel in one embodiment of the present application;

[0058] Fig.35 It is a schematic diagram of the structure of a display panel in another embodiment of the present application.

[0059] Description of reference numerals:

[0060] 10-first driving sub-circuit, 20-second driving sub-circuit, 11-first switch module, 21-second switch module, 22-driving module, 221-voltage stabilizing circuit, 2211-first latch circuit, 222-control circuit, 2221-second latch circuit, 30-pixel circuit, 31-storage module, 32-data writing module, 33-first reset module, 34-second reset module, 35-third reset module, 36-first light-emitting control module, 37-second light-emitting control module, 100-display panel, 110 first refresh area, 120-second refresh area, 130-third refresh area, 140-fourth refresh area, 15-fifth refresh area, 101-column gate driving circuit, 40-row gate driving circuit, 50-scanning control circuit, 60-controller. DETAILED DESCRIPTION

[0061] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0063] In the following embodiments, when a layer, region, or element is "connected", it can be interpreted that the layer, region, or element is not only directly connected but also connected through other constituent elements placed therebetween. For example, when a layer, region, element, etc. is described as being connected or electrically connected, the layer, region, element, etc. can be connected or electrically connected not only directly or directly, but also through another layer, region, element, etc. placed therebetween.

[0064] Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another. It will also be understood that expressions used in the singular include plural expressions unless the expression in the singular has an obviously different meaning in the context.

[0065] Electronic or electrical devices and / or any other related devices or components according to the embodiments of the concepts of the present application described herein (for example, a display device including a display panel and a display panel driver, wherein the display panel driver also includes a drive controller, a gate driver, a gamma reference voltage generator, a data driver, and an emission driver) can be implemented using any appropriate hardware, firmware (such as a dedicated integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices may be processes or threads that run on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using standard storage devices (e.g., such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media (e.g., such as CD-ROMs, flash drives, etc.). Moreover, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed on one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the concepts of the present application.

[0066] Although exemplary embodiments of display modules and display devices including display modules have been specifically described herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that display modules and display devices including display modules constructed according to the principles of the present application may be implemented in addition to those specifically described herein. The present application is also defined in the claims and their equivalents.

[0067] Figure 1 The circuit diagram of the pixel circuit of the 7T1C architecture in the related art is shown in FIG. Figure 1 The pixel circuit of the 7T1C architecture includes 7 transistors and 1 storage capacitor. The pixel circuit includes a driving transistor, a gate reset unit, an anode reset unit, a data writing unit, a threshold compensation unit and a light emitting control unit.

[0068] Specifically, the first electrode of the driving transistor T3 is used to receive the data signal Data, and the second electrode of the transistor T3 can be used to output the driving current. The current value of the driving current is determined by the data signal Data and directly affects the luminous brightness of the light-emitting device. The gate reset unit includes a transistor T1, the first electrode of the transistor T1 is connected to the reset voltage signal Vinit1, and the second electrode of the transistor T1 is connected to the gate of the transistor T3. The transistor T1 is used to pull down the gate voltage of the transistor T3 to the voltage of the reset voltage signal Vinit1 according to the scanning signal received by the gate, so as to reset the gate of the transistor T3. The anode reset unit includes a transistor T7, the first electrode of the transistor T7 is used to receive the reset voltage signal Vinit2, and the second electrode of the transistor T7 is connected to the anode of the light-emitting device. The transistor T7 is used to pull down the anode voltage of the light-emitting device to the voltage of the reset voltage signal Vinit2 according to the scanning signal received by the gate after the gate of the transistor T3 is reset, so as to reset the anode of the light-emitting device. The voltage of the reset voltage signal Vinit2 can be understood as the starting charging voltage of the anode of the light-emitting device.

[0069] The data writing unit includes a transistor T4, a first electrode of the transistor T4 is connected to the data signal line, a second electrode of the transistor T4 is connected to the first electrode of the transistor T3, and the transistor T4 is used to control the on-off of the signal transmission path between the data signal and the first electrode of the transistor T3 according to the scanning signal. The threshold compensation unit includes a transistor T2 and a storage capacitor C1. The storage capacitor C1 is connected to the first voltage terminal ELVDD and the gate of the transistor T3 respectively. The first electrode of the transistor T2 is connected to the second electrode of the transistor T3, and the second electrode of the transistor T2 is connected to the gate of the transistor T3. The transistor T2 is used to control the on-off of the signal transmission path between the gate and the second electrode of the transistor T3 according to the scanning signal, so as to store the compensation result in the storage capacitor C1. By setting the threshold compensation unit, the threshold voltage of the transistor T3 can be compensated, so as to avoid the threshold voltage of the transistor T3 from affecting the brightness of the light-emitting device. The light-emitting control unit includes a transistor T5 and a transistor T6. The first electrode of the transistor T5 is connected to the first voltage terminal ELVDD, and the second electrode of the transistor T5 is connected to the first electrode of the transistor T3. The transistor T5 is used to control the on / off of the signal transmission path between the first voltage terminal ELVDD and the first electrode of the transistor T3 according to the light emitting control signal EM. The first electrode of the transistor T6 is connected to the second electrode of the transistor T3, and the second electrode of the transistor T6 is connected to the anode of the light emitting device. The transistor T6 is used to control the on / off of the signal transmission path between the second electrode of the transistor T3 and the anode of the light emitting device according to the light emitting control signal EM.

[0070] It should be noted that each transistor in the pixel circuit can be any one of a P-type transistor and an N-type transistor, and the types of each transistor may not be exactly the same. Specifically, if the pixel circuit is a low-temperature polycrystalline silicon (LTPS) type circuit, then each transistor in the pixel circuit may be a P-type transistor. Based on the driving timing of the pixel circuit, transistors T2, T4 and T7 can be connected to the same scan signal, transistor T1 is connected to another scan signal, and transistors T5 and T6 are connected to the light-emitting control signal. If the pixel circuit is a low-temperature polycrystalline oxide (LTPO) type circuit, then some of the transistors in the pixel circuit may be N-type transistors, for example Figure 1 The transistors T1 and T2 shown in the figure are N-type transistors, and the remaining transistors T3-T7 are P-type transistors. Accordingly, transistors T2 and T4 need to be connected to different scanning signals. In some embodiments, all transistors in the pixel circuit may be N-type transistors. It is understood that the pixel circuit may also be Figure 2 The other architectures such as 8T1C shown are not described in detail here. The scanning control circuit of this embodiment can be applied to any pixel circuit including a P-type transistor.

[0071] The row gate drive circuit is used to generate a row scan signal to control the on and off of each transistor in the pixel circuit. Among them, the row gate drive circuit can be a gate drive integration on an array substrate (Gate Driven on Array, GOA), and the gate drive integration on the array substrate can reduce the volume of the display module and reduce the preparation cost of the display module. In each embodiment of the present application, the row gate drive circuit is provided as an example of a gate drive integration on an array substrate. When the pixel circuit includes only one type of transistor, the row gate drive circuit can include only two groups of GOA circuits, and the two groups of GOA circuits are used to generate a light-emitting control signal and a scanning signal of the transistor respectively. When the pixel circuit includes both P-type transistors and N-type transistors, since the P-type transistor is turned on in response to a signal in a low-level state, and the N-type transistor is turned on in response to a signal in a high-level state, the row gate drive circuit also needs to include three or five groups of GOA circuits to control the on and off states of each transistor respectively. Among them, the three groups of GOA circuits are used to generate a light-emitting control signal, a scanning signal of a P-type transistor, and a scanning signal of an N-type transistor, respectively. For pixel circuits with more complex architectures, more GOA circuits are required, for example, five groups. Optionally, if the row gate drive circuit includes a large number of GOA circuits, multiple groups of GOA circuits can be set on both sides of the display screen to avoid the black border on one side of the display screen being too wide. In the related art, in order to reduce the power consumption of the display screen, the only way is to use overall frequency reduction, but the overall frequency conversion strategy is not flexible enough, which affects the user's viewing experience.

[0072] Specifically, the circuit diagram of the GOA circuit may be determined according to the types of scanning signals for P-type transistors and N-type transistors that need to be generated. Figure 3 is a circuit diagram of a GOA circuit for generating a scan signal of a P-type transistor. The circuit of this embodiment may be referred to as a GOA circuit of an 8T2C architecture. Figure 4 for Figure 3 The signal timing diagram of the GOA circuit of the embodiment is shown in FIG. Figure 4 , the low level state of the scan signal G_out is enabled to control the P-type transistor receiving the scan signal G_out to be turned on. Figure 5 is a circuit diagram of a GOA circuit for generating a scan signal of an N-type transistor. The circuit of this embodiment may be referred to as a GOA circuit of a 10T3C architecture. Figure 6 for Figure 5 The signal timing diagram of the GOA circuit of the embodiment is shown in FIG. Figure 6, the high level state of the scanning signal G_out is enabled to control the N-type transistor receiving the scanning signal G_out to be turned on. The STV signal received by the GOA circuit may come from an external controller, and the external controller may include but is not limited to any one of a display driver chip (Display Driver IC, DDIC) and an application processor (Application Processor, AP).

[0073] Therefore, the present application provides a column gate driving circuit that can partially refresh a display panel to reduce the power consumption of the display panel. Figure 7 FIG. 1 is a schematic diagram of a structure of a gate driving circuit in one embodiment of the present application. Figure 7 As shown, the column gate driving circuit includes: a first driving sub-circuit 10 and a second driving sub-circuit 20.

[0074] The first driving sub-circuit 10 is used to receive the data signal Data and output the received data signal Data to the pixel circuit. The second driving sub-circuit 20 is used to receive the data signal Data, the first gate control signal SW1 and the first enable control signal EN1, generate a column scanning signal according to the data signal Data, the first gate control signal SW1 and the first enable control signal EN1, and output it to the first target transistor of the pixel circuit; wherein the first target transistor is located on the data signal Data writing path between the second electrode and the gate of the driving transistor.

[0075] It should be noted that Figure 7 Only one column gate driving circuit is shown. In an actual product, the display panel may include multiple column gate driving circuits and multiple pixel circuits.

[0076] In the application, the first target transistor can be any one of a P-type transistor and an N-type transistor. The first enable control signal EN1EN and the first gate control signal SW1 can come from a display driver chip, which is a mainstream controller in current display devices. It can be understood that some display driver chips can integrate touch functions and can be called touch display driver chips (Touch and Display Driver Integration, TDDI). Another exemplary embodiment, the enable control signal EN and the first gate control signal SW1 can also come from an application processor, which can also be called an application chip, and the application chip is usually a system-on-chip (System on Chip, SoC). Based on the high integration characteristics of SoC, the volume of the display device can be greatly reduced. Therefore, according to the specific hardware solution of the display device, an appropriate controller can be selected to generate the first enable control signal EN1EN and the first gate control signal SW1, which is not limited in this embodiment.

[0077] It can be understood that the first driving subcircuit 10 receives the data signal Data and outputs the received data signal Data to the pixel circuit to provide the data signal Data to the pixel circuit in the data writing stage. In addition, the second driving subcircuit 20 generates a target column scanning signal OP1 and outputs it to the first target transistor of the pixel circuit, thereby controlling the on and off of the first target transistor. Since the first target transistor is located on the data signal Data writing path between the second pole and the gate of the driving transistor, the data writing process can be controlled by the second driving subcircuit 20, thereby controlling the data refresh process of the pixel circuit. On this basis, the data refresh process of the pixel circuit in each display area can be controlled based on the column gate driving circuit, thereby realizing local refresh of the display panel and reducing the power consumption of the display panel.

[0078] Specific examples include Figure 8 As shown, Figure 8 FIG. 1 is a schematic diagram of the refresh area division of a display panel in one embodiment of the present application; Figure 8 In the illustrated embodiment, the display screen can be divided into three refresh areas, and the refresh frequencies of the first refresh area 110 on the left and the second refresh area 120 on the right are the same, but different from the refresh frequency of the third refresh area 130 in the middle.

[0079] The column gate driving circuit includes a first driving subcircuit 10 and a second driving subcircuit 20. The first driving subcircuit 10 can transmit the data signal Data to the pixel circuit to control the pixel circuit to drive the light-emitting element; the second driving subcircuit 20 outputs the target column scanning signal OP1 to the gate of the second target transistor according to the data signal Data, the second gate control signal SW2 and the first enable control signal EN1, so as to realize the multiplexing of the data signal Data, and at the same time, the on-off of the first target transistor can be controlled by the target column scanning signal OP1. Since the first target transistor is located in the data signal Data writing path between the second pole and the gate of the driving transistor, the writing process of the data signal Data can be controlled by the target column scanning signal OP1, thereby controlling the data refresh process of the pixel circuit. On this basis, the data refresh process of the pixel circuit in each display area can be controlled based on the column gate driving circuit, thereby realizing the local refresh of the display panel and reducing the power consumption of the display panel.

[0080] In one embodiment, Fig. 9 is a schematic diagram of the structure of a column gate driving circuit in another embodiment of the present application. Fig. 9As shown, the first driving sub-circuit 10 is also used to receive the second gate control signal SW2; wherein the first driving sub-circuit 10 includes: a first switch module 11. The first end of the first switch module 11 is used to receive the data signal Data, the second end of the first switch module 11 is connected to the pixel circuit, and the control end of the first switch module 11 is used to receive the second gate control signal SW2, so as to turn on the first end and the second end of the first switch module 11 in response to the second gate control signal SW2, so as to output the data signal Data.

[0081] The second gate control signal SW2 may come from a display driver chip or an application processor. The first switch module 11 may include a switch transistor Tp1, a first electrode of the switch transistor Tp1 is used to receive a data signal Data, a second electrode of the switch transistor Tp1 is connected to a pixel circuit, and a gate of the switch transistor Tp1 is used to receive a second gate control signal SW2.

[0082] In this embodiment, the control end of the first switch module 11 responds to the first gate control signal SW1 to turn on the first end and the second end of the first switch module 11 to output the data signal Data to the pixel circuit. The first switch module 11 can control the output data signal Data to the pixel circuit, so that the pixel circuit can drive the light-emitting element to emit light based on the data signal Data.

[0083] In one embodiment, Fig.10 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig.10 As shown, the second driving sub-circuit 20 includes: a second switch module 21 and a driving module 22 .

[0084] A second switch module 21, wherein the first end of the second switch module 21 is used to receive the data signal Data, and the control end of the second switch module 21 is used to receive the first gate control signal SW1, so as to turn on the first end and the second end of the second switch module 21 in response to the first gate control signal SW1; a driving module 22, wherein the first end of the driving module 22 is connected to the second end of the second switch module 21, and the second end of the driving module 22 is connected to the gate of the first target transistor, and the driving module 22 is used to generate a target column scanning signal OP1 according to the data signal Data and the first enable control signal EN1. The level state of the target column scanning signal OP1 can be the same as that of the first enable control signal EN1, or it can be opposite. For example, Fig.11 : is a signal timing diagram of a gate driving circuit in one embodiment of the present application. Fig.11 As shown, the level state of the target column scanning signal OP1 may be the same as the first enable control signal EN1.

[0085] The first gate control signal SW1 may come from a display driver chip or an application processor.

[0086] It can be understood that the data signal Data can be controlled to be output to the driving module 22 through the second switch module 21, so that the driving module 22 generates the target column scanning signal OP1 according to the data signal Data and the first enable control signal EN1. In addition, by controlling the on and off of the first switch module 11 and the second switch module 21, it is possible to avoid the first switch module 11 and the second switch module 21 being turned on at the same time. Exemplarily, the first switch module 11 is turned on in a high level state, and the second switch module 21 is turned off in a high level state, then the timing of the first gate control signal SW1 and the second gate control signal SW2 can be as follows: Fig.11 As shown, the first switch module 11 is briefly turned on, and the second switch module 21 is briefly turned off, so as to avoid the first switch module 11 and the second switch module 21 being turned on at the same time, so that the first drive sub-circuit 10 can output the data signal Data to the pixel circuit stably for a long time. Through the above configuration, the first switch module 11 and the second switch module 21 are prevented from outputting the data signal Data at the same time, thereby reducing the signal interference on the first drive sub-circuit 10 and the second drive sub-circuit 20, ensuring the accuracy of the column scanning signal and the data signal Data output to the pixel circuit, which is conducive to the precise control of the local refresh of the display panel.

[0087] In one embodiment, Fig.12 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig.12 As shown, the second switch module 21 includes: an oxide transistor Ti1.

[0088] The first electrode of the oxide transistor Ti1 is used to receive the data signal Data, the second electrode of the oxide transistor Ti1 is connected to the first end of the driving module 22, and the control end of the oxide transistor Ti1 is used to receive the first gate control signal SW1, so as to turn on the first electrode and the second electrode of the oxide transistor Ti1 in response to the first gate control signal SW1 and output the data signal Data.

[0089] The oxide transistor Ti1 may be an N-type transistor.

[0090] It can be understood that the oxide transistor Ti1 has the advantages of high carrier mobility, low deposition temperature and high transparency, and has low leakage current compared to low-temperature polysilicon thin film transistors. Therefore, it is beneficial to reduce the voltage drop of the data signal Data during transmission, and then output a relatively stable signal to the driving module 22.

[0091] In one embodiment, Fig.13 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig.13 As shown, the driving module 22 includes: a first transistor T1 , a second transistor T2 and a voltage stabilizing circuit 221 .

[0092] The first electrode of the first transistor T1 is used to be connected to the first voltage terminal, and the first voltage terminal is used to output a high-level state signal. The second electrode of the first transistor T1 is used to be connected to the gate of the first target transistor, and the gate of the first transistor T1 is used to receive the first enable control signal EN1, so as to turn on the first electrode and the second electrode of the first transistor T1 in response to the first enable control signal EN1, and output a high-level state signal.

[0093] The second electrode of the second transistor T2 is used to be connected to the second voltage terminal, and the second voltage terminal is used to output a low-level state signal. The gate of the second transistor T2 is used to receive the first enable control signal EN1, so as to turn on the first electrode and the second electrode of the second transistor T2 in response to the first enable control signal EN1, and output a low-level state signal.

[0094] Among them, the third gate control signal SW3 is a constant voltage signal, for example, the third gate control signal SW3 can be a constant voltage signal of 2V, and the third gate control signal SW3 can come from the display driver chip or from the application processor. The first transistor T1 is a first type transistor, and the second transistor T2 is a second type transistor. In one example, the first type transistor is a P-type transistor, and the second type transistor is an N-type transistor. In another example, the first type transistor is an N-type transistor, and the second type transistor is a P-type transistor. For the convenience of explanation below, the first type transistor is a P-type transistor and the second type transistor is an N-type transistor.

[0095] The voltage stabilizing circuit 221 is respectively connected to the second end of the second switch module 21, the first electrode of the first transistor T1, the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first voltage end. The voltage stabilizing circuit 221 is used to cooperate with the first transistor T1 to output a steady-state target column scanning signal OP1 according to the data signal Data, the third gate control signal SW3, the high-level state signal, and the low-level state signal.

[0096] It can be understood that, since the transistor types of the first transistor T1 and the second transistor T2 are different, when the gate of the first transistor T1 and the gate of the second transistor T2 both receive the first enable control signal EN1, one of the first transistor T1 and the second transistor T2 is turned on and the other is turned on, and the situation of simultaneous on and off will not occur. When the first transistor T1 is turned on in response to the first enable control signal EN1, the first transistor T1 outputs a high-level state signal, and the voltage stabilizing circuit 221 performs steady-state processing on the high-level signal output by the first transistor T1, so that the driving module 22 can output a steady-state high-level state signal to the gate of the first target transistor. When the second transistor T2 is turned on in response to the first enable control signal EN1, the second transistor T2 outputs a low-level state signal to the voltage stabilizing circuit 221, and the low-level state signal is output after being processed in a steady state by the voltage stabilizing circuit 221, so that the driving module 22 can output a steady-state low-level state signal to the gate of the first target transistor.

[0097] Based on the above situation, the on-off state of the first target transistor can be controlled by controlling the high and low level states of the target column scanning signal OP1 output by the driving module 22, thereby controlling the on-off state of the data signal Data writing path, so as to control the data refresh process and realize partial refresh of the display panel. Taking the first target transistor as a P-type transistor as an example, the first target transistor receives a high-level state signal to turn on, and the corresponding pixel circuit refreshes data; the first target transistor receives a low-level state signal to turn off, and the corresponding pixel circuit cannot refresh data, so that the data of the previous frame can be maintained. Therefore, by controlling the on-off state of the first target transistor of the pixel circuit in different display areas, the refresh frequency of each display area can be controlled.

[0098] In one embodiment, Fig.14 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig.14 As shown, the voltage stabilizing circuit 221 includes: a third transistor T3, a fourth transistor T4 and a fifth transistor T5, wherein the third transistor T3 is a first type transistor, and the fourth transistor T4 and the fifth transistor T5 are second type transistors.

[0099] The first electrode of the third transistor T3 is used to be connected to the first voltage terminal, and the gate of the third transistor T3 is used to receive the first enable control signal EN1, so as to turn on the first electrode and the second electrode of the third transistor T3 in response to the first enable control signal EN1, and output a high-level state signal. The first electrode of the third transistor T3 and the first electrode of the first transistor T1 are both connected to the first voltage terminal, and the gate of the third transistor T3 and the gate of the first transistor T1 both receive the first enable control signal EN1. It can be understood that the third transistor T3 and the first transistor T1 are symmetrical structures. By setting the third transistor T3 and the first transistor T1 to a symmetrical structure, external interference can be reduced, and the stability of the high-level state signal output by the first transistor T1 is ensured.

[0100] The first electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the second electrode of the fourth transistor T4 is connected to the first electrode of the second transistor T2, and the gate of the fourth transistor T4 is connected to the second end of the second switch module 21. The first electrode of the fifth transistor T5 is used to be connected to the gate of the first target transistor, the second electrode of the fifth transistor T5 is connected to the first electrode of the second transistor T2, and the gate of the fifth transistor T5 is used to receive the third gate control signal SW3, and the voltage of the third gate control signal SW3 is in the voltage selection interval of the data signal Data. It can be found that the fourth transistor T4 and the fifth transistor T5 are also symmetrical structures. Since the output signal of the first transistor T1 needs to be output through the fifth transistor T5, by setting the fourth transistor T4 and the fifth transistor T5 to a symmetrical structure, external interference can be reduced and the stability of the low-level state signal output by the second transistor T2 can be ensured.

[0101] It should be noted that, since the second electrode of the fifth transistor T5 is connected to the first electrode of the second transistor T2, the second transistor T2 outputs a signal in a low-level state when it is turned on, and since the voltage of the third gate control signal SW3 is in the voltage selection interval of the data signal Data, when the second transistor T2 is turned on, the voltage difference between the second electrode and the gate of the fifth transistor T5 is large, and the third gate control signal SW3 is relatively a high-level state signal, then the second transistor T2, which is an N-type transistor, can be turned on, and then output a low-level state signal.

[0102] In another embodiment, Fig.15 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig.15As shown, the voltage stabilizing circuit 221 includes: a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9. Among them, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are first type transistors, and the fourth transistor T4, the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are second type transistors.

[0103] The first electrode of the third transistor T3 is used to be connected to the first voltage terminal, the second electrode of the third transistor T3 is connected to the first latch circuit 2211, and the gate of the third transistor T3 is used to receive the first enable control signal EN1. The third transistor T3 and the first transistor T1 are symmetrical structures, and by setting the third transistor T3 and the first transistor T1 to be symmetrical structures, external interference can be reduced, and the stability of the high-level state signal output by the first transistor T1 is ensured.

[0104] The fourth transistor T4, the second electrode of the fourth transistor T4 is connected to the first electrode of the second transistor T2, and the gate of the fourth transistor T4 is connected to the second end of the second switch module 21. The second electrode of the fifth transistor T5 is connected to the first electrode of the second transistor T2, and the gate of the fifth transistor T5 is used to receive the third gate control signal SW3, and the voltage of the third gate control signal SW3 is in the voltage selection interval of the data signal Data. The fourth transistor T4 and the fifth transistor T5 are also symmetrical structures. Since the output signal of the first transistor T1 needs to be output through the fifth transistor T5, by setting the fourth transistor T4 and the fifth transistor T5 to a symmetrical structure, external interference can be reduced and the stability of the low-level state signal output by the second transistor T2 can be ensured.

[0105] The first latch circuit 2211 is respectively connected to the first voltage terminal, the second electrode of the first transistor T1, the second electrode of the third transistor T3, the first electrode of the fourth transistor T4 and the first electrode of the fifth transistor T5, and the first latch circuit 2211 is used to output a steady-state target column scanning signal OP1 according to a high-level state signal and a low-level state signal.

[0106] In this embodiment, the first latch circuit 2211 outputs a steady-state target column scan signal OP1 according to a high-level state signal and a low-level state signal, thereby avoiding the influence of changes in environmental factors such as temperature on the level state of the target column scan signal OP1, thereby avoiding the level state fluctuation of the target column scan signal OP1 causing the first target transistor to have an on-off error, thereby improving the stability and reliability of the column gate drive circuit.

[0107] In one embodiment, Fig.16 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig.16As shown, the first latch circuit 2211 includes: a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9, wherein the sixth transistor T6 and the seventh transistor T7 are first type transistors, and the eighth transistor T8 and the ninth transistor T9 are second type transistors.

[0108] The first electrode of the sixth transistor T6 is used to be connected to the first voltage terminal, the second electrode of the sixth transistor T6 is connected to the first node N1, and the gate of the sixth transistor T6 is used to receive the second node signal. The first electrode of the seventh transistor T7 is used to be connected to the first voltage terminal, the second electrode of the seventh transistor T7 is connected to the second node N2, and the gate of the seventh transistor T7 is used to receive the first node signal. The second electrode of the eighth transistor T8 is connected to the first electrode of the fourth transistor T4, the second electrode of the eighth transistor T8 is connected to the first node N1, and the gate of the eighth transistor T8 is used to receive the second node signal. The first electrode of the ninth transistor T9 is used to be connected to the gate of the first target transistor, the second electrode of the ninth transistor T9 is connected to the first electrode of the fifth transistor T5, and the gate of the ninth transistor T9 is used to receive the first node signal.

[0109] It can be understood that the principle of the first latch circuit 2211 is similar to the SR latch, and the output signals of the sixth transistor T6 and the eighth transistor are used as the gate signals of the seventh transistor T7 and the ninth transistor T9, and the output signals of the seventh transistor T7 and the ninth transistor T9 are used as the gate signals of the sixth transistor T6 and the eighth transistor. Specifically, if the level state of the first node signal is a low level state, the seventh transistor T7 is kept turned on; if the level state of the first node signal is a high level state, the ninth transistor T9 is kept turned on. If the level state of the second node signal is a low level state, the sixth transistor T6 is kept turned on; if the level state of the second node signal is a high level state, the eighth transistor T8 is kept turned on. Therefore, in this embodiment, the conduction state of one of the sixth transistor T6 and the eighth crystal can be maintained. By maintaining the above-mentioned conduction state, the influence of the changes in factors such as temperature in the environment on the level state of the first node signal (i.e., the target column scanning signal OP1) can be avoided, thereby avoiding the situation where the level state fluctuation of the target column scanning signal OP1 causes the first target transistor to have an on-off error, thereby improving the stability and reliability of the column gate drive circuit.

[0110] In one embodiment, Fig.17 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig.17 As shown, the voltage stabilizing circuit 221 further includes: a first voltage stabilizing capacitor C1.

[0111] The first end of the first voltage-stabilizing capacitor C1 is connected to the first voltage end, and the second end of the first voltage-stabilizing capacitor C1 is connected to the second end of the second switch module 21 and the gate of the fourth transistor T4 respectively.

[0112] It can be understood that by connecting the first end of the first stabilizing capacitor C1 to the first voltage end, the high level state signal of the first voltage end is kept stable, and the data signal Data output by the second end of the second switch module 21 is kept stable, so as to provide a stable gate signal to the gate of the fourth transistor T4.

[0113] In another embodiment, Fig.18 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig.18 As shown, the driving module 22 includes: a first transistor M1, a second transistor M2 and a control circuit 222. The first transistor M1 is a first type transistor, and the second transistor M2 is a second type transistor.

[0114] The first electrode of the first transistor M1 is used to be connected to the first voltage terminal, the first voltage terminal is used to output a low-level state signal, the second electrode of the first transistor M1 is used to be connected to the gate of the first target transistor, the gate of the first transistor M1 is used to receive the first node signal. The first electrode of the second transistor M2 is used to be connected to the second voltage terminal, the second voltage terminal is used to output a high-level state signal, and the gate of the second transistor M2 is used to receive the first node signal.

[0115] It can be understood that the gate of the first transistor M1 and the gate of the second transistor M2 both receive the first node signal, and since the first transistor M1 is a first type transistor and the second transistor M2 is a second type transistor, only one of the first transistor M1 and the second transistor M2 is turned on, and when the first transistor M1 is turned on, the target column scanning signal OP1 output by the driving module 22 is in a low level state; when the second transistor M2 is turned on, the target column scanning signal OP1 output by the driving module 22 is in a high level state.

[0116] The control circuit 222 is respectively connected to the first end of the second switch module 21, the gate of the first transistor M1, the gate of the second transistor M2, the first voltage end, and the second voltage end. The control circuit 222 is used to cooperate with the first transistor M1 to output a steady-state first node signal according to the data signal Data, the first enable control signal EN1, the third gate control signal SW3, the high-level state signal, and the low-level state signal. By outputting the first node signal, the control circuit 222 can control the on-off state of the first transistor M1 and the second transistor M2, and then control the on-off of the first target transistor to control the data refresh process of the pixel circuit, thereby realizing partial refresh of the display panel and reducing the power consumption of the display panel.

[0117] In one embodiment, Fig.19 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig.19 As shown, the control circuit 222 includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7. The fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are first type transistors, and the third transistor M3 and the fourth transistor M4 are second type transistors.

[0118] The first electrode of the third transistor M3 is used to be connected to the first voltage terminal, the second electrode of the third transistor M3 is used to be connected to the first node N1, and the gate of the third transistor M3 is used to receive the first enable control signal EN1, so as to turn on the first electrode and the second electrode of the third transistor M3 in response to the first enable control signal EN1, and output a low-level state signal. The first electrode of the fourth transistor M4 is used to be connected to the first voltage terminal, the second electrode of the fourth transistor M4 is connected to the second node N2, and the gate of the fourth transistor M4 is used to receive the first enable control signal EN1. The third transistor M3 and the fourth transistor M4 are symmetrical structures. By setting the third transistor M3 and the first transistor M1 to a symmetrical structure, external interference can be reduced, the stability of the low-level state signal output by the first transistor M1 is ensured, and the stability of the first node signal is ensured.

[0119] The second electrode of the fifth transistor M5 is used to be connected to the second voltage terminal, and the gate of the fifth transistor M5 is used to receive the first enable control signal EN1, so as to turn on the first and second electrodes of the fifth transistor M5 in response to the first enable control signal EN1 and output a high level state signal.

[0120] The second electrode of the sixth transistor M6 is connected to the first electrode of the fifth transistor M5, and the gate of the sixth transistor M6 is connected to the second end of the second switch module 21. The second electrode of the seventh transistor M7 is connected to the first electrode of the fifth transistor M5, and the gate of the seventh transistor M7 is used to receive the third gate control signal SW3, and the voltage of the third gate control signal SW3 is in the voltage selection interval of the data signal Data. The sixth transistor M6 and the seventh transistor M7 are also symmetrical structures. Since the output signal of the fifth transistor M5 needs to be output through the seventh transistor M7, therefore, by setting the fourth transistor M4 and the fifth transistor M5 to a symmetrical structure, external interference can be reduced, and the stability of the high-level state signal output by the second transistor M2 is ensured, and the stability of the low-level state signal output by the second transistor M2 is ensured.

[0121] It should be noted that, since the second electrode of the seventh transistor M7 is connected to the first electrode of the fifth transistor M5, the fifth transistor M5 outputs a high-level state signal when it is turned on, and since the voltage of the third gate control signal SW3 is in the voltage selection interval of the data signal Data, the voltage difference between the second electrode and the gate of the seventh transistor M7 is large when the second transistor M2 is turned on, and the third gate control signal SW3 is relatively a low-level state signal. Then, the second transistor M2, which is a P-type transistor, can be turned on, and then output a low-level state signal.

[0122] In one embodiment, Fig. 20 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig. 20 As shown, the control circuit 222 includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a second latch circuit 2221.

[0123] The first electrode of the third transistor M3 is used to be connected to the first voltage terminal, the second electrode of the third transistor M3 is used to be connected to the first node N1, and the gate of the third transistor M3 is used to receive the first enable control signal EN1, so as to turn on the first electrode and the second electrode of the third transistor M3 in response to the first enable control signal EN1, and output a low-level state signal. The first electrode of the fourth transistor M4 is used to be connected to the first voltage terminal, and the gate of the fourth transistor M4 is used to receive the first enable control signal EN1. The third transistor M3 and the fourth transistor M4 are symmetrical structures. By setting the third transistor M3 and the first transistor M1 to a symmetrical structure, external interference can be reduced, the stability of the low-level state signal output by the first transistor M1 is ensured, and the stability of the first node signal is ensured.

[0124] The second electrode of the fifth transistor M5 is used to be connected to the second voltage terminal, and the gate of the fifth transistor M5 is used to receive the first enable control signal EN1, so as to turn on the first and second electrodes of the fifth transistor M5 in response to the first enable control signal EN1 and output a high level state signal.

[0125] The first electrode of the sixth transistor M6 is connected to the second electrode of the fourth transistor M4, the second electrode of the sixth transistor M6 is connected to the first electrode of the fifth transistor M5, and the gate of the sixth transistor M6 is connected to the second end of the second switch module 21. The second electrode of the seventh transistor M7 is connected to the first electrode of the fifth transistor M5, and the gate of the seventh transistor M7 is used to receive the third gate control signal SW3, and the voltage of the third gate control signal SW3 is in the voltage selection interval of the data signal Data. The sixth transistor M6 and the seventh transistor M7 are also symmetrical structures. Since the output signal of the fifth transistor M5 needs to be output through the seventh transistor M7, by setting the fourth transistor M4 and the fifth transistor M5 to a symmetrical structure, external interference can be reduced and the stability of the high-level state signal output by the fifth transistor M5 can be ensured.

[0126] The second latch circuit 2221 is respectively connected to the first voltage end, the second electrode of the third transistor M3, the second electrode of the fourth transistor M4, the first electrode of the sixth transistor M6 and the first electrode of the seventh transistor M7, and the second latch circuit 2221 is used to output a steady-state target column scanning signal OP1 according to a high-level state signal and a low-level state signal.

[0127] In this embodiment, the second latch circuit 2221 outputs a steady-state target column scan signal OP1 according to a high-level state signal and a low-level state signal, thereby avoiding the influence of changes in environmental factors such as temperature on the level state of the target column scan signal OP1, thereby avoiding the level state fluctuation of the target column scan signal OP1 causing the first target transistor to have an on-off error, thereby improving the stability and reliability of the column gate drive circuit.

[0128] In one embodiment, Fig.21 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig.21 As shown, the second latch circuit 2221 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11, wherein the eighth transistor M8 and the ninth transistor M9 are second type transistors, and the tenth transistor M10 and the eleventh transistor M11 are first type transistors.

[0129] The first electrode of the eighth transistor M8 is used to be connected to the first voltage terminal, the second electrode of the eighth transistor M8 is connected to the first node N1, and the gate of the eighth transistor M8 is used to receive the second node signal. The first electrode of the ninth transistor M9 is used to be connected to the first voltage terminal, the second electrode of the ninth transistor M9 is connected to the second node N2, and the gate of the ninth transistor M9 is used to receive the first node signal. The first electrode of the tenth transistor M10 is connected to the first node N1, the second electrode of the tenth transistor M10 is connected to the first electrode of the seventh transistor M7, and the gate of the tenth transistor M10 is used to receive the second node signal. The first electrode of the eleventh transistor M11 is connected to the second node N2, the second electrode of the eleventh transistor M11 is connected to the first electrode of the sixth transistor M6, and the gate of the eleventh transistor M11 is used to receive the first node signal.

[0130] It can be understood that the principle of the second latch circuit 2221 is similar to the SR latch, and the output signals of the eighth transistor M8 and the tenth transistor are used as the gate signals of the ninth transistor M9 and the eleventh transistor M11, and the output signals of the ninth transistor M9 and the eleventh transistor M11 are used as the gate signals of the sixth transistor M6 and the eighth crystal. Specifically, if the level state of the first node signal is a low level state, the eleventh transistor M11 is kept turned on; if the level state of the first node signal is a high level state, the ninth transistor M9 is kept turned on. If the level state of the second node signal is a low level state, the tenth transistor M10 is kept turned on; if the level state of the second node signal is a high level state, the eighth transistor M8 is kept turned on. Therefore, in this embodiment, the conduction state of one of the eighth transistor M8 and the tenth crystal can be maintained. By maintaining the above-mentioned conduction state, the influence of changes in environmental factors such as temperature on the level state of the first node signal can be avoided, thereby avoiding the level state fluctuation of the first node signal causing conduction errors in the first transistor M1 and the second transistor M2, and then causing on-off errors in the first target transistor, thereby improving the stability and reliability of the column gate drive circuit.

[0131] In one embodiment, Fig. 22 is a schematic diagram of the structure of a gate drive circuit in another embodiment of the present application. Fig. 22 As shown, the control circuit 222 also includes: a second voltage stabilizing capacitor.

[0132] The first end of the second voltage-stabilizing capacitor is connected to the first voltage end, and the second end of the second voltage-stabilizing capacitor is connected to the second end of the second switch module 21 and the gate of the sixth transistor M6 respectively.

[0133] It can be understood that by connecting the first end of the second stabilizing capacitor to the first voltage end, the low-level state signal of the first voltage end is kept stable, and the data signal Data output by the second end of the second switch module 21 is kept stable, so as to provide a stable gate signal to the gate of the sixth transistor M6.

[0134] Based on the same inventive concept, the present application also provides a pixel circuit. Fig.23 is a schematic diagram of the structure of a pixel circuit in one embodiment of the present application. Fig.23 As shown, the pixel circuit includes: a driving transistor T01, a data writing module 32, a storage module and a first target transistor T02.

[0135] The driving transistor T01 is used to provide a driving current to the light-emitting element. The first end of the data writing module 32 is used to receive the data signal Data, the second end of the data writing module 32 is connected to the first electrode of the driving transistor T01, and the control end of the data writing module 32 is used to receive the first row scanning signal S1, so as to turn on the first electrode and the second electrode of the data writing transistor T04 in response to the first row scanning signal S1, and output the data signal Data to the first electrode of the driving transistor T01. The first end of the storage module is used to receive the first power supply voltage Vdd, and the second end of the storage module is connected to the gate of the driving transistor T01. The first target transistor T02 is located on the data signal Data writing path between the second electrode and the gate of the driving transistor T01, and the gate of the first target transistor T02 is used to receive the target column scanning signal OP1, so as to turn on the first electrode and the second electrode of the first target transistor T02 in response to the target column scanning signal OP1.

[0136] The target column scanning signal OP1 may be output by the column gate scanning circuit of any of the above embodiments.

[0137] It can be understood that in the writing stage, the data writing module 32 responds to the first row scanning signal S1 to turn on the first and second electrodes of the data writing transistor T04, outputs the data signal Data to the first electrode of the driving transistor T01, and the data voltage is written into the gate of the driving transistor T01 through the driving transistor T01 and the first target transistor T02, so as to realize the data refresh of the pixel circuit. Therefore, by controlling the conduction of the first target transistor T02 through the target column scanning signal OP1, the data writing process can be controlled, and then the data refresh process of the pixel circuit can be controlled.

[0138] In the above pixel circuit, since the first target transistor T02 is located in the data signal Data writing path between the second electrode and the gate of the driving transistor T01, the on-off of the first target transistor T02 will affect the on-off of the data signal Data writing path. Therefore, by controlling the on-off of the first target transistor through the target column scanning signal OP1, the writing process of the data signal Data can be controlled, and then the data refresh process of the pixel circuit can be controlled. On this basis, the data refresh process of the pixel circuit in each display area can be controlled by controlling the target column scanning signal OP1 output to each pixel circuit, thereby realizing partial refresh of the display panel and reducing the power consumption of the display panel.

[0139] In one embodiment, Fig.24 is a schematic diagram of the structure of a pixel circuit in another embodiment of the present application. Fig.24 As shown, the pixel circuit further includes: a second target transistor T03.

[0140] The second target transistor T03 is located on the data signal Data writing path between the second electrode and the gate of the driving transistor T01, and the gate of the second target transistor T03 is used to receive the target row scan signal OP2 to turn on the first and second electrodes of the second target transistor T03 in response to the target row scan signal OP2.

[0141] It can be understood that, since the first target transistor T02 and the second target transistor T03 are both located on the data signal Data writing path between the second electrode and the gate of the driving transistor T01, the data signal Data can be written to the gate of the driving transistor T01 through the first target transistor T02 and the second target transistor T03 only when the first target transistor T02 and the second target transistor T03 are both turned on. Since the first target transistor T02 turns on the first electrode and the second electrode of the second target transistor T03 in response to the target column scanning signal OP1, and the second target transistor T03 turns on the first electrode and the second electrode of the second target transistor T03 in response to the target row scanning signal OP2, and the pixel circuit at any position can be determined based on the row and column, the data refresh process of the pixel circuit at any position can be controlled by the target column scanning signal OP1 and the target row scanning signal OP2, and therefore, the data refresh of any area of ​​the display panel can be realized based on the above pixel circuit. Fig.25 FIG. 1 is a schematic diagram of the refresh area division of the display panel in another embodiment of the present application. Fig.25 As shown, the display screen can be divided into two refresh areas, and the refresh frequencies of the middle fourth refresh area 140 and the peripheral fifth refresh area 150 are different.

[0142] In one embodiment, Fig.26 is a schematic diagram of the structure of a pixel circuit in another embodiment of the present application. Fig.26 As shown, the pixel circuit further includes: a first reset module 33 .

[0143] The first end of the first reset module 33 is connected to the second electrode of the driving transistor T01, the second end of the first reset module 33 is used to receive the first reset signal Vint1, and the control end of the first reset module 33 is used to receive the second row scanning signal S2, so as to output the first reset signal Vint1 to the second electrode of the driving transistor T01 in response to the second row scanning signal S2.

[0144] It can be understood that, since the first end of the first reset module 33 is connected to the second electrode of the driving transistor T01, when the first reset module 33 turns on the first end and the second end of the first reset module 33 in response to the second row scanning signal S2, the first reset module 33 outputs the first reset signal Vint1 to the second electrode of the driving transistor T01, and the first reset signal Vint1 needs to be written into the gate of the driving transistor T01 via the first target transistor T02. Therefore, controlling the on and off of the first target transistor T02 by the target column scanning signal OP1 can also control the resetting of the gate of the driving transistor T01.

[0145] In the case where the pixel circuit includes a first target transistor T02 and a second target transistor T03, only when both the first target transistor T02 and the second transistor are turned on, can the first reset signal Vint1 be written into the gate of the driving transistor T01 via the first target transistor T02 and the second target transistor. Therefore, the writing process of the first reset signal Vint1 of the pixel circuit at any position can be controlled based on the target row scan signal OP2 and the target column scan signal OP1.

[0146] In one embodiment, Fig. 27 is a schematic diagram of the structure of a pixel circuit in another embodiment of the present application. Fig. 27 As shown, the pixel circuit further includes: a second reset module 34 .

[0147] The first end of the second reset module 34 is used to receive the second reset signal Vint2, the second end of the second reset module 34 is connected to the anode of the light-emitting element, and the control end of the second reset module 34 is used to receive the third row scanning signal S3, so as to output the second reset signal Vint2 to the anode of the light-emitting device in response to the third row scanning signal S3.

[0148] In the application, in the reset stage, the control end of the second reset module 34 responds to the third row scan signal S3 to turn on the first end and the second end of the second reset module 34, and the second reset signal Vint2 is written into the anode of the light-emitting device to reset the anode of the light-emitting device to improve the display uniformity of the display panel.

[0149] In one embodiment, Fig.28 is a schematic diagram of the structure of a pixel circuit in another embodiment of the present application. Fig.28 As shown, the pixel circuit further includes: a third reset module 35 .

[0150] The first end of the third reset module 35 is used to receive the third reset signal Vint3, the second end of the third reset module 35 is connected to the first electrode of the driving transistor T01, and the control end of the third reset module 35 is used to receive the third row scanning signal S3, so as to output the third reset signal Vint3 to the first electrode of the driving transistor T01 in response to the third row scanning signal S3.

[0151] In the application, in the reset stage, the control end of the third reset module 35 responds to the third row scanning signal S3 to turn on the first end and the second end of the third reset module 35, and the third reset signal Vint3 is written into the first electrode of the driving transistor T01 to reset the first electrode of the driving transistor T01 to compensate for the threshold offset of the driving transistor T01 and improve the frequency conversion flicker problem.

[0152] In one embodiment, Fig.29 is a schematic diagram of the structure of a pixel circuit in another embodiment of the present application. Fig.29 As shown, the pixel circuit further includes: a first light emitting control module 36 and a second light emitting control module 37 .

[0153] The first end of the first light-emitting control module 36 is used to receive the first power supply voltage Vdd, the second end of the first light-emitting control module 36 is connected to the first electrode of the driving transistor T01, and the control end of the first light-emitting control module 36 is used to receive the light-emitting control signal EM to turn on the first end and the second end of the first light-emitting control module 36 in the light-emitting stage in response to the light-emitting control signal EM.

[0154] The first end of the second light-emitting control module 37 is connected to the second electrode of the driving transistor T01, and the second end of the second light-emitting control module 37 is connected to the anode of the light-emitting element. The control end of the second light-emitting control module 37 is used to receive the light-emitting control signal EM to turn on the first end and the second end of the second light-emitting control module 37 in the light-emitting stage in response to the light-emitting control signal EM.

[0155] It can be understood that in the light-emitting stage, the first light-emitting control module 36 responds to the light-emitting control signal EM, the first end and the second end of the first light-emitting control module 36 are turned on, and the first pole of the driving transistor T01 is connected to the first power supply voltage Vdd; the second light-emitting control module 37 responds to the light-emitting control signal EM, the first end and the second end of the second light-emitting control module 37 are turned on, and the second pole of the driving transistor T01 is connected to the light-emitting device, and then the second power supply voltage Vss is turned on, so that the driving transistor T01 can provide a driving current to the light-emitting device to drive the light-emitting device to emit light.

[0156] Based on the above embodiments, in one embodiment, Fig.30 is a structural schematic diagram of a pixel circuit in another embodiment of the present application, Fig.31 is a schematic diagram of the structure of a pixel circuit in another embodiment of the present application. Fig.30 and 31 As shown, the data writing module 32 may include a writing transistor, a first electrode of the writing transistor is used to receive the data signal Data, a second electrode of the writing transistor is connected to the first electrode of the driving transistor T01, and a gate of the writing transistor is used to receive the first row scanning signal S1.

[0157] The storage module may include a storage capacitor Cst, a first end of the storage capacitor Cst is used to receive the first power supply voltage Vdd, and a second end of the storage capacitor Cst is connected to the gate of the driving transistor T01.

[0158] The first reset module 33 may include a first reset transistor T05 , a first electrode of the first reset transistor T05 is connected to a second electrode of the driving transistor T01 , a second electrode of the first reset transistor T05 is used to receive a first reset signal Vint1 , and a gate of the first reset transistor T05 is used to receive a second row scanning signal S2 .

[0159] The second reset module 34 may include a second reset transistor T06 , a first electrode of the second reset transistor T06 is used to receive the second reset signal Vint2 , a second electrode of the second reset transistor T06 is connected to the anode of the light emitting element, and a gate of the second reset module 34 is used to receive the third row scanning signal S3 .

[0160] The third reset module 35 may include a third reset transistor T07 , a first electrode of the third reset transistor T07 is used to receive a third reset signal Vint3 , a second electrode of the third reset transistor T07 is connected to a first electrode of the driving transistor T01 , and a gate of the third reset transistor T07 is used to receive a third row scanning signal S3 .

[0161] The first light emitting control submodule may include a first light emitting control transistor T08, a gate of the first light emitting control transistor T08 is used to receive a light emitting control signal EM, a first electrode of the first light emitting control transistor T08 is used to receive a first power supply voltage Vdd, and a second electrode of the first light emitting control transistor T08 is connected to the first electrode of the driving transistor T01.

[0162] The second light emitting control submodule may include a second light emitting control transistor T09, a gate of which is used to receive a light emitting control signal EM, a first electrode of which is connected to the second electrode of the driving transistor T01, and a second electrode of which is connected to the anode of the light emitting device.

[0163] In one embodiment, Fig.30 As shown, the type of the first target transistor T02 is N-type. When the target column scanning signal OP1 is in a high level state, the first target transistor T02 is turned on. When the target column scanning signal OP1 is in a low level state, the first target transistor T02 is turned off. The first target transistor T02 is used to respond to the target column scanning signal OP1 and turn on during the data writing phase of the pixel circuit.

[0164] The second target transistor T03 is of N type. When the target row scan signal OP2 is in a high level state, the second target transistor T03 is turned on. When the target row scan signal OP2 is in a low level state, the second target transistor T03 is turned off. The second target transistor T03 is used to respond to the target row scan signal OP2 and turn on during the data writing phase of the pixel circuit.

[0165] It can be understood that after determining the types of the first target transistor T02 and the second target transistor T03, the level states of the target row scan signal OP2 and the target column scan signal OP1 can be determined according to the types of the first target transistor T02 and the second target transistor T03, thereby controlling the on and off of the first target transistor T02 and the second target transistor T03 to achieve data refresh in any area of ​​the display panel.

[0166] In another embodiment, Fig.31 As shown, the type of the first target transistor T02 is P-type. When the target column scanning signal OP1 is in a low level state, the first target transistor T02 is turned on. When the target column scanning signal OP1 is in a high level state, the first target transistor T02 is turned off. The first target transistor T02 is used to respond to the target column scanning signal OP1 and turn on during the data writing phase of the pixel circuit.

[0167] The type of the second target transistor T03 is N-type. When the target row scan signal OP2 is in a high level state, the second target transistor T03 is turned on. When the target row scan signal OP2 is in a low level state, the second target transistor T03 is turned off. The second target transistor T03 is used to respond to the target row scan signal OP2 and turn on during the data writing phase of the pixel circuit.

[0168] After determining the types of the first target transistor T02 and the second target transistor T03, the level states of the target row scan signal OP2 and the target column scan signal OP1 can be determined according to the types of the first target transistor T02 and the second target transistor T03, thereby controlling the on and off of the first target transistor T02 and the second target transistor T03 to achieve data refresh in any area of ​​the display panel.

[0169] In one embodiment, the present application further provides a display control circuit. Fig.32 is a schematic diagram of a structure of a display control circuit in one embodiment of the present application. Fig.32 As shown, the display control circuit includes: a column gate driving circuit 101 as in any of the above embodiments; and a pixel circuit 30 as in any of the above embodiments.

[0170] It can be understood that the column gate driving circuit 101 outputs the target column scanning signal OP1 to the first target transistor of the pixel circuit 30 to control the on and off of the first target transistor. Since the first target transistor is located in the data signal Data writing path between the second electrode and the gate of the driving transistor, the data refresh process of the pixel circuit 30 can be controlled. On this basis, the data refresh process of the pixel circuit 30 in each display area can be controlled based on the column gate driving circuit 101, thereby realizing partial refresh of the display panel and reducing the power consumption of the display panel.

[0171] In one embodiment, Fig.33 is a schematic diagram of a structure of a display control circuit in another embodiment of the present application. Fig.33 As shown, the pixel circuit 30 further includes a second target transistor, which is located on a data signal Data writing path between the second electrode and the gate of the driving transistor.

[0172] The display control circuit further includes: a row gate driving circuit 40 and a scanning control circuit 50 .

[0173] The row gate driving circuit 40 is used to output the initial row scanning signal. The input end of the scanning control circuit 50 is connected to the row gate driving circuit 40, and is used to generate the target row scanning signal OP2 according to the initial row scanning signal and the second enable control signal EN2, and output it to the second target transistor, wherein the second target transistor is located on the data signal Data writing path between the second electrode and the gate of the driving transistor.

[0174] It can be understood that, since the first target transistor and the second target transistor are both located on the data signal Data writing path between the second electrode and the gate of the driving transistor, the data signal Data can be written to the gate of the driving transistor through the first target transistor and the second target transistor only when both the first target transistor and the second target transistor are turned on. Since the first target transistor turns on the first electrode and the second electrode of the second target transistor in response to the target column scan signal OP1, and the second target transistor turns on the first electrode and the second electrode of the second target transistor in response to the target row scan signal OP2, and the pixel circuit 30 at any position can be determined based on the row and column, the data refresh process of the pixel circuit 30 at any position can be controlled by the target column scan signal OP1 and the target row scan signal OP2, and therefore, the data refresh of any area of ​​the display panel can be realized based on the above display control circuit.

[0175] In one embodiment, when the second enable control signal EN2 is in the first level state, the level state of the target scan signal is the same as that of the initial scan signal.

[0176] When the second enable control signal EN2 is in the second level state, the level state of the target row scan signal OP2 is the target level state, wherein the first level state and the second level state are different, and the target level state is the level state that turns off the second target transistor. According to the initial scan signal with the second level state, the scan control circuit 50 can generate a target scan signal that continues to be in the target level state to control the corresponding second target transistor to remain disconnected, thereby avoiding data refresh of the corresponding pixel circuit 30, so that the data of the previous frame can be maintained. Among them, the first level state and the second level state are different, for example, the first level state can be a low level state, and the second level state can be a high level state, for example, and the first level state can be a high level state, and the second level state can be a low level state. The first level state and the second level state can be determined according to the type of the second target transistor, which is not limited in this embodiment.

[0177] In one embodiment, the present application further provides a display panel, Fig.34 is a schematic diagram of the structure of a display panel in one embodiment of the present application. Fig.34 As shown, the display panel 100 comprises: a display control circuit as in any of the above embodiments and a controller 60. The controller 60 is connected to the column gate driving circuit 101 and is used to provide a data signal Data, a first gate control signal SW1 and a first enable control signal EN1.

[0178] In the display panel 100, the controller 60 is connected to the column gate driving circuit 101, and provides the data signal Data, the first gate control signal SW1 and the first enable control signal EN1 to the column gate driving circuit 101. The column gate driving circuit 101 outputs the target column scanning signal OP1 to the gate of the second target transistor according to the data signal Data, the second gate control signal SW2 and the first enable control signal EN1, and the on and off of the first target transistor can be controlled by the target column scanning signal OP1. Since the first target transistor is located in the data signal Data writing path between the second electrode and the gate of the driving transistor, the controller 60 can control the writing process of the data signal Data by controlling the provided signal, and then control the data refresh process of the pixel circuit 30. On this basis, the data refresh process of the pixel circuit 30 in each display area can be controlled based on the column gate driving circuit 101, thereby realizing the local refresh of the display panel 100 and reducing the power consumption of the display panel 100.

[0179] In one embodiment, the controller 60 is further used to obtain a picture to be displayed, determine a refresh area and a non-refresh area according to the picture to be displayed, and output a data signal Data, a first gate control signal SW1 and a first enable control signal EN1 to the column gate drive circuit 101;

[0180] Among them, the first enable control signal EN1 received by the column gate drive circuit 101 connected to the pixels in the refresh area is in a first level state, so that the level state of the target column scan signal OP1 is a level state that turns on the first target transistor; the first enable control signal EN1 received by the column gate drive circuit 101 connected to the pixels in the non-refresh area is in a second level state, so that the level state of the target column scan signal OP1 is a level state that turns off the first target transistor.

[0181] It can be understood that the column gate drive circuit 101 connected to the pixels in the refresh area provides a first enable control signal EN1 in a first level state to turn on the corresponding first target transistors, thereby causing the pixel circuit 30 in the corresponding refresh area to perform data refresh. The column gate drive circuit 101 connected to the pixels in the non-refresh area provides a first enable control signal EN1 in a second level state to turn off the corresponding first target transistors, thereby preventing the pixel circuit 30 in the corresponding non-refresh area from performing data refresh. The controller 60 can control the data refresh process of the pixel circuit 30 in each display area by controlling the signals provided to each column gate drive circuit 101, thereby achieving partial refresh of the display panel 100 and reducing the power consumption of the display panel 100.

[0182] In one embodiment, Fig.35 is a schematic diagram of the structure of a display panel in another embodiment of the present application. Fig.35As shown, the display control circuit also includes: a row gate driving circuit 40 and a scanning control circuit 50. The row gate driving circuit 40 is used to output an initial row scanning signal. The input end of the scanning control circuit 50 is connected to the row gate driving circuit 40, and is used to generate a target row scanning signal OP2 according to the initial row scanning signal and the second enable control signal EN2, and output it to the second target transistor, which is located on the data signal Data writing path between the second electrode and the gate of the driving transistor.

[0183] Among them, the controller 60 is also used to output a second enable control signal EN2 to the scanning control circuit 50; when the second enable control signal EN2 is in a first level state, the scanning control circuit 50 outputs a target row scanning signal OP2 to control the conduction of the second target transistor in the pixel circuit 30 of the refresh area; when the second enable control signal EN2 is in a second level state, the scanning control circuit 50 outputs a target row scanning signal OP2 to control the disconnection of the second target transistor in the pixel circuit 30 of the corresponding non-refresh area.

[0184] It can be understood that since the first target transistor and the second target transistor are both located on the data signal Data writing path between the second electrode and the gate of the driving transistor, the data signal Data can be written to the gate of the driving transistor through the first target transistor and the second target transistor only when both the first target transistor and the second target transistor are turned on. Since the first target transistor turns on the first electrode and the second electrode of the second target transistor in response to the target column scanning signal OP1, and the second target transistor turns on the first electrode and the second electrode of the second target transistor in response to the target row scanning signal OP2, and the pixel circuit 30 at any position can be determined based on the row and column, therefore, the controller 60 can control the data refresh process of the pixel circuit 30 at any position by controlling the signal output to each column gate driving circuit 101 and each scanning control circuit 50, and the above-mentioned display panel 100 can realize data refresh of any display area.

[0185] In one embodiment, the controller 60 is a display driver chip.

[0186] In another embodiment, the controller 60 may also be an application processor.

[0187] Based on the same inventive concept, an embodiment of the present application further provides a display device (not shown), which includes the display panel 100 in the above embodiment.

[0188] It can be understood that the display device in the embodiments of the present application can be an OLED display device, a QLED display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a wearable device, an Internet of Things device, or any other product or component with a display function, and the embodiments disclosed in the present application are not limited to this.

[0189] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0190] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0191] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A column gate drive circuit, characterized in that: include: A first driving sub-circuit, configured to receive a data signal and output the received data signal to a pixel circuit; The second driving subcircuit is used to receive the data signal, the first gate control signal and the first enable control signal, generate a target column scanning signal according to the data signal, the first gate control signal and the first enable control signal, and output it to the first target transistor of the pixel circuit; wherein the first target transistor is located on the data signal writing path between the second electrode and the gate of the driving transistor.

2. The column gate driving circuit according to claim 1, characterized in that: The first driving sub-circuit is further configured to receive a second gate control signal; wherein the first driving sub-circuit comprises: A first switch module, wherein the first end of the first switch module is used to receive the data signal, the second end of the first switch module is connected to the pixel circuit, and the control end of the first switch module is used to receive the second gate control signal to turn on the first end and the second end of the first switch module in response to the second gate control signal to output the data signal.

3. The column gate driving circuit according to claim 1, characterized in that: The second driving sub-circuit comprises: A second switch module, wherein a first end of the second switch module is used to receive the data signal, and a control end of the second switch module is used to receive the first gate control signal, so as to conduct the first end and the second end of the second switch module in response to the first gate control signal; A driving module, wherein a first end of the driving module is connected to a second end of the second switch module, a second end of the driving module is connected to a gate of the first target transistor, and the driving module is used to generate the target column scanning signal according to the data signal and the first enable control signal.

4. The column gate driving circuit according to claim 3, characterized in that: The second switch module includes: An oxide transistor, wherein the first electrode of the oxide transistor is used to receive the data signal, the second electrode of the oxide transistor is connected to the first end of the driving module, and the control end of the oxide transistor is used to receive the first gate control signal to turn on the first electrode and the second electrode of the oxide transistor in response to the first gate control signal.

5. The column gate driving circuit according to claim 3, characterized in that: The driving module comprises: a first transistor, wherein a first electrode of the first transistor is used to be connected to a first voltage terminal, the first voltage terminal is used to output a high level state signal, a second electrode of the first transistor is used to be connected to a gate of the first target transistor, and the gate of the first transistor is used to receive the first enable control signal; a second transistor, wherein a second electrode of the second transistor is used to be connected to a second voltage terminal, the second voltage terminal is used to output a low level state signal, and a gate of the second transistor is used to receive the first enable control signal; a voltage stabilizing circuit, the voltage stabilizing circuit being connected to the second end of the second switch module, the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor, and the first voltage end, respectively, and the voltage stabilizing circuit being used for cooperating with the first transistor to output the steady-state target column scanning signal according to the data signal, the third gate control signal, the high-level state signal, and the low-level state signal; The third gate control signal is a constant voltage signal, the first transistor is a first type transistor, and the second transistor is a second type transistor.

6. The column gate driving circuit according to claim 5, characterized in that: The voltage stabilizing circuit comprises: a third transistor, wherein a first electrode of the third transistor is used to be connected to the first voltage terminal, and a gate of the third transistor is used to receive the first enable control signal; a fourth transistor, wherein a first electrode of the fourth transistor is connected to a second electrode of the third transistor, a second electrode of the fourth transistor is connected to a first electrode of the second transistor, and a gate of the fourth transistor is connected to a second end of the second switch module; a fifth transistor, wherein a first electrode of the fifth transistor is connected to a gate of the first target transistor, a second electrode of the fifth transistor is connected to a first electrode of the second transistor, and the gate of the fifth transistor is used to receive a third gate control signal, and a voltage of the third gate control signal is within a voltage selection interval of the data signal; Among them, the third transistor is the first type transistor, and the fourth transistor and the fifth transistor are the second type transistors.

7. The column gate driving circuit according to claim 5, characterized in that: The voltage stabilizing circuit comprises: a third transistor, wherein a first electrode of the third transistor is used to be connected to the first voltage terminal, and a gate of the third transistor is used to receive the first enable control signal; a fourth transistor, wherein a second electrode of the fourth transistor is connected to a first electrode of the second transistor, and a gate of the fourth transistor is connected to a second end of the second switch module; a fifth transistor, wherein a second electrode of the fifth transistor is connected to a first electrode of the second transistor, and a gate of the fifth transistor is used to receive a third gate control signal, and a voltage of the third gate control signal is within a voltage selection interval of the data signal; a first latch circuit, the first latch circuit being connected to the first voltage terminal, the second electrode of the first transistor, the second electrode of the third transistor, the first electrode of the fourth transistor, and the first electrode of the fifth transistor, respectively, and the first latch circuit being used for outputting the target column scanning signal in a steady state according to the high level state signal and the low level state signal; Among them, the third transistor is the first type transistor, and the fourth transistor and the fifth transistor are the second type transistors.

8. The column gate driving circuit according to claim 7, characterized in that: The first latch circuit comprises: a sixth transistor, wherein a first electrode of the sixth transistor is connected to the first voltage terminal, a second electrode of the sixth transistor is connected to the first node, and a gate of the sixth transistor is used to receive a second node signal; a seventh transistor, wherein a first electrode of the seventh transistor is connected to the first voltage terminal, a second electrode of the seventh transistor is connected to the second node, and a gate of the seventh transistor is connected to receive a first node signal; an eighth transistor, wherein a second electrode of the eighth transistor is connected to a first electrode of the fourth transistor, a second electrode of the eighth transistor is connected to the first node, and a gate of the eighth transistor is used to receive the second node signal; a ninth transistor, wherein a first electrode of the ninth transistor is connected to a gate of the first target transistor, a second electrode of the ninth transistor is connected to a first electrode of the fifth transistor, and a gate of the ninth transistor is used to receive the first node signal; Among them, the sixth transistor and the seventh transistor are the first type transistors, and the eighth transistor and the ninth transistor are the second type transistors.

9. The column gate driving circuit according to any one of claims 6 to 8, characterized in that: The voltage stabilizing circuit further includes: A first voltage-stabilizing capacitor, wherein a first end of the first voltage-stabilizing capacitor is connected to the first voltage end, and a second end of the first voltage-stabilizing capacitor is respectively connected to the second end of the second switch module and the gate of the fourth transistor.

10. The column gate driving circuit according to claim 3, characterized in that: The driving module comprises: a first transistor, wherein a first electrode of the first transistor is used to be connected to a first voltage terminal, the first voltage terminal is used to output a low level state signal, a second electrode of the first transistor is used to be connected to a gate of the first target transistor, and the gate of the first transistor is used to receive a first node signal; a second transistor, wherein a first electrode of the second transistor is used to be connected to a second voltage terminal, the second voltage terminal is used to output a high level state signal, and a gate of the second transistor is used to receive the first node signal; a control circuit, the control circuit being connected to the first end of the second switch module, the gate of the first transistor, the gate of the second transistor, the first voltage end, and the second voltage end, respectively, and the control circuit being used to cooperate with the first transistor to output the first node signal in a steady state according to the data signal, the first enable control signal, the third gate control signal, the high level state signal, and the low level state signal; The third gate control signal is a constant voltage signal, the first transistor is a first type transistor, and the second transistor is a second type transistor.

11. The column gate driving circuit according to claim 10, characterized in that: The control circuit comprises: a third transistor, wherein a first electrode of the third transistor is used to be connected to the first voltage terminal, a second electrode of the third transistor is used to be connected to the first node, and a gate of the third transistor is used to receive the first enable control signal; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the first voltage terminal, a second electrode of the fourth transistor is connected to the second node, and a gate of the fourth transistor is connected to receive the first enable control signal; a fifth transistor, wherein a second electrode of the fifth transistor is used to be connected to the second voltage terminal, and a gate of the fifth transistor is used to receive the first enable control signal; a sixth transistor, wherein a second electrode of the sixth transistor is connected to a first electrode of the fifth transistor, and a gate of the sixth transistor is connected to a second end of the second switch module; a seventh transistor, wherein a second electrode of the seventh transistor is connected to a first electrode of the fifth transistor, and a gate of the seventh transistor is used to receive a third gate control signal, and a voltage of the third gate control signal is within a voltage selection interval of the data signal; Among them, the fifth transistor, the sixth transistor and the seventh transistor are first type transistors, and the third transistor and the fourth transistor are second type transistors.

12. The column gate driving circuit according to claim 10, characterized in that: The control circuit comprises: a third transistor, wherein a first electrode of the third transistor is used to be connected to the first voltage terminal, a second electrode of the third transistor is used to be connected to the first node, and a gate of the third transistor is used to receive the first enable control signal; a fourth transistor, wherein a first electrode of the fourth transistor is used to be connected to the first voltage terminal, and a gate of the fourth transistor is used to receive the first enable control signal; a fifth transistor, wherein a second electrode of the fifth transistor is used to be connected to the second voltage terminal, and a gate of the fifth transistor is used to receive the first enable control signal; a sixth transistor, wherein a first electrode of the sixth transistor is connected to a second electrode of the fourth transistor, a second electrode of the sixth transistor is connected to a first electrode of the fifth transistor, and a gate of the sixth transistor is connected to a second end of the second switch module; a seventh transistor, wherein a second electrode of the seventh transistor is connected to a first electrode of the fifth transistor, and a gate of the seventh transistor is used to receive a third gate control signal, and a voltage of the third gate control signal is within a voltage selection interval of the data signal; a second latch circuit, the second latch circuit being connected to the first voltage terminal, the second electrode of the third transistor, the second electrode of the fourth transistor, the first electrode of the sixth transistor and the first electrode of the seventh transistor respectively, and the second latch circuit being used for outputting a steady-state target column scanning signal according to the high-level state signal and the low-level state signal; Among them, the fifth transistor, the sixth transistor and the seventh transistor are first type transistors, and the third transistor and the fourth transistor are second type transistors.

13. The column gate driving circuit according to claim 12, characterized in that: The second latch circuit comprises: an eighth transistor, wherein a first electrode of the eighth transistor is connected to the first voltage terminal, a second electrode of the eighth transistor is connected to the first node, and a gate of the eighth transistor is used to receive a second node signal; a ninth transistor, wherein a first electrode of the ninth transistor is connected to the first voltage terminal, a second electrode of the ninth transistor is connected to the second node, and a gate of the ninth transistor is used to receive a first node signal; a tenth transistor, wherein a first electrode of the tenth transistor is connected to the first node, a second electrode of the tenth transistor is connected to the first electrode of the seventh transistor, and a gate of the tenth transistor is used to receive the second node signal; an eleventh transistor, a first electrode of the eleventh transistor being connected to the second node, a second electrode of the eleventh transistor being connected to the first electrode of the sixth transistor, and a gate of the eleventh transistor being used for receiving the first node signal; Among them, the eighth transistor and the ninth transistor are second-type transistors, and the tenth transistor and the eleventh transistor are first-type transistors.

14. The column gate driving circuit according to any one of claims 11 to 13, characterized in that: The control circuit further comprises: A second voltage-stabilizing capacitor, wherein a first end of the second voltage-stabilizing capacitor is connected to the first voltage end, and a second end of the second voltage-stabilizing capacitor is respectively connected to a second end of the second switch module and a gate of the sixth transistor.

15. A pixel circuit, characterized in that: The pixel circuit comprises: A driving transistor, used for providing a driving current to the light emitting element; A data writing module, wherein a first end of the data writing module is used to receive a data signal, a second end of the data writing module is connected to a first electrode of the driving transistor, and a control end of the data writing module is used to receive a first row scanning signal, so as to turn on the first electrode and the second electrode of the data writing transistor in response to the first row scanning signal, and output the data signal to the first electrode of the driving transistor; A storage module, wherein a first terminal of the storage module is used to receive a first power supply voltage, and a second terminal of the storage module is connected to a gate of the driving transistor; A first target transistor, wherein the first target transistor is located on a data signal writing path between the second electrode and the gate of the driving transistor, and the gate of the first target transistor is used to receive a target column scanning signal to turn on the first electrode and the second electrode of the first target transistor in response to the target column scanning signal.

16. The pixel circuit according to claim 15, characterized in that: The pixel circuit further includes: A second target transistor, the second target transistor is located on a data signal writing path between the second electrode and the gate of the driving transistor, the gate of the second target transistor is used to receive a target row scan signal to turn on the first electrode and the second electrode of the second target transistor in response to the target row scan signal.

17. The pixel circuit according to claim 15 or 16, characterized in that: The pixel circuit further includes: A first reset module, wherein the first end of the first reset module is connected to the second electrode of the driving transistor, the second end of the first reset module is used to receive a first reset signal, and the control end of the first reset module is used to receive a second row scanning signal to output the first reset signal to the second electrode of the driving transistor in response to the second row scanning signal.

18. The pixel circuit according to claim 15, characterized in that: The pixel circuit further includes: A second reset module, wherein the first end of the second reset module is used to receive a second reset signal, the second end of the second reset module is connected to the anode of the light-emitting element, and the control end of the second reset module is used to receive a third row scan signal to output the second reset signal to the anode of the light-emitting device in response to the third row scan signal.

19. The pixel circuit according to claim 15, characterized in that: The pixel circuit further includes: A third reset module, wherein the first end of the third reset module is used to receive a third reset signal, the second end of the third reset module is connected to the first electrode of the driving transistor, and the control end of the third reset module is used to receive a third row scanning signal to output the third reset signal to the first electrode of the driving transistor in response to the third row scanning signal.

20. The pixel circuit according to claim 15, characterized in that: The pixel circuit further includes: a first light-emitting control module, wherein a first terminal of the first light-emitting control module is used to receive a first power supply voltage, a second terminal of the first light-emitting control module is connected to a first electrode of the driving transistor, and a control terminal of the first light-emitting control module is used to receive a light-emitting control signal, so as to conduct the first terminal and the second terminal of the first light-emitting control module in a light-emitting stage in response to the light-emitting control signal; A second light-emitting control module, wherein the first end of the second light-emitting control module is connected to the second electrode of the driving transistor, the second end of the second light-emitting control module is connected to the anode of the light-emitting element, and the control end of the second light-emitting control module is used to receive a light-emitting control signal to turn on the first end and the second end of the second light-emitting control module in the light-emitting stage in response to the light-emitting control signal.

21. The pixel circuit according to claim 16, characterized in that: The type of the first target transistor is N-type, and the first target transistor is used to respond to the target column scanning signal and turn on during the data writing phase of the pixel circuit; The type of the second target transistor is N-type, and the second target transistor is used to respond to the target row scanning signal and be turned on during the data writing phase of the pixel circuit.

22. The pixel circuit according to claim 16, characterized in that: The type of the first target transistor is P-type, and the first target transistor is used to respond to the target column scanning signal and turn on during the data writing phase of the pixel circuit; The type of the second target transistor is N-type, and the second target transistor is used to respond to the target row scanning signal and be turned on during the data writing phase of the pixel circuit.

23. A display control circuit, characterized in that: The display control circuit comprises: The column gate drive circuit according to any one of claims 1 to 14; A pixel circuit as claimed in any one of claims 15 to 22.

24. The display control circuit according to claim 23, characterized in that: The pixel circuit further includes a second target transistor, which is located on a data signal writing path between the second electrode and the gate of the driving transistor; The display control circuit further includes: A row gate driving circuit, used for outputting an initial row scanning signal; A scanning control circuit, wherein the input end of the scanning control circuit is connected to the row gate driving circuit, and is used to generate a target row scanning signal according to the initial row scanning signal and the second enable control signal, and output it to the second target transistor, wherein the second target transistor is located on the data signal writing path between the second electrode and the gate of the driving transistor.

25. The display control circuit according to claim 24, characterized in that: When the second enable control signal is in the first level state, the level state of the target scanning signal is the same as that of the initial scanning signal; When the second enable control signal is in a second level state, the level state of the target row scan signal is a target level state, wherein the first level state is different from the second level state, and the target level state is a level state that turns off the second target transistor.

26. A display panel, characterized in that: The display panel comprises: The display control circuit according to any one of claims 23 to 25; A controller is connected to the column gate driving circuit and is used to provide the data signal, the first gate control signal and the first enable control signal.

27. The display panel according to claim 26, characterized in that: The controller is further used to obtain a picture to be displayed, determine a refresh area and a non-refresh area according to the picture to be displayed, and output the data signal, the first gate control signal and the first enable control signal to the column gate drive circuit; Among them, the first enable control signal received by the column gate drive circuit connected to the pixels in the refresh area is in a first level state, so that the level state of the target column scan signal is a level state that turns on the first target transistor; the first enable control signal received by the column gate drive circuit connected to the pixels in the non-refresh area is in a second level state, so that the level state of the target column scan signal is a level state that turns off the first target transistor.

28. The display panel according to claim 27, characterized in that: The display control circuit also includes: a row gate drive circuit and a scan control circuit; The row gate driving circuit is used to output an initial row scanning signal; The input end of the scanning control circuit is connected to the row gate driving circuit, and is used to generate a target row scanning signal according to the initial row scanning signal and the second enabling control signal, and output it to the second target transistor, which is located on the data signal writing path between the second electrode and the gate of the driving transistor; In which, the controller is also used to output a second enable control signal to the scanning control circuit; when the second enable control signal is in a first level state, the scanning control circuit outputs a target row scanning signal to control the conduction of the second target transistor in the pixel circuit of the refresh area; when the second enable control signal is in a second level state, the scanning control circuit outputs a target row scanning signal to control the disconnection of the second target transistor in the pixel circuit corresponding to the non-refresh area.

29. The display panel according to any one of claims 26 to 28, characterized in that: The controller is a display driver chip.

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