Nonvolatile dual-port storage and calculation integrated unit circuit, chip and electronic equipment

Abstract

The embodiment of the invention discloses a nonvolatile dual-port storage and calculation integrated unit circuit, a dual-port storage and calculation integrated array circuit, a chip and electronic equipment, and the nonvolatile dual-port storage and calculation integrated unit circuit comprises two nonvolatile storage units, a write selection unit, a calculation selection unit, an analog-to-digital conversion unit and a calculation unit. A write selection unit selects an input data storage unit from the two nonvolatile storage units and stores the weight data into the input data storage unit; the analog-to-digital conversion unit performs analog-to-digital conversion on the analog weight data, and the calculation selection unit generates data to be calculated and generates a calculation control signal; and the calculation unit calculates the target digital weight data and the to-be-calculated data according to the calculation control signal. According to the embodiment of the invention, calculation is carried out while data is written, the efficiency of data calculation is improved, the nonvolatile storage unit is adopted to store data, data loss after circuit power failure is avoided, and the application range of the circuit is further expanded.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a non-volatile dual-port storage-computing integrated unit circuit, a dual-port storage-computing integrated array circuit, a chip and an electronic device. Background Art

[0002] Computing-in-Memory (CIM) refers to the technology of combining computing with storage and directly embedding algorithms inside the memory. Simply put, it is to operate the data input into the neural network with the weight parameters pre-stored in the memory unit to realize the weighted accumulation of the input data, which is the convolution operation. The convolution operation is the core component unit of the deep learning algorithm and accounts for more than 90% of the operations in most current artificial intelligence (AI) chips. This means that through the new architecture of computing-in-memory, 90% or even more of the operations can be completed and output directly by the memory.

[0003] Currently, the common storage and computing integrated memory is generally a single-port storage and computing integrated memory (Single-Port Computing-in-Memory, SP-CIM), that is, one port is provided to access the memory, and at the same time, only write operations or computing operations can be performed on the memory through a single port.

[0004] In the calculation of neural networks, data processing is mainly performed in the form of a matrix rather than a single row or column. Each write operation can only write one row of weight data, which means that before the calculation, at least Y write operations are required to ensure that the storage cell array in the CIM is filled with weight data, where Y is the total number of rows in the storage cell array.

[0005] However, SP-CIM has only one port and cannot support simultaneous writing and computing operations, so it is impossible for SP-CIM to maintain peak computing power for a long time. In addition, since it takes a long time to write a large amount of data to SP-CIM, the long writing time will interrupt the computing process, thus affecting the final computing efficiency.

[0006] In addition, most existing SP-CIMs use volatile random access memory cells to store input data, which means that after the memory loses power, the stored data cannot be saved. Therefore, how to further improve the computing efficiency of the storage-computing integrated memory and avoid data loss after the memory loses power is a problem that needs to be solved. Summary of the invention

[0007] An embodiment of the present disclosure provides a non-volatile dual-port integrated storage and computing unit circuit, which includes: two non-volatile storage units, a write selection unit, an analog-to-digital conversion unit, a calculation selection unit and a calculation unit; the write selection unit is used to select an input data storage unit for storing currently input weight data from the two non-volatile storage units according to an input write selection signal, and store the weight data in the input data storage unit in the form of analog weight data; the analog-to-digital conversion unit is used to perform analog-to-digital conversion on the analog weight data stored in the two non-volatile storage units respectively, to obtain digital weight data corresponding to the two non-volatile storage units respectively; the calculation selection unit is used to convert the input initial data to be calculated into data to be calculated, and output the data to be calculated to the calculation unit; and generate a calculation control signal according to the input calculation selection signal, and output the calculation control signal to the calculation unit; the calculation unit is used to obtain the target digital weight data indicated by the calculation control signal from the analog-to-digital conversion unit according to the calculation control signal, and calculate the target digital weight data and the data to be calculated to obtain the calculation result and output the calculation result.

[0008] According to another aspect of the embodiments of the present disclosure, a dual-port storage and computing integrated array circuit is provided, the circuit comprising: a controller, a dual-port storage and computing module array and a first preset number of computing selection units; the dual-port storage and computing module array comprises a first preset number of dual-port storage and computing module groups, each dual-port storage and computing module group comprises a second preset number of dual-port storage and computing modules, each dual-port storage and computing module comprises two non-volatile storage units, a write selection unit, an analog-to-digital conversion unit and a computing unit in the above-mentioned non-volatile dual-port storage and computing integrated unit circuit, each dual-port storage and computing module group corresponds to a computing selection unit, and the computing selection unit is a computing selection unit in the above-mentioned non-volatile dual-port storage and computing integrated unit circuit; the controller is used to send a write selection signal to the write selection unit included in each dual-port storage and computing module , the write selection unit stores the input weight data into the non-volatile storage unit corresponding to the write selection signal; the controller is also used to send a calculation selection signal to the calculation selection unit corresponding to each dual-port storage and calculation module group; for each calculation selection unit in the first preset number of calculation selection units, the calculation selection unit is used to generate a calculation control signal corresponding to the calculation selection signal according to the calculation selection signal, and output the calculation control signal and the data to be calculated corresponding to the calculation selection unit to the second preset number of calculation units corresponding to the calculation selection unit; the calculation unit is used to receive the target digital weight data indicated by the calculation control signal from the corresponding analog-to-digital conversion unit according to the calculation control signal, and calculate the target digital weight data and the received data to be calculated, obtain the calculation result and output the calculation result.

[0009] According to another aspect of an embodiment of the present disclosure, a chip is provided, which includes the above-mentioned non-volatile dual-port storage-computation-in-one unit circuit or dual-port storage-computation-in-one array circuit.

[0010] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, the electronic device comprising the above chip.

[0011] The non-volatile dual-port integrated storage and computing unit circuit, dual-port integrated storage and computing array circuit, chip and electronic device provided by the above-mentioned embodiments of the present disclosure include two non-volatile storage units, a write selection unit, a calculation selection unit, an analog-to-digital conversion unit and a calculation unit in the non-volatile dual-port integrated storage and computing unit circuit. The write selection unit selects an input data storage unit from the two non-volatile storage units according to an input write selection signal, and stores the weight data into the input data storage unit in the form of analog weight data. The analog-to-digital conversion unit performs analog-to-digital conversion on the analog weight data respectively stored in the two non-volatile storage units to obtain digital weight data. The calculation selection unit generates and outputs a calculation control signal and data to be calculated to the calculation unit according to the input calculation selection signal. The calculation unit receives the target digital weight data indicated by the calculation control signal from the analog-to-digital conversion unit according to the calculation control signal, and calculates the target digital weight data and the data to be calculated to obtain a calculation result. The circuit provided by the embodiment of the present disclosure can enable two non-volatile storage units to perform data writing operations and data calculation operations at the same time. Compared with the existing single-port storage and calculation integrated memory, while writing weight data to a part of the storage units in the storage and calculation array, the stored weight data can be extracted from another part of the storage units to perform calculations with the input initial data to be calculated, and the calculation efficiency is greatly improved. It also realizes that the writing and calculation of weight data are independent of each other and do not interfere with each other. The two can be performed in parallel. The circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications. In addition, the circuit provided by the embodiment of the present disclosure uses a non-volatile storage unit to store analog weight data. After converting the analog weight data into digital weight data, the calculation operation is performed according to the processing method of the digital signal, thereby improving the calculation efficiency of the circuit, avoiding data loss after the circuit is powered off, and further expanding the scope of application of the circuit.

[0012] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps;

[0014] Figure 1 It is a structural schematic diagram of a non-volatile dual-port integrated storage and computing unit circuit provided by an exemplary embodiment of the present disclosure;

[0015] Figure 2 is another structural schematic diagram of a non-volatile dual-port integrated storage and computing unit circuit provided by an exemplary embodiment of the present disclosure;

[0016] Figure 3 is another structural schematic diagram of a non-volatile dual-port integrated storage and computing unit circuit provided by an exemplary embodiment of the present disclosure;

[0017] Figure 4 is another structural schematic diagram of a non-volatile dual-port integrated storage and computing unit circuit provided by an exemplary embodiment of the present disclosure;

[0018] Figure 5 is an exemplary structural diagram of a computing unit provided by an exemplary embodiment of the present disclosure;

[0019] Figure 6 It is a structural diagram of a dual-port storage-computation-in-one array circuit provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0021] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0022] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0023] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0024] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0025] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0026] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0027] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0028] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0029] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0030] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0031] Application Overview

[0032] In order to solve the computing efficiency bottleneck and data loss after the memory is powered off in the current single-port storage and computing integrated memory, the embodiments of the present disclosure provide a non-volatile dual-port storage and computing integrated unit circuit and a dual-port storage and computing integrated array circuit. Multiple non-volatile dual-port storage and computing integrated unit circuits can be included in the dual-port storage and computing integrated array circuit. The non-volatile dual-port storage and computing integrated unit circuit is composed of two non-volatile storage units, a write selection unit, a calculation selection unit, an analog-to-digital conversion unit and a calculation unit. Through the analog-to-digital conversion unit, the analog weight data stored in the two non-volatile storage units can be converted into digital weight data. Through the write selection unit and the calculation selection unit, data writing operations and data calculation operations can be performed on the two non-volatile storage units at the same time.

[0033] Compared with the existing single-port storage and computing integrated memory, the circuit provided by the embodiment of the present disclosure can extract the stored weight data and the input feature data from another part of the storage unit for operation while writing weight data to a part of the storage unit in the storage and computing array, thereby realizing that the writing and calculation of weight data are independent of each other and do not interfere with each other, and the two can be performed in parallel. The circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications. In addition, the circuit provided by the embodiment of the present disclosure uses a non-volatile storage unit to store analog weight data. After converting the analog weight data into digital weight data, the calculation operation is performed according to the processing method of the digital signal, thereby improving the calculation efficiency of the circuit, avoiding data loss after the circuit is powered off, and further expanding the scope of application of the circuit.

[0034] Exemplary Structure

[0035] Figure 1 The schematic diagram of the structure of a non-volatile dual-port integrated storage and computing unit circuit provided by an exemplary embodiment of the present disclosure is shown in FIG. The various components included in the circuit can be integrated into one chip, or can be set in different chips or circuit boards, and data communication links are established between these chips or circuit boards.

[0036] like Figure 1 As shown, the circuit includes: two non-volatile storage units 101, a write selection unit 102, an analog-to-digital conversion unit 103, a calculation selection unit 104, and a calculation unit 105. Among them, the non-volatile storage unit refers to a random access memory device in which the stored data does not disappear after the power is cut off. For example, the type of the non-volatile storage unit used in this embodiment can be a resistance random access memory (RRAM), a magnetic random access memory (MRAM), etc.

[0037] In this embodiment, the write selection unit 102 is used to select an input data storage unit for storing the currently input weight data from the two non-volatile storage units 101 according to the input write selection signal, and store the weight data in the input data storage unit in a manner of simulating weight data. Generally, the circuit provided in this embodiment can be applied in a neural network accelerator, so the weight data can be a weight parameter involved in the calculation in the neural network.

[0038] The two non-volatile storage units 101 are usually used to store single bits included in the input multi-bit weight data, which are the weight data described above. The non-volatile storage unit can usually be equivalent to a resistor or a conductance, and the resistance value of the resistor is adjusted by programming operation to write the weight data. The stored weight data is in the form of an analog signal. In this embodiment, the analog signal is called analog weight data.

[0039] The non-volatile dual-port integrated storage and computing unit circuit provided in this embodiment can generally constitute an integrated storage and computing module in an integrated storage and computing array. Figure 1 As shown, WD ij is the input single-bit weight data, i and j represent the position of the storage-computation-integrated module based on the non-volatile dual-port storage-computation-integrated unit circuit in the storage-computation-integrated array, i is the row number, and j is the column number. Figure 1 When the first nonvolatile storage unit 1011 in the embodiment is an input data storage unit, the single-bit weight data input to the first nonvolatile storage unit 1011 is represented as WD ij [0], when the write selection unit 102 selects Figure 1 When the second non-volatile storage unit 1012 in the embodiment is an input data storage unit, the single-bit weight data input to the second non-volatile storage unit 1012 is represented as WD ij [1].

[0040] The write selection unit 102 may be implemented by using a device such as a transistor, for example, an analog switch device, and the state of the analog switch device may be changed by changing the write selection signal. Figure 1 As shown, the write selection signal is represented by WRT_MUX_SEL, and WRT_MUX_SELB is the inversion of WRT_MUX_SEL. When WRT_MUX_SEL is 1 and WRT_MUX_SELB is 0, the write selection signal will be WD ij When the first non-volatile storage unit 1011 is input, WRT_MUX_SEL is 0 and WRT_MUX_SELB is 1, the write selection signal WD ij Input the second non-volatile storage unit 1012.

[0041] In this embodiment, the analog-to-digital conversion unit 103 is used to perform analog-to-digital conversion on the analog weight data stored in the two non-volatile storage units 101 to obtain digital weight data corresponding to the two non-volatile storage units 101. Figure 1 As shown, the first non-volatile storage unit 1011 stores the simulation weight data BL ij [0] is output to the analog-to-digital conversion unit 103, and the second non-volatile storage unit 1012 converts the analog weight data BLij [1] is output to the analog-to-digital conversion unit 103, which can ij [0] Perform analog-to-digital conversion to obtain Bit0 or Bitb0 (Bitb0 is the inverted data of Bit0), and ij [1] Perform analog-to-digital conversion to obtain Bit1 or Bitb1 (Bitb1 is the inverted data of Bit1).

[0042] Optionally, the analog-to-digital conversion unit 103 may include two analog-to-digital converters, which respectively perform analog-to-digital conversion on the analog weight data stored in the first non-volatile storage unit 1011 and the second non-volatile storage unit 1012 to obtain digital weight data corresponding to the first non-volatile storage unit 1011 and the second non-volatile storage unit 1012. Alternatively, the analog-to-digital conversion unit 103 may also include an analog-to-digital converter and a selection switch, and the selection switch may switch the non-volatile storage unit connected to the analog-to-digital converter under the control of the input calculation selection signal, thereby performing analog-to-digital conversion on the analog weight data stored in the currently connected non-volatile storage unit to obtain digital weight data.

[0043] In this embodiment, the calculation selection unit 104 is used to convert the input initial data to be calculated into data to be calculated, and output the data to be calculated to the calculation unit 105; and generate a calculation control signal according to the input calculation selection signal, and output the calculation control signal to the calculation unit 105.

[0044] The initial data to be calculated may be data in the neural network to be used for calculation with weight data, such as text data, image data, audio data, video data, and feature data obtained by extracting features from the above data. Usually, the initial data to be calculated is single-bit data, for example, the initial data to be calculated may be a bit included in multi-bit feature data in the neural network. Figure 1 As shown, NN j The calculation selection unit 104 can further generate data to be calculated based on the initial data to be calculated, and output the data to be calculated to the calculation unit 105. For example, the calculation selection unit 104 can perform an inversion operation on the initial data to be calculated, and output the inverted data NN to the calculation unit 105. j b is output as the data to be calculated to the calculation unit 105. Alternatively, the calculation selection unit 104 may directly output the initial data to be calculated to the calculation unit 105. In this case, the data to be calculated is the same as the initial data to be calculated.

[0045] The above-mentioned calculation control signal is used to control the on-off of the line through which the digital weight data output by the above-mentioned analog-to-digital conversion unit 103 enters the calculation unit 105. Usually, the calculation control signal can be a fixed high level (indicating "1") or a low level (indicating "0"). Optionally, the calculation selection unit 104 can output the calculation selection signal as a calculation control signal to the calculation unit 105, or the calculation selection unit 104 can include two output terminals, and generate a corresponding calculation control signal according to the calculation selection signal, and the calculation control signal is output to the calculation unit 105 by the output terminal corresponding to the calculation selection signal, and the calculation unit 105 receives the corresponding digital weight data according to the calculation control signal for calculation. For example, when Figure 1 When the calculation selection signal CIM_MUX_SEL shown is 1, the calculation control signal CIM_CTR output by the calculation selection unit 104 instructs the calculation unit 105 to receive the digital weight data Bit0 or Bitb0 corresponding to the first non-volatile storage unit 1011 for calculation; when the calculation selection signal CIM_MUX_SEL is 0, CIM_CTR instructs the calculation unit 105 to receive the digital weight data Bit1 or Bitb1 corresponding to the second non-volatile storage unit 1012 for calculation.

[0046] In this embodiment, the calculation unit 105 is used to obtain the target digital weight data indicated by the calculation control signal from the analog-to-digital conversion unit 103 according to the calculation control signal, and calculate the target digital weight data and the data to be calculated to obtain the calculation result and output the calculation result.

[0047] As an example, the computing unit 105 may include two multipliers, and a controlled switch may also be provided inside the computing unit 105. The controlled switch may control the digital weight signal corresponding to the first non-volatile storage unit 1011 output by the analog-to-digital conversion unit 103 to enter the multiplier indicated by the computing control signal according to the received computing control signal, and the multiplier calculates the input digital weight data and the data to be calculated.

[0048] It should be noted that the calculation unit 105 in this embodiment can be set according to the application scenario of the dual-port storage and calculation integrated circuit. For example, the calculation unit 105 can be a multiplier, a NOR gate, etc. Generally, when the dual-port storage and calculation integrated circuit provided in this embodiment is used for the operation of a neural network, the calculation result output by the calculation unit 105 is the product of the initial data to be calculated and the weight data, that is, Figure 1 The NN shown j With WD ij [0] or WD ij The product of [1].

[0049] The above-mentioned embodiments of the present disclosure provide a non-volatile dual-port integrated storage and computing unit circuit, in which two non-volatile storage units, a write selection unit, a computing selection unit, an analog-to-digital conversion unit and a computing unit are arranged. The write selection unit selects an input data storage unit from the two non-volatile storage units according to an input write selection signal, and stores the weight data into the input data storage unit in the form of analog weight data. The analog-to-digital conversion unit performs analog-to-digital conversion on the analog weight data respectively stored in the two non-volatile storage units to obtain digital weight data. The computing selection unit generates and outputs a computing control signal and data to be calculated to the computing unit according to the input computing selection signal. The computing unit receives the target digital weight data indicated by the computing control signal from the analog-to-digital conversion unit according to the computing control signal, and calculates the target digital weight data and the data to be calculated to obtain a calculation result. The circuit provided by the embodiment of the present disclosure can enable two non-volatile storage units to perform data writing operations and data calculation operations at the same time. Compared with the existing single-port storage and calculation integrated memory, while writing weight data to a part of the storage units in the storage and calculation array, the stored weight data can be extracted from another part of the storage units and the input initial data to be calculated for calculation, so that the writing of weight data and the use of weight data for calculation are independent and do not interfere with each other. The two can be performed in parallel, and the calculation efficiency is greatly improved. The circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications. In addition, the circuit provided by the embodiment of the present disclosure uses a non-volatile storage unit to store analog weight data. After the analog weight data is converted into digital weight data by an analog-to-digital conversion unit, the calculation operation is performed according to the processing method of the digital signal. On the basis of improving the calculation efficiency of the circuit, the data loss caused by the power failure of the circuit and the possible need for repeated writing are avoided, and the scope of application of the circuit is further expanded.

[0050] In some optional implementations, the analog-to-digital conversion unit 103 is further configured to:

[0051] The input calculation selection signal is received, a target non-volatile storage unit is determined from the two non-volatile storage units 101 according to the calculation selection signal, and the analog weight data stored in the target non-volatile storage unit is converted into digital weight data.

[0052] like Figure 2 As shown, the calculation selection signal CIM_MUX_SEL is simultaneously input into the analog-to-digital conversion unit 103 and the calculation selection unit 104. An analog-to-digital converter and a signal switching switch can be set inside the analog-to-digital conversion unit 103. The signal switching switch can select to perform analog-to-digital conversion on the analog weight data in the first non-volatile storage unit 1011 when CIM_MUX_SEL is 1, and output Figure 2The digital weight data Bit0 or Bitb0 corresponding to the first non-volatile storage unit 1011 shown in the figure; the signal switching switch can perform analog-to-digital conversion on the analog weight data in the second non-volatile storage unit 1012 when CIM_MUX_SEL is 0, and output Figure 2 The digital weight data Bit1 or Bitb1 corresponding to the second non-volatile memory unit 1012 is shown.

[0053] In this embodiment, under the control of the calculation selection signal, the analog-to-digital conversion unit selects the analog-to-digital conversion of the analog weight data stored in one of the non-volatile storage units, without the need to separately set up a corresponding analog-to-digital converter for each non-volatile storage unit, thereby reducing the number of components in the analog-to-digital conversion unit, reducing the area occupied by the analog-to-digital conversion unit, and thereby reducing the power consumption and cost of the entire circuit.

[0054] In some optional implementations, such as Figure 2 As shown, the calculation selection unit 104 includes a first output terminal 1041 and a second output terminal 1042 .

[0055] The calculation selection unit 104 is further used for:

[0056] When the calculation selection signal is the first signal, the data to be calculated is output to the calculation unit 105 through the first output terminal 1041; a calculation control signal is generated and the calculation control signal is output to the calculation unit 105 through the second output terminal 1042;

[0057] When the calculation selection signal is the second signal, the data to be calculated is output to the calculation unit 105 through the second output terminal 1042; a calculation control signal is generated and the calculation control signal is output to the calculation unit 105 through the first output terminal 1041;

[0058] The calculation unit 105 is further configured to:

[0059] When receiving the calculation control signal output by the second output terminal 1042, the digital weight data corresponding to the first non-volatile storage unit 1011 of the two non-volatile storage units 101 is used as the target digital weight data to calculate with the data to be calculated, and the calculation result is obtained and output;

[0060] When the calculation control signal output by the first output terminal 1041 is received, the digital weight data corresponding to the second non-volatile storage unit 1012 of the two non-volatile storage units 101 is used as the target digital weight data to calculate with the data to be calculated, and the calculation result is obtained and output.

[0061] Specifically, assuming that the first signal is digital "1", the second signal is digital "0", the calculation control signal is digital "1". Figure 2 As shown, if the calculation selection signal CIM_MUX_SEL is "1", the calculation unit 105 receives the data to be calculated from the first output terminal 1041 of the calculation selection unit, and at the same time, the controlled switch connected to the second output terminal 1042 inside the calculation unit 105 disconnects the line between the port for outputting Bit1 or Bitb1 of the analog-to-digital conversion unit 103 and the calculation unit 105 under the action of the calculation control signal, and connects the line between the port for outputting Bit0 or Bitb0 and the calculation unit 105, so that the calculation unit 105 can then calculate Bit0 or Bitb0 and the input data to be calculated. Similarly, if the calculation selection signal CIM_MUX_SEL is "0", the calculation unit 105 receives the data to be calculated from the second output terminal 1042 of the calculation selection unit, and at the same time, the controlled switch connected to the first output terminal 1041 inside the calculation unit 105 disconnects the line between the port for outputting Bit0 or Bitb0 of the analog-to-digital conversion unit 103 and the calculation unit 105 under the action of the calculation control signal, and at the same time connects the line between the port for outputting Bit1 or Bitb1 of the analog-to-digital conversion unit 103 and the calculation unit 105, and the calculation unit 105 can then calculate Bit1 or Bitb1 and the input data to be calculated. The above-mentioned controlled switch can use devices such as transistors to realize its function.

[0062] This embodiment, by setting the first output terminal and the second output terminal in the calculation selection unit, can make the calculation unit receive the calculation control signal from one of the output terminals more quickly and specifically, and then receive the currently selected digital weight data from the analog-to-digital conversion unit, and receive the data to be calculated from the other output terminal of the calculation selection unit, thereby facilitating the flexible switching of the storage units involved in the calculation and improving the efficiency of the calculation. The calculation unit can not only complete the calculation of the stored weight data and the input data to be calculated, but also switch the non-volatile storage unit involved in the calculation between the two non-volatile storage units according to the calculation control signal, without the need to separately set a device for switching the path of the digital weight data entering the calculation unit before each calculation unit, thereby improving the integration of the circuit, reducing the number of components, and thus reducing the area, power consumption and cost of the circuit.

[0063] In some optional implementations, the computing unit 105 includes a first multiplier 1051 and a second multiplier 1052 , the first multiplier 1051 is connected to the first output terminal 1041 , and the second multiplier 1052 is connected to the second output terminal 1042 .

[0064] The second multiplier 1052 is used to prohibit the calculation of the digital weight data corresponding to the second non-volatile storage unit 1012 when receiving the calculation control signal output by the second output terminal 1042; the first multiplier 1051 is used to calculate the digital weight data corresponding to the first non-volatile storage unit 1011 and the data to be calculated when receiving the data to be calculated output by the first output terminal 1041, obtain the multiplication result and output the multiplication result.

[0065] The first multiplier 1051 is used to prohibit the calculation of the digital weight data corresponding to the first non-volatile storage unit 1011 when receiving the calculation control signal output by the first output terminal 1041; the second multiplier 1052 is used to calculate the digital weight data corresponding to the second non-volatile storage unit 1012 and the data to be calculated when receiving the data to be calculated output by the second output terminal 1042, to obtain the multiplication result and output the multiplication result.

[0066] Specifically, Figure 2 As shown, the first multiplier 1051 is connected to the first output terminal 1041, and the second multiplier 1052 is connected to the second output terminal 1042, and the first multiplier 1051 and the second multiplier 1052 are physically connected. When CIM_MUX_SEL is "1", the initial data NN to be calculated is j After being processed by the calculation selection unit 104, the data to be calculated NN is generated j b0 (for example, it can be NN j Inverted data, or directly NN j As the data output to be calculated), NN j b0 is output from the first output terminal 1041 to the first multiplier 1051. At the same time, the second output terminal 1042 is connected to a fixed level (e.g., a high level), that is, the calculation control signal "1" is output from the second output terminal 1042 to the second multiplier 1052, and the controlled switch device included in the second multiplier 1052 disconnects the line between the port for outputting Bit1 or Bitb1 of the analog-to-digital conversion unit 103 and the second multiplier 1052, and at the same time activates the function of the first multiplier 1051. The first multiplier 1051 performs a comparison between the inverted data Bitb0 of the digital weight data Bit0 output by the analog-to-digital conversion unit 103 and the NN j b0 (or directly process Bit0 and NN j b0 is processed) to obtain the multiplication result (i.e. Bit0*NN j 0).

[0067] Similarly, when CIM_MUX_SEL is "0", NN j After being processed by the calculation selection unit 104, the data to be calculated NN is generated jb1,NN j b1 is output from the second output terminal 1042 to the second multiplier 1052. At the same time, the first output terminal 1041 outputs the calculation control signal "1" to the first multiplier 1051, and the controlled switch device included in the first multiplier 1051 disconnects the line between the port for outputting Bit0 or Bitb0 of the analog-to-digital conversion unit 103 and the first multiplier 1051, and activates the function of the second multiplier 1052. The second multiplier 1052 performs a calculation on the inverted data Bitb1 of the digital weight data Bit1 output by the analog-to-digital conversion unit 103 and the NN j b1 (or directly process Bit1 and NN j b1 is processed) to obtain the multiplication result (i.e. Bit1*NN j 1).

[0068] It should be noted that this embodiment does not limit the implementation method of the multiplier. For example, the multiplication calculation can be implemented by an AND gate, or by a combination of a NOT gate and a NOR gate.

[0069] This embodiment realizes switching between the first multiplier and the second multiplier according to the calculation selection signal by setting the first multiplier and the second multiplier in the calculation unit, and the first multiplier and the second multiplier perform multiplication calculations on the weight data and the initial data to be calculated in the first non-volatile storage unit and the second non-volatile storage unit in turn. This circuit can be applied to processes such as convolution operations of neural networks, which helps to improve the calculation efficiency of neural network accelerators. In addition, in the neural network accelerator, multiple calculation units can correspond to the same calculation selection unit, so there is no need to set a calculation selection unit 104 for each pair of storage units separately. The first multiplier and the second multiplier of the calculation unit can realize switching in different storage units, which simplifies the circuit structure and improves the integration of the circuit.

[0070] In some optional implementations, the first multiplier 1051 includes a first NOR gate, and the second multiplier 1052 includes a second NOR gate; the calculation selection unit 104 includes an inverter 1043 and an output selector 1044 .

[0071] The inverter 1043 is used to perform an inversion operation on the initial data to be calculated to obtain the data to be calculated.

[0072] The output selector 1044 is used to output the data to be calculated from the first output terminal 1041 to the first NOR gate when the calculation selection signal is the first signal; and to output the data to be calculated from the second output terminal 1042 to the second NOR gate when the calculation selection signal is the second signal.

[0073] The first NOR gate is used to receive the first inverted digital weight data corresponding to the first non-volatile storage unit 1011 output by the analog-to-digital conversion unit 103, and perform NOR calculation on the data to be calculated and the first inverted digital weight data to obtain the multiplication result of the weight data input into the first non-volatile storage unit 1011 and the initial data to be calculated.

[0074] The second NOR gate is used to receive the second inverted digital weight data corresponding to the second non-volatile storage unit 1012 output by the analog-to-digital conversion unit 103, and perform NOR calculation on the data to be calculated and the second inverted digital weight data to obtain the multiplication result of the weight data input into the second non-volatile storage unit 1012 and the initial data to be calculated.

[0075] Specifically, Figure 3 As shown, the first NOR gate may include P1, P2, N2, N4, and the second NOR gate may include P3, P4, N1, N3. The first NOR gate and the second NOR gate have a common data output terminal Q. P1, P2, P3, P4 are P-type MOS transistors, and N1, N2, N3, N4 are N-type MOS transistors. VDD represents a high level, and GND represents a low level.

[0076] like Figure 3 As shown, Bitb0 is the inverted data of the digital weight data Bit0, Bit0 is the digital weight data obtained by performing analog-to-digital conversion on the analog weight data in the first non-volatile storage unit 1011, and the analog-to-digital conversion unit 103 outputs Bitb0 to the first NOR gate. Similarly, the analog-to-digital conversion unit 103 outputs Bitb1 corresponding to the second non-volatile storage unit 1012 to the second NOR gate.

[0077] Figure 3 The specific execution process of the circuit shown is: when CIM_MUX_SEL is 1, the first output terminal 1041 outputs NN j The inverted data NN j b0, and at the same time, the NN outputted by the second output terminal 1042 j If b1 is high (indicating digital "1"), P4 is turned off and N3 is turned on. The second NOR gate composed of P3, P4, N1, and N3 cannot perform NOR calculation. The first NOR gate composed of P1, P2, N2, and N4 inputs NN. j b0 and Bitb0 are ORed, and the calculation result output at the Q end is equivalent to NN j The product of bit 1 and bit 0.

[0078] When CIM_MUX_SEL is 0, the second output terminal 1042 outputs NN j The inverted data NN j b1, and at the same time, the NN outputted by the first output terminal 1041j If b0 is high, P2 is turned off and N4 is turned on. The first NOR gate cannot perform NOR calculation. The second NOR gate inputs NN. j b1 and Bitb1 are ORed, and the calculation result output at the Q end is equivalent to NN j The product of bit 1 and bit 2.

[0079] It should be understood that Figure 3 The circuit structure is only an exemplary structure, and the type and position of the components constituting the calculation unit 105 can be arbitrarily set as needed. As long as the circuit architecture can realize the functions of the first multiplier 1051 and the second multiplier 1052, it is within the scope of the embodiment of the present disclosure. Figure 3 Bitb0 in the input is changed from input P1 to input P2, and NN j b0 is changed from input P2 to input P1.

[0080] In this embodiment, by setting the first NOR gate and the second NOR gate, the two output ends of the calculation selection unit switch the first NOR gate and the second NOR gate. There is no need to set other control elements in the calculation unit to select the non-volatile storage unit participating in the calculation between the first non-volatile storage unit and the second non-volatile storage unit, thereby reducing the number of components used, simplifying the circuit structure, helping to reduce the area occupied by the circuit, and reducing power consumption and cost.

[0081] In some optional implementations, the calculation selection unit 104 is further configured to:

[0082] In response to receiving the read data mode selection signal, a corresponding read control signal is generated according to the calculation selection signal, and the read control signal is output through two output terminals included in the calculation selection unit 104.

[0083] like Figure 3 As shown, BIST_MODE represents the input mode selection signal. When BIST_MODE=0, it indicates that the read data mode selection signal is received. Correspondingly, when BIST_MODE=1, it indicates that the calculation mode selection signal is received. It should be understood that the schemes described in the above embodiments are all operating processes in the calculation mode.

[0084] As an example, Figure 3When the calculation selection signal CIM_MUX_SEL shown is 1, a read data control signal indicating that the weight data is read from the first non-volatile storage unit 1011 can be generated. When CIM_MUX_SEL is 0, a read data control signal indicating that the weight data is read from the second non-volatile storage unit 1012 can be generated. The read data control signal can be composed of the signals output by the first output terminal 1041 and the second output terminal 1042. For example, when Figure 3 The NN shown j b0 is "0", NN j When b1 is "1", it indicates that the weight data is read from the first non-volatile storage unit 1011. j b0 is "1", NN j When b1 is “0”, it indicates that the weight data is read from the second non-volatile storage unit 1012 .

[0085] The calculation unit 105 is further configured to:

[0086] When the read control signal is the third signal, the line between the first digital signal output terminal of the analog-to-digital conversion unit 103 and the data output terminal of the calculation unit 105 is controlled to be connected, and the digital weight data corresponding to the first non-volatile storage unit 1011 is output from the data output terminal.

[0087] When the read control signal is the fourth signal, the line between the second digital signal output terminal of the analog-to-digital conversion unit 103 and the data output terminal of the calculation unit 105 is controlled to be connected, and the digital weight data corresponding to the second non-volatile storage unit 1012 is output from the data output terminal.

[0088] The first digital signal output terminal of the analog-to-digital conversion unit 103 may be: Figure 3 The port for outputting Bitb0 shown in FIG. 1 may be a port for outputting Bitb0, and the second digital signal output terminal of the analog-to-digital conversion unit 103 may be a port for outputting Bitb0. Figure 3 The port shown is used to output Bitb1.

[0089] The third signal and the fourth signal may be a combination signal of the first output terminal 1041 and the second output terminal 1042. Figure 3 The NN shown j b0 is "0", NN j When b1 is "1", it indicates that the read data signal is the third signal; when NN j b0 is "1", NN j When b1 is "0", it indicates that the read data signal is the fourth signal.

[0090] like Figure 3 As shown, when NN j b0 is "0", NN jWhen b1 is "1", P4 is turned off and N3 is turned on, and the output terminal Q of the calculation unit 105 cannot change with the change of Bitb1. At the same time, P2 is turned on and N4 is turned off, and the Q terminal can change with the change of Bitb0, thereby realizing the reading of weight data from the first non-volatile storage unit.

[0091] Similarly, when NN j b0 is "1", NN j When b1 is "0", the Q end cannot change with the change of Bitb0, but can change with the change of Bitb1, thereby realizing the reading of weight data from the second non-volatile storage unit.

[0092] This embodiment achieves accurate reading of weight data from a non-volatile storage unit by controlling the on / off of a line between an output terminal of the calculation unit 105 and two digital signal output terminals of the analog-to-digital conversion unit 103 by a read control signal, thereby improving the convenience of reading data in a read data mode.

[0093] Optionally, the computing unit 105 is further configured to:

[0094] When the read control signal is the third signal, the line between the first digital signal output terminal of the analog-to-digital conversion unit 103 and the data output terminal of the calculation unit 105 is controlled to be conductive; the first inverted digital weight data output by the first digital signal output terminal is received, and the first inverted digital weight data is inverted to obtain the digital weight data corresponding to the first non-volatile storage unit 1011, and the digital weight data corresponding to the first non-volatile storage unit 1011 is output.

[0095] When the read control signal is the fourth signal, the line between the second digital signal output terminal of the analog-to-digital conversion unit 103 and the data output terminal of the calculation unit 105 is controlled to be conductive; the second inverted digital weight data output by the second digital signal output terminal is received, and the second inverted digital weight data is inverted to obtain the digital weight data corresponding to the second non-volatile storage unit 1012, and the digital weight data corresponding to the second non-volatile storage unit 1012 is output.

[0096] Specifically, Figure 3 As shown, the first inverted weight data is Bitb0, and the second inverted weight data is Bitb1. j b0 is "0", NN j When b1 is "1", it means that the read data signal is the third signal. At this time, P4 is off, N3 is on, P2 is on, N4 is off, and P1, P2, N3, and N2 form an inverter. Therefore, the Q terminal outputs the inverted data Bit0 of Bitb0, that is, the Q terminal outputs the digital weight data corresponding to the first non-volatile storage unit 1011. Similarly, when NN jb0 is "1", NN j When b1 is "0", it means that the read data signal is the fourth signal. At this time, P2 is cut off, P4 is turned on, N3 is cut off, N4 is turned on, P3, P4, N1, and N4 form an inverter. Therefore, the Q end outputs the inverted data Bit1 of Bitb1, that is, the Q end outputs the digital weight data corresponding to the second non-volatile storage unit 1012.

[0097] This embodiment realizes the inversion operation of the inverted weight data output by the analog-to-digital conversion unit without changing the structure of the calculation unit, thereby outputting the weight data in the non-volatile storage unit, effectively utilizing the structure of the calculation unit, and realizing an efficient weight data reading function.

[0098] In some optional implementations, such as Figure 4 As shown, the calculation selection unit 104 includes a first control switch 1041 and a second control switch 1042;

[0099] The first control switch 1041 is used to receive a calculation selection signal, and when the calculation selection signal is a first signal, input the first digital weight data corresponding to the first signal output by the analog-to-digital conversion unit 103 into the calculation unit 105 .

[0100] The second control switch 1042 is used to receive a calculation selection signal, and when the calculation selection signal is a second signal, input the second digital weight data corresponding to the second signal output by the analog-to-digital conversion unit 103 into the calculation unit 105 .

[0101] The calculation unit 105 includes a multiplier for receiving input data to be calculated, performing multiplication calculation on the first digital weight data or the second digital weight data, and outputting a multiplication calculation result. It should be noted that this embodiment does not limit the implementation method of the multiplier. For example, the multiplication calculation can be implemented by an AND gate, or by combining a NOT gate and a NOR gate 1053 to implement the multiplication calculation.

[0102] like Figure 4 As shown, the calculation selection signal is represented by CIM_MUX_SEL, and CIM_MUX_SELB is calculated by the selection unit 104 ( Figure 4 The first control switch 1041 is a signal that inverts CIM_MUX_SEL (not shown). Bit0 is the digital weight data corresponding to the first non-volatile storage unit 1011, and Bit1 is the digital weight data corresponding to the second non-volatile storage unit 1012. When CIM_MUX_SEL is a first signal (e.g., "1"), the first control switch 1041 can input Bit0 into the calculation unit 105. When CIM_MUX_SEL is a second signal (e.g., "0"), the second control switch 1042 can input Bit1 into the calculation unit 105.

[0103] The first control switch 1041 and the second control switch 1042 can be implemented by using devices such as transistors, and the first control switch 1041 and the second control switch 1042 can be turned on or off according to the calculation selection signal. Generally, the first control switch 1041 and the second control switch 1042 perform opposite operations under the same calculation selection signal. For example, when the calculation selection signal is the first signal (e.g., "1"), the first control switch 1041 inputs Bit0 into the calculation unit 105, and the second control switch 1042 is turned off; when the calculation selection signal is the second signal (e.g., "0"), the second control switch 1042 inputs Bit1 into the calculation unit 105, and the first control switch 1041 is turned off. In this way, only one storage unit can be selected to participate in the calculation at the same time, and the storage unit that does not participate in the calculation can receive the weight data stored therein.

[0104] This embodiment achieves simple and efficient switching of the data to be calculated by setting the first control switch and the second control switch in the calculation selection unit, and flexibly selects the non-volatile storage unit participating in the calculation from multiple non-volatile storage units, which helps to efficiently calculate the weight data in a part of the non-volatile storage units in the storage and calculation array while writing data to another part of the non-volatile storage units, thereby improving the flexibility of circuit configuration and operating efficiency.

[0105] Optional, such as Figure 4 As shown, the computing unit 105 may include a first inverter 1051 , a second inverter 1052 , and a NOT gate 1053 .

[0106] The first inverter 1051 is used for performing an inversion operation on the first digital weight data to obtain first inverted digital weight data when the calculation selection signal is the first signal, and inputting the first inverted digital weight data into the NOR gate 1053 .

[0107] The second inverter 1052 is used for performing an inversion operation on the second digital weight data to obtain second inverted digital weight data when the calculation selection signal is the second signal, and inputting the second inverted digital weight data into the NOR gate 1053 .

[0108] The NOR gate 1053 is used to perform a NOR operation on the data to be calculated and the input first inverted digital weight data when the calculation selection signal is the first signal, and output the multiplication calculation result of the initial data to be calculated and the first digital weight data; when the calculation selection signal is the second signal, perform a NOR operation on the data to be calculated and the input second inverted digital weight data, and output the multiplication calculation result of the initial data to be calculated and the second digital weight data.

[0109] like Figure 4As shown, the first control switch 1041 can control the first inverter 1051 to output the data Bitb inverted for Bit0 when the calculation selection signal CIM_MUX_SEL is the first signal (e.g., "1"). The second control switch 1042 can control the second inverter 1052 to output the data Bitb inverted for Bit1 when the calculation selection signal CIM_MUX_SEL is the second signal (e.g., "0").

[0110] Generally, the first control switch 1041 and the second control switch 1042 perform opposite operations under the same calculation selection signal. For example, when the calculation selection signal is "1", the first control switch 1041 enables the first inverter 1051, and the second control switch 1042 disables the second inverter 1052; when the calculation selection signal is "0", the first control switch 1041 disables the first inverter 1051, and the first inverter 1051 is disabled.

[0111] like Figure 4 As shown, the data to be calculated is the initial data to be calculated NN output by the calculation selection unit 104. j Negated data NN j b, NOR gate 1053 to NN j b and Bitb are OR-not operated, and the output data is NN j The product of Bit0 or Bit1.

[0112] By setting a first inverter, a second inverter, and an NOR gate in the calculation unit, it is achieved that under the control of the first control switch and the second control switch, the weight data stored in the non-volatile storage unit currently selected for the calculation and the data to be calculated are multiplied. The circuit structure and function implementation are simpler, which helps to improve the efficiency of circuit configuration, reduce the cost of circuit implementation, and reduce the complexity of circuit operation. At the same time, multiplication calculation is performed by means of inverters and NOR gates, which can increase the swing of the level of the weight data and the data to be calculated, and improve the accuracy of the calculation.

[0113] Optionally, the computing unit 105 is further configured to:

[0114] In response to receiving a read data mode selection signal, a read control signal is generated; based on the read control signal, the weight data stored in the storage unit currently selected by the calculation selection unit 104 is output.

[0115] The above-mentioned read control signal is used to control whether the weight data input by the calculation selection unit 104 to the calculation unit 105 participates in the operation. As an example, the calculation unit 105 may include a data selection switch. When a read data mode selection signal is received, the read data mode selection signal can be used as a read control signal, and the data selection switch is controlled by the read control signal to connect the calculation selection unit 104 with the data output terminal of the calculation unit 105, thereby outputting the weight data stored in the storage unit currently selected by the calculation selection unit 104. Correspondingly, when a calculation data mode selection signal is received, the calculation data mode selection signal can be used as a calculation control signal, and the data selection switch is controlled by the calculation control signal to connect the weight data input by the calculation selection unit 104 with the data to be calculated NN input to the calculation unit 105. j Perform calculations and output the results.

[0116] As another example, Figure 4 As shown in the figure, BIST_MODE indicates the input mode selection signal. When BIST_MODE=0, it indicates that the read data mode selection signal is received. When BIST_MODE=1, it indicates that the calculation mode selection signal is received. When the read data mode selection signal is received, NN j b is set to 0, and the NOR gate 1053 inverts Bitb after inverting Bit0 or Bit1 again, and outputs Bit0 or Bit1, thereby realizing the reading of weight data from the currently selected storage unit. Correspondingly, when the calculation data mode selection signal is received, NN j b is directly input to NOR gate 1053, NN j b and Bitb are OR-not operated, and the output data is NN j The product of Bit0 or Bit1.

[0117] This embodiment realizes switching between the data reading mode and the calculation mode by using the calculation unit, and can flexibly control the function of the circuit without changing the circuit structure, thereby further expanding the application scope of the circuit.

[0118] Optionally, the first control switch 1041 may include a first switch element and a second switch element, the first switch element being used to connect the first inverter 1051 to a level representing first data when the calculation selection signal is the first signal, and the second switch element being used to connect the first inverter 1051 to a level representing second data when the calculation selection signal is the first signal.

[0119] The second control switch 1042 includes a third switch element and a fourth switch element. The third switch element is used to connect the second inverter 1052 to the level representing the first data when the calculation selection signal is the second signal, and the fourth switch element is used to connect the second inverter 1052 to the level representing the second data when the calculation selection signal is the second signal.

[0120] like Figure 5 As shown, it shows an exemplary structural diagram of the calculation unit 105, the first inverter 1051 includes P2 and N1, the second inverter 1052 includes P4 and N3, the first control switch 1041 includes a first switch element and a second switch element P1 and N2 respectively, and the second control switch 1042 includes a third switch element and a fourth switch element P3 and N4 respectively. P1, P2, P3, and P4 are P-type MOS tubes, and N1, N2, N3, and N4 are N-type MOS tubes. Assume that the first signal is "1" (corresponding to the high level VDD), the first data is "1" (corresponding to the high level), and the second data is "0" (corresponding to the low level GND), that is, when CIM_MUX_SEL is 1, CIM_MUX_SELB is 0, at this time P1 and N2 are both turned on, P3 and N4 are both turned off, that is, P2 and N1 included in the first inverter 1051 are enabled, and P4 and N3 included in the second inverter 1052 are prohibited from outputting data, and the output Bitb is the inverted data of Bit0 (the first inverted digital weight data). Similarly, let the second signal be "0" (corresponding to a low level), that is, when CIM_MUX_SEL is 0, CIM_MUX_SELB is 1, at which time P3 and N4 are both turned on, and P1 and N2 are both turned off, that is, P4 and N3 included in the second inverter 1052 are enabled, and P2 and N1 included in the first inverter 1051 are prohibited from outputting data, and the output Bitb is the inverted data of Bit1 (the second inverted digital weight data). Bitb and NN j b input NOR gate 1053.

[0121] It should be understood that Figure 5 The types and positions of the first switch element, the second switch element, the third switch element and the fourth switch element shown, as well as the types and positions of the devices constituting the first inverter 1051 and the second inverter 1052 can be arbitrarily set as needed, as long as the circuit architecture that can realize the functions of the first inverter 1051, the second inverter 1052, the first control switch 1041 and the second control switch 1042 is within the scope of the embodiments of the present disclosure. For example, Bit0 can be changed from P2 and N1 input to P1 and N2 input, Bit1 can be changed from P4 and N3 input to P3 and N4 input; CIM_MUX_SEL can be changed from P3 and N2 input to P4 and N1 input, and CIM_MUX_SELB can be changed from P1 and N3 input to P2 and N3 input.

[0122] Above Figure 5 P1, P2, N1, N2, and P3, P4, N3, N4 shown constitute a three-state buffer gate, which can effectively isolate the weight data involved in the calculation from the weight data not involved in the calculation, thereby improving the accuracy of circuit storage and calculation.

[0123] This embodiment realizes the function of realizing the calculation selection signal with fewer components by setting the first switch element, the second switch element, the third switch element, and the fourth switch element in cooperation with the first inverter and the second inverter. Moreover, it is only necessary to switch the calculation selection signal between the first signal and the second signal to realize the selection of the non-volatile storage unit participating in the calculation between the two non-volatile storage units, thereby simplifying the circuit structure and reducing the complexity of the circuit operation.

[0124] Figure 6 The schematic diagram of the structure of a dual-port storage-computation integrated array circuit provided by an exemplary embodiment of the present disclosure is shown in FIG. The various components included in the circuit can be integrated into one chip, or can be set in different chips or circuit boards, and data communication links are established between these chips or circuit boards.

[0125] like Figure 6 As shown, the dual-port storage and computing integrated array circuit includes: a controller 601, a first preset number of computing selection units 602 and a dual-port storage and computing module array 603.

[0126] In this embodiment, the dual-port storage and computing module array 603 includes a first preset number of dual-port storage and computing module groups, each of which includes a second preset number of dual-port storage and computing modules, and each dual-port storage and computing module includes the above Figure 1-Figure 5 The two non-volatile storage units, write selection unit, analog-to-digital conversion unit and computing unit in the non-volatile dual-port storage and computing integrated unit circuit described in any corresponding embodiment, each dual-port storage and computing module group corresponds to a computing selection unit, and the computing selection unit is the computing selection unit in the above-mentioned non-volatile dual-port storage and computing integrated unit circuit.

[0127] like Figure 6 As shown, the first preset number may be the number of rows of the dual-port storage and computing module array 603, and the second preset number may be the number of columns of the dual-port storage and computing module array 603. The number of rows and the number of columns of the dual-port storage and computing module array 603 in the figure are Y, and X, respectively. 0,0 、2P-CIM C 0,1 ……2P-CIM C Y-1,X-1Each row of the dual-port storage and calculation module array 603 in the figure corresponds to a calculation selection unit (including CIM_SEL0-CIM_SEL Y-1 ).

[0128] Each row of the dual-port storage and calculation module array 603 can simultaneously input multi-bit weight data, and each bit of the multi-bit weight data is correspondingly stored in a non-volatile storage unit in a dual-port storage and calculation module. Figure 6 As shown, the single-bit weight data included in the L multi-bit weight data corresponding to the input in row 0 is represented as WD 0,0 -WD 0,X-1 The single-bit weight data included in the L multi-bit weight data corresponding to the input in the Y-1th row is represented as WD Y-1,0 -WD Y-1,X-1 WD 0,0 -WD 0,X-1 is divided into L groups, each group includes K single bits, and K single bits constitute a multi-bit weight data. Similarly, WD Y-1,0 -WD Y-1,X-1 It is divided into L groups, each group includes K single bits, and K single bits constitute a multi-bit weight data. For example, X is 32, and a row can store 4 8-bit weight data. The initial data to be calculated input to each row can usually be a single bit contained in a multi-bit data (such as N-bit data), that is, the single bit contained in the multi-bit data is expressed as NN0-NN N-1 The multi-bit data may be, for example, multi-bit feature data to be calculated in a neural network. During calculation, based on the calculation clock, multiple groups of data to be calculated are calculated in sequence. For example, in the first calculation clock cycle, NN0-NN1 of the first multi-bit data is calculated. N-1 The corresponding rows are input respectively, and each calculation unit included in the corresponding row calculates the input data to be calculated and the stored weight data; in the second calculation clock cycle, NN0-NN of the second multi-bit data is calculated. N-1 The corresponding rows are input respectively, and the calculation units included in the corresponding rows calculate the input data to be calculated and the stored weight data. This process is repeated until the calculation of multiple multi-bit data is completed.

[0129] It should be noted that the number of bits N of the input multi-bit data may be the same as or different from the number of rows Y of the dual-port storage and computing module array 603. For the convenience of description in the drawings, the number of bits N and Y of the multi-bit data shown in 6 are the same, that is, the data to be calculated input in each calculation cycle includes NN0-NN Y-1. In order to make the dual-port storage and computing module array 603 more versatile, the number of rows Y of the dual-port storage and computing module array 603 is usually set to a larger value, and the number of bits N of the input multi-bit data is less than Y. Therefore, one or more multi-bit data can be input in one calculation cycle. For example, when N is 8 and Y is 16, one multi-bit data can be input in one calculation cycle, that is, NN0-NN7 are input to 8 rows respectively, or 2 multi-bit data can be input in one calculation cycle, that is, NN0-NN7 of the first multi-bit data are input to the first 8 rows respectively, and NN0-NN7 of the second multi-bit data are input to the second 8 rows respectively.

[0130] In this embodiment, the controller 601 is used to send a write selection signal to the write selection unit included in each dual-port storage and calculation module, and the write selection unit stores the input weight data into the non-volatile storage unit corresponding to the write selection signal. Figure 6 As shown, the write selection signals corresponding to each row are all WRT_MUX_SEL, that is, weight data can be written to each row at the same time.

[0131] Optional, such as Figure 6 As shown, each row of the dual-port memory module array 603 corresponds to two word lines, WWL i [0] (first word line) and WWL i [1] (second word line), where i is the row number. i [0] corresponds to the first non-volatile storage unit of each dual-port storage and computing module in the i-th row, WWL i [1] The second non-volatile storage unit included in each dual-port storage and computing module of the corresponding i-th row. For a row of the dual-port storage and computing module array 603, each write selection unit located in the row can select a target word line from the first word line and the second word line corresponding to the row according to the received write selection signal, and store the input weight data into the non-volatile storage unit corresponding to the target word line.

[0132] In this embodiment, the controller 601 is further configured to send a calculation selection signal to the calculation selection unit corresponding to each dual-port storage and calculation module group. Figure 6 As shown, the calculation selection signals corresponding to each row are all CIM_MUX_SEL, that is, each row can be controlled to perform calculation at the same time.

[0133] Typically, the write selection signal and the calculation selection signal sent at the same time correspond to different storage units in each dual-port storage and calculation module. In the current calculation operation, the controller 601 can send a calculation selection signal for selecting a first non-volatile storage unit from the corresponding two non-volatile storage units for calculation to the calculation selection unit included in each dual-port storage and calculation module. At the same time, when it is necessary to write weight data to the second non-volatile storage unit of the two non-volatile storage units, the controller 601 can send a write selection signal for selecting the second non-volatile storage unit from the corresponding two non-volatile storage units for data writing to the write selection unit included in each dual-port storage and calculation module. The write selection unit can store the received weight data in the second non-volatile storage unit according to the write selection signal.

[0134] After at least one calculation operation is completed using the first non-volatile storage unit included in each dual-port storage and calculation module, if it is necessary to use the weight data stored in the second non-volatile storage unit included in each dual-port storage and calculation module to perform a calculation operation, the controller 601 can send a calculation selection signal for selecting the second non-volatile storage unit from the corresponding two non-volatile storage units to perform calculations to the calculation selection unit included in each dual-port storage and calculation module. At the same time, when it is necessary to write weight data to the first non-volatile storage unit of the two non-volatile storage units, the controller 601 can also send a write selection signal for selecting the first non-volatile storage unit from the corresponding two non-volatile storage units to write data to the write selection unit included in each dual-port storage and calculation module, and the write selection unit can store the received weight data in the first non-volatile storage unit according to the write selection signal.

[0135] Through the above process, in the process of performing a calculation operation using a non-volatile storage unit included in each dual-port storage and calculation module, another non-volatile storage unit included in each dual-port storage and calculation module can store the currently input weight data. When the calculation operation is completed, if it is necessary to switch the weight data and the input data to be calculated for calculation, the non-volatile storage unit participating in the calculation can be switched between the two non-volatile storage units included in each dual-port storage and calculation module, and new weight data can be input to the other non-volatile storage unit at the same time, thereby realizing the independence of the write operation and the calculation operation of the dual-port storage and calculation module array 603.

[0136] In this embodiment, for each calculation selection unit in the first preset number of calculation selection units 602, the calculation selection unit is used to generate a calculation control signal corresponding to the calculation selection signal based on the calculation selection signal, and output the calculation control signal and the data to be calculated corresponding to the calculation selection unit to the second preset number of calculation units corresponding to the calculation selection unit.

[0137] In this embodiment, the calculation unit is used to receive the target digital weight data indicated by the calculation control signal from the corresponding analog-to-digital conversion unit according to the calculation control signal, and calculate the target digital weight data and the received data to be calculated to obtain and output the calculation result.

[0138] Specifically, Figure 6 Each calculation selection unit shown is connected to each calculation unit in the corresponding row, and each calculation unit can simultaneously use the to-be-calculated data and the calculation control signal received from the calculation selection unit to perform calculation. The calculation process can refer to the above Figure 1-Figure 5 The contents described in the corresponding embodiments will not be repeated here.

[0139] The dual-port storage and calculation integrated array circuit provided by the above-mentioned embodiment of the present disclosure, by using the above-mentioned non-volatile dual-port storage and calculation integrated unit circuit, constructs the dual-port storage and calculation integrated module array including the dual-port storage and calculation integrated module array, and can write weight data to a part of the non-volatile storage unit in the dual-port storage and calculation integrated module array, while extracting the stored weight data from another part of the non-volatile storage unit and the input data to be calculated for calculation, so that the writing weight data and the calculation using the weight data are independent and do not interfere with each other, and the calculation efficiency is greatly improved. The circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications. In addition, the circuit provided in this embodiment uses a non-volatile storage unit to store analog weight data, and after converting the analog weight data into digital weight data through an analog-to-digital conversion unit, the calculation operation is performed according to the processing method of the digital signal. On the basis of improving the calculation efficiency of the circuit, the data loss caused by the power failure of the circuit and the need for repeated writing that may occur are avoided, and the scope of application of the circuit is further expanded.

[0140] Optional, such as Figure 6 As shown, the circuit further includes an addition tree 604 and a shift accumulator 605 .

[0141] The addition tree 604 is used to accumulate the calculation results output by the dual-port storage and calculation modules located at the same position in each dual-port storage and calculation module group to obtain a first accumulation result. Figure 6 As shown, when each row of the dual-port storage and calculation modules is used as a dual-port storage and calculation module group, when each dual-port storage and calculation module finishes calculating, the addition tree 604 can accumulate the calculation results output by the dual-port storage and calculation modules included in each column of the array to obtain the first accumulation result corresponding to each column (s0-s1 in the figure). X-1 ). It should be noted that Figure 6 s0-s X-1 are the results of multiplying and adding Y single-bit weight data and the data to be calculated, that is, s0-s X-1are all multi-bit data. For example, if the number of rows Y is 32, then s0-s X-1 It is the result of multiplication and addition of 32 pairs of single-bit data, and the number of bits can be 6.

[0142] The shift accumulator 605 is used to perform shift accumulation on each first accumulation result to obtain a second accumulation result (SUM0-SUM L-1 ). Usually, when the shift accumulator 605 performs a shift-accumulate operation, it targets s0-s X-1 For example, if the number of columns X involved in the operation is 32, and each row stores 4 (i.e. L is 4) 8-bit weight data, then s0-s X-1 It can be divided into 4 groups, and each group of data performs shift accumulation respectively, and the obtained SUM contains 4 second accumulation results, and each second accumulation result is the result of multiplying and adding Y 8-bit weight data and Y data to be calculated.

[0143] Optionally, since the neural network usually performs multiplication and addition calculations on a one-to-one correspondence of a plurality of multi-bit input data (such as feature data) and a plurality of multi-bit weight data, after performing multiplication and accumulation calculations on a plurality of single-bit data to be calculated and a plurality of single-bit weight data input each time, the second accumulation results obtained each time can be shifted and accumulated multiple times to obtain the multiplication and addition results of the plurality of multi-bit input data and the plurality of multi-bit weight data.

[0144] This embodiment realizes the calculation and shift accumulation of multiple multi-bit feature data and multiple multi-bit weight data by setting an addition tree and a shift accumulator. Therefore, when the dual-port storage and computing module array is applied to a neural network computing scenario, the neural network calculation and the weight data are written to the dual-port storage and computing module array efficiently at the same time, thereby improving the efficiency of the neural network calculation.

[0145] Optionally, the circuit can also switch between calculation mode and read data mode. The controller 601 can send a read data mode selection signal or a calculation mode selection signal to the calculation selection unit. The first preset number of calculation selection units 602 can generate a corresponding read control signal in response to receiving the read data mode selection signal according to the calculation selection signal, and output the read control signal to the corresponding calculation unit through the two output ends of the calculation selection unit. Each calculation unit determines the read data storage unit from the corresponding two non-volatile storage units according to the read control signal, and outputs the weight data stored in the read data storage unit.

[0146] like Figure 6As shown, BIST_MODE represents the input mode selection signal. When BIST_MODE=0, it represents the read data mode selection signal. Correspondingly, when BIST_MODE=1, it represents the calculation mode selection signal. It should be noted that Figure 6 The object to which the mode selection signal is input is only an optional implementation method. The mode selection signal can also be input into the computing unit included in the dual-port storage and computing module array (such as Figure 4 The scheme shown), the computing unit switches between the computing mode and the data reading mode.

[0147] It should be understood that the calculation processes described in the above embodiments are all operating processes in the calculation mode. In addition, for the working process in the data reading mode, reference can be made to the relevant description of the above dual-port storage and calculation integrated circuit.

[0148] The embodiment of the present disclosure further provides a chip on which a non-volatile dual-port storage-computing integrated unit circuit or a dual-port storage-computing integrated array circuit is integrated. The technical details of the non-volatile dual-port storage-computing integrated unit circuit are as follows: Figure 1-Figure 5 As shown in the relevant description, the technical details of the dual-port storage and computing array circuit are as follows Figure 6 As shown in the relevant description, no further description is given here.

[0149] The embodiments of the present disclosure also provide an electronic device, which includes the chip described in the above embodiments. In addition, the electronic device may also include an input device, an output device, and necessary memory, etc. Among them, the input device may include such as a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting weight data and feature data. The output device may include such as a display, a printer, and a communication network and its connected remote output device, etc., for outputting calculation results, etc. The memory is used to store the data input by the above input device, as well as the data generated during the operation of the non-volatile dual-port storage and calculation integrated unit circuit or the dual-port storage and calculation integrated array circuit. The memory may include volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0150] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0151] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other.

[0152] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0153] The circuits of the present disclosure may be implemented in many ways. For example, the circuits of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps of the method used in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the functions of the circuits of the present disclosure. Thus, the present disclosure also covers recording media storing programs for executing the functions of the circuits of the present disclosure.

[0154] It should also be noted that in the circuit of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as an equivalent solution of the present disclosure.

[0155] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0156] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A non-volatile dual-port storage and computing unit circuit, comprising: two non-volatile storage units, a write selection unit, an analog-to-digital conversion unit, a calculation selection unit, and a calculation unit; The write selection unit is used to select an input data storage unit for storing currently input weight data from the two non-volatile storage units according to an input write selection signal, and store the weight data into the input data storage unit in a manner of simulating weight data; The analog-to-digital conversion unit is used to perform analog-to-digital conversion on the analog weight data stored in the two non-volatile storage units to obtain digital weight data corresponding to the two non-volatile storage units respectively; The calculation selection unit is used to convert the input initial data to be calculated into data to be calculated, and output the data to be calculated to the calculation unit; and generating a calculation control signal according to the input calculation selection signal, and outputting the calculation control signal to the calculation unit; The calculation unit is used to obtain the target digital weight data indicated by the calculation control signal from the analog-to-digital conversion unit according to the calculation control signal, and calculate the target digital weight data and the data to be calculated to obtain a calculation result and output the calculation result.

2. The circuit according to claim 1, wherein The analog-to-digital conversion unit is further used for: The input calculation selection signal is received, a target non-volatile storage unit is determined from the two non-volatile storage units according to the calculation selection signal, and the analog weight data stored in the target non-volatile storage unit is converted into digital weight data.

3. The circuit according to claim 1, wherein: The calculation selection unit includes a first output terminal and a second output terminal; The calculation selection unit is further used for: When the calculation selection signal is the first signal, the data to be calculated is output to the calculation unit through the first output terminal; a calculation control signal is generated and the calculation control signal is output to the calculation unit through the second output terminal; When the calculation selection signal is the second signal, the data to be calculated is output to the calculation unit through the second output terminal; a calculation control signal is generated and the calculation control signal is output to the calculation unit through the first output terminal; The computing unit is further configured to: When receiving the calculation control signal output by the second output terminal, the digital weight data corresponding to the first non-volatile storage unit of the two non-volatile storage units is used as the target digital weight data to calculate with the data to be calculated, to obtain a calculation result and output the calculation result; When the calculation control signal output by the first output terminal is received, the digital weight data corresponding to the second non-volatile storage unit of the two non-volatile storage units is used as the target digital weight data to calculate with the data to be calculated, and a calculation result is obtained and output.

4. The circuit according to claim 3, wherein: The calculation unit includes a first multiplier and a second multiplier, the first multiplier is connected to the first output terminal, and the second multiplier is connected to the second output terminal; The second multiplier is used to prohibit the calculation of the digital weight data corresponding to the second non-volatile storage unit when receiving the calculation control signal output by the second output terminal; the first multiplier is used to calculate the digital weight data corresponding to the first non-volatile storage unit and the data to be calculated when receiving the data to be calculated output by the first output terminal, obtain a multiplication result and output the multiplication result; The first multiplier is used to prohibit the calculation of the digital weight data corresponding to the first non-volatile storage unit when receiving the calculation control signal output by the first output end; the second multiplier is used to calculate the digital weight data corresponding to the second non-volatile storage unit and the data to be calculated when receiving the data to be calculated output by the second output end, obtain the multiplication result and output the multiplication result.

5. The circuit according to claim 4, wherein: The first multiplier includes a first NOR gate, and the second multiplier includes a second NOR gate; the calculation selection unit includes an inverter and an output terminal selector; The inverter is used to perform an inversion operation on the initial data to be calculated to obtain the data to be calculated; The output terminal selector is used to output the data to be calculated from the first output terminal to the first NOR gate when the calculation selection signal is a first signal; and to output the data to be calculated from the second output terminal to the second NOR gate when the calculation selection signal is a second signal; The first NOR gate is used to receive the first inverted digital weight data corresponding to the first non-volatile memory unit output by the analog-to-digital conversion unit, and perform NOR calculation on the data to be calculated and the first inverted digital weight data to obtain a multiplication calculation result of the weight data input into the first non-volatile memory unit and the initial data to be calculated; The second NOR gate is used to receive the second inverted digital weight data corresponding to the second non-volatile storage unit output by the analog-to-digital conversion unit, and perform NOR calculation on the data to be calculated and the second inverted digital weight data to obtain the multiplication result of the weight data input into the second non-volatile storage unit and the initial data to be calculated.

6. The circuit according to any one of claims 1 to 5, wherein: The calculation selection unit is further used for: In response to receiving a read data mode selection signal, generating a corresponding read control signal according to the calculation selection signal, and outputting the read control signal through two output terminals included in the calculation selection unit; The computing unit is further configured to: When the read control signal is a third signal, controlling the line between the first digital signal output terminal of the analog-to-digital conversion unit and the data output terminal of the calculation unit to be connected, and outputting the digital weight data corresponding to the first non-volatile storage unit from the data output terminal; When the read control signal is the fourth signal, the line between the second digital signal output terminal of the analog-to-digital conversion unit and the data output terminal of the calculation unit is controlled to be connected, and the digital weight data corresponding to the second non-volatile storage unit is output by the data output terminal.

7. The circuit according to claim 1, wherein: The calculation selection unit includes a first control switch and a second control switch; The first control switch is used to receive the calculation selection signal, and when the calculation selection signal is a first signal, input the first digital weight data corresponding to the first signal output by the analog-to-digital conversion unit into the calculation unit as the target digital weight data; The second control switch is used to receive the calculation selection signal, and when the calculation selection signal is a second signal, input the second digital weight data corresponding to the second signal output by the analog-to-digital conversion unit as the target digital weight data into the calculation unit; The calculation unit includes a multiplier, which is used to receive input data to be calculated, perform multiplication calculation on the first weight data or the second weight data, and output the multiplication calculation result.

8. A dual-port storage and computing integrated array circuit, comprising: A controller, a dual-port storage and computing module array, and a first preset number of computing selection units; The dual-port storage and computing module array includes a first preset number of dual-port storage and computing module groups, each dual-port storage and computing module group includes a second preset number of dual-port storage and computing modules, each dual-port storage and computing module includes two non-volatile storage units, a write selection unit, an analog-to-digital conversion unit and a computing unit in the non-volatile dual-port storage and computing integrated unit circuit according to any one of claims 1 to 7, each dual-port storage and computing module group corresponds to a computing selection unit, and the computing selection unit is a computing selection unit in the non-volatile dual-port storage and computing integrated unit circuit according to any one of claims 1 to 7; The controller is used to send a write selection signal to a write selection unit included in each dual-port storage and calculation module, and the write selection unit stores the input weight data into a non-volatile storage unit corresponding to the write selection signal; The controller is also used to send a calculation selection signal to the calculation selection unit corresponding to each dual-port storage and calculation module group; For each of the first preset number of calculation selection units, the calculation selection unit is used to generate a calculation control signal corresponding to the calculation selection signal according to the calculation selection signal, and output the calculation control signal and the to-be-calculated data corresponding to the calculation selection unit to the second preset number of calculation units corresponding to the calculation selection unit; The calculation unit is used to receive the target digital weight data indicated by the calculation control signal from the corresponding analog-to-digital conversion unit according to the calculation control signal, and calculate the target digital weight data and the received data to be calculated to obtain a calculation result and output the calculation result.

9. A chip, characterized in that: It comprises the non-volatile dual-port integrated storage and computing unit circuit according to any one of claims 1 to 7 or the dual-port integrated storage and computing array circuit according to claim 8.

10. An electronic device comprising the chip according to claim 9.

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