Memory, memory system, and operating method of memory

Abstract

The invention discloses a memory, a memory system and an operation method of the memory, and belongs to the technical field of storage. According to the memory, when each memory string in a memory block is erased, if a first memory string which is erased and a second memory string which is not erased exist in the memory strings, a selection line coupled with a first selection tube of the first memory string is floated in advance before a selection line coupled with a first selection tube of the second memory string is floated; therefore, the erasing speed of the first memory string is reduced, the first memory string is prevented from being excessively erased in the process of erasing the second memory string, the possibility of transverse diffusion of the memory units in the subsequent first memory string after programming is reduced, and the drift of the threshold voltage of the memory units in the first memory string is weakened.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a memory, a storage system, and a method for operating the memory. Background Art

[0002] With the development of semiconductor technology, memory is widely used in various types of electronic devices. In the process of operation, electronic devices inevitably perform erasing operations on storage blocks in the memory. When erasing storage blocks, due to different process parameters (process variation), the erasing speeds of various storage strings in the storage block are inconsistent, which leads to different erasing depths of various storage strings. The erasing depth can be expressed as the threshold voltage of the storage cell in the erased state in the storage string. If the threshold voltage of such storage cell is low, the storage string will show a deeper erasing depth. If the threshold voltage of such storage cell is high, the storage string will show a shallower erasing depth.

[0003] After being programmed, memory cells in a memory string with a deep erase depth are prone to lateral spreading, causing the threshold voltage of the memory cells to drift. Summary of the invention

[0004] The embodiments of the present application provide a memory, a memory system, and a memory operation method, which can reduce the lateral diffusion of a memory string and weaken the drift of the threshold voltage of a memory cell in the memory string. The technical solution is as follows:

[0005] In a first aspect, a memory is provided, the memory comprising a memory array and a peripheral circuit, the memory array comprising a memory block and a first selection line, the memory block comprising a plurality of memory strings, each memory string comprising a first selection tube, the first selection line being coupled to the first selection tube, and the peripheral circuit being coupled to the first selection line;

[0006] The peripheral circuit is configured to perform an erase operation on the plurality of storage strings in the storage block. To perform the erase operation, the peripheral circuit is configured as follows:

[0007] At a first moment, floating a first selection line coupled to a first selection transistor of a first storage string, wherein the first storage string is a storage string that has been erased among the plurality of storage strings;

[0008] At a second moment after the first moment, a first selection line coupled to a first selection transistor of a second storage string is floated, and the second storage string is a storage string that has not been completely erased among the plurality of storage strings.

[0009] In a possible implementation, the memory array further includes a first doped semiconductor layer and a plurality of word lines, the first doped semiconductor layer is coupled to one end of each memory string close to the first selection tube, each memory string further includes a plurality of memory cells, the plurality of word lines are respectively coupled to the plurality of memory cells of each memory string, and the peripheral circuit is also coupled to the plurality of word lines;

[0010] The peripheral circuit is further configured as:

[0011] At a third moment before the first moment, applying a first voltage to a first doped semiconductor layer coupled to each memory string in the memory block;

[0012] From the third moment to the first moment, applying a second voltage to the first selection line coupled to the first selection transistor of the first storage string, wherein the second voltage is less than the first voltage;

[0013] From the third moment to the second moment, applying the second voltage to the first selection line coupled to the first selection transistor of the second storage string;

[0014] At the third moment, a third voltage is applied to the word line coupled to each memory cell of each memory string in the memory block, and the third voltage is lower than the first voltage.

[0015] In a possible implementation, each memory string in the memory block further includes a second selection tube, the memory array further includes a second doped semiconductor layer and a second selection line, the second doped semiconductor layer is coupled to one end of each memory string close to the second selection tube, the second selection line is coupled to the second selection tube, and the peripheral circuit is also coupled to the second selection line;

[0016] The peripheral circuit is further configured as:

[0017] At the third moment, applying a fourth voltage to the second doped semiconductor layer coupled to each memory string in the memory block;

[0018] At the third moment, the second selection line coupled to the second selection transistor of each storage string in the storage block is floated.

[0019] In a possible implementation manner, the first doped semiconductor layer is coupled to a bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer.

[0020] In a possible implementation manner, the first doped semiconductor layer is coupled to a source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0021] In a possible implementation, each memory string in the memory block further includes a second selection tube, the memory array further includes a second doped semiconductor layer and a second selection line, the second doped semiconductor layer is coupled to one end of each memory string close to the second selection tube, the second selection line is coupled to the second selection tube, and the peripheral circuit is also coupled to the second selection line;

[0022] The peripheral circuit is further configured as:

[0023] At the third moment, a fifth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block.

[0024] In a possible implementation manner, the peripheral circuit is further configured as follows:

[0025] From the third moment to the second moment, applying a sixth voltage to the second selection line coupled to the second selection transistor of each storage string in the storage block, wherein the sixth voltage is less than the fifth voltage;

[0026] At the second moment, the second selection line coupled to the second selection transistor of each storage string in the storage block is floated.

[0027] In a possible implementation manner, the peripheral circuit is further configured as follows:

[0028] From the third moment to the fourth moment, a seventh voltage is applied to the second selection line coupled to the second selection tube of the first storage string, and at the fourth moment, the second selection line coupled to the second selection tube of the first storage string is floated, and the seventh voltage is less than the fifth voltage;

[0029] From the third moment to a fifth moment after the fourth moment, the seventh voltage is applied to the second selection line coupled to the second selection tube of the second storage string, and at the fifth moment, the second selection line coupled to the second selection tube of the second storage string is floated.

[0030] In a possible implementation, the first doped semiconductor layer is coupled to a bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer;

[0031] The second doped semiconductor layer is coupled to the source line, and the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0032] In a possible implementation, the first doped semiconductor layer is coupled to a source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer;

[0033] The second doped semiconductor layer is coupled to the bit line, and the second doped semiconductor layer is an N-type doped semiconductor layer.

[0034] In a possible implementation, the storage string includes multiple sub-strings, each sub-string includes a first selection tube and multiple storage units, each first selection tube in the same storage string is coupled to the same first selection line, and the first selection tubes in different storage strings are coupled to different first selection lines.

[0035] In a possible implementation manner, the peripheral circuit is further configured as follows:

[0036] At a sixth moment after the second moment, performing an erase verification operation on each storage string in the storage block;

[0037] In the case that there is a second memory string that fails the erasure verification in the memory block, the step of performing the erasing operation on the plurality of memory strings in the memory block is performed.

[0038] In a second aspect, a storage system is provided, the storage system comprising a memory configured to store data and a controller coupled to the memory and configured to control the memory, wherein the memory comprises a storage array and a peripheral circuit, the storage array comprises a storage block and a first selection line, the storage block comprises a plurality of storage strings, each storage string comprises a first selection tube, the first selection line is coupled to the first selection tube, and the peripheral circuit is coupled to the first selection line; the peripheral circuit is configured to perform an erase operation on the plurality of storage strings in the storage block, and to perform the erase operation, the peripheral circuit is configured as follows:

[0039] At a first moment, floating a first selection line coupled to a first selection transistor of a first storage string, wherein the first storage string is a storage string that has been erased among the plurality of storage strings;

[0040] At a second moment after the first moment, a first selection line coupled to a first selection transistor of a second storage string is floated, and the second storage string is a storage string that has not been completely erased among the plurality of storage strings.

[0041] In a possible implementation, the memory array further includes a first doped semiconductor layer and a plurality of word lines, the first doped semiconductor layer is coupled to one end of each memory string close to the first selection tube, each memory string further includes a plurality of memory cells, the plurality of word lines are respectively coupled to the plurality of memory cells of each memory string, and the peripheral circuit is also coupled to the plurality of word lines;

[0042] The peripheral circuit is further configured as:

[0043] At a third moment before the first moment, applying a first voltage to a first doped semiconductor layer coupled to each memory string in the memory block;

[0044] From the third moment to the first moment, applying a second voltage to the first selection line coupled to the first selection transistor of the first storage string, wherein the second voltage is less than the first voltage;

[0045] From the third moment to the second moment, applying the second voltage to the first selection line coupled to the first selection transistor of the second storage string;

[0046] At the third moment, a third voltage is applied to the word line coupled to each memory cell of each memory string in the memory block, and the third voltage is lower than the first voltage.

[0047] In a possible implementation, each memory string in the memory block further includes a second selection tube, the memory array further includes a second doped semiconductor layer and a second selection line, the second doped semiconductor layer is coupled to one end of each memory string close to the second selection tube, the second selection line is coupled to the second selection tube, and the peripheral circuit is also coupled to the second selection line;

[0048] The peripheral circuit is further configured as:

[0049] At the third moment, applying a fourth voltage to the second doped semiconductor layer coupled to each memory string in the memory block;

[0050] At the third moment, the second selection line coupled to the second selection transistor of each storage string in the storage block is floated.

[0051] In a possible implementation manner, the first doped semiconductor layer is coupled to a bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer.

[0052] In a possible implementation manner, the first doped semiconductor layer is coupled to a source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0053] In a possible implementation, each memory string in the memory block further includes a second selection tube, the memory array further includes a second doped semiconductor layer and a second selection line, the second doped semiconductor layer is coupled to one end of each memory string close to the second selection tube, the second selection line is coupled to the second selection tube, and the peripheral circuit is also coupled to the second selection line;

[0054] The peripheral circuit is further configured as:

[0055] At the third moment, a fifth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block.

[0056] In a possible implementation manner, the peripheral circuit is further configured as follows:

[0057] From the third moment to the second moment, applying a sixth voltage to the second selection line coupled to the second selection transistor of each storage string in the storage block, wherein the sixth voltage is less than the fifth voltage;

[0058] At the second moment, the second selection line coupled to the second selection transistor of each storage string in the storage block is floated.

[0059] In a possible implementation manner, the peripheral circuit is further configured as follows:

[0060] From the third moment to the fourth moment, a seventh voltage is applied to the second selection line coupled to the second selection tube of the first storage string, and at the fourth moment, the second selection line coupled to the second selection tube of the first storage string is floated, and the seventh voltage is less than the fifth voltage;

[0061] From the third moment to a fifth moment after the fourth moment, the seventh voltage is applied to the second selection line coupled to the second selection tube of the second storage string, and at the fifth moment, the second selection line coupled to the second selection tube of the second storage string is floated.

[0062] In a possible implementation, the first doped semiconductor layer is coupled to a bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer;

[0063] The second doped semiconductor layer is coupled to the source line, and the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0064] In a possible implementation, the first doped semiconductor layer is coupled to a source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer;

[0065] The second doped semiconductor layer is coupled to the bit line, and the second doped semiconductor layer is an N-type doped semiconductor layer.

[0066] In a possible implementation, the storage string includes multiple sub-strings, each sub-string includes a first selection tube and multiple storage units, each first selection tube in the same storage string is coupled to the same first selection line, and the first selection tubes in different storage strings are coupled to different first selection lines.

[0067] In a possible implementation manner, the peripheral circuit is further configured as follows:

[0068] At a sixth moment after the second moment, performing an erase verification operation on each storage string in the storage block;

[0069] In the case that there is a second memory string that fails the erasure verification in the memory block, the step of performing the erasing operation on the plurality of memory strings in the memory block is performed.

[0070] In a possible implementation, the storage system further includes a host; the host is coupled to the controller, and the host is configured to: send data to the memory or receive data from the memory through the controller.

[0071] In a third aspect, a method for operating a memory is provided, wherein the memory includes a memory array and a peripheral circuit, the memory array includes a memory block and a first selection line, the memory block includes a plurality of memory strings, each memory string includes a first selection tube, the first selection line is coupled to the first selection tube, and the peripheral circuit is coupled to the first selection line; the method includes performing an erasing operation on the plurality of memory strings in the memory block, the erasing operation including:

[0072] At a first moment, floating a first selection line coupled to a first selection transistor of a first storage string, wherein the first storage string is a storage string that has been erased among the plurality of storage strings;

[0073] At a second moment after the first moment, a first selection line coupled to a first selection transistor of a second storage string is floated, and the second storage string is a storage string that has not been completely erased among the plurality of storage strings.

[0074] In a possible implementation, the memory array further includes a first doped semiconductor layer and a plurality of word lines, the first doped semiconductor layer is coupled to one end of each memory string close to the first selection tube, each memory string further includes a plurality of memory cells, and the plurality of word lines are respectively coupled to the plurality of memory cells of each memory string;

[0075] The erasing operation further includes:

[0076] At a third moment before the first moment, applying a first voltage to a first doped semiconductor layer coupled to each memory string in the memory block;

[0077] From the third moment to the first moment, applying a second voltage to the first selection line coupled to the first selection transistor of the first storage string, wherein the second voltage is less than the first voltage;

[0078] From the third moment to the second moment, applying the second voltage to the first selection line coupled to the first selection transistor of the second storage string;

[0079] At the third moment, a third voltage is applied to the word line coupled to each memory cell of each memory string in the memory block, and the third voltage is lower than the first voltage.

[0080] In a possible implementation, each memory string in the memory block further includes a second selection tube, the memory array further includes a second doped semiconductor layer and a second selection line, the second doped semiconductor layer is coupled to one end of each memory string close to the second selection tube, and the second selection line is coupled to the second selection tube;

[0081] The erasing operation further includes:

[0082] At the third moment, applying a fourth voltage to the second doped semiconductor layer coupled to each memory string in the memory block;

[0083] At the third moment, the second selection line coupled to the second selection transistor of each storage string in the storage block is floated.

[0084] In a possible implementation manner, the first doped semiconductor layer is coupled to a bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer.

[0085] In a possible implementation manner, the first doped semiconductor layer is coupled to a source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0086] In a possible implementation, each memory string in the memory block further includes a second selection tube, the memory array further includes a second doped semiconductor layer and a second selection line, the second doped semiconductor layer is coupled to one end of each memory string close to the second selection tube, and the second selection line is coupled to the second selection tube;

[0087] The erasing operation further includes:

[0088] At the third moment, a fifth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block.

[0089] In a possible implementation manner, the erasing operation further includes:

[0090] From the third moment to the second moment, applying a sixth voltage to the second selection line coupled to the second selection transistor of each storage string in the storage block, wherein the sixth voltage is less than the fifth voltage;

[0091] At the second moment, the second selection line coupled to the second selection transistor of each storage string in the storage block is floated.

[0092] In a possible implementation manner, the erasing operation further includes:

[0093] From the third moment to the fourth moment, a seventh voltage is applied to the second selection line coupled to the second selection tube of the first storage string, and at the fourth moment, the second selection line coupled to the second selection tube of the first storage string is floated, and the seventh voltage is less than the fifth voltage;

[0094] From the third moment to a fifth moment after the fourth moment, the seventh voltage is applied to the second selection line coupled to the second selection tube of the second storage string, and at the fifth moment, the second selection line coupled to the second selection tube of the second storage string is floated.

[0095] In a possible implementation, the first doped semiconductor layer is coupled to a bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer;

[0096] The second doped semiconductor layer is coupled to the source line, and the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0097] In a possible implementation, the first doped semiconductor layer is coupled to a source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer;

[0098] The second doped semiconductor layer is coupled to the bit line, and the second doped semiconductor layer is an N-type doped semiconductor layer.

[0099] In a possible implementation, the storage string includes multiple sub-strings, each sub-string includes a first selection tube and multiple storage units, each first selection tube in the same storage string is coupled to the same first selection line, and the first selection tubes in different storage strings are coupled to different first selection lines.

[0100] In a possible implementation, after the first selection line coupled to the first selection transistor of the floating second storage string, the method further includes:

[0101] At a sixth moment after the second moment, performing an erase verification operation on each storage string in the storage block;

[0102] In the case that there is a second memory string that fails the erasure verification in the memory block, the step of performing the erasing operation on the plurality of memory strings in the memory block is performed.

[0103] The technical solution provided by the embodiment of the present application reduces the erasure speed of the first storage string by floating the selection line coupled to the first selection tube of the first storage string in advance before floating the selection line coupled to the first selection tube of the second storage string when performing an erasure operation on each storage string in a storage block, thereby avoiding excessive erasure of the first storage string during the erasing of the second storage string, reducing the possibility of lateral diffusion of subsequent storage cells in the first storage string after programming, and weakening the drift of the threshold voltage of the storage cells in the first storage string. BRIEF DESCRIPTION OF THE DRAWINGS

[0104] Figure 1 is a schematic diagram of a memory according to an exemplary embodiment;

[0105] Figure 2 is a schematic diagram of an electrical structure of a storage array according to an exemplary embodiment;

[0106] Figure 3 is a cross-sectional side view of a substring according to an exemplary embodiment;

[0107] Figure 4 is a schematic structural diagram of a peripheral circuit according to an exemplary embodiment;

[0108] Figure 5 is a schematic diagram showing a principle of lateral diffusion according to an exemplary embodiment;

[0109] Figure 6 is a schematic diagram showing a threshold voltage drift caused by lateral diffusion according to an exemplary embodiment;

[0110] Figure 7 is a flow chart showing a method for operating a memory according to an exemplary embodiment;

[0111] Figure 8 is a voltage waveform diagram of a storage block during single-end erasing according to an exemplary embodiment;

[0112] Fig. 9 is a voltage waveform diagram of a storage block during double-terminal erasing according to an exemplary embodiment;

[0113] Fig.10 is another voltage waveform diagram of a storage block during double-terminal erasing according to an exemplary embodiment;

[0114] Fig.11 is a flow chart showing a method for performing block erase operation of a memory according to an exemplary embodiment;

[0115] Fig.12is a schematic diagram of a storage system according to an exemplary embodiment;

[0116] Fig.13 is a schematic diagram of a memory card according to an exemplary embodiment;

[0117] Fig.14 is a schematic diagram of a solid state drive according to an exemplary embodiment. DETAILED DESCRIPTION

[0118] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0119] In this application, the terms "first", "second", etc. are used to distinguish the same or similar items with substantially the same role and function. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on the quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms.

[0120] These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, a first element can be referred to as a second element, and similarly, a second element can also be referred to as a first element. Both the first element and the second element can be elements, and in some cases, can be separate and different elements.

[0121] Here, at least one means one or more than one, for example, at least one element can be one element, two elements, three elements, or any other integer greater than or equal to one. At least two means two or more than two, for example, at least two elements can be two elements, three elements, or any other integer greater than or equal to two.

[0122] Figure 1 is a schematic diagram of a memory according to an exemplary embodiment. Figure 1 As shown, the memory 100 includes a memory array 110 , a plurality of bit lines (BL) 120 , a plurality of word lines (WL) 130 , and a peripheral circuit 140 .

[0123] The memory array 110 includes a plurality of substrings 111 , which are arranged in an array above a substrate (not shown), and each substring 111 extends vertically above the substrate.

[0124] Each substring 111 includes a plurality of memory cells 112, and the plurality of memory cells 112 in each substring 111 are vertically stacked above the substrate of the memory array 110. Each memory cell 112 has the function of storing data, and the stored data is determined by the number of electrons stored in the memory cell 112, and the number of electrons stored in the memory cell 112 can determine the magnitude of the threshold voltage of the memory cell 112, so the threshold voltage of the memory cell 112 can indicate the data stored therein. The memory cell 112 is a floating gate field effect transistor or a charge trap field effect transistor. In some embodiments, the memory cell 112 can have two possible storage states, for example, the memory cell 112 can be a single level cell (SLC) storing one bit of data. For example, the threshold voltage corresponding to the first storage state "0" of the SLC can be in a first voltage range, and the threshold voltage corresponding to the first storage state "1" of the SLC can be in a second voltage range. In other embodiments, the memory cell 112 can store at least two bits of data, for example, the memory cell 112 is a multi-level cell (MLC), and the MLC can store two bits per memory cell, or three bits per memory cell (also known as a triple level cell (TLC)), or four bits per memory cell (also known as a quad level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values.

[0125] Each substring 111 further includes an upper selector 113 and a lower selector 114, which are used to activate the selected substring when erasing, programming or erasing the memory cell. The upper selector 113 is also called a top select gate (TSG), and the lower selector 114 is also called a bottom select gate (BSG).

[0126] The memory 100 further includes a plurality of drain select lines (DSL) 150, each DSL 150 being coupled to an upper select transistor 113 in at least one substring 111. Figure 1 As shown, the upper selection tubes 113 of the plurality of substrings 111 at the same height or similar height from the substrate support surface are coupled to the same DSL 150. Different DSLs are coupled to different substrings 111, for example Figure 2The electrical structure diagram of a storage array according to an exemplary embodiment is shown, DSL0 is coupled to the TSGs of multiple substrings 111 represented by thin solid lines, and DSL1 is coupled to the TSGs of multiple substrings 111 represented by thick solid lines. All substrings 111 coupled to the same DSL can be regarded as a storage string (string), that is, a storage string includes at least one substring 111. When a storage string includes a substring 111, this substring 111 can also be called a storage string, and TSGs of different storage strings are coupled to different DSLs. When a storage string includes multiple substrings 111, the TSGs in the multiple substrings 111 are coupled to the same DSL, and the TSGs of different storage strings are coupled to different DSLs. Still with Figure 2 For example, DSL0 and DSL1 in FIG. 1 are used to organize all substrings 111 coupled to DSL0 into one storage string, and all substrings 111 coupled to DSL1 are organized into another storage string by DSL1. At this time, the DSL coupled to the storage string is also coupled to the peripheral circuit 140, so that the peripheral circuit 140 controls the switch state of each TSG on the storage string through the DSL.

[0127] The memory 100 further includes a plurality of source select lines (SSL) 160, each SSL 160 being coupled to a lower select transistor 114 in at least one substring 111. Figure 1 As shown, the lower selection tubes 114 in the plurality of substrings 111 at the same height or similar height from the substrate support surface are coupled to the same SSL 160. Different SSLs are coupled to different substrings 111. Figure 2 Taking SSL0 and SSL1 in the example, SSL0 is coupled to the BSG of multiple substrings 111 represented by thin solid lines, and SSL1 is coupled to the BSG of multiple substrings 111 represented by thick solid lines. In other embodiments, the storage strings are not divided according to SSL, but divided according to DSL. For example, all substrings 111 coupled to the same SSL are regarded as one storage string, that is, a storage string includes at least one substring 111, and BSGs of different storage strings are coupled to different SSLs. In the case where a storage string includes multiple substrings 111, the BSGs in the multiple substrings 111 are coupled to the same SSL. Still in the example of FIG. Figure 2 Taking SSL0 and SSL1 in the example, all substrings 111 coupled to SSL0 are organized into one storage string by SSL0, and all substrings 111 coupled to SSL1 are organized into another storage string by SSL1. At this time, the SSL coupled to the storage string is also coupled to the peripheral circuit 140, so that the peripheral circuit 140 controls the switch state of each BSG on the storage string through the SSL.

[0128] One end of each substring 111 is coupled to a bit line 120, for example, one end of the substring is coupled to a bit line contact, and the bit line 120 is also coupled to the bit line contact. The other end of the substring 111 is coupled to a source line (SL) 170, for example, the other end of the substring is coupled to a substrate, and the source line 170 is also coupled to the substrate.

[0129] like Figure 2 As shown, one bit line (BL) can be coupled to a plurality of substrings 11. Figure 1 and Figure 2 As shown, multiple substrings 111 may be coupled to the same SL 170 .

[0130] like Figure 1 As shown, the storage cells 112 at the same height or similar height from the substrate support surface in different substrings 111 are in the same layer, and multiple storage cells 112 in the same layer form a storage cell row 11a, that is, the storage array 110 includes multiple storage cell rows, and multiple word lines 130 are respectively coupled to the multiple storage cell rows. All substrings 111 in the storage array 110 that share the same group of word lines form a storage block 11b, and each substring 111 in the same storage block 31b is coupled to the same source line 170.

[0131] As the number of memory cell layers increases, multiple stacked substrings 111 need to be formed through multiple etchings. For example, Figure 3 A cross-sectional side view of a substring is shown according to an exemplary embodiment. Figure 3 , the substring 111 can extend vertically above the doped semiconductor layer 310 through the memory cell stack layer 320. The doped semiconductor layer 310 is coupled to the source line. In some embodiments, the doped semiconductor layer 310 is an N-type doped semiconductor layer, in which case the doped semiconductor layer 310 can serve as a substrate, that is, an N-shaped substrate. In other embodiments, the doped semiconductor layer 310 is a P-type doped semiconductor layer, in which case the doped semiconductor layer 310 is a P-well in the substrate, and the substrate is a P-type substrate.

[0132] The memory cell stack layer 320 includes alternating gate conductive layers 330 and gate-to-gate dielectric layers 340. The number of pairs of gate conductive layers 330 and gate-to-gate dielectric layers 340 in the memory cell stack layer 320 can determine the number of memory cells 112 in the memory array 110. The gate conductive layers 330 can include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In one possible embodiment, each gate conductive layer 330 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 330 includes a doped polysilicon layer. Each gate conductive layer 330 can include a gate surrounding the memory cell 112, and can extend laterally at the top of the memory cell stack layer 320 as a DSL 150, at the bottom of the memory cell stack layer 320 as an SSL 160, or between the DSL and the SSL as a WL 130.

[0133] like Figure 3 As shown, the substring 111 also includes a channel structure 350 extending vertically through the memory cell stack layer 320, and the channel structure 350 includes a channel hole filled with at least one semiconductor material (such as a semiconductor channel) and at least one dielectric material (such as a memory film). In some embodiments, the semiconductor channel includes silicon (such as a memory film). In some embodiments, the memory film is a composite dielectric layer including a tunnel layer, a trap layer, and a barrier layer. The channel structure 350 may have a cylindrical shape (such as a column shape). According to some embodiments, the semiconductor channel, the trap layer (also referred to as a memory layer), and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The trap layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0134] like Figure 3 As shown, a doped semiconductor layer 360 is stacked on top of the memory cell stack layer 320 in the substring 111. The doped semiconductor layer 360 is also called a bit line contact. The doped semiconductor layer 360 is coupled to the bit line and is an N-type doped semiconductor layer.

[0135] In the case where the doped semiconductor layer 360 is an N-type doped semiconductor layer, the substring 111 can be erased in a gate-induced drain leakage (GIDL) erasing manner through the bit line coupled to the doped semiconductor layer 360 and the DSL coupled to the TSG in the substring 111. For example, an erase voltage is applied to the bit line coupled to the doped semiconductor layer 360 so that the erase voltage acts on the doped semiconductor layer 360, and a voltage less than the erase voltage is applied to the DSL coupled to the TSG in the substring 111 so that a voltage difference is formed between the gate of the TSG and the doped semiconductor layer 360. The voltage difference causes band-to-band tunneling to occur at a position between the gate of the TSG and the doped semiconductor layer 360, and GIDL is generated, and holes in the GIDL move from this position to the channel of the substring 111, thereby realizing hole injection from this position to the channel of the substring 111, so that the potential of the channel increases. A voltage less than the erase voltage (referred to as a low voltage, such as 0V) is applied to the word line coupled to each memory cell in the substring 111 to apply the low voltage to the gate of the memory cell. As the channel potential of the memory cell increases, the voltage difference between the gate of the memory cell and the channel of the memory cell increases. When the voltage difference is greater than the tunneling voltage of the memory cell, the voltage difference causes a tunneling effect to be generated between the channel of the memory cell and the gate of the memory cell, and then the holes in the channel of the memory cell tunnel to the storage layer of the memory cell to eliminate the electrons in the storage layer, thereby erasing the memory cell.

[0136] In some embodiments, when the doped semiconductor layer 310 is an N-type doped semiconductor layer, the substring block can be erased in a GIDL erasing manner through the source line coupled to the doped semiconductor layer 310 and the SSL coupled to the BSG in the substring 111. For example, an erase voltage is applied to the source line, and a voltage (referred to as a low voltage) less than the erase voltage is applied to the SSL coupled to the BSG, so that a GIDL is generated at a position between the gate of the BSG and the doped semiconductor layer 310, and holes in the GIDL move toward the channel, thereby injecting holes from this position into the channel of the substring 111, so that the potential of the channel is increased, and a low voltage is applied to the word line coupled to each storage cell in the substring 111. As the channel potential of the storage cell increases, when the voltage difference between the gate of the storage cell and the channel of the storage cell is greater than the tunneling voltage of the storage cell, the holes in the channel tunnel to the storage layer of the storage cell to eliminate the electrons in the storage layer, thereby erasing the storage cell.

[0137] Based on this, when the doped semiconductor layer 310 and the doped semiconductor layer 310 are both N-type doped semiconductor layers, the peripheral circuit can perform an erasing operation on the substring 111 at either end of the substring 111 using the GIDL erasing method (i.e., a single-ended GIDL erasing method), or, alternatively, can perform an erasing operation on the substring 111 at both ends of the substring 111 using the GIDL erasing method (i.e., a double-ended GIDL erasing method).

[0138] In other embodiments, when the doped semiconductor layer 310 is a P-type doped semiconductor layer, an erasing operation is performed on the substring 111 based on the erasing method of the P-type doped semiconductor layer. For example, an erasing voltage is applied to the source line to apply the erasing voltage to the P-type doped semiconductor layer, and the erasing voltage causes the P-type doped semiconductor layer to generate holes, and a low voltage is applied to the BSG of the substring 111 and the word lines coupled to each storage cell, so that the low voltage acts on the gate of the BSG and the gate of each storage cell. Since the low voltage is less than the erasing voltage, the holes move from the P-type doped semiconductor layer to the channel of the substring 111, so that holes are injected from the P-type doped semiconductor layer into the channel, so that the potential of the channel increases. As the channel potential of the storage cell increases, when the voltage difference between the gate of the storage cell and the channel of the storage cell is greater than the tunneling voltage of the storage cell, the holes in the channel tunnel to the storage layer of the storage cell to eliminate the electrons in the storage layer, thereby erasing the storage cell.

[0139] Based on this, when the doped semiconductor layer 360 is an N-type doped semiconductor layer and the doped semiconductor layer 310 is a P-type doped semiconductor layer, dual-end erasure can be performed on the substring 111, for example, single-end GIDL erasure is performed on one end of the substring 111 close to the N-type doped semiconductor layer, and erasure based on the P-type doped semiconductor layer is performed on the other end of the substring 111. Alternatively, single-end erasure is performed on the substring 111, for example, single-end GIDL erasure is performed on one end of the substring 111 close to the P-type doped semiconductor layer, and erasure based on the P-type doped semiconductor layer is not performed on the other end of the substring 111, or single-end GIDL erasure is not performed on one end of the substring 111 close to the P-type doped semiconductor layer, and erasure based on the P-type doped semiconductor layer is performed on the other end of the substring 111.

[0140] The storage cell 112 introduced above can be in an erased state or a programmed state, and there can be multiple programming states. The erased state is used to indicate the original state of the storage cell before programming, or the state in which no data is stored, which can also be understood as the stored data is "0"; the programmed state is used to indicate the state in which different data is stored. For example, for the above-mentioned SLC storage cell, it can store 1 bit of data, so only one bit of binary data "0" is needed to represent the erased state, and one bit of binary data "1" is needed to represent the programmed state. For the above-mentioned MLC storage cell, it can store 2 bits of data, so one erased state is needed to represent the data "00" and three programmed states are needed to represent the data "01", "10" and "11".

[0141] The above-mentioned erased state and programmed state are essentially reflected by the threshold voltage of the memory cell. Since the memory cell can realize electron capture, by applying voltage between the gate electrode and the channel, the tunneling effect can be used to allow electrons to pass through the tunneling layer to the storage layer, that is, the electron capture layer, so that the electrons are bound in the storage layer. Changes in the amount of electrons in the storage layer will cause changes in the threshold voltage of the memory cell. Therefore, if data is to be stored in the memory cell, it can be achieved by injecting corresponding electrons into the storage layer. Here, the process of injecting electrons can be called "programming", that is, the state of the memory cell is adjusted from the erased state to a different programming state through programming.

[0142] Return to reference Figure 1 , the peripheral circuit 140 is coupled to the plurality of word lines 130, and the peripheral circuit 140 controls the voltage V of the word line 130 coupled to the selected storage string. WL and the voltage V of the bit line coupled to the selected memory string BL , the storage cells in the selected storage string are controlled to implement the following operation method.

[0143] The peripheral circuit 140 includes various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 4 A schematic diagram of the structure of a peripheral circuit is shown according to an exemplary embodiment. Figure 3 The peripheral circuit 140 shown includes a page buffer / sense amplifier 402, a column decoder / bit line (BL) driver 404, a row decoder / word line (WL) driver 406, a voltage generator 408, a control logic unit 410, a register 412, an interface (I / F) 414, and a data bus 316. In some examples, the peripheral circuit 140 also includes a page buffer / sense amplifier 402, a column decoder / bit line (BL) driver 404, a row decoder / word line (WL) driver 406, a voltage generator 408, a control logic unit 410, a register 412, an interface (I / F) 414, and a data bus 316. Figure 34. The page buffer / sense amplifier 402 may be configured to read data from the memory array 110 and program (write) data to the memory array 110 according to control signals from the control logic unit 410. In one example, the page buffer / sense amplifier 402 may store a page of programming data (write data) to be programmed into one page of the memory array 110. In another example, the page buffer / sense amplifier 402 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 112 coupled to the selected word line. In yet another example, the page buffer / sense amplifier 402 may also sense a low-power signal from a bit line representing a data bit stored in the memory cell 112, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 404 may be configured to be controlled by the control logic unit 410, and select one or more substrings 111 by applying a bit line voltage generated from the voltage generator 408.

[0144] The row decoder / word line driver 406 may be configured to be controlled by the control logic unit 410 and select / deselect the memory block 31b of the memory array 110 to select / deselect the word line 130 of the block 31b. The row decoder / word line driver 406 may also be configured to drive the word line using the word line voltage generated from the voltage generator 408. In some embodiments, the row decoder / word line driver 406 may also select / deselect and drive the DSL and SSL. As described in detail below, the row decoder / word line driver 406 is configured to perform an erase operation on the memory cell 112 coupled to the (one or more) selected word lines. The voltage generator 408 may be configured to be controlled by the control logic unit 410 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 110.

[0145] The control logic unit 410 may be coupled to each peripheral circuit 140 described above, and is configured to control the operation of each peripheral circuit 140. The register 412 may be coupled to the control logic unit 410, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit 140. The interface 414 may be coupled to the control logic unit 410, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 410, and to buffer status information received from the control logic unit 410 and relay them to the host. The interface 414 may also be coupled to the column decoder / bit line driver 404 via the data bus 316, and act as a data I / O interface and a data buffer to buffer data and relay them to or from the memory array 110.

[0146] The peripheral circuit is configured as follows: taking the storage block as the unit, the storage string in the storage block is erased. As the number of erases increases, the erase depths of the various storage strings are inconsistent. The erase depth of the storage string refers to the erase depth of the substring in the storage string. The erase depths of the various substrings in the same storage string are consistent. The erase depth of the substring is indicated by the threshold voltage of the storage cell in the substring. For example, the lower the threshold voltage of the storage cell, the shallower the erase depth of the substring. The shallower the threshold voltage of the storage cell, the higher the threshold voltage of the storage cell, and the deeper the erase depth of the substring. After programming, the storage cells in the substring with a deeper erase depth are prone to lateral diffusion, which causes the threshold voltage of the storage cell to drift. The following is an example of a storage cell in a substring with a deeper erase depth. Figure 5 and Figure 6 Taking the following as an example, the principles of lateral diffusion and threshold voltage drift are introduced respectively.

[0147] Figure 5 is a schematic diagram showing a principle of lateral diffusion according to an exemplary embodiment. Assume that Figure 5 The figure shows a substring with a deeper erase depth, and shows some memory cells on the substring: memory cell n-1 to memory cell n+1, which are coupled to word lines WLn-1 to WLn+1 respectively. Each memory cell includes a channel, a tunnel layer, a capture layer, and a barrier layer. Figure 5As shown, after the substring is first erased and then programmed with full block random, it is assumed that the memory cell n is in the programming state P, and the two memory cells adjacent to the memory cell n (memory cells n+1 and n-1) are both in the erased state E. Since the memory cells n+1 and n-1 are in the erased state E, the capture layer of the memory cell n-1 and the capture layer of the memory cell n+1 both store a small amount of electrons or no electrons, and the threshold voltages of the memory cells n-1 and n+1 are relatively low. Since the memory cell n is in the programming state P, and the higher the programming state P, the greater the threshold voltage of the memory cell n, which leads to a greater threshold voltage difference between the memory cells n and the memory cells n-1, triggering the electrons in the capture layer of the memory cell n to move to the capture layer of the memory cell n-1 and the capture layer of the memory cell n+1, that is, lateral diffusion occurs.

[0148] The electrons in the capture layer of the memory cell n move to both sides, which reduces the number of electrons in the capture layer, resulting in a decrease in the threshold voltage of the memory cell n, that is, causing the threshold voltage of the memory cell n to drift. Figure 6 According to a schematic diagram of threshold voltage drift caused by lateral diffusion shown in an exemplary embodiment, assuming that the threshold voltage VT is as shown in curve 601 when the memory cell n is in the programming state P, after the electrons in the capture layer of the memory cell n diffuse laterally, the threshold voltage VT curve 601 drifts to the left, and a curve 602 is obtained.

[0149] The threshold voltage of the memory cell in the erased state on the substring with a deeper erase depth is lower than the threshold voltage of the memory cell in the erased state on the substring with a shallow erase depth. Especially for the substring with a deeper erase depth, once the memory cell in the programmed state appears, the adjacent memory cells are all in the erased state. Since the threshold voltage of the adjacent memory cells is lower, the electrons stored in the memory cell in the programmed state diffuse more seriously to the adjacent memory cells, which in turn causes the threshold voltage of the memory cell in the programmed state to drift more seriously. In the case of a more serious threshold voltage drift, the data stored in the memory cell may change, thereby reducing the data retention characteristics of the memory cell.

[0150] Based on this, the present application provides a method for operating a memory to prevent the memory strings in a memory block from being over-erased and to prevent the memory strings with a deep erase depth from appearing. Figure 7A flowchart of a method for operating a memory is shown according to an exemplary embodiment, wherein the memory includes a memory array and a peripheral circuit. Taking the memory as the above-mentioned memory 100 as an example, the memory array is the memory array 110. There is at least one memory block in the memory array, each memory block includes multiple memory strings, each memory string includes at least one substring, and the first selection tube of each substring in the same memory string is coupled to the same first selection line. The first selection tube can be the BSG or TSG of the substring. For example, if each TSG of the same memory string is coupled to the same DSL, and each BSG of the same memory string is not coupled to the same SSL, then the first selection tube is the TSG. If each TSG of the same memory string is coupled to the same DSL, and the BSG of the same memory string is not coupled to the same SSL, then the first selection tube can be the TSG or the BSG.

[0151] For the convenience of description, the selection line coupled to the first selection tube of the substring is called the first selection line, the doped semiconductor layer close to the first selection tube in the doped semiconductor layers coupled at both ends of the substring is called the first doped semiconductor layer, and the contact line (such as BL or SL) coupled to the first doped semiconductor layer is called the first contact line. For example, if the first selection tube is BSG, the first doped semiconductor layer is a P-well or N-type substrate in the substrate, and the first contact line is SL. If the first selection tube is TSG, the first doped semiconductor layer is an N-type doped semiconductor layer, and the first contact line is BL.

[0152] For ease of description, the selection tube at the other end of the substring is referred to as the second selection tube, the doped semiconductor layer close to the second selection tube in the doped semiconductor layer coupled at both ends of the substring is referred to as the second doped semiconductor layer, and the contact line (such as BL or SL) coupled to the second doped semiconductor layer is referred to as the second contact line. For example, if the first selection tube is TSG, the second selection tube is BSG, the second doped semiconductor layer is a P-well or N-type substrate in the substrate, and the second contact line is SL; if the first selection tube is BSG, the second selection tube is TSG, the second doped semiconductor layer is an N-type doped semiconductor layer, and the second contact line is BL.

[0153] The peripheral circuit is configured to execute a method for operating a memory, and the method includes performing an erasing operation on a plurality of storage strings in a storage block. The storage block is any storage block in a storage array for which data erasure is to be completed, and there is at least one storage string in the storage block that has not been completely erased, and the at least one storage string is a part of the storage strings in the storage block or all the storage strings in the storage block. In order to distinguish between the storage strings that have been completely erased and the storage strings that have not been completely erased in the storage block, the storage strings that have been completely erased in the storage block are referred to as the first storage strings, and the storage strings that have not been completely erased in the storage block are referred to as the second storage strings. It should be understood that the first storage string and the second storage string are different storage strings in the storage block, the first selection tube in the first storage string is different from the first selection tube in the second storage string, the first selection line coupled to the first selection tube in the first storage string is different from the first selection line coupled to the first selection tube in the second storage string, the second selection tube in the first storage string is different from the second selection tube in the second storage string, and the first selection line coupled to the second selection tube in the first storage string is different from the first selection line coupled to the second selection tube in the second storage string.

[0154] Exemplarily, if all storage strings in the storage block are second storage strings, the erase operation is described as follows:

[0155] Starting from the third moment, a first voltage is applied to the first contact line coupled to the first doped semiconductor layer coupled to each storage string in the storage block, and the first voltage is applied until the seventh moment, so that the first voltage acts on the first doped semiconductor layer coupled to each storage string from the third moment to the seventh moment. From the third moment to the second moment, a second voltage is continuously applied to the first selection line coupled to the first selection tube of each storage string in the storage block, so that the voltage (i.e., gate voltage) of the gate of the first selection tube of each storage string is maintained (kept) at the second voltage from the third moment to the second moment. From the second moment to the seventh moment, the first selection line coupled to the first selection tube of each storage string is floated, so that the gate of the first selection tube of each storage string is in a floating state. From the third moment to the seventh moment, a third voltage is continuously applied to the word line coupled to each storage cell of each storage string in the storage block.

[0156] Among them, the third moment is the starting moment of the erase operation on multiple storage strings in the storage block, the seventh moment is the end moment of the erase operation, the second moment is any moment between the third moment and the seventh moment, and the second moment is the time of floating the first selection tube during the erasure process of the storage block when all storage strings in the storage block have not completed the erasure. The value of the second moment may be the same or different in different application scenarios. Here, the embodiment of the present application does not limit the second moment. The first voltage can also be called an erase voltage or an erase pulse. The first voltage is greater than the second voltage. The second voltage is used to turn on the storage string. The second voltage is greater than or equal to 0V and less than the threshold voltage of the first selection tube. The first voltage is greater than the third voltage, and the voltage difference between the first voltage and the third voltage is greater than the tunneling voltage of the storage unit. The third voltage is greater than or equal to 0V. Here, the embodiment of the present application does not limit the value range of the first voltage, the second voltage and the third voltage.

[0157] For the above-mentioned erasing operation, if the first doped semiconductor layer is a P-type doped semiconductor layer, from the third moment to the seventh moment, the first voltage causes the P-type doped semiconductor layer to continuously generate holes. From the third moment to the second moment, since the gate voltage of the first selection tube in the storage string (i.e., the second voltage) and the gate voltage of each storage unit (i.e., the third voltage) are both less than the first voltage, the holes move to the channel of the storage string where the first selection tube is located (i.e., the channel of each substring in the storage string) to raise the potential of the channel. From the second moment to the seventh moment, the gate of each first selection tube is in a floating state, so that the gate of the first selection tube and the first doped semiconductor layer coupled to the substring where the first selection tube is located are coupled into a capacitor, and the voltage jump principle at both ends of the capacitor causes the gate voltage of the first selection tube to change with the change of the first voltage on the first doped semiconductor layer, thereby reducing the voltage difference between the gate of the first selection tube and the first doped semiconductor layer, and the voltage difference reduction reduces the holes transmitted to the channel of the storage string, reducing the speed of increasing the channel potential.

[0158] For the above-mentioned erase operation, if the first doped semiconductor layer is an N-type doped semiconductor layer, from the third moment to the second moment, since the gate voltage (i.e., the second voltage) of the first selection tube is less than the first voltage on the first doped semiconductor layer, a GIDL is generated at the position between the gate of the first selection tube and the first doped semiconductor layer, and the holes in the GIDL move toward the channel of the storage string to raise the potential of the channel. From the third moment to the second moment, the gate of the first selection tube is in a floating state, so that the voltage difference between the gate of the first selection tube and the first doped semiconductor layer is reduced, and the voltage difference reduction reduces the number of holes in the GIDL, thereby reducing the number of holes transmitted to the channel of the storage string, and reducing the speed of increasing the channel potential.

[0159] For the above-mentioned erasing operation, from the third moment to the seventh moment, as the channel potential of the storage string increases, when the voltage difference (i.e., voltage difference) between the channel and the gate of any storage cell of the storage string is greater than the tunneling voltage of the storage cell, the data stored in the storage cell can be erased. From the second moment to the seventh moment, as the number of holes transmitted to the channel of the storage string decreases, the speed of electron elimination in the storage layer of the storage cell decreases, thereby preventing the storage string that has not been completely erased from being over-erased during the execution of this erasing operation.

[0160] In the case where there are a first storage string and a second storage string in a storage block, if the first selection tube of each storage string is floated at the second moment according to the above-mentioned erasing operation, then the electrons in the storage layer of the storage unit of the first storage string that has been erased after the second moment will continue to be eliminated, thereby increasing the erase depth of the first storage string, which makes it easy for the first storage string to be over-erased, especially after multiple erase operations are performed on the storage block. After the first storage string is erased, as the number of subsequent erase operations increases, the electrons in the storage layer of the storage unit of the first storage string will continue to be eliminated, thereby further increasing the possibility of over-erasing the first storage string.

[0161] Based on this, when there are a first storage string and a second storage string in a storage block, during an erase operation on the storage block, before floating the first selection tube of the second storage string, the first selection tube of the first storage string is floated in advance, and then the second storage string is floated normally. For the sake of convenience of description, the time of floating the first selection tube of the first storage string is referred to as a first moment, wherein the first moment is any moment between a third moment and a second moment, that is, the third moment is before the first moment, and the second moment is after the first moment. The first moment can be obtained based on specific product testing. Here, the embodiment of the present application does not limit the first moment.

[0162] Exemplarily, when there are a first storage string and a second storage string in a storage block, the erase operation on the multiple storage strings in the storage block includes: at a third moment before the first moment, applying a first voltage to a first doped semiconductor layer coupled to each storage string in the storage block; from the third moment to the first moment, applying a second voltage to a first selection line coupled to a first selection tube of the first storage string, and from the third moment to the second moment, applying a second voltage to a first selection line coupled to the first selection tube of the second storage string; at the third moment, applying a third voltage to a word line coupled to each storage cell of each storage string in the storage block.

[0163] For example, Figure 7A voltage waveform diagram of a storage block during single-ended erasure according to an exemplary embodiment. Assuming T0 is the third moment, T1 is the first moment, T2 is the second moment, and T3 is the seventh moment, starting from the third moment T0, a first voltage is applied to the first contact line coupled to the first doped semiconductor layer coupled to each storage string in the storage block until the first voltage is applied to the seventh moment T3, so that the first voltage acts on the first doped semiconductor layer coupled to each storage string from the third moment to the seventh moment. From the third moment T0 to the seventh moment T3, a third voltage is applied to the word line coupled to the storage cell of each storage string (not in Figure 7 ).

[0164] From the third moment T0 to the first moment T1, the applied voltage of the first selection line coupled to the first selection tube of the first storage string in the storage block is the second voltage, so that the gate of the first selection tube of the first storage string is maintained at the second voltage from the third moment T0 to the first moment T1. Under the action of the first voltage and the second voltage, the holes generated by the first doped semiconductor layer coupled to the first storage string or the holes generated at the position between the first doped semiconductor layer and the first selection tube move toward the channel of the first storage string (i.e., the channel of each substring of the first storage string) to raise the potential of the channel. From the third moment T0 to the first moment T3, the applied voltage of the word line coupled to the storage unit of the first storage string is the third voltage (not in Figure 7 ), so that the voltage of the gate of the storage cell of the first storage string (i.e., the gate voltage) is maintained at a third voltage. During this period, as the channel potential of the first storage string increases, when the voltage difference between the channel and the gate of any storage cell of the first storage string is greater than the tunneling voltage of the storage cell, the electrons in the storage layer of the storage cell of the first storage string are eliminated.

[0165] From the third moment T0 to the second moment T2, the voltage applied to the first selection line coupled to the first selection tube of the second storage string in the storage block is the second voltage, so that the gate of the first selection tube of the second storage string is maintained at the second voltage from the third moment T0 to the second moment T2. Under the action of the first voltage and the second voltage, the holes generated by the first doped semiconductor layer coupled to the second storage string or the holes generated at the position between the first doped semiconductor layer and the first selection tube move toward the channel of the second storage string (i.e., the channel of each substring of the second storage string) to raise the potential of the channel. From the third moment T0 to the second moment T2, a third voltage is applied to the word line coupled to the storage cell of the second storage string (not in Figure 7 ), so that the gate voltage of the gate of the storage cell of the second storage string is maintained at a third voltage, during which, as the channel potential of the second storage string increases, when the voltage difference between the channel and the gate of any storage cell of the second storage string is greater than the tunneling voltage of the storage cell, the electrons in the storage layer of the storage cell of the second storage string are eliminated.

[0166] In the case where there are a first storage string and a second storage string in the storage block, the erasing operation performed on the plurality of storage strings in the storage block further includes: Figure 8 As shown in step 801 and step 802, it should be understood that the step numbers are used to distinguish different operations, and the step numbers do not represent the actual order of the operations, and the step numbers may be changed.

[0167] 801. At a first moment, a first selection line coupled to a first selection transistor of a first storage string is floated, where the first storage string is a storage string that has been erased among a plurality of storage strings of a storage block.

[0168] Still Figure 7 For example, starting from the third moment T0, after a first time period, the first moment T1 is reached, and the first selection line coupled to the gate of the first selection tube of the first storage string is floated from the first moment T1 until the floating ends at the seventh moment T3. During this period, the gate of the first selection tube of the first storage string is in a floating state, so that the gate of the first selection tube of the first storage string and the corresponding first doped semiconductor layer (that is, the first doped semiconductor layer coupled to the substring where the first selection tube is located) are coupled to form a capacitor. The voltage jump principle at both ends of the capacitor causes the gate voltage of the first selection tube of the first storage string to change with the change of the first voltage, thereby reducing the voltage difference between the gate of the first selection tube of the first storage string and the corresponding first doped semiconductive layer, resulting in a reduction in the holes transmitted to the channel of the first storage string, so that the speed of eliminating electrons in the storage layer of the storage unit of the first storage string from the first moment T1 to the seventh moment T3 is reduced, thereby preventing the first storage string from being over-erased, and reducing the increase in the erase depth of the first storage string during the execution of this erase operation.

[0169] It should be understood that, since different storage cells in a storage block may be in different programming states, the threshold voltage of a storage cell in a higher programming state is higher, and multiple erasing processes may be required for the storage block before the erasure of each storage string in the storage block is completed. The present application can improve the over-erasure caused by the continued erasure of the storage string that has been erased in the subsequent erasing process by reasonably setting the first moment and the second moment, so that when the erasure of each storage string in the storage block is completed, the erasure depth of each storage string is approximately the same and the storage cells in each storage string are not over-erased, so that the threshold voltage of each storage cell in the erased state in the storage block is The voltage will not shift significantly to the left, that is, the threshold voltage will not be significantly reduced. Even after subsequent programming, the two adjacent memory cells in the programmed state are in the erased state. Since the threshold voltage of the memory cell in the erased state is not significantly reduced, the threshold voltage difference between the memory cell in the programmed state and the memory cell in the erased state will not be so large, and then the number of electrons in the memory cell in the programmed state moving to the memory cell in the erased state will be reduced, which will weaken the lateral diffusion and reduce the drift of the threshold voltage of the memory cell in the programmed state. Correspondingly, the data retention characteristics of the memory cell are increased.

[0170] 802. At a second moment after the first moment, a first selection line coupled to a first selection transistor of a second storage string is floated, where the second storage string is a storage string that has not been completely erased among a plurality of storage strings in a storage block.

[0171] Still Figure 7 For example, starting from the first moment T1, after a second time period, the second moment T2 is reached, and the first selection line coupled to the first selection tube of the second storage string is floated from the second moment T2 until the floating ends at the seventh moment T3. During this period, the gate of the first selection tube of the second storage string is in a floating state, so that the gate of the first selection tube of the second storage string is coupled to the corresponding first doped semiconductor layer (that is, the first doped semiconductor layer coupled to the substring where the first selection tube is located) to form a capacitor. The voltage jump principle at both ends of the capacitor makes the gate voltage of the first selection tube of the second storage string change with the change of the first voltage, so that the voltage difference between the gate of the first selection tube of the second storage string and the corresponding first doped semiconductor layer is reduced, resulting in a reduction in holes transmitted to the channel of the second storage string, so that the speed of eliminating electrons in the storage layer of the storage unit of the second storage string from the second moment T2 to the seventh moment T3 is reduced, thereby preventing the second storage string from being over-erased.

[0172] The erase operation performed on the plurality of storage strings of the storage block further includes: at a third moment, applying a fourth voltage to the second doped semiconductor layer coupled to each storage string in the storage block, and at the third moment, floating the second selection line coupled to the second selection tube of each storage string in the storage block to prevent holes from being injected into the channel from the second selection tube of the storage string. The fourth voltage is greater than 0V, and the fourth voltage may be the same as or different from the first voltage.

[0173] Still Figure 7 For example, starting from the third moment T0, a fourth voltage is applied to the second contact line coupled to the second doped semiconductor layer coupled to each storage string in the storage block, until the fourth voltage is applied to the seventh moment T3, so that the fourth voltage acts on the second doped semiconductor layer. Starting from the third moment T0, the second selection line coupled to the second selection tube of each storage string in the storage block is floated until the floating is finished at the seventh moment T3. During this period, the gate of the second selection tube is in a floating state, so that the gate of the second selection tube is coupled to the corresponding second doped semiconductor layer (that is, the second doped semiconductor layer coupled to the substring where the second selection tube is located) to form a capacitor. The voltage jump principle at both ends of the capacitor makes the gate voltage of the second selection tube change with the change of the fourth voltage to maintain the voltage difference between the gate of the second selection tube and the second doped semiconductor layer basically unchanged, and the voltage difference is greater than 0V. When the second doped semiconductor layer is an N-type doped semiconductor layer, the voltage difference is not enough to generate GIDL or the GIDL generated by the voltage difference is relatively small, and the holes in the GIDL are not enough to erase the data in the storage unit. In the case where the second doped semiconductor layer is a P-type doped semiconductor layer, the voltage difference is relatively small, which is not enough to cause a large number of holes in the second doped semiconductor layer to enter the channel, and thus is not enough to erase the data in the storage cell. Thus, holes are injected into the channel from one end of the storage string in the storage block to erase the data stored in the storage cell of the storage string, thereby realizing single-end erasure.

[0174] The method provided by the embodiment of the present application reduces the erasure speed of the first storage string by floating the selection line coupled to the first selection tube of the first storage string in advance before floating the selection line coupled to the first selection tube of the second storage string when performing an erasure operation on multiple storage strings in a storage block, thereby avoiding excessive erasure of the first storage string during the process of erasing the second storage string, reducing the possibility of lateral diffusion of subsequent storage cells in the first storage string after programming, and weakening the drift of the threshold voltage of the storage cells in the first storage string.

[0175] The method provided by the embodiment of the present application reduces the erasure speed of the first storage string by floating the selection line coupled to the first selection tube of the first storage string in advance before floating the selection line coupled to the first selection tube of the second storage string when performing an erasure operation on multiple storage strings in a storage block, thereby avoiding excessive erasure of the first storage string during the process of erasing the second storage string, reducing the possibility of lateral diffusion of subsequent storage cells in the first storage string after programming, and weakening the drift of the threshold voltage of the storage cells in the first storage string.

[0176] In other embodiments, if the first doped semiconductor layer coupled to each storage string of the storage block is coupled to BL, the first doped semiconductor layer is an N-type doped semiconductor layer, the second doped semiconductor layer coupled to each storage string of the storage block is coupled to SL, the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer, the storage strings in the storage block can also be dual-terminal erased. Alternatively, if the first doped semiconductor layer coupled to each storage string of the storage block is coupled to SL, the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer, the second doped semiconductor layer coupled to each storage string of the storage block is coupled to BL, the second doped semiconductor layer is an N-type doped semiconductor layer, the storage strings in the storage block can also be dual-terminal erased.

[0177] In the case of double-end erasing, in some embodiments, during the erasing operation on multiple memory strings of a memory block, the selection line coupled to the first selection tube or the second selection tube of the first memory string is floated in advance. The following is an introduction to this early floating scheme:

[0178] Among them, the process of floating the first selection tube of the first storage string in advance is the same as the process of floating the second selection tube of the first storage string in advance. Here, the following introduction is made by taking the first selection tube of the first storage string in advance as an example. The process of floating the second selection tube of the first storage string in advance can refer to the process of floating the first selection tube of the first storage string in advance.

[0179] Exemplarily, the erase operation performed on multiple storage strings of a storage block includes: at a third moment, applying a fifth voltage to the second doped semiconductor layer coupled to each storage string in the storage block; at a first moment, floating the first selection line coupled to the first selection tube of the first storage string (such as step 801 above); at a second moment after the first moment, floating the first selection line coupled to the first selection tube of the second storage string (such as step 802 above); from the third moment to the second moment, applying a sixth voltage to the second selection line coupled to the second selection tube of each storage string in the storage block, and at the second moment, floating the second selection line coupled to the second selection tube of each storage string in the storage block, because the first moment is before the second moment, thereby achieving early floating of the first selection tube of the first storage string.

[0180] Among them, the fifth voltage is greater than 0, the fifth voltage may be the same as or different from the first voltage, and the sixth voltage is less than the fifth voltage. For example, the sixth voltage is greater than or equal to 0 and less than the fifth voltage, and the sixth voltage may be the same as or different from the second voltage. Here, the embodiment of the present application does not limit the value range of the fifth voltage and the sixth voltage.

[0181] For any storage string in the storage block, a fifth voltage is applied to the second doped semiconductor layer coupled to the storage string, and a sixth voltage is applied to the second selection line coupled to the second selection tube of the storage string to achieve hole injection into the channel of the storage string. The method of injecting holes is the same as the method of injecting holes into the channel by applying the first voltage and the second voltage to the storage string. The difference lies in that the directions of injecting holes into the channel of the storage string are different. For example, applying the fifth voltage and the sixth voltage to the storage string achieves hole injection from the second selection tube of the storage string into the channel of the storage string, and applying the first voltage and the second voltage to the storage string achieves hole injection from the first selection tube of the storage string into the channel of the storage string.

[0182] Combine the following Fig. 9 The control process of floating the first selection tube of the first storage string in advance during double-end erasing is introduced as follows.

[0183] Fig. 9 1 is a voltage waveform diagram of a storage block during double-terminal erasing according to an exemplary embodiment, wherein a process of applying voltage to a first contact line, a gate of a first selection tube of a first storage string, and a gate of a second selection tube of a second storage string is similar to Figure 7 Similar, no further elaboration is required here.

[0184] like Fig. 9As shown, starting from the third moment T0, the fifth voltage is applied to the second contact line coupled to the second doped semiconductor layer coupled to each memory string in the memory block, and the fifth voltage is applied until the seventh moment T3, so that the fifth voltage acts on the second doped semiconductor layer. From the third moment T0 to the seventh moment T3, the third voltage is continuously applied to the word line coupled to each memory cell of each memory string (not in Fig. 9 ).

[0185] From the third moment T0 to the second moment T2, the sixth voltage is continuously applied to the second selection line coupled to the second selection tube of each storage string in the storage block, so that the gate voltage of the second selection tube is maintained at the sixth voltage. Under the action of the fifth voltage and the sixth voltage, the holes generated in the second doped semiconductor layer coupled to the storage string or the holes generated at the position between the second doped semiconductor layer and the second selection tube move toward the channel of the storage string to raise the potential of the channel. As the channel potential of each storage string increases, when the voltage difference between the channel and the gate of any storage cell is greater than the tunneling voltage of the storage cell, the electrons in the storage layer of the storage cell are eliminated.

[0186] The second selection line coupled to the second selection tube of each storage string is floated from the second moment T2 until the floating ends at the seventh moment T3. During this period, the gate of the second selection tube of each storage string is in a floating state, so that the gate of the second selection tube of the storage string is coupled to the corresponding second doped semiconductor layer (that is, the second doped semiconductor layer coupled to the substring where the second selection tube is located) to form a capacitor. The voltage jump principle at both ends of the capacitor makes the gate voltage of the second selection tube of each storage string change with the change of the fifth voltage, so that the voltage difference between the gate of the second selection tube of each storage string and the corresponding second doped semiconductor layer is reduced, resulting in a reduction in holes transmitted to the channel of each storage string, so that the speed of eliminating electrons in the storage layer of the storage unit of each storage string from the second moment T2 to the seventh moment T3 is reduced, thereby preventing each storage string from being over-erased.

[0187] In the case of double-end erasing, in some embodiments, during the erasing operation on multiple storage strings of a storage block, the first selection tube of the first storage string and the second selection line coupled to the second selection tube are advanced. This early floating scheme is introduced as follows.

[0188] For ease of description, the time of floating the second selection tube of the first storage string is called the fourth moment, and the time of floating the second selection tube of the second storage string is called the fifth moment. The fourth moment is any moment between the third moment and the fifth moment, and the fourth moment may be the same as the first moment or different from the first moment. The fifth moment is any moment between the third moment and the seventh moment, and the fifth moment may be the same as the second moment or different from the second moment. Here, the fourth moment and the fifth moment are not limited in the embodiment of the present application.

[0189] Exemplarily, the erase operation performed on multiple storage strings of a storage block includes: at a third moment, applying a fifth voltage to the second doped semiconductor layer coupled to each storage string in the storage block; at a first moment, floating the first selection line coupled to the first selection tube of the first storage string (such as step 801 above); at a second moment after the first moment, floating the first selection line coupled to the first selection tube of the second storage string (such as step 802 above); from the third moment to the fourth moment, applying a seventh voltage to the second selection line coupled to the second selection tube of the first storage string, and at the fourth moment, floating the second selection line coupled to the second selection tube of the first storage string; from the third moment to the fifth moment after the fourth moment, applying a seventh voltage to the second selection line coupled to the second selection tube of the second storage string, and at the fifth moment, floating the second selection line coupled to the second selection tube of the second storage string. Since the first moment is before the second moment and the fourth moment is before the fifth moment, the first selection tube and the second selection tube of the first storage string are floated in advance.

[0190] Among them, the seventh voltage is less than the fifth voltage. For example, the seventh voltage is greater than or equal to 0 and less than the fifth voltage. The seventh voltage may be the same as the second voltage or may be different from the second voltage. The embodiment of the present application does not limit the value range of the seventh voltage.

[0191] For any storage string, a fifth voltage is applied to the second doped semiconductor layer coupled to the storage string, and a seventh voltage is applied to the second selection line coupled to the second selection tube of the storage string to achieve hole injection into the channel of the storage string. The method of injecting holes is the same as the method of injecting holes into the channel by applying the first voltage and the second voltage to the storage string. The difference lies in that the directions of injecting holes into the channel of the storage string are different. For example, applying the fifth voltage and the seventh voltage to the storage string achieves hole injection from the second selection tube of the storage string into the channel of the storage string, and applying the first voltage and the second voltage to the storage string achieves hole injection from the first selection tube of the storage string into the channel of the storage string.

[0192] Combine the following Fig.10 The control process of floating the selection tubes at both ends of the first storage string in advance during double-end erasing is introduced as follows.

[0193] Fig.10 1 is another voltage waveform diagram of a memory block during double-terminal erasing according to an exemplary embodiment, wherein the process of applying voltage to the first contact line, the first selection line coupled to the first selection tube of the first memory string, and the first selection line coupled to the first selection tube of the second memory string is similar to Figure 7 Similar, no further elaboration is required here.

[0194] like Fig.10 As shown, starting from the third moment T0, the fifth voltage is applied to the second contact line coupled to the second doped semiconductor layer coupled to each memory string in the memory block, and the fifth voltage is applied until the seventh moment T3, so that the fifth voltage acts on the second doped semiconductor layer. From the third moment T0 to the seventh moment T3, the third voltage is continuously applied to the word line coupled to each memory cell of each memory string (not in Fig.10 ).

[0195] From the third moment T0 to the fourth moment T4, the seventh voltage is continuously applied to the second selection line coupled to the second selection tube of each storage string in the storage block, so that the gate voltage of the second selection tube of each storage string is maintained at the seventh voltage. Under the action of the fifth voltage and the seventh voltage, the holes generated in the second doped semiconductor layer coupled to the storage string or the holes generated at the position between the second doped semiconductor layer and the second selection tube move toward the channel of the storage string to raise the potential of the channel. As the channel potential of each storage string increases, when the voltage difference between the channel and the gate of any storage cell is greater than the tunneling voltage of the storage cell, the electrons in the storage layer of the storage cell of the storage string are eliminated.

[0196] The second selection line coupled to the second selection tube of the first storage string is floated from the fourth moment T4 until the floating ends at the seventh moment T3. During this period, the gate of the second selection tube of the first storage string is in a floating state, and the gate of the second selection tube of the first storage string and the corresponding second doped semiconductor layer (that is, the second doped semiconductor layer coupled to the substring where the second selection tube is located) are coupled to form a capacitor. The voltage jump principle at both ends of the capacitor causes the gate voltage of the second selection tube of the first storage string to change with the change of the fifth voltage, thereby reducing the voltage difference between the gate of the second selection tube of the first storage string and the corresponding second doped semiconductor layer, resulting in a reduction in holes transmitted to the channel of the first storage string, so that the speed of eliminating electrons in the storage layer of the storage unit of the first storage string from the fourth moment T4 to the seventh moment T3 is reduced, thereby preventing the first storage string from being over-erased.

[0197] From the fourth moment T4 to the fifth moment T5, the seventh voltage is continuously applied to the second selection line coupled to the second selection tube of the second storage string, so that the gate voltage of the second selection tube of the second storage string is maintained at the seventh voltage, and under the action of the fifth voltage and the seventh voltage, the holes generated in the second doped semiconductor layer coupled to the second storage string or the holes generated at the position between the second doped semiconductor layer and the second selection tube move toward the channel of the second storage string to raise the potential of the channel, and when the voltage difference between the channel and the gate of any storage cell of the second storage string is greater than the tunneling voltage of the storage cell, the electrons in the storage layer of the storage cell of the storage string are eliminated. Starting from the fifth moment, the second selection line coupled to the second selection tube of the second storage string is floated. During this period, the gate of the second selection tube of the second storage string is in a floating state, so that the gate of the second selection tube of the second storage string and the corresponding second doped semiconductor layer (that is, the second doped semiconductor layer coupled to the substring where the second selection tube is located) are coupled to form a capacitor. The voltage jump principle at both ends of the capacitor makes the gate voltage of the second selection tube of the second storage string change with the change of the fifth voltage, thereby reducing the voltage difference between the gate of the second selection tube of the second storage string and the corresponding second doped semiconductor layer, resulting in a reduction in holes transmitted to the channel of the second storage string, so that the speed of eliminating electrons in the storage layer of the storage unit of the second storage string from the fifth moment T5 to the seventh moment T3 is reduced, thereby preventing the second storage string from being over-erased.

[0198] For the above-mentioned erasing operation on multiple storages in the storage block, the erasing operation is terminated at the seventh moment. It is assumed that at the sixth moment after the seventh moment, the voltages of the various control lines (such as BL, SL, DSL, SSL and BL) coupled to the peripheral circuit of the storage block have all been restored to their respective initial voltages, and the single erasing process of the storage block is terminated. At the sixth moment, an erasure verification operation is performed on each storage string in the storage block to verify whether there are still unerased storage strings in the storage block. For example, if it is verified that there are unsuccessfully erased storage cells in any storage string, the storage string is an unerased storage string, and the storage string is not verified at this time, and the storage string is the second storage string. If it is verified that all storage cells of any storage string are successfully erased (that is, there are no unsuccessfully erased storage cells), the storage string is a storage string that has been completely erased, and the storage string is verified at this time, and the storage string is the first storage string.

[0199] In the case that there is a second storage string in the storage block that has not passed the erasure verification, it means that the second storage string has not completed the erasure after the erasure process of the above-mentioned storage block, then the erasure operation is performed on multiple storage strings in the storage block again, and at the first moment, the first selection line coupled to the first selection tube of the first storage string is floated, and at the second moment, the first selection line coupled to the first selection tube of the second storage string is floated.

[0200] For example, Fig.11 According to a flowchart of a block erase operation method of a memory shown in an exemplary embodiment, an erase pulse (such as a first voltage) is applied to a certain memory block in the memory to perform an erase operation on the memory block, and an erase verification operation is performed on each memory string in the memory block to determine whether all memory strings in the memory block have passed the erase verification. If yes, it means that all memory strings in the memory block have been erased, and the next erase verification operation is no longer performed on the memory block. If not, it is necessary to further determine whether all memory strings in the memory block have not passed the erase verification. If all memory strings in the memory block have not passed the erase verification, an erase pulse is applied to the memory block again to perform the next erase operation on the memory block. During this period, the first selection tubes of each memory string of the memory block are simultaneously floated. If not all the storage strings in the storage block have failed the erasure verification, then a part of the storage strings in the storage block have failed the erasure verification, and another part of the storage strings have passed the erasure verification, and an erase pulse is applied to the storage block again to perform the next erase operation on the storage block. During this period, the duration of applying voltage to the first selection tube of the storage string that has passed the erasure verification is reduced to achieve early floating of the first selection tube of the storage string that has passed the erasure verification, and then floating the first selection tube of the storage string that has not passed the erasure verification. Among them, the storage string that has passed the erasure verification is the first storage string, and the storage string that has not passed the erasure verification is the second storage string. After performing multiple erase operations on the storage block, all the storage strings of the storage block pass the erasure verification.

[0201] It should be understood that if a part of the storage strings in the storage block fails the erasure verification and another part of the storage strings passes the erasure verification, in the process of applying the erase pulse to the storage block again, the duration of applying the voltage to the first selection tube of the storage string that passed the erasure verification only needs to be reduced once without having to be reduced multiple times, such as reducing the duration from the third moment to the second moment to the duration from the third moment to the first moment. In the case where the first storage string and the second storage string are stored in the storage block at the same time, the first selection tube of the first storage string can be floated at the first moment during each erase operation on the storage block.

[0202] The memory 100 described above can be applied in a storage system to provide data storage services for hosts in the storage system. Next, the architecture of the storage system is introduced as follows.

[0203] Fig.12 is a schematic diagram of a storage system according to an exemplary embodiment. Fig.12As shown, storage system 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0204] like Fig.12 As shown, the storage system 400 includes a host 401 and a storage subsystem 402. The host 401 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 401 may be configured to send data to the memory 100 in the storage subsystem 402. Alternatively, the host 401 may be configured to receive data from the memory 100.

[0205] The storage subsystem 402 includes one or more memories 100 and a controller 200. The memory 100 is coupled to the controller 200. The memory 100 can be any memory disclosed in the present application. Optionally, the memory 100 is a NAND flash memory device. The NAND flash memory device is, for example, a three-dimensional (3D) NAND flash memory device.

[0206] According to some embodiments, the controller 200 is also coupled to the host 401. The controller 200 may manage data stored in the memory 100 and communicate with the host 401.

[0207] In one possible implementation, the controller 200 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0208] In one possible implementation, the controller 200 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smart phones, tablets, laptops, etc., as well as enterprise storage arrays.

[0209] The controller 200 may be configured to control operations of the memory 100, such as read, erase, and program operations. The controller 200 may also be configured to manage various functions regarding data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In one possible implementation, the controller 200 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 100.

[0210] The controller 200 may also perform any other suitable functions, for example, formatting the memory 100. The controller 200 may communicate with an external device (e.g., the host 401) according to a specific communication protocol. For example, the controller 200 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced mini disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0211] The controller 200 and one or more memories 100 may be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an eMMC package). That is, the storage system 400 may be implemented and packaged into different types of terminal electronic products.

[0212] Fig.13 is a schematic diagram of a memory card according to an exemplary embodiment. Fig.13 As shown, the controller 200 and the single memory 100 may be integrated into a memory card 500. The memory card 500 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 500 may also include a processor that connects the memory card 500 to a host (e.g., Fig.12 A memory card connector 501 is coupled to a host 401 in the memory card connector.

[0213] Fig.14 is a schematic diagram of a solid state drive according to an exemplary embodiment. Fig.14As shown, the controller 200 and the plurality of memories 100 may be integrated into a solid state drive (SSD) 600. The solid state drive 600 may also include a processor that connects the solid state drive 600 to a host (eg, Fig.12 The solid-state drive connector 601 is coupled to the host 401 in the memory card. In one possible implementation, the storage capacity and / or operation speed of the solid-state drive 600 is greater than the storage capacity and / or operation speed of the memory card 500.

[0214] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A memory, characterized in that: The memory includes a memory array and a peripheral circuit, the memory array includes a memory block and a first selection line, the memory block includes a plurality of memory strings, each memory string includes a first selection tube, the first selection line is coupled to the first selection tube, and the peripheral circuit is coupled to the first selection line; the peripheral circuit is configured to perform an erase operation on the plurality of memory strings in the memory block, and to perform the erase operation, the peripheral circuit is configured as follows: At a first moment, floating a first selection line coupled to a first selection transistor of a first storage string, wherein the first storage string is a storage string that has been erased among the plurality of storage strings; At a second moment after the first moment, a first selection line coupled to a first selection transistor of a second storage string is floated, and the second storage string is a storage string that has not been completely erased among the plurality of storage strings.

2. The memory according to claim 1, characterized in that: The memory array further comprises a first doped semiconductor layer and a plurality of word lines, wherein the first doped semiconductor layer is coupled to one end of each memory string close to the first selection tube, each memory string further comprises a plurality of memory cells, the plurality of word lines are respectively coupled to the plurality of memory cells of each memory string, and the peripheral circuit is also coupled to the plurality of word lines; The peripheral circuit is further configured as: At a third moment before the first moment, applying a first voltage to a first doped semiconductor layer coupled to each memory string in the memory block; From the third moment to the first moment, applying a second voltage to the first selection line coupled to the first selection transistor of the first storage string, wherein the second voltage is less than the first voltage; From the third moment to the second moment, applying the second voltage to the first selection line coupled to the first selection transistor of the second storage string; At the third moment, a third voltage is applied to the word line coupled to each memory cell of each memory string in the memory block, and the third voltage is lower than the first voltage.

3. The memory according to claim 2, characterized in that: Each memory string in the memory block further includes a second selection tube, the memory array further includes a second doped semiconductor layer and a second selection line, the second doped semiconductor layer is coupled to one end of each memory string close to the second selection tube, the second selection line is coupled to the second selection tube, and the peripheral circuit is also coupled to the second selection line; The peripheral circuit is further configured as: At the third moment, applying a fourth voltage to the second doped semiconductor layer coupled to each memory string in the memory block; At the third moment, the second selection line coupled to the second selection transistor of each storage string in the storage block is floated.

4. The memory according to claim 3, characterized in that: The first doped semiconductor layer is coupled to the bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer.

5. The memory according to claim 3, characterized in that: The first doped semiconductor layer is coupled to a source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

6. The memory according to claim 2, characterized in that: Each memory string in the memory block further includes a second selection tube, the memory array further includes a second doped semiconductor layer and a second selection line, the second doped semiconductor layer is coupled to one end of each memory string close to the second selection tube, the second selection line is coupled to the second selection tube, and the peripheral circuit is also coupled to the second selection line; The peripheral circuit is further configured as: At the third moment, a fifth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block.

7. The memory according to claim 6, characterized in that: The peripheral circuit is further configured as: From the third moment to the second moment, applying a sixth voltage to the second selection line coupled to the second selection transistor of each storage string in the storage block, wherein the sixth voltage is less than the fifth voltage; At the second moment, the second selection line coupled to the second selection transistor of each storage string in the storage block is floated.

8. The memory according to claim 6, characterized in that: The peripheral circuit is further configured as: From the third moment to the fourth moment, a seventh voltage is applied to the second selection line coupled to the second selection tube of the first storage string, and at the fourth moment, the second selection line coupled to the second selection tube of the first storage string is floated, and the seventh voltage is less than the fifth voltage; From the third moment to a fifth moment after the fourth moment, the seventh voltage is applied to the second selection line coupled to the second selection tube of the second storage string, and at the fifth moment, the second selection line coupled to the second selection tube of the second storage string is floated.

9. The memory according to any one of claims 6 to 8, characterized in that: The first doped semiconductor layer is coupled to a bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer; The second doped semiconductor layer is coupled to the source line, and the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

10. The memory according to any one of claims 6 to 8, characterized in that: The first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer; The second doped semiconductor layer is coupled to the bit line, and the second doped semiconductor layer is an N-type doped semiconductor layer.

11. The memory according to any one of claims 1 to 10, characterized in that: The storage string includes multiple substrings, each substring includes a first selection tube and multiple storage units, each first selection tube in the same storage string is coupled to the same first selection line, and the first selection tubes in different storage strings are coupled to different first selection lines.

12. The memory according to any one of claims 1 to 11, characterized in that: The peripheral circuit is further configured as: At a sixth moment after the second moment, performing an erase verification operation on each storage string in the storage block; In the case that there is a second memory string that fails the erasure verification in the memory block, the step of performing an erasing operation on the plurality of memory strings in the memory block is performed.

13. A storage system, characterized in that: The storage system includes a memory configured to store data and a controller coupled to the memory and configured to control the memory, wherein the memory includes a storage array and a peripheral circuit, the storage array includes a storage block and a first selection line, the storage block includes a plurality of storage strings, each storage string includes a first selection tube, the first selection line is coupled to the first selection tube, and the peripheral circuit is coupled to the first selection line; the peripheral circuit is configured to perform an erase operation on the plurality of storage strings in the storage block, and to perform the erase operation, the peripheral circuit is configured as follows: At a first moment, floating a first selection line coupled to a first selection transistor of a first storage string, wherein the first storage string is a storage string that has been erased among the plurality of storage strings; At a second moment after the first moment, a first selection line coupled to a first selection transistor of a second storage string is floated, and the second storage string is a storage string that has not been completely erased among the plurality of storage strings.

14. The storage system according to claim 13, characterized in that: The storage system further includes a host; the host is coupled to the controller, and the host is configured to send data to the memory or receive data from the memory through the controller.

15. A method for operating a memory, characterized in that: The memory includes a memory array, the memory array includes a memory block and a first selection line, the memory block includes a plurality of memory strings, each memory string includes a first selection transistor; the method includes performing an erasing operation on the plurality of memory strings in the memory block, the erasing operation includes: At a first moment, floating a first selection line coupled to a first selection transistor of a first storage string, wherein the first storage string is a storage string that has been erased among the plurality of storage strings; At a second moment after the first moment, a first selection line coupled to a first selection transistor of a second storage string is floated, and the second storage string is a storage string that has not been completely erased among the plurality of storage strings.

16. The method according to claim 15, characterized in that The memory array further comprises a first doped semiconductor layer and a plurality of word lines, wherein the first doped semiconductor layer is coupled to one end of each memory string close to the first selection tube, each memory string further comprises a plurality of memory cells, and the plurality of word lines are respectively coupled to the plurality of memory cells of each memory string; The erasing operation further includes: At a third moment before the first moment, applying a first voltage to a first doped semiconductor layer coupled to each memory string in the memory block; From the third moment to the first moment, applying a second voltage to the first selection line coupled to the first selection transistor of the first storage string, wherein the second voltage is less than the first voltage; From the third moment to the second moment, applying the second voltage to the first selection line coupled to the first selection transistor of the second storage string; At the third moment, a third voltage is applied to the word line coupled to each memory cell of each memory string in the memory block, and the third voltage is lower than the first voltage.

17. The method according to claim 16, characterized in that Each memory string in the memory block further includes a second selection tube, the memory array further includes a second doped semiconductor layer and a second selection line, the second doped semiconductor layer is coupled to one end of each memory string close to the second selection tube, and the second selection line is coupled to the second selection tube; The erasing operation further includes: At the third moment, applying a fourth voltage to the second doped semiconductor layer coupled to each memory string in the memory block; At the third moment, the second selection line coupled to the second selection transistor of each storage string in the storage block is floated.

18. The method according to claim 17, characterized in that The first doped semiconductor layer is coupled to the bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer.

19. The method according to claim 17, characterized in that The first doped semiconductor layer is coupled to a source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

20. The method according to claim 16, characterized in that Each memory string in the memory block further includes a second selection tube, the memory array further includes a second doped semiconductor layer and a second selection line, the second doped semiconductor layer is coupled to one end of each memory string close to the second selection tube, and the second selection line is coupled to the second selection tube; The erasing operation further includes: At the third moment, a fifth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block.

21. The method according to claim 20, characterized in that The erasing operation further includes: From the third moment to the second moment, applying a sixth voltage to the second selection line coupled to the second selection transistor of each storage string in the storage block, wherein the sixth voltage is less than the fifth voltage; At the second moment, the second selection line coupled to the second selection transistor of each storage string in the storage block is floated.

22. The method according to claim 20, characterized in that The erasing operation further includes: From the third moment to the fourth moment, a seventh voltage is applied to the second selection line coupled to the second selection tube of the first storage string, and at the fourth moment, the second selection line coupled to the second selection tube of the first storage string is floated, and the seventh voltage is less than the fifth voltage; From the third moment to a fifth moment after the fourth moment, the seventh voltage is applied to the second selection line coupled to the second selection tube of the second storage string, and at the fifth moment, the second selection line coupled to the second selection tube of the second storage string is floated.

23. The method according to any one of claims 20 to 22, characterized in that The first doped semiconductor layer is coupled to a bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer; The second doped semiconductor layer is coupled to the source line, and the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

24. The method according to any one of claims 20 to 22, characterized in that The first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer; The second doped semiconductor layer is coupled to the bit line, and the second doped semiconductor layer is an N-type doped semiconductor layer.

25. The method according to any one of claims 15 to 24, characterized in that The storage string includes multiple substrings, each substring includes a first selection tube and multiple storage units, each first selection tube in the same storage string is coupled to the same first selection line, and the first selection tubes in different storage strings are coupled to different first selection lines.

26. The method according to any one of claims 15 to 25, characterized in that After the first selection line coupled to the first selection transistor of the floating second storage string, the method further includes: At a sixth moment after the second moment, performing an erase verification operation on each storage string in the storage block; In the case that there is a second memory string that fails the erasure verification in the memory block, the step of performing an erasing operation on the plurality of memory strings in the memory block is performed.

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