Operation method of memory, memory, storage system and electronic equipment

Abstract

The invention provides an operation method of a memory, the memory, a memory system and electronic equipment, relates to the field of memory, and solves the problem that the reliability of an NAND flash memory is relatively low due to the fact that initial threshold voltage drifts in a memory unit. According to the specific scheme, the operation method of the memory is provided, the memory comprises a plurality of word lines, each word line comprises a plurality of memory units, the method comprises the steps that first programming operation is carried out on a selected word line in the word lines, the first programming operation comprises the step that one-pulse is applied to the selected word line, and programming the plurality of memory cells in the selected word line into N programming states. And performing a second programming operation on the selected word line, and programming the plurality of memory cells in the selected word line to N target programming states, N being a positive integer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of storage, and in particular to a method for operating a storage, a storage, a storage system, and an electronic device. Background Art

[0002] With the continuous development of information technology and the advent of the big data era, NAND flash memory has gradually become the mainstream product of non-volatile memory with its advantages of large capacity and low cost. By programming each storage cell in the NAND flash memory and changing the threshold voltage (Vth) of each storage cell, information can be stored.

[0003] However, as the demand for NAND flash memory storage capacity continues to increase, NAND flash memory continues to develop in the direction of device size reduction and multi-value storage technology, resulting in more serious initial threshold voltage shift (IVS) of each storage cell in the NAND flash memory, which can also be called more serious rapid charge loss, resulting in lower reliability of the NAND flash memory. Summary of the invention

[0004] The embodiments of the present disclosure provide a memory operation method, a memory, a storage system and an electronic device, which solve the problem of low reliability of NAND flash memory due to initial threshold voltage drift of a memory cell.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a method for operating a memory is provided, wherein the memory includes a plurality of word lines, each word line includes a plurality of memory cells, and the method includes: performing a first programming operation on a selected word line among the plurality of word lines, the first programming operation includes applying a single pulse one-pulse to the selected word line, and programming the plurality of memory cells in the selected word line to N programming states. Performing a second programming operation on the selected word line, and programming the plurality of memory cells in the selected word line to N target programming states, where N is a positive integer.

[0007] The memory operation method provided by the embodiment of the present disclosure first performs a first programming operation on a selected word line among multiple word lines, and the first programming operation includes applying a single pulse to the selected word line to program multiple memory cells in the selected word line into N programming states. Then, a second programming operation is performed on the selected word line to program multiple memory cells in the selected word line into N target programming states, thereby solving the problem that the threshold voltages of multiple memory cells in the selected word line drift downward as a whole due to rapid charge loss, and the problem that the threshold voltage distribution curves of the multiple memory cells are widened, thereby improving the reliability of the memory.

[0008] In some embodiments, the first programming operation does not include a verify operation.

[0009] In the memory operation method provided by the embodiment of the present disclosure, the first programming operation does not include a verification operation. When programming multiple storage cells in a selected word line, compared with the incremental step pulse programming method, time can be saved and programming efficiency can be improved.

[0010] In some embodiments, applying a single pulse to the selected word line includes applying a plurality of consecutive programming voltages to the selected word line.

[0011] In some embodiments, a plurality of consecutive programming voltages increase sequentially, or decrease sequentially.

[0012] In some embodiments, the number of the plurality of consecutive programming voltages is N.

[0013] In some embodiments, the memory further includes multiple bit lines, multiple memory cells in a selected word line are coupled to the multiple bit lines, and a first programming operation includes: applying a programming voltage to the selected word line, applying a first bit line voltage to a selected bit line among the multiple bit lines, and applying a second bit line voltage to an unselected bit line among the multiple bit lines, thereby programming the memory cells among the multiple memory cells coupled to the selected bit line to the same programming state, and the first bit line voltage is less than the second bit line voltage.

[0014] In the memory operation method provided by the embodiment of the present disclosure, the first programming operation does not include a verification operation. When programming multiple storage cells in a selected word line, compared with the incremental step pulse programming method, time can be saved and programming efficiency can be improved.

[0015] In some embodiments, performing a second programming operation on the selected word line includes: performing a second programming operation on a plurality of memory cells in the selected word line using an incremental step pulse programming (ISPP) method.

[0016] The memory operation method provided by the embodiment of the present disclosure performs a second programming operation on a selected word line after a first programming operation, and programs multiple memory cells in the selected word line into N target programming states, thereby solving the problem that the threshold voltages of multiple memory cells in the selected word line drift downward as a whole due to rapid charge loss, and the problem that the threshold voltage distribution curves of the multiple memory cells widen, thereby improving the reliability of the NAND flash memory.

[0017] In some embodiments, the second programming operation includes a verify operation.

[0018] In the memory operation method provided by the embodiment of the present disclosure, the second programming operation includes a verification operation. By performing the second programming operation on the selected word line, the multiple storage cells in the selected word line are programmed again and verified, so that the storage cells in the selected word line can be programmed to the target programming state more accurately, and the problem of the overall low drift of the threshold voltages of the multiple storage cells in the selected word line due to the rapid charge loss and the widening of the threshold voltage distribution curves of the multiple storage cells can be solved, thereby improving the reliability of the NAND flash memory.

[0019] In some embodiments, a threshold voltage distribution range of memory cells in an Nth programming state after a first programming operation is greater than a threshold voltage distribution range of memory cells in an Nth programming state after a second programming operation.

[0020] On the other hand, a memory is provided, which includes a peripheral circuit and a memory array coupled to the peripheral circuit, the memory array including a plurality of word lines, each word line including a plurality of memory cells. The peripheral circuit is configured to perform a first programming operation on a selected word line among the plurality of word lines, the first programming operation including applying a single pulse one-pulse to the selected word line to program the plurality of memory cells in the selected word line to N programming states. A second programming operation is performed on the selected word line to program the plurality of memory cells in the selected word line to N target programming states, where N is a positive integer.

[0021] In some embodiments, the first programming operation does not include a verify operation.

[0022] In some embodiments, the peripheral circuit is specifically configured to apply a plurality of consecutive programming voltages to the selected word line.

[0023] In some embodiments, a plurality of consecutive programming voltages increase sequentially, or decrease sequentially.

[0024] In some embodiments, the number of the plurality of consecutive programming voltages is N.

[0025] In some embodiments, the memory array further comprises a plurality of bit lines, and the plurality of memory cells in the selected word line are coupled to the plurality of bit lines. The peripheral circuit is specifically configured to apply a programming voltage to the selected word line, apply a first bit line voltage to a selected bit line among the plurality of bit lines, and apply a second bit line voltage to an unselected bit line among the plurality of bit lines, so that the memory cells coupled to the selected bit line among the plurality of memory cells are programmed to the same programming state, and the first bit line voltage is less than the second bit line voltage.

[0026] In some embodiments, the peripheral circuit is specifically configured to perform a second programming operation on a plurality of memory cells in a selected word line using an incremental step pulse programming (ISPP) method.

[0027] In some embodiments, the second programming operation includes a verify operation.

[0028] In some embodiments, a threshold voltage distribution range of memory cells in an Nth programming state after a first programming operation is greater than a threshold voltage distribution range of memory cells in an Nth programming state after a second programming operation.

[0029] On the other hand, a storage system is provided. The storage system includes a controller and at least one memory coupled to the controller. The controller is used to control the reading and writing of the memory. The memory includes the aforementioned memory.

[0030] On the other hand, an electronic device is provided. The electronic device includes a processor and a storage system coupled to the processor, wherein the storage system includes the storage system provided above.

[0031] It can be understood that the beneficial effects that can be achieved by the memory, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the memory operation method described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0033] Figure 1 is a schematic structural diagram of an electronic device according to some embodiments;

[0034] Figure 2 is a schematic diagram of the structure of a memory according to some embodiments;

[0035] Figure 3 is a schematic diagram of the structure of a storage array according to some embodiments;

[0036] Figure 4 is a schematic diagram of a change in a voltage applied to a memory cell according to some embodiments;

[0037] Figure 5 is a schematic diagram of a threshold voltage distribution curve according to some embodiments;

[0038] Figure 6 is a schematic structural diagram of a storage unit according to some embodiments;

[0039] Figure 7 is a schematic diagram of another threshold voltage distribution curve according to some embodiments;

[0040] Figure 8 is a flow chart of a method for operating a memory according to some embodiments;

[0041] Fig. 9 is another schematic diagram of a change in a voltage applied to a memory cell according to some embodiments;

[0042] Fig.10 is a schematic diagram of another threshold voltage distribution curve according to some embodiments;

[0043] Fig.11 FIG. 4 is a schematic diagram of another variation of a voltage applied to a memory cell according to some embodiments. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0045] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0047] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0048] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0049] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0050] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0051] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0052] Before introducing the embodiments of the present disclosure, the technical terms and background technologies involved in the present disclosure are first introduced.

[0053] The term "three-dimensional memory" refers to a semiconductor device formed by a string of memory cell transistors (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on the main surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or the source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., the lateral surface) of the substrate or the source layer. The string address is the address corresponding to the "memory cell string". The "selected word line (word line, WL)" is the word line corresponding to the word line address in the read request instruction, and the "unselected word line" is the word line other than the word line corresponding to the word line address in the read request instruction.

[0054] Single level cell (SLC): Each memory cell has only one storage bit and can only store one data item.

[0055] Multi-level cell (MLC): Each memory cell has two storage bits and can store two data items.

[0056] Triple level cell (TLC): Each memory cell has three storage bits and can store three data items simultaneously.

[0057] Quad level cell (QLC): Each memory cell has four storage bits and can store four data items simultaneously.

[0058] Fast charge loss: refers to the fact that after programming, the stability of electrons captured by shallow energy traps in the memory cell is lower than that of electrons captured by deep energy traps. In the short time after programming is completed, the electrons captured by shallow energy traps will be quickly released and return to the channel, causing the threshold voltage to shift down and widen the threshold voltage distribution.

[0059] like Figure 1 As shown, a storage system 100 is usually provided in an electronic device 10. The storage system 100 includes a memory 200 and a controller 300. The controller 300 is coupled to the memory 200, and data can be read from the memory 200 or written to the memory 200 through the controller 300.

[0060] It is understood that the storage system 100 may include a controller 300 and one or more memories 200. For example, in one embodiment, the controller 300 and a single memory 200 may be integrated into a memory card. The memory card may include a PCMCIA (PC) card, a compact flash card (CF card), a smart media card (SM card), a memory stick, a multimedia card (MMC), a secure digital card (SD card), a universal flash storage (UFS), etc. Among them, the multimedia card may be divided into MMC, a reduced-size MMC (RS-MMC), a mini MMC (MMCmicro), etc.; the secure digital card includes SD, a mini SD card (miniSD), a micro SD card (microSD), a secure digital high capacity SD card (SDHC), etc. Further, the memory card may also include a memory card connector for coupling the memory card to a host.

[0061] In another embodiment, the controller 300 and the plurality of memories 200 may be integrated into a solid state disk (SSD). The SSD may further include an SSD connector for coupling the SSD to a host. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of the memory card. In addition, the electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc., and the embodiments of the present disclosure are not limited thereto.

[0062] like Figure 2 As shown, the memory 200 generally includes a memory array 210 and peripheral circuits. The peripheral circuits include a connection terminal 221, a control logic circuit 222, a register 223, a voltage generator 224, a row driver 225, a column driver 226, and a page buffer 227.

[0063] The connection terminal 221 is mainly used to receive the read instruction and write instruction sent by the controller 300 and send the read data to the controller 300. The control logic circuit 222 is mainly used to control the row driver 225 to connect the voltage generator 224 with the corresponding word line according to the received read instruction, and control the column driver 226 to connect the voltage generator 224 with the corresponding bit line (BL), so as to read the corresponding data. The register 223 includes an address register, a status register, etc. Among them, the address register is used to store the word line address and the string address in the read request instruction. The status register is used to store the current state of the memory, including the ready and busy states. When the control logic circuit 222 is reading data from the storage array 210 or writing data to the storage array 210, the state stored in the status register is the "busy" state, and the next read or write operation cannot be performed. When the storage array 210 completes the reading process or the writing process, the state stored in the status register is switched to the "ready" state, and the next read or write operation can be performed. The page buffer 227 includes a first register and a second register, wherein the first register is used to cache data read from the storage array 210 , and the second register is used to cache data transferred from the first register.

[0064] The memory array 210 in the memory 200 may include a plurality of memory cells arranged at the intersection of word lines and bit lines. According to the difference in the structure of the memory array 210, the memory may be divided into a two-dimensional memory and a three-dimensional memory. Figure 3 As shown, it is a schematic diagram of the structure of a storage array 210 in a three-dimensional memory, and the storage array 210 includes word lines WL1-WL3 and bit lines BL1-BL7. A plurality of storage cells on each bit line perpendicular to each word line form a storage cell string 211. A top selective gate (TSG) is provided at the top of each storage cell string 211, and a bottom selective gate (BSG) is provided at the bottom. A plurality of storage cell strings 211 can be provided on each bit line, and each word line can be coupled to storage cells in a plurality of storage cell strings 211. The difference between a two-dimensional memory and a three-dimensional memory is that in a two-dimensional memory, there is only one storage cell in a storage cell string 211 perpendicular to each bit line.

[0065] The smallest unit of programming in NAND flash memory is page. Take a certain storage cell in a page as an example. When data needs to be stored in the storage cell, the conduction voltage can be input to the top selection tube (TSG) and the bottom selection tube (BSG) respectively to turn on the top selection tube and the bottom selection tube, and then the programming voltage is applied to the word line coupled to the storage cell, and the programming permission voltage is applied to the bit line coupled to the storage cell, so that the threshold voltage (Vth) of the storage cell can be programmed to achieve information storage. When data needs to be read from the storage cell, the conduction voltage can be input to the top selection tube and the bottom selection tube respectively to turn on the top selection tube and the bottom selection tube, and then the read voltage is applied to the word line coupled to the storage cell, and the conduction voltage is applied to the bit line coupled to the storage cell, so that the information can be read.

[0066] At present, the related art uses an incremental step pulse program (ISPP) method to program NAND flash memory. Specifically, taking a memory cell in a page of NAND flash memory as an example, during the programming process, a continuously increasing programming voltage is applied to a word line coupled to the memory cell, and a turn-on voltage is applied to a bit line coupled to the memory cell, thereby implementing programming of the memory cell.

[0067] For example, Figure 4 The diagram is a schematic diagram of a change in voltage applied to a memory cell. Taking a memory cell in a page of a NAND flash memory as an example, when programming starts, a first programming voltage Vcg-P1 can be applied to the word line coupled to the memory cell, a programming enable voltage can be applied to the bit line coupled to the memory cell, and then a programming verification voltage Vcg-V can be applied to the word line to verify whether the threshold voltage Vth of the memory cell reaches the target threshold. If the target threshold is not reached, a second programming voltage Vcg-P2 is applied to the word line coupled to the memory cell, a programming enable voltage is applied to the bit line coupled to the memory cell, and then a programming verification voltage Vcg-V is applied to the word line again to verify whether the threshold voltage Vth of the memory cell reaches the target threshold, wherein the difference between the second programming voltage Vcg-P2 and the first programming voltage Vcg-P1 is λ. The above steps are continuously repeated, and programming voltages of increasing λ such as Vcg-P3 to Vcg-P5 are applied to the word line coupled to the memory cell, so that the threshold voltage Vth of the memory cell increases continuously, and verification is performed after each application of the programming voltage until the threshold voltage Vth of the memory cell reaches the target threshold value, and then programming of the memory cell is stopped, thereby completing the programming of the memory cell, which can also be called programming the memory cell to the target programming state.

[0068] By adopting the above-mentioned incremental step pulse programming method, the storage cells in the NAND flash memory can be programmed to any one of a plurality of different programming states, based on which the storage cells in the NAND flash memory can realize multi-value storage.

[0069] For example, a NAND flash memory includes a plurality of storage cells, and the plurality of storage cells are programmed into a plurality of programming states using the above-mentioned incremental step pulse programming method.

[0070] When the plurality of memory cells are multi-level cells (MLC), the storage data amount of each memory cell is 2 bits / cell. After programming the plurality of memory cells into a plurality of programming states, the threshold voltage distribution of the plurality of memory cells may be as follows: Figure 5 As shown in (a), it can be understood that at this time, the multiple storage cells are programmed to 4 programming states, and the 4 programming states are respectively "11", "10", "01" and "00".

[0071] When the plurality of memory cells are three-level cells (TLC), the storage data amount of each memory cell is 3 bits / cell. After programming the plurality of memory cells into a plurality of programming states, the threshold voltage distribution of the plurality of memory cells may be as follows: Figure 5 As shown in (b), it can be understood that at this time, the multiple storage cells are programmed to 8 programming states, and the 8 programming states are respectively "111", "110", "101", "100", "011", "010", "001" and "000".

[0072] When the plurality of memory cells are quad-level cells (QLC), the amount of storage data of each memory cell is 4 bits / cell. After programming the plurality of memory cells into a plurality of programming states, the threshold voltage distribution of the plurality of memory cells may be as follows: Figure 5 As shown in (b), it can be understood that at this time, the multiple storage cells are programmed to 16 programming states, and the 16 programming states are respectively "1111", "1110", "1101", "1100", "1011", "1010", "1001", "1000", "0111", "0110", "0101", "0100", "0011", "0010", "0001" and "0000".

[0073] As the demand for storage capacity continues to increase, NAND flash memory continues to develop towards device size reduction and multi-value storage technology, which will lead to more serious rapid charge loss of each storage cell in NAND flash memory, resulting in lower reliability of NAND flash memory.

[0074] Specifically, Figure 6 As shown in (a) of FIG. 1 , a NAND flash memory includes a first storage unit 610 and a second storage unit 620 as an example. The two storage units each include a source (source, S), a drain (drain, D) and a control gate (control gate, CG). The control gate is coupled to a word line (WL). The source of the first storage unit 610 is coupled to the drain of the second storage unit 620. The first storage unit 610 further includes a channel 611, a tunneling oxide layer (BE-tunneling oxide) 612, a trap layer 613 and a block layer 614. The second storage unit 620 further includes a channel 621 coupled to the channel 611, a tunneling oxide layer 622 coupled to the tunneling oxide layer 612, a trap layer 623 coupled to the trap layer 613, and a block layer 624 coupled to the block layer 614. Among them, the length of the control gate of the first storage unit 610 is Lg1, which can also be called the gate length Lg1, the gate length of the second storage unit 620 is Lg2, and the distance between the control gate of the first storage unit 610 and the control gate of the second storage unit 620 is Ls, which can also be called the gate spacing Ls.

[0075] As NAND flash memory continues to develop in the direction of device size reduction and multi-value storage technology, the gate length Lg1 of the first storage cell 610 and the gate length Lg2 of the second storage cell will continue to decrease, and the gate spacing Ls between the control gate of the first storage cell 610 and the control gate of the second storage cell 620 will also continue to decrease, which will aggravate the lateral migration of charges in the first storage cell 610 and the second storage cell 620, resulting in more serious rapid charge loss in the first storage cell 610 and the second storage cell 620.

[0076] like Figure 6 As shown in (b), taking the first memory cell 610 as an example, as the gate length Lg1 of the first memory cell 610 decreases, and the gate spacing between the first memory cell 610 and the second memory cell 620 decreases, after programming, the electrons stored in the shallow energy level traps in the trap layer 613 of the first memory cell 610 will be released in a short time after the programming is completed due to their low stability, and will return to the channel 611, which can also be called de-trapping, thereby causing more serious rapid charge loss in the first memory cell 610.

[0077] The rapid charge loss is more serious, which will cause the threshold voltage of the storage cell in the NAND flash memory to drift downward as a whole after programming. It will also cause the threshold voltage distribution curve of the storage cell in the NAND flash memory to widen after programming, resulting in lower reliability of the NAND flash memory.

[0078] Specifically, Figure 7 As shown in (a) in FIG. 1 , a NAND flash memory includes multiple memory cells as an example. The post-programming curve represents the threshold voltage distribution curve of the multiple memory cells after programming is completed, and the post-fast charge loss (IVS) curve represents the threshold voltage distribution curve of the multiple memory cells after the fast charge loss. It can be understood that the fast charge loss will cause the threshold voltage of the multiple memory cells to drift downward as a whole after programming. Moreover, the fast charge loss will also cause the threshold voltage distribution curve of the multiple memory cells after programming to widen and overlap, such as Figure 7 As shown in (b) in FIG. 1 , the threshold voltages of the plurality of memory cells after programming drift downward, and the threshold voltage distribution curves of the plurality of memory cells after programming widen, which will result in reduced reliability of the plurality of memory cells when reading and writing data, resulting in lower reliability of the NAND flash memory.

[0079] In order to solve the problem that the initial threshold voltage of a memory cell drifts and the reliability of a NAND flash memory is low, an embodiment of the present disclosure provides a memory operation method, which can improve the reliability of the NAND flash memory.

[0080] like Figure 8 As shown, a method for operating a memory provided by an embodiment of the present disclosure includes steps S801-S802. The memory includes a plurality of word lines, each word line includes a plurality of storage cells, and the embodiment of the present disclosure does not limit the specific number of word lines included in the memory and the specific number of storage cells included in each word line. In a possible embodiment, the memory may be the above-mentioned memory 200.

[0081] S801. Perform a first programming operation on a selected word line among a plurality of word lines. The first programming operation includes applying a single pulse one-pulse to the selected word line to program a plurality of storage cells in the selected word line into N programming states, where N is a positive integer.

[0082] Optionally, the selected word line may be one of a plurality of word lines, or may be a plurality of word lines, which is not limited in the embodiments of the present disclosure.

[0083] Specifically, applying a single pulse to the selected word line includes applying a plurality of consecutive programming voltages to the selected word line.

[0084] Optionally, the multiple consecutive programming voltages increase or decrease sequentially, which is not limited in the embodiments of the present disclosure.

[0085] In a possible embodiment, the number of the plurality of continuous programming voltages is N.

[0086] Optionally, the specific value of N is related to the type of storage cells in the selected word line. The embodiment of the present disclosure does not limit the type of storage cells in the selected word line, and does not limit the specific value of N.

[0087] For example, when multiple storage cells in the selected word line are SLC, the value of N is 1. When multiple storage cells in the selected word line are MLC, the value of N is 3. When multiple storage cells in the selected word line are TLC, the value of N is 7. When the storage cells in the selected word line are QLC, the value of N is 15.

[0088] In a possible embodiment, the memory also includes multiple bit lines, and multiple memory cells in a selected word line are coupled to the multiple bit lines. The first programming operation specifically includes: applying a programming voltage to the selected word line, applying a first bit line voltage to a selected bit line among the multiple bit lines, and applying a second bit line voltage to an unselected bit line among the multiple bit lines, thereby programming the memory cells coupled to the selected bit line among the multiple memory cells to the same programming state, and the first bit line voltage is less than the second bit line voltage.

[0089] It can be understood that the first programming operation does not include a verification operation, so when programming a plurality of memory cells in a selected word line, time can be saved and programming efficiency can be improved compared with the above-mentioned incremental step pulse programming method.

[0090] Optionally, the selected bit line may be one of a plurality of bit lines, or may be a plurality of a plurality of bit lines, which is not limited in the embodiments of the present disclosure.

[0091] Optionally, the unselected bit line may be one of a plurality of bit lines, or may be a plurality of a plurality of bit lines, which is not limited in the embodiments of the present disclosure.

[0092] Among them, the first bit line voltage is used to allow programming of the memory cell coupled to the selected bit line, and the first bit line voltage can also be called a programming enable voltage. The second bit line voltage is used to prohibit programming of the memory cell coupled to the unselected bit line, and the second bit line voltage can also be called a programming inhibit voltage.

[0093] For example, Fig. 9 As shown, the multiple storage cells in the selected word line are TLC, the value of N is 7, the first programming operation programs the multiple storage cells in the selected word line to the 7 programming states L1-L7, the multiple continuous programming voltages applied to the selected word line are successively reduced, the multiple programming voltages are all greater than the turn-on voltage Vpass, the memory includes the first bit line to the seventh bit line, and the selected bit line in each pulse cycle is one of the 7 bit lines for example.

[0094] Before programming the multiple memory cells in the selected word line, the multiple memory cells are in the erased state L0, and the threshold voltage distribution curves of the multiple memory cells are as follows: Fig.10 As shown in (a) in .

[0095] In the first pulse cycle, the selected bit line may be the first bit line, and the unselected bit lines may be the second to seventh bit lines. The first programming voltage V1 may be applied to the selected word line, the first bit line voltage may be applied to the first bit line, and the second bit line voltage may be applied to the second to seventh bit lines, so that the memory cells coupled to the first bit line are programmed to the same programming state L7. Fig. 9 In FIG. 1 , “√” indicates that the first bit line voltage is applied, and “X” indicates that the second bit line voltage is applied.

[0096] In the second pulse cycle, the selected bit line can be the second bit line, and the unselected bit lines can be the first bit line and the third to seventh bit lines. The second programming voltage V2 can be applied to the selected word line, the first bit line voltage can be applied to the second bit line, and the second bit line voltage can be applied to the first bit line and the third to seventh bit lines, so that the storage cells coupled to the second bit line can be programmed to the same programming state L6.

[0097] During the third pulse cycle to the sixth pulse cycle, a third programming voltage V3 to a sixth programming voltage V6 that decreases successively can be applied to the selected word line, and the first bit line voltage can be applied successively to the selected third bit line to the sixth bit line, so that the storage cells coupled to the third bit line to the sixth bit line can be programmed into programming states L5-L2 respectively. The specific process can refer to the description of the first pulse cycle and the second pulse cycle above, and the embodiments of the present disclosure will not be repeated here.

[0098] In the seventh pulse cycle, the selected bit line may be the seventh bit line, and the unselected bit lines may be the first bit line to the sixth bit line. The seventh programming voltage V7 may be applied to the selected word line, the first bit line voltage may be applied to the seventh bit line, and the second bit line voltage may be applied to the first bit line to the sixth bit line, so that the memory cells coupled to the seventh bit line are programmed to the same programming state L7. Due to the existence of fast charge loss, the threshold voltages of the multiple memory cells in the selected word line drift downward as a whole after programming, and the threshold voltage distribution curves of the multiple memory cells are widened. The threshold voltage distribution curves of the multiple memory cells after the first programming operation are as shown in FIG. Fig.10 As shown in (b) in .

[0099] It can be understood that through the seven pulse cycles, the storage cells coupled to the first bit line to the seventh bit line can be programmed to the L1-L7 programming states respectively, and there is no verification operation during the programming process, thereby saving programming time and improving programming efficiency.

[0100] For example, Fig.11As shown, the multiple storage cells in the selected word line are TLC, the value of N is 7, the first programming operation programs the multiple storage cells in the selected word line to the 7 programming states L1-L7, the multiple continuous programming voltages applied to the selected word line increase in sequence, the multiple programming voltages are all greater than the turn-on voltage Vpass, the memory includes the first bit line to the seventh bit line, and the selected bit line in each pulse cycle is a plurality of the 7 bit lines as an example.

[0101] Before programming the multiple memory cells in the selected word line, the multiple memory cells are in the erased state L0, and the threshold voltage distribution curves of the multiple memory cells are as follows: Fig.10 As shown in (a) in .

[0102] In the first pulse cycle, the selected bit line can be the first bit line to the seventh bit line, the first programming voltage V1 can be applied to the selected word line, and the first bit line voltage can be applied to the first bit line to the seventh bit line, so that the storage cells coupled to the first bit line to the seventh bit line can be programmed to the same programming state L1.

[0103] In the second pulse cycle, the selected bit line can be the second to seventh bit lines, and the unselected bit line can be the first bit line. The second programming voltage V2 can be applied to the selected word line, the first bit line voltage can be applied to the second to seventh bit lines, and the second bit line voltage can be applied to the first bit line, so that the memory cells coupled to the second to seventh bit lines will be programmed to the same programming state L2, and the memory cells coupled to the first bit line will maintain the first programming state L1.

[0104] During the third pulse cycle to the sixth pulse cycle, the third programming voltage V3 to the sixth programming voltage V6 which increase successively can be applied to the selected word line, and the number of selected bit lines in each pulse cycle can be reduced successively, so that the storage cells coupled to the third bit line to the sixth bit line can be programmed into programming states L3-L6 respectively. The specific process can refer to the description of the first pulse cycle and the second pulse cycle mentioned above, and the embodiments of the present disclosure will not be repeated here.

[0105] In the seventh pulse cycle, the selected bit line may be the seventh bit line, and the unselected bit lines may be the first bit line to the sixth bit line. The seventh programming voltage V7 may be applied to the selected word line, the first bit line voltage may be applied to the seventh bit line, and the second bit line voltage may be applied to the first bit line to the sixth bit line, so that the memory cells coupled to the seventh bit line are programmed to the same programming state L7, and the memory cells coupled to the remaining bit lines will maintain their respective corresponding programming states. Due to the existence of rapid charge loss, the threshold voltages of the multiple memory cells in the selected word line drift downward as a whole after programming, and the threshold voltage distribution curves of the multiple memory cells are widened. The threshold voltage distribution curves of the multiple memory cells after the first programming operation are as shown in FIG. Fig.10 As shown in (b) in .

[0106] It can be understood that through the seven pulse cycles, the storage cells coupled to the first bit line to the seventh bit line can be programmed to the L1-L7 programming states respectively, and there is no verification operation during the programming process, thereby saving programming time and improving programming efficiency.

[0107] S802 , performing a second programming operation on the selected word line to program a plurality of memory cells in the selected word line to N target programming states.

[0108] In a possible embodiment, the N target programming states may be predetermined according to types of the plurality of memory cells.

[0109] Exemplarily, when the plurality of memory cells are TLC, before programming the plurality of memory cells, seven target programming states of the plurality of memory cells may be determined by simulation or experiment.

[0110] Specifically, performing the second programming operation on the selected word line includes: performing the second programming operation on a plurality of storage cells in the selected word line by using an incremental step pulse programming method.

[0111] For example, the multiple memory cells in the selected word line are TLC, the value of N is 7, and after the first programming operation of the multiple memory cells in the selected word line, the threshold voltage distribution curve is as follows: Fig.10 For multiple memory cells programmed to the same programming state L1 after the first programming operation, the following can be used: Figure 4 The incremental step pulse programming method shown is programmed to Fig.10 The target programming state L1 is shown in (c) of FIG. The multiple memory cells in the remaining programming states can also adopt this method, so that the multiple memory cells in the selected word line are programmed to 7 target programming states. At this time, the threshold voltage distribution curves of the multiple memory cells after the first programming operation are as follows: Fig.10 For the specific process, please refer to the above Figure 4 The related description of the prior art and the related description of the incremental step pulse programming are not repeated here in the embodiments of the present disclosure.

[0112] It can be understood that the second programming operation includes a verification operation. By performing the second programming operation on the selected word line, programming the multiple storage cells in the selected word line again, and verifying, the storage cells in the selected word line can be programmed to the target programming state more accurately, and the problem of the overall low drift of the threshold voltages of the multiple storage cells in the selected word line due to fast charge loss and the widening of the threshold voltage distribution curves of the multiple storage cells can be solved, thereby improving the reliability of the NAND flash memory.

[0113] In a possible embodiment, a threshold voltage distribution range of memory cells in the Nth programming state after the first programming operation is greater than a threshold voltage distribution range of memory cells in the Nth programming state after the second programming operation.

[0114] For example, after the first programming operation, the threshold voltage distribution range of the memory cell in the first programming state L1 is as follows: Fig.10 As shown in (b), the threshold voltage distribution range of the memory cell in the first programming state L1 after the second programming operation is as follows: Fig.10 As shown in (c) in FIG. 1 , it can be understood that the threshold voltage distribution range of the memory cells in the first programming state L1 after the first programming operation is greater than the threshold voltage distribution range of the memory cells in the first programming state L1 after the second programming operation. By performing the second programming operation after the first programming operation, the problem of the overall drift of the threshold voltages of the multiple memory cells in the selected word line to a lower level due to the rapid charge loss and the problem of the widening of the threshold voltage distribution curves of the multiple memory cells are solved.

[0115] In a possible embodiment, when M memory cells out of K memory cells reach the target programming state after the second programming operation, it can be determined that the K memory cells are programmed to the target programming state, and the K memory cells are memory cells programmed to the same programming state after the first programming operation, M and K are both positive integers, M is less than or equal to K, and the embodiments of the present disclosure do not limit the specific values ​​of K and M.

[0116] For example, taking the value of K as 1000 and the value of M as 900, and taking 1000 memory cells as an example where they are programmed to the same programming state after the first programming operation, when 900 of the 1000 memory cells reach the target programming state after the second programming operation, it can be determined that the 1000 memory cells are programmed successfully without continuously performing the second programming operation until all the 1000 memory cells are programmed to the target programming state and then stopping, thereby saving programming time and improving programming efficiency.

[0117] The memory operation method provided by the embodiment of the present disclosure first performs a first programming operation on a selected word line among multiple word lines, and the first programming operation includes applying a single pulse to the selected word line to program multiple memory cells in the selected word line into N programming states. Then, a second programming operation is performed on the selected word line to program multiple memory cells in the selected word line into N target programming states, thereby solving the problem that the threshold voltages of multiple memory cells in the selected word line drift downward as a whole due to rapid charge loss, and the problem that the threshold voltage distribution curves of the multiple memory cells are widened, thereby improving the reliability of the NAND flash memory. In addition, the first programming operation does not include a verification operation, and when programming multiple memory cells in the selected word line, compared with the above-mentioned incremental step pulse programming method, time can be saved and programming efficiency can be improved.

[0118] The present disclosure also provides a memory, which includes a peripheral circuit and a memory array coupled to the peripheral circuit, wherein the memory array includes a plurality of word lines, and each word line includes a plurality of memory cells. In a possible embodiment, the structure of the memory may be as follows: Figure 2 The structure of the memory 200 is shown.

[0119] The peripheral circuit is configured to perform a first programming operation on a selected word line among the multiple word lines, the first programming operation includes applying a single pulse to the selected word line to program multiple memory cells in the selected word line to N programming states. The peripheral circuit is also configured to perform a second programming operation on the selected word line to program multiple memory cells in the selected word line to N target programming states, where N is a positive integer.

[0120] Optionally, the selected word line may be one of a plurality of word lines, or may be a plurality of word lines, which is not limited in the embodiments of the present disclosure.

[0121] In a possible embodiment, the peripheral circuit is specifically configured to apply a plurality of continuous programming voltages to the selected word line.

[0122] Optionally, the multiple consecutive programming voltages increase or decrease sequentially, which is not limited in the embodiments of the present disclosure.

[0123] In a possible embodiment, the number of the plurality of continuous programming voltages is N.

[0124] Optionally, the specific value of N is related to the type of storage cells in the selected word line. The embodiment of the present disclosure does not limit the type of storage cells in the selected word line, and does not limit the specific value of N.

[0125] In a possible embodiment, the memory further includes a plurality of bit lines, and the plurality of storage cells in the selected word line are coupled to the plurality of bit lines. When performing the first programming operation, the peripheral circuit is specifically configured to apply a programming voltage to the selected word line, apply a first bit line voltage to a selected bit line among the plurality of bit lines, and apply a second bit line voltage to an unselected bit line among the plurality of bit lines, so that the storage cells coupled to the selected bit line among the plurality of storage cells are programmed to the same programming state, and the first bit line voltage is less than the second bit line voltage.

[0126] It can be understood that the first programming operation does not include a verification operation, so when programming a plurality of memory cells in a selected word line, time can be saved and programming efficiency can be improved compared with the above-mentioned incremental step pulse programming method.

[0127] Optionally, the selected bit line may be one of a plurality of bit lines, or may be a plurality of a plurality of bit lines, which is not limited in the embodiments of the present disclosure.

[0128] Optionally, the unselected bit line may be one of a plurality of bit lines, or may be a plurality of a plurality of bit lines, which is not limited in the embodiments of the present disclosure.

[0129] In a possible embodiment, the N target programming states may be predetermined according to types of the plurality of memory cells.

[0130] In a possible embodiment, the peripheral circuit is specifically configured to perform a second programming operation on multiple memory cells in a selected word line by using an incremental step pulse programming method. It can be understood that the second programming operation includes a verification operation. By performing the second programming operation on the selected word line, programming the multiple memory cells in the selected word line again, and verifying, the problem of the overall drift of the threshold voltages of the multiple memory cells in the selected word line to a lower level due to the rapid charge loss and the problem of the threshold voltage distribution curve of the multiple memory cells widening can be solved, thereby improving the reliability of the NAND flash memory.

[0131] In a possible embodiment, a threshold voltage distribution range of memory cells in the Nth programming state after the first programming operation is greater than a threshold voltage distribution range of memory cells in the Nth programming state after the second programming operation.

[0132] In the memory provided by the embodiment of the present disclosure, the peripheral circuit first performs a first programming operation on a selected word line among multiple word lines, and the first programming operation includes applying a single pulse to the selected word line to program multiple storage cells in the selected word line into N programming states. Then, the peripheral circuit performs a second programming operation on the selected word line to program multiple storage cells in the selected word line into N target programming states, thereby solving the problem that the threshold voltages of multiple storage cells in the selected word line drift downward as a whole due to rapid charge loss, and the problem that the threshold voltage distribution curves of the multiple storage cells are widened, thereby improving the reliability of the NAND flash memory. In addition, the first programming operation does not include a verification operation, and when programming multiple storage cells in the selected word line, compared with the above-mentioned incremental step pulse programming method, time can be saved and programming efficiency can be improved.

[0133] The present disclosure also provides a storage system, which includes a controller and at least one memory coupled to the controller, wherein the controller is used to control the reading and writing of the memory, and the memory is the memory provided by the above-mentioned embodiment of the present disclosure, and the structure of the memory can be as follows: Figure 2 The structure of the memory 200 shown in the figure, the structure of the storage system can be as in the above example, Figure 1The structure of the storage system 100 is shown in FIG.

[0134] The present disclosure also provides an electronic device, which includes a processor and a storage system coupled to the processor. The storage system is the storage system provided by the above-mentioned embodiment of the present disclosure. The structure of the storage system can be as follows: Figure 1 The structure of the storage system 100 shown in FIG. 1 may be as follows: Figure 1 The structure of the electronic device 10 is shown.

[0135] It should be noted that the relevant descriptions about the operating methods of the memory in the above embodiments can be correspondingly referred to in the embodiments of the memory, storage system and electronic device, and the embodiments of the present disclosure will not be repeated here.

[0136] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for operating a memory, characterized in that: The memory includes a plurality of word lines, each word line includes a plurality of memory cells, and the method includes: Performing a first programming operation on a selected word line among the plurality of word lines, wherein the first programming operation includes applying a single pulse one-pulse to the selected word line to program a plurality of memory cells in the selected word line into N programming states; A second programming operation is performed on the selected word line to program a plurality of memory cells in the selected word line to N target programming states, where N is a positive integer.

2. The method according to claim 1, characterized in that The first programming operation does not include a verification operation.

3. The method according to claim 2, characterized in that The applying a single pulse to the selected word line includes: applying a plurality of continuous programming voltages to the selected word line.

4. The method according to claim 3, characterized in that The plurality of consecutive programming voltages increase sequentially or decrease sequentially.

5. The method according to claim 4, characterized in that The number of the plurality of consecutive programming voltages is N.

6. The method according to claim 5, characterized in that The memory further includes a plurality of bit lines, a plurality of memory cells in the selected word line are coupled to the plurality of bit lines, and the first programming operation includes: A programming voltage is applied to the selected word line, a first bit line voltage is applied to a selected bit line among the multiple bit lines, and a second bit line voltage is applied to an unselected bit line among the multiple bit lines, so that the memory cells among the multiple memory cells coupled to the selected bit line are programmed to the same programming state, and the first bit line voltage is less than the second bit line voltage.

7. The method according to any one of claims 1 to 6, characterized in that The performing a second programming operation on the selected word line includes: The incremental step pulse programming (ISPP) method is adopted to perform a second programming operation on the plurality of storage cells in the selected word line.

8. The method according to claim 7, characterized in that The second programming operation includes a verification operation.

9. The method according to claim 8, characterized in that A threshold voltage distribution range of the memory cells in the Nth programming state after the first programming operation is greater than a threshold voltage distribution range of the memory cells in the Nth programming state after the second programming operation.

10. A memory, characterized in that: The memory includes a peripheral circuit and a memory array coupled to the peripheral circuit, the memory array includes a plurality of word lines, each word line includes a plurality of memory cells; The peripheral circuit is configured to perform a first programming operation on a selected word line among the plurality of word lines, wherein the first programming operation includes applying a single pulse one-pulse to the selected word line to program a plurality of memory cells in the selected word line into N programming states; A second programming operation is performed on the selected word line to program a plurality of memory cells in the selected word line to N target programming states, where N is a positive integer.

11. The memory according to claim 10, characterized in that: The first programming operation does not include a verification operation.

12. The memory according to claim 11, characterized in that: The peripheral circuit is specifically configured to apply a plurality of continuous programming voltages to the selected word line.

13. The memory according to claim 12, characterized in that: The plurality of consecutive programming voltages increase sequentially or decrease sequentially.

14. The memory according to claim 13, characterized in that: The number of the plurality of consecutive programming voltages is N.

15. The memory according to claim 14, characterized in that: The memory array further comprises a plurality of bit lines, and the plurality of memory cells in the selected word line are coupled to the plurality of bit lines; The peripheral circuit is specifically configured to apply a programming voltage to the selected word line, apply a first bit line voltage to a selected bit line among the multiple bit lines, and apply a second bit line voltage to an unselected bit line among the multiple bit lines, so as to program the memory cells among the multiple memory cells coupled to the selected bit line to the same programming state, and the first bit line voltage is less than the second bit line voltage.

16. The memory according to any one of claims 10 to 15, characterized in that: The peripheral circuit is specifically configured to perform a second programming operation on a plurality of storage cells in the selected word line by adopting an incremental step pulse programming (ISPP) method.

17. The memory according to claim 16, characterized in that: The second programming operation includes a verification operation.

18. The memory according to claim 17, characterized in that: A threshold voltage distribution range of the memory cells in the Nth programming state after the first programming operation is greater than a threshold voltage distribution range of the memory cells in the Nth programming state after the second programming operation.

19. A storage system, characterized in that: The storage system includes a controller and at least one memory coupled to the controller, wherein the controller is used to control the reading and writing of the memory, and the memory is the memory according to any one of claims 10-18.

20. An electronic device, characterized in that: The electronic device includes a processor and a storage system coupled to the processor, and the storage system is the storage system as claimed in claim 19.

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