Evaluation device for embedded storage unit of system on chip

Abstract

The invention provides an evaluation system for embedded storage units of a system-on-chip, and the evaluation system comprises a plurality of storage units which are respectively arranged in a plurality of corresponding systems-on-chip in an embedded manner; the evaluation function module is used for generating first evaluation signal data; the processor unit is used for controlling the evaluation function module to execute the evaluation program; when the evaluation function module executes the evaluation program, the first evaluation signal data is written into the plurality of storage units at the same time for evaluation; the first evaluation signal data is the evaluation signal data after speed increasing processing. The method can be used for evaluating the embedded storage units of a plurality of systems on chip at the same time, and the test time consumption can be greatly reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor chips, and in particular relates to a system-on-chip embedded storage unit evaluation device. Background Art

[0002] At present, with the development of design and manufacturing technology, integrated circuit design has developed from transistor integration to logic gate integration, and now to IP integration, that is, System on Chip (SoC) design technology. When designing a system on chip, it is necessary to effectively utilize its internal hardware resources (such as designing embedded storage units), thereby effectively reducing the development cost of electronic / information system products, shortening the development cycle, and improving product competitiveness. This is the most important product development method that the industry will adopt in the future. The embedded storage units of the system on chip can include: Read only Memory (ROM), Random Access Memory (RAM), Double Data Rate (DDR), etc. These storage units interact with the central processing unit (CPU) through a cache mechanism.

[0003] The purpose of chip evaluation is to discover defects generated during the wafer production process or assembly process through evaluation, and to remove defective products. In order to improve the efficiency of the chip evaluation operation process, the use of semiconductor integrated circuit automatic test equipment (Automatic Test Equipment, ATE) for evaluation has become a mainstream trend. However, there are still the following difficulties in the evaluation of embedded storage units in system-on-chip: 1. Dedicated embedded storage unit evaluation devices for system-on-chip are expensive and have single functions, and cannot be used for the evaluation of embedded storage units of multiple systems-on-chip at the same time; 2. The evaluation speed of existing embedded storage unit evaluation devices for system-on-chip is often restricted by the upper limit of the operating rate of the algorithm graphics generation unit in the semiconductor integrated circuit automatic test machine, which cannot meet the actual application requirements.

[0004] Therefore, there is an urgent need to provide a system-on-chip embedded storage unit evaluation device to solve at least one of the following technical problems: the dedicated system-on-chip embedded storage unit evaluation device in the prior art is relatively expensive and has a single function, and cannot be used for the evaluation of embedded storage units of multiple systems-on-chip at the same time; and the evaluation speed of the existing system-on-chip embedded storage unit evaluation device is often restricted by the upper limit of the operating rate of the algorithm graphic generation unit in the semiconductor integrated circuit automatic tester, and cannot meet the actual application requirements. Summary of the invention

[0005] In view of the technical problems that the dedicated on-chip embedded storage unit evaluation device in the prior art is expensive and has a single function, and cannot be used for the evaluation of embedded storage units of multiple on-chip systems at the same time; and the evaluation speed of the existing on-chip embedded storage unit evaluation device is often restricted by the upper limit of the operating rate of the algorithm graphic generation unit in the semiconductor integrated circuit automatic tester, and cannot meet the actual application needs, the present invention proposes a system-on-chip embedded storage unit evaluation device, in order to solve at least one of the above technical problems.

[0006] In a preferred embodiment of the present invention, a system for evaluating an embedded storage unit of a system on chip is provided, the evaluation system comprising:

[0007] A storage unit, wherein the storage unit is plural in number and the plural storage units are respectively embedded in the corresponding plural systems on chip;

[0008] An evaluation function module, the evaluation function module is used to generate first evaluation signal data;

[0009] A processor unit, the processor unit is used to control the evaluation function module to execute the evaluation program; wherein,

[0010] When the evaluation function module executes the evaluation program, the first evaluation signal data is simultaneously written into a plurality of the storage units for evaluation;

[0011] The first evaluation signal data is the evaluation signal data after speed increase processing.

[0012] Preferably, the evaluation function module includes:

[0013] A first functional unit, the first functional unit is used to generate first initial evaluation signal data required for evaluation, the first initial evaluation signal data includes a graphic analog signal, an address signal and a control signal, the control signal includes a clock signal, and the first initial evaluation signal data is in a serial mode;

[0014] A second functional unit, the second functional unit is used to receive and cache and control the sequence of the first initial evaluation signal data generated by the first functional unit, and convert the first initial evaluation signal data into a digital signal;

[0015] a third functional unit, the third functional unit being configured to receive the digital signal output by the second functional unit, and to increase the speed of the digital signal to obtain first evaluation signal data;

[0016] A fourth functional unit receives the first evaluation signal data and distributes the first evaluation signal data to the plurality of storage units via a plurality of pin drivers.

[0017] Preferably, the first functional unit is an algorithm graph generating unit, and the algorithm graph generating unit comprises:

[0018] A graphic simulation signal generating subunit, wherein the graphic simulation signal generating unit is used to generate a graphic simulation signal;

[0019] An address signal generating subunit, wherein the address signal generating unit is used to generate an address signal;

[0020] A control signal generating subunit, wherein the control signal generating unit is used to generate a control signal;

[0021] The instruction storage subunit is used to store program instructions generated by the graphic simulation signal, address signal and control signal.

[0022] Preferably, the second functional unit includes an A / D conversion subunit.

[0023] Preferably, the third functional unit is a speed increasing subunit, and the speed increasing subunit includes:

[0024] A first converter, which converts the first initial evaluation signal data in a serial mode into a parallel mode and outputs the data;

[0025] A large capacity storage device, wherein the large capacity storage device is used to store the first initial evaluation signal data in the parallel mode;

[0026] a second converter, wherein the second converter receives the clock signal from the first functional unit, increases the speed of the clock signal to a predetermined speed, and outputs the clock signal increased to the predetermined speed;

[0027] The third converter receives the clock signal increased in speed to a predetermined speed, reads the first initial evaluation signal data stored in the large-capacity storage in parallel, and converts the first initial evaluation signal data into the first initial evaluation signal data in serial form.

[0028] Compared with the prior art, the present invention can bring at least one of the following beneficial effects:

[0029] 1. The evaluation function module included in the system-on-chip embedded storage unit evaluation device of the present application is used to generate first evaluation signal data; when the evaluation function module executes the evaluation program, the first evaluation signal data is simultaneously written to a plurality of the storage units for evaluation, which can significantly improve the evaluation performance;

[0030] 2. The evaluation function module of the embedded storage unit evaluation device of a system on chip of the present application includes a first functional unit for generating first initial evaluation signal data required for evaluation, wherein the first initial evaluation signal data includes a graphic analog signal, an address signal and a control signal, wherein the control signal includes a clock signal, and the first initial evaluation signal data is in a serial mode, and the first initial evaluation signal data can better meet the evaluation requirements in actual scenarios;

[0031] 3. The third functional unit is used to receive the digital signal output by the second functional unit, and increase the speed of the digital signal to obtain the first evaluation signal data; the third functional unit is a speed increasing subunit, and the speed increasing subunit includes: a first converter, which converts the first initial evaluation signal data in the serial mode into a parallel mode and outputs it; a large-capacity storage device, which is used to store the first initial evaluation signal data in the parallel mode; a second converter, which receives the clock signal from the first functional unit, increases the speed of the clock signal to a predetermined speed, and outputs the clock signal increased to the predetermined speed; a third converter, which receives the clock signal increased to the predetermined speed, reads the first initial evaluation signal data stored in the large-capacity storage device in parallel, and converts it into the first initial evaluation signal data in serial form; this setting greatly improves the evaluation performance of the embedded storage unit of the on-chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and their implementation methods.

[0033] Figure 1 In one embodiment of the present invention, a system for evaluating an embedded storage unit of a system on chip is disclosed.

[0034] Figure 2 The schematic diagram is a principle block diagram of a first functional unit in a system on chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Various aspects of the present invention are described in further detail below.

[0036] Unless otherwise defined or indicated, all professional and scientific terms used herein have the same meanings as those familiar to those skilled in the art. In addition, any methods and materials similar or equivalent to those described herein can be applied to the method of the present invention.

[0037] Unless otherwise clearly specified and limited, the "or" mentioned in the present invention includes the relationship of "and". The "and" is equivalent to the Boolean logic operator "AND", the "or" is equivalent to the Boolean logic operator "OR", and "AND" is a subset of "OR".

[0038] It is to be understood that although the terms "first", "second", etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the first element may be referred to as the second element without departing from the teachings of the present invention.

[0039] In the present invention, the terms "consisting mainly of" and "consisting of" are included in the terms "containing", "including" or "comprising".

[0040] Unless otherwise clearly specified and limited, the terms "connected", "connected" and "connection" in the present invention should be understood in a broad sense, for example, it can be a fixed connection, or it can be connected through an intermediary medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0041] For example, if an element (or component) is referred to as being on, coupled to, or connected to another element, the element may be directly formed on, coupled to, or connected to the other element, or there may be one or more intervening elements between them. In contrast, if the expressions "directly on," "directly coupled to," and "directly connected to" are used herein, then no intervening elements are indicated. Other words used to describe the relationship between elements should be similarly interpreted, such as "between" and "directly between," "attached" and "directly attached," "adjacent" and "directly adjacent," and the like.

[0042] It should also be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings. The words "inner" and "outer" used refer to directions toward or away from the geometric center of a particular component, respectively. It can be understood that these terms are used here to describe the relationship of one element, layer or region relative to another element, layer or region as shown in the drawings. In addition to the orientations described in the drawings, these terms should also include other orientations of the device.

[0043] Other aspects of the present invention will be apparent to those skilled in the art in view of the disclosure herein.

[0044] See attached Figure 1-2 The present invention provides an evaluation system for an embedded storage unit of a system on chip, the evaluation system comprising:

[0045] A storage unit 110, wherein the storage unit 110 is plural in number and the plural storage units 110 are respectively embedded in the corresponding plural systems on chip;

[0046] An evaluation function module 120, wherein the evaluation function module 120 is used to generate first evaluation signal data;

[0047] The processor unit 130 is used to control the evaluation function module to execute the evaluation program; wherein,

[0048] When the evaluation function module 120 executes the evaluation program, the first evaluation signal data is simultaneously written into the plurality of storage units 110 for evaluation;

[0049] The first evaluation signal data is the evaluation signal data after speed increase processing;

[0050] described.

[0051] It should be noted that the storage unit 110 is selected from any one of a read-only memory, a random access memory, and a double rate synchronous dynamic random access memory.

[0052] As a preferred implementation, the evaluation function module includes:

[0053] A first functional unit 121, the first functional unit 121 is used to generate first initial evaluation signal data required for evaluation, the first initial evaluation signal data includes a graphic analog signal, an address signal and a control signal, the control signal includes a clock signal, and the first initial evaluation signal data is in a serial mode;

[0054] A second functional unit 122, the second functional unit 122 is used to receive and cache and control the sequence of the first initial evaluation signal data generated by the first functional unit 121, and convert the first initial evaluation signal data into a digital signal;

[0055] A third functional unit 123, the third functional unit 123 is used to receive the digital signal output by the second functional unit 122, and increase the speed of the digital signal to obtain first evaluation signal data;

[0056] The fourth functional unit 124 receives the first evaluation signal data, and distributes the first evaluation signal data to the plurality of storage units via the plurality of pin drivers 125 .

[0057] As a preferred embodiment, the first functional unit 121 is an algorithm graph generating unit, and the algorithm graph generating unit includes:

[0058] A graphic analog signal generating subunit 1211, wherein the graphic analog signal generating subunit 1211 is used to generate a graphic analog signal, wherein the graphic analog signal is a write data graphic;

[0059] An address signal generating subunit 1212, wherein the address signal generating unit 1212 has a logic circuit composed of row and column address generators for generating address signals;

[0060] A control signal generating subunit 1213, wherein the control signal generating subunit 1213 is used to generate control signals, wherein the control signals are read / write signals, chip select signals and enable signals for evaluation;

[0061] The instruction storage subunit 1214 is used to store program instructions generated by the graphic simulation signal, address signal, and control signal.

[0062] As a preferred implementation, the second functional unit 122 includes an A / D conversion subunit.

[0063] As a preferred implementation, the third functional unit 123 is a speed increasing subunit, and the speed increasing subunit 123 includes:

[0064] A first converter, which converts the first initial evaluation signal data in a serial mode into a parallel mode and outputs the data;

[0065] A large capacity storage device, wherein the large capacity storage device is used to store the first initial evaluation signal data in the parallel mode;

[0066] a second converter, wherein the second converter receives the clock signal from the first functional unit, increases the speed of the clock signal to a predetermined speed, and outputs the clock signal increased to the predetermined speed;

[0067] The third converter receives the clock signal increased in speed to a predetermined speed, reads the first initial evaluation signal data stored in the large-capacity storage in parallel, and converts the first initial evaluation signal data into the first initial evaluation signal data in serial form.

[0068] Based on this application, it should be understood by those skilled in the art that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0069] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

[0070] All documents mentioned in the present invention are cited as references in this application, just as each document is cited as reference separately. In addition, it should be understood that after reading the above content of the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the claims attached to this application.

Claims

1. A system for evaluating an embedded storage unit on a system on a chip, characterized in that: The evaluation system comprises: A storage unit, wherein the storage unit is plural in number and the plural storage units are respectively embedded in the corresponding plural systems on chip; An evaluation function module, the evaluation function module is used to generate first evaluation signal data; A processor unit, the processor unit is used to control the evaluation function module to execute the evaluation program; wherein, When the evaluation function module executes the evaluation program, the first evaluation signal data is simultaneously written into a plurality of the storage units for evaluation; The first evaluation signal data is the evaluation signal data after speed increase processing.

2. The evaluation system for an embedded storage unit of a system on chip as claimed in claim 1, characterized in that: The evaluation function module includes: A first functional unit, the first functional unit is used to generate first initial evaluation signal data required for evaluation, the first initial evaluation signal data includes a graphic analog signal, an address signal and a control signal, the control signal includes a clock signal, and the first initial evaluation signal data is in a serial mode; A second functional unit, the second functional unit is used to receive and cache and control the sequence of the first initial evaluation signal data generated by the first functional unit, and convert the first initial evaluation signal data into a digital signal; a third functional unit, the third functional unit being configured to receive the digital signal output by the second functional unit, and to increase the speed of the digital signal to obtain first evaluation signal data; A fourth functional unit receives the first evaluation signal data and distributes the first evaluation signal data to the plurality of storage units via a plurality of pin drivers.

3. The evaluation system for an embedded storage unit of a system on chip as claimed in claim 2, characterized in that: The first functional unit is an algorithm graph generating unit, and the algorithm graph generating unit includes: A graphic simulation signal generating subunit, wherein the graphic simulation signal generating unit is used to generate a graphic simulation signal; An address signal generating subunit, wherein the address signal generating unit is used to generate an address signal; A control signal generating subunit, wherein the control signal generating unit is used to generate a control signal; The instruction storage subunit is used to store program instructions generated by the graphic simulation signal, address signal and control signal.

4. The evaluation system for an embedded storage unit of a system on chip as claimed in claim 3, characterized in that: The second functional unit includes an A / D conversion subunit.

5. The evaluation system for an embedded storage unit of a system on chip as claimed in claim 4, characterized in that: The third functional unit is a speed increasing subunit, and the speed increasing subunit includes: A first converter, which converts the first initial evaluation signal data in a serial mode into a parallel mode and outputs the data; A large capacity storage device, wherein the large capacity storage device is used to store the first initial evaluation signal data in the parallel mode; a second converter, wherein the second converter receives the clock signal from the first functional unit, increases the speed of the clock signal to a predetermined speed, and outputs the clock signal increased to the predetermined speed; The third converter receives the clock signal increased in speed to a predetermined speed, reads the first initial evaluation signal data stored in the large-capacity storage in parallel, and converts the first initial evaluation signal data into the first initial evaluation signal data in serial form.

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