MOSFET device with semi-super junction structure and manufacturing method thereof

Abstract

The invention relates to an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a semi-super junction structure and a manufacturing method thereof, and the method comprises the following steps: providing a substrate, and sequentially forming an N-type layer, a P-type layer and a source region layer doped with an N-type material on the substrate from bottom to top; etching a first groove penetrating through the N-type layer, the P-type layer and the source region layer; injecting a P-type material along the first groove so as to form a first P column in the substrate; etching a second groove penetrating through the source region layer; and injecting a P-type material along the second groove to form a second P column penetrating through the substrate and the N-type layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular, to a MOSFET device with a semi-superjunction structure and a method for manufacturing the same. Background Art

[0002] Modern power electronic devices are developing towards high power density and high efficiency. Silicon carbide (SiC) power devices have developed rapidly in the field of high-efficiency power conversion in recent years due to their excellent device characteristics such as high voltage, high frequency, high temperature and high power density.

[0003] Structurally, silicon carbide MOSFETs are available in two types: planar and trench. Trench power MOSFET devices have the advantages of high integration, low on-resistance, fast switching speed, and low switching loss, and have almost completely replaced planar power MOSFET devices in the low-voltage and high-voltage fields, becoming the mainstream of related applications.

[0004] However, with the wide expansion of application fields and the continuous improvement of equipment performance, people's demand for trench power MOSFET devices with lower on-resistance is also increasing. As a structure that effectively reduces the electric field and improves the withstand voltage, the superjunction structure can obtain lower gate oxide layer electric field strength and lower on-resistance if applied to trench power MOSFET.

[0005] In view of this, it is necessary to provide an improved MOSFET device. Summary of the invention

[0006] The embodiments of the present application provide a MOSFET device with a semi-super junction structure and a method for manufacturing the same, for improving the voltage withstand characteristics of the device.

[0007] According to one aspect of the present application, a method for manufacturing a MOSFET device with a semi-super junction structure is provided, the method comprising the following steps: providing a substrate, and sequentially forming an N-type layer, a P-type layer, and a source layer doped with N-type material on the substrate from bottom to top; etching a first groove penetrating the N-type layer, the P-type layer, and the source layer; injecting P-type material along the first groove to form a first P column in the substrate; etching a second groove penetrating the source layer; and injecting P-type material along the second groove to form a second P column penetrating the substrate and the N-type layer.

[0008] In some embodiments of the present application, optionally, forming an N-type layer, a P-type layer, and a source region layer doped with N-type material in sequence from bottom to top on the substrate includes: injecting N-type material within a first depth range in the substrate to form the N-type layer; injecting P-type material into the portion of the N-type layer above a second depth to inversely form the P-type layer reaching the upper surface of the substrate; and injecting N-type material into the portion of the P-type layer above a third depth to form the source region layer.

[0009] In some embodiments of the present application, optionally, etching a first groove passing through the N-type layer, the P-type layer and the source layer includes: depositing a hard mask layer above the source layer; etching the hard mask layer to form a first pattern; and etching the source layer, the P-type layer, and the N-type layer according to the first pattern to form the first groove.

[0010] In some embodiments of the present application, optionally, etching a second groove passing through the source layer includes: depositing a silicon dioxide layer on the surface of the first groove, and spin-coating a photoresist material to cover the silicon dioxide layer and the hard mask layer; exposing the photoresist material to remove a portion thereof to form a second pattern; etching the silicon dioxide layer according to the second pattern to form the second groove; and removing the remaining portion of the photoresist material.

[0011] In some embodiments of the present application, optionally, the method also includes the following steps: removing the silicon dioxide layer on the surface of the first groove; sputtering a carbon film and activating annealing; removing the carbon film; growing gate oxide and depositing polysilicon in the first groove; removing the polysilicon on the source layer; depositing silicon dioxide on the source layer; etching the silicon dioxide and the P-type layer above the second groove to form a contact hole entering the P-type layer; depositing a tungsten plug in the contact hole; and depositing a metal layer to lead out an electrode.

[0012] In some embodiments of the present application, optionally, the doping concentration of the N-type layer is lower than the doping concentration of the P-type layer, and the doping concentration of the P-type layer is lower than the doping concentration of the source region layer.

[0013] In some embodiments of the present application, optionally, the width of the first P-pillar at its narrowest point is smaller than the width of the second P-pillar at its narrowest point.

[0014] In some embodiments of the present application, optionally, a depth of the first P column is greater than a depth of the second P column.

[0015] In some embodiments of the present application, optionally, injecting P-type material along the first trench includes: injecting P-type material along the first trench at a predetermined angle relative to perpendicular to the precipitate, so that the first P column has a structure that is wide at the top and narrow at the bottom.

[0016] In some embodiments of the present application, optionally, injecting P-type material along the first groove includes: injecting P-type material along the first groove at a predetermined angle relative to perpendicular to the precipitation to form a first portion of the first P column; and injecting P-type material along the first groove from a vertical direction to form a second portion of the first P column.

[0017] In some embodiments of the present application, optionally, the doping concentration of the first P column, the doping concentration of the second P column, and the doping concentration of the N-type layer are substantially equal.

[0018] In some embodiments of the present application, optionally, the substrate material includes SiC, the N-type material includes a P element, and / or the P-type material is metal Al.

[0019] According to another aspect of the present application, a MOSFET device with a semi-super junction structure is provided, comprising at least one transistor unit, wherein the transistor unit comprises: a substrate and an N-type layer, a P-type layer and a source region layer doped with N-type material formed thereon in sequence from bottom to top; a first P column located in the substrate; and a second P column passing through the substrate and the N-type layer.

[0020] In some embodiments of the present application, optionally, the width of the first P-pillar at its narrowest point is smaller than the width of the second P-pillar at its narrowest point.

[0021] In some embodiments of the present application, optionally, a depth of the first P column is greater than a depth of the second P column.

[0022] In some embodiments of the present application, optionally, the first P-pillar has a structure that is wide at the top and narrow at the bottom.

[0023] In some embodiments of the present application, optionally, the doping concentration of the first P column, the doping concentration of the second P column, and the doping concentration of the N-type layer are substantially equal.

[0024] According to another aspect of the present application, a MOSFET device having a semi-super junction structure is provided, wherein the MOSFET device is manufactured according to any one of the methods described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects and advantages of the present application will become more fully apparent from the following detailed description in conjunction with the accompanying drawings, wherein the same or similar elements are represented by the same reference numerals.

[0026] Figure 1 A method for manufacturing a MOSFET device having a semi-super junction structure according to an embodiment of the present application is shown;

[0027] Figure 2 A MOSFET device with a semi-super junction structure according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] For the purpose of brevity and illustration, the principles of the present application are described herein mainly with reference to its exemplary embodiments. However, those skilled in the art will readily recognize that the same principles are equally applicable to all types of MOSFET devices having a semi-superjunction structure and methods of manufacturing the same, and that the same or similar principles may be implemented therein, and any such changes do not depart from the true spirit and scope of the present application.

[0029] According to one aspect of the present application, a method for manufacturing a MOSFET device with a semi-super junction structure is provided. The manufacturing method deposits P columns at two different locations to improve the voltage resistance characteristics of the MOSFET device. Specifically, the manufacturing method includes the following steps: providing a substrate 101, and sequentially forming an N-type layer 102, a P-type layer 103, and a source layer 104 doped with an N-type material on the substrate 101 from bottom to top; etching a first groove 106 penetrating the N-type layer 102, the P-type layer 103, and the source layer 104; injecting a P-type material along the first groove 106 to form a first P column 111 in the substrate 101; etching a second groove 110 penetrating the source layer 104; and injecting a P-type material along the second groove 110 to form a second P column 112 penetrating the substrate 101 and the N-type layer 102. Two P column structures can be formed through the above steps of the manufacturing method. In addition, as will be described in detail below, when the first P column 111 and the second P column 112 are formed by ion beam implantation with equal energy, the implantation depth of the first P column 111 will be deeper overall due to the influence of the trench depth.

[0030] like Figure 1 As shown, a substrate 101 is first provided, and then a plurality of transistor units can be formed on the substrate 101. Figure 1 As shown in a-1c, an N-type layer 102, a P-type layer 103 and a source layer 104 doped with an N-type material may be sequentially formed from bottom to top on a substrate 101. In some embodiments of the present application, the substrate 101 may be mainly composed of SiC, while the N-type material is the P element and the P-type material is metal Al.

[0031] In some embodiments of the present application, the N-type layer 102, the P-type layer 103 and the source layer 104 doped with the N-type material are sequentially formed from bottom to top on the substrate 101, including the following processes: (1) Figure 1 As shown in a, firstly, N-type material is implanted into a first depth range in the substrate 101 to form an N-type layer 102. (2) Figure 1 As shown in FIG. 2 , a P-type material is injected into the portion of the N-type layer 102 above the second depth to invert and form a P-type layer 103 reaching the upper surface of the substrate 101. For example, a bulk Al injection can be performed. Specifically, multiple injections can be used to invert the SiC above the JFET into a P-type layer. (3) Figure 1 As shown in Fig. 3, N-type material is injected into the portion above the third depth of the P-type layer 103 to form a source layer 104. The first depth, second depth, and third depth here are intended to distinguish different objects to be processed (substrate 101, N-type layer 102, and P-type layer 103, respectively), and do not mean that there must be a difference in the values. The depth in this article is based on the surface of the device to be processed / being processed.

[0032] Then, the first trench 106 and the second trench 110 may be etched in sequence. Figure 1 d-1f to etch the first trench 106 penetrating the N-type layer 102, the P-type layer 103 and the source layer 104. In some embodiments of the present application, specifically, etching the first trench 106 penetrating the N-type layer 102, the P-type layer 103 and the source layer 104 includes the following process: (1) First, as shown in Figure 1 As shown in FIG. d, a hard mask layer 105 may be deposited on the source layer 104. For example, a hard mask layer may be formed by depositing silicon dioxide, thereby facilitating the formation of the groove shape. (2) Secondly, as Figure 1 As shown in FIG. 5 , the hard mask layer 105 can be etched to form a first pattern. For example, a specific pattern can be engraved on the hard mask layer 105 by a high-energy ultraviolet laser beam, and the etched portion will be able to pass through the plasma, while the remaining portion will not allow the ion beam to pass through. (3) Finally, as shown in FIG. Figure 1 As shown in FIG. 5 , plasma can be used to etch the source layer 104, the P-type layer 103, and the N-type layer 102 according to the first pattern to form the first trench 106. The above process will realize the pattern designed according to the first trench 106 as the first trench 106, thereby realizing the transfer from the pattern to the trench.

[0033] Then, if Figure 1 As shown in g-1j, a second trench 110 penetrating the source layer 104 may be etched. In some embodiments of the present application, specifically, etching the second trench 110 penetrating the source layer 104 includes: (1) first, as shown in Figure 1 As shown in FIG. 6 , a silicon dioxide layer 108 is deposited on the surface of the first trench 106 (for example, silicon dioxide can be deposited by low pressure chemical vapor deposition). (2) Next, as shown in FIG. Figure 1As shown in FIG. 1 , a photoresist material 109 is spin-coated on the surface to cover the silicon dioxide layer 108, the hard mask layer 105, etc. (3) Again, as shown in FIG. Figure 1 As shown in FIG. 1 , the photoresist material 109 is exposed to light to remove a portion thereof, thereby forming a second pattern. (4) Finally, as shown in FIG. Figure 1 As shown in FIG. 1 , the silicon dioxide layer 108 is etched according to the second pattern to form a second groove 110. The above process will realize the pattern designed according to the second groove 110 as the second groove 110, thereby realizing the transfer from the pattern to the groove. Figure 1 As shown in FIG. 1 , the remaining portion of the photoresist material 109 can also be removed to facilitate subsequent processing.

[0034] According to the above two parts, the first trench 106 and the second trench 110 can be formed respectively. Subsequently, P-type material can be injected through the first trench 106 and the second trench 110 to form a first P column 111 under the first trench 106 and a second P column 112 under the second trench 110 respectively.

[0035] Specifically, if Figure 1 1, a P-type material may be implanted along the first trench 106 to form a first P column 111 in the substrate 101. At the same time, a P-type material may be implanted along the second trench 110 to form a second P column 112 penetrating the substrate 101 and the N-type layer 102. The two P columns may be formed by the same ion beam implantation.

[0036] Specifically, in some embodiments of the present application, the injection of the P-type material along the first trench 106 may include the following process: the P-type material is injected along the first trench 106 at a predetermined angle relative to the vertical direction of the deposition, so that the first P column 111 is wide at the top and narrow at the bottom. Considering the concentration distribution of the P column area, multiple injections may be used.

[0037] In some embodiments of the present application, injecting the P-type material along the first trench 106 may include the following process: injecting the P-type material along the first trench 106 at a predetermined angle relative to the vertical direction to form a first portion of the first P column 111; and injecting the P-type material from a vertical direction along the first trench 106 to form a second portion of the first P column 111. In this way, a P column region may be formed in which the first portion is a structure that is wide at the top and narrow at the bottom, and the second portion is a structure of equal width.

[0038] Furthermore, in some embodiments of the present application, the width of the narrowest portion of the first P-pillar 111 is smaller than the width of the narrowest portion of the second P-pillar 112 .

[0039] In some embodiments of the present application, the method further includes the following steps, which can be implemented in the order of the numbers shown in the figure: Figure 1As shown in FIG. 1 , the silicon dioxide layer 108 on the surface of the first trench 106 can be removed by wet method; Figure 1 As shown in n, a carbon film 114 is sputtered on the surface and activated annealing; Figure 1 As shown in o, remove the carbon film 114; Figure 1 As shown in p, gate oxide is grown in the first trench 106 and polysilicon 115 is deposited; Figure 1 As shown in FIG. q, the polysilicon on the source layer 104 is removed, thereby etching the gate poly back to the gate oxide surface; Figure 1 As shown in r, silicon dioxide 116 is deposited on the source region layer 104; Figure 1 As shown in FIG. 5 , the silicon dioxide and the P-type layer 103 are etched on the second trench 110 to form a contact hole 117 that enters the P-type layer 103; Figure 1 As shown in FIG. 1 , a tungsten plug 118 is deposited in the contact hole 117; Figure 1 As shown in Fig. 1, a metal layer 119 is deposited on the surface for extracting electrodes.

[0040] In some embodiments of the present application, the doping concentration of the N-type layer 102 is lower than the doping concentration of the P-type layer 103, and the doping concentration of the P-type layer 103 is lower than the doping concentration of the source layer 104. In addition, in some embodiments of the present application, the doping concentration of the first P column 111, the doping concentration of the second P column 112, and the doping concentration of the N-type layer 102 are substantially equal.

[0041] Due to the different trench depths, when implanted with ion beams of the same energy, the depths of the first P column 111 and the second P column 112 will be different. Therefore, in some embodiments of the present application, the depth of the first P column 111 is greater than that of the second P column 112.

[0042] The MOSFET device with a semi-superjunction structure manufactured by the above manufacturing method forms a trapezoidal electric field in the drift region when the device is subjected to reverse withstand voltage, which greatly increases the device breakdown voltage and reduces the on-resistance. In addition, the introduction of the P column region forms a depletion region that wraps the gate oxide layer when the device is subjected to reverse withstand voltage, effectively reducing the electric field in the gate oxide, improving the reliability of the device and expanding its application scenarios. The P injection region can form a charge balance with the N-type layer, which can reduce the impact of the N-type layer injection on the breakdown voltage and improve the product process and performance window. The injection of the above P column region adopts a self-aligned process, which can effectively improve the process window. On the other hand, by utilizing the charge balance between the P injection region and the epitaxial layer, the resistivity of the drift region can be greatly reduced, and the on-resistance of the device can be reduced.

[0043] According to another aspect of the present application, a MOSFET device with a semi-super junction structure is provided, including at least one transistor unit, the transistor unit including: a substrate 101 and an N-type layer 102, a P-type layer 103 and a source region layer 104 doped with N-type material formed thereon from bottom to top; a first P column 111, which is located in the substrate 101; and a second P column 112, which penetrates the substrate 101 and the N-type layer 102.

[0044] In some embodiments of the present application, the width of the narrowest part of the first P-pillar 111 is smaller than the width of the narrowest part of the second P-pillar 112 .

[0045] In some embodiments of the present application, the depth of the first P-pillar 111 is greater than the depth of the second P-pillar 112 .

[0046] In some embodiments of the present application, the first P-pillar 111 has a structure that is wide at the top and narrow at the bottom.

[0047] In some embodiments of the present application, the doping concentration of the first P column 111 , the doping concentration of the second P column 112 , and the doping concentration of the N-type layer 102 are substantially equal.

[0048] like Figure 2 As shown in Figures 2a and 2b, there is a P column region below the trench and the body junction, and the hole concentration in the P column region is equivalent to the electron concentration in the drift region. For the convenience of research, only half of the P column region is used for illustration below. It should be understood that the following conclusions also apply to the other half of the P column region.

[0049] like Figure 2 As shown in a, regions a and b are P-type doped regions, and c and d are n-type doped regions. The hole concentration in regions a and b is equivalent to the electron concentration in regions c and d. When the entire device is subjected to reverse withstand voltage, it is completely depleted, forming a charge balance, thereby improving the device withstand voltage.

[0050] In addition, the width of region b is greater than that of region a, and region b is grounded through a body junction.

[0051] During reverse withstand voltage, region b is more easily depleted, and the depletion region expands to both sides, eventually connecting region a to form a space charge region. As described in detail above, the width of region a is determined by the trench width and the deposited oxide layer. Region a can be implanted at an angle to protect the gate oxide at the bottom of the trench and form a wide implant region at the top. Region a is a P-type floating region.

[0052] like Figure 2As shown in Figures 2a and 2b, the depth of region a (floating) is greater than that of region b (grounded), which is determined by the different thicknesses of the injection barrier layer. After power is turned on, a wave effect will be formed between region a and region b. By using the charge balance between the P injection region and the epitaxial layer, the resistivity of the drift region can be greatly reduced, and the on-resistance of the device can be reduced.

[0053] According to another aspect of the present application, a MOSFET device having a semi-super junction structure is provided, wherein the MOSFET device is manufactured according to any one of the methods described above.

[0054] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Those skilled in the art can think of other feasible changes or substitutions based on the technical scope disclosed in the present application, and such changes or substitutions are all included in the protection scope of the present application. In the absence of conflict, the implementation modes of the present application and the features in the implementation modes can also be combined with each other. The protection scope of the present application shall be subject to the description of the claims.

Claims

1. A method for manufacturing a MOSFET device having a semi-super junction structure, characterized in that: The method comprises: Providing a substrate, and sequentially forming an N-type layer, a P-type layer, and a source region layer doped with an N-type material on the substrate from bottom to top; Etching a first trench penetrating the N-type layer, the P-type layer and the source region layer; Injecting a P-type material along the first trench to form a first P column in the substrate; Etching a second trench penetrating the source region layer; and A P-type material is implanted along the second trench to form a second P-column penetrating the substrate and the N-type layer.

2. The method according to claim 1, wherein: Forming an N-type layer, a P-type layer, and a source region layer doped with an N-type material on the substrate in sequence from bottom to top includes: Implanting N-type material within a first depth range in the substrate to form the N-type layer; Implanting a P-type material into a portion of the N-type layer above the second depth to inversely form the P-type layer reaching the upper surface of the substrate; and An N-type material is implanted into a portion of the P-type layer above the third depth to form the source region layer.

3. The method according to claim 1, wherein: Etching a first trench that penetrates the N-type layer, the P-type layer, and the source region layer includes: depositing a hard mask layer over the source region layer; etching the hard mask layer to form a first pattern; and The source region layer, the P-type layer, and the N-type layer are etched according to the first pattern to form the first trench.

4. The method according to claim 3, wherein: Etching a second trench penetrating the source region layer comprises: Depositing a silicon dioxide layer on the surface of the first groove, and spin coating a photoresist material to cover the silicon dioxide layer and the hard mask layer; exposing the photoresist material to remove a portion thereof, thereby forming a second pattern; etching the silicon dioxide layer according to the second pattern to form the second groove; and The remaining portion of the photoresist material is removed.

5. The method according to claim 4, further comprising: removing the silicon dioxide layer on the surface of the first trench; sputtering a carbon film on the surface and activating annealing; removing the carbon film; growing gate oxide and depositing polysilicon in the first trench; removing the polysilicon on the source region layer; depositing silicon dioxide on the source region layer; Etching the silicon dioxide and the P-type layer on the second trench to form a contact hole entering the P-type layer; depositing a tungsten plug in the contact hole; as well as A metal layer is deposited on the surface for extraction electrodes.

6. The method according to claim 1, wherein: The doping concentration of the N-type layer is lower than the doping concentration of the P-type layer, and the doping concentration of the P-type layer is lower than the doping concentration of the source region layer.

7. The method according to claim 1, wherein: The width of the first P-pillar at its narrowest point is smaller than the width of the second P-pillar at its narrowest point.

8. The method according to claim 1, wherein: The depth of the first P pillar is greater than the depth of the second P pillar.

9. The method according to claim 1, wherein: Injecting the P-type material along the first trench includes: injecting the P-type material along the first trench at a predetermined angle relative to perpendicularity to the precipitate, so that the first P column has a structure that is wide at the top and narrow at the bottom.

10. The method according to claim 1, wherein: Implanting a P-type material along the first trench includes: injecting a P-type material along the first trench at a predetermined angle relative to perpendicularity to the precipitate to form a first portion of the first P column; and A P-type material is implanted along the first trench from a vertical direction to form a second portion of the first P column.

11. The method according to claim 1, wherein: The doping concentration of the first P column, the doping concentration of the second P column, and the doping concentration of the N-type layer are substantially equal.

12. The method according to claim 1, wherein: The substrate material includes SiC, the N-type material includes a P element, and / or the P-type material is metal Al.

13. A MOSFET device having a semi-super junction structure, comprising at least one transistor unit, characterized in that: The transistor unit comprises: A substrate and an N-type layer, a P-type layer and a source region layer doped with an N-type material formed thereon in sequence from bottom to top; A first P column located in the substrate; and A second P column runs through the substrate and the N-type layer; wherein, Optionally, the width of the first P-pillar at its narrowest point is smaller than the width of the second P-pillar at its narrowest point. Optionally, a depth of the first P-pillar is greater than a depth of the second P-pillar. Optionally, the first P-pillar has a structure that is wide at the top and narrow at the bottom. Optionally, the doping concentration of the first P column, the doping concentration of the second P column, and the doping concentration of the N-type layer are substantially equal.

14. A MOSFET device having a semi-superjunction structure, characterized in that: The MOSFET device is manufactured according to the method according to any one of claims 1 to 12.

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