Semiconductor structure
By using locally inserted oxides or other materials to form the SOZ structure, the problem of high cost of silicon overlay technology and easy cracking of thin wafers is solved, and cost reduction and performance improvement are achieved.
Patent Information
- Application Number
- CN202410856744.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-28
- Filing Date
- 2024-06-28
- Publication Date
- 2024-12-31
AI Technical Summary
Due to the high cost of insulating silicon overlay technology, the existing insulating layer is difficult to meet the requirements of Moore's Law for cost reduction per bit, and thin silicon wafers are prone to rupture or breaking in the assembly process.
Using local insertion of different materials (such as oxides, tungsten or diamonds) to form the SOZ structure, as the insulating layer and conductive layer of the semiconductor island, replaces the traditional entire insulating layer with silicon wafers, improves the conductivity and thermal conductivity, and chemically Mechanical planarization and other processes achieve thinning.
It reduces the production cost of semiconductor structures, improves conductivity and thermal conductivity, enhances the mechanical support of thinner wafers, avoids cracking or fracture problems, and achieves the high-performance advantage of silicon overlay technology with insulating layer.
Smart Images
Figure CN119230477A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure that realizes insulation or function by using a cheaper bulk silicon wafer substrate instead of a more expensive whole silicon on insulator (SOI) wafer. Background Art
[0002] The current silicon integrated circuit (IC) industry can integrate more than billions of transistors in a silicon die. Most integrated circuits are built in wafers of "bulk" silicon substrates. The term bulk usually means that a common silicon substrate material is used to accommodate all transistors manufactured by a single manufacturing method, and the transistor bodies are usually connected and biased at a common substrate voltage (for example, an N-type metal-oxide-semiconductor field effect transistor (MOSFET) in the p-well of the bulk silicon substrate and a P-type metal-oxide-semiconductor field effect transistor in the n-well of the bulk silicon substrate).
[0003] In contrast to the use of the bulk silicon substrate, there is a so-called silicon on insulator (SOI) substrate. The most advanced SOI transistors are manufactured based on a silicon substrate of a pre-prepared entire SOI wafer for certain special applications. Because SOI transistors are more expensive than transistors manufactured in the bulk silicon substrate, where the bulk silicon substrate is connected to the entire bulk silicon wafer, and the bulk silicon wafer is more commonly used in the manufacture of most integrated circuits, the main disadvantage of SOI transistor technology is that the cost of each transistor manufactured in the SOI wafer is much higher than the cost of each transistor manufactured in the bulk silicon wafer, resulting in the cost reduction of each generation of SOI transistors being difficult to meet the strict requirements of Moore's Law for cost reduction per bit. Therefore, the existing SOI technology has not become a mainstream commodity process technology, in which the mainstream commodity process technology has always been dominated by bulk silicon substrate technology. However, due to the high performance advantages of SOI technology in some special applications (such as high frequency, low noise, radiation-resistant or microwave equipment), SOI technology is still needed.
[0004] Several new methods for preparing whole-on-insulator silicon wafers have been developed in the prior art, such as (1) bonding two silicon wafers together, each of which has a bulk silicon substrate covered with silicon dioxide on its surface, and then flipping one silicon wafer onto the other silicon wafer, and the two silicon wafers are well connected due to the mutual bonding force between the silicon dioxide molecules, resulting in a layer of oxide sandwiched between the two oxide-covered silicon wafers. Then one of the silicon wafers is ground to a specific thickness to form a silicon-on-insulator wafer with a single crystal silicon layer on the oxide layer on the silicon wafer as a substrate carrier, or (2) another method for forming a whole-on-insulator silicon wafer is to implant oxide atoms into the surface of the silicon wafer and use heat treatment to form an embedded silicon dioxide layer, that is, because the implanted oxide layer is embedded in the original silicon wafer, a silicon film is formed on the silicon dioxide layer. Both of the above methods can be used to manufacture whole-on-insulator silicon wafers, but the cost is much higher than using bulk silicon wafers, especially for silicon wafers with large sizes (such as 8 inches or 12 inches). Well-known silicon processes can then create metal oxide semiconductor field effect transistors and even bipolar complementary metal oxide semiconductor field effect transistors (BiCMOS) in an entire silicon-on-insulator wafer.
[0005] For bulk silicon and silicon-on-insulator technologies, a silicon wafer is used as the basic carrier material, which is biased to ground voltage for p-type wafers or positive supply voltage for n-type wafers. In addition, for better conductivity, the back side of the silicon wafer is polished, and then some metal layers are placed on the back side of the silicon wafer.
[0006] In recent years, there is an urgent need to make silicon wafers thinner through some special "thinning technologies" after the integrated circuit process is completed. For example, the thickness of the original silicon wafer may be about 300 to 500 microns, while the thinned silicon wafer can be as thin as 50 microns. However, the challenge of thinning silicon wafers is how to prevent cracking or breaking during the subsequent assembly / packaging process.
[0007] Therefore, the present invention discloses a method of constructing a heterogeneous wafer substrate with different materials other than silicon, thereby creating the term "SOZ" by using "Z" as a representative term for special materials to describe its general characteristics. For example, if silicon-on-insulator requires oxide as the substrate of the transistor, the present invention calls SOZ=SOI. But Z can be a conductive material (such as a metal such as tungsten) to provide some high-demand special functions (such as higher conductivity, higher thermal conductivity and stronger support for thinned wafer substrates), or an insulator like diamond to provide higher thermal conductivity and mechanical support for thinned wafer substrates. Another new inventive feature of the present invention is that this Z material is inserted below the original surface of the silicon substrate in a locally formed manner, rather than using the entire silicon wafer. For example, SOZ (Z=oxide) is suitable for a single transistor without the need to use an expensive entire silicon-on-insulator wafer in the most advanced silicon-on-insulator technology. Therefore, SOZ starts with a bulk silicon wafer and then forms local SOZ transistors (such as SOI devices, SO-tungsten or SO-diamond devices), but other devices can still take the form of bulk transistors with a common connection substrate or be used as deep junction-type electrostatic discharge protection devices, etc. Summary of the invention
[0008] One embodiment of the present invention discloses a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a semiconductor island, a shallow trench isolation (STI) region, a first buried layer, and a second buried layer. The semiconductor substrate has an original surface. The semiconductor island is formed based on the semiconductor substrate. The shallow trench isolation (STI) region surrounds the semiconductor island. The first buried layer is a localized layer below the semiconductor island, and the material of the first buried layer is different from the material of the semiconductor substrate. The second buried layer is a localized layer below the first buried layer, and the material of the second buried layer is different from the material of the semiconductor substrate.
[0009] In one embodiment of the present invention, a material of the second buried layer is different from a material of the first buried layer.
[0010] In one embodiment of the present invention, the first buried layer is a buried insulating layer, and the second buried layer is a metal-containing layer.
[0011] In one embodiment of the present invention, the first buried insulating layer includes a thermal oxide layer and a deposited dielectric layer, and the bottom surface of the semiconductor island is completely isolated by the first buried insulating layer.
[0012] In one embodiment of the present invention, the semiconductor structure further comprises a vertically extended dielectric layer, wherein the vertically extended dielectric layer surrounds the sidewalls of the semiconductor island.
[0013] In one embodiment of the present invention, the thermal conductivity of the second buried layer is higher than the thermal conductivity of the semiconductor substrate.
[0014] Another embodiment of the present invention discloses a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a semiconductor island, a shallow trench isolation region and a buried layer. The semiconductor substrate has an original surface. The semiconductor island is formed based on the semiconductor substrate. The shallow trench isolation region surrounds the semiconductor island. The buried layer is below the semiconductor island, wherein the thermal conductivity of the buried layer is higher than the thermal conductivity of the semiconductor substrate.
[0015] In one embodiment of the present invention, the buried layer is a metal-containing layer.
[0016] In one embodiment of the present invention, the buried layer includes a first portion extending into the shallow trench isolation region.
[0017] In one embodiment of the present invention, the shallow trench isolation region includes an oxide layer below the first portion of the buried layer.
[0018] In one embodiment of the present invention, the shallow trench isolation region includes a dielectric layer above the first portion of the buried layer.
[0019] Another embodiment of the present invention discloses a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a semiconductor island, a shallow trench isolation region and a buried layer. The semiconductor substrate has an original surface. The semiconductor island is formed based on the semiconductor substrate. The shallow trench isolation region surrounds the semiconductor island. The buried layer is in the shallow trench isolation region and below the original surface, wherein the buried layer is distributed along the periphery of the semiconductor island, and the thermal conductivity of the buried layer is higher than the thermal conductivity of the semiconductor substrate.
[0020] In one embodiment of the present invention, a top surface of the buried layer is lower than a bottom of the semiconductor island.
[0021] In one embodiment of the present invention, the buried layer includes a first portion directly below the semiconductor island.
[0022] In one embodiment of the present invention, a local insulating layer is below the semiconductor island and above the buried layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1A The flowchart is a method for manufacturing a localized SOZ (LSOZ) structure disclosed in the first embodiment of the present invention.
[0024] Figure 1B Yes Description Figure 1A Step 30 in .
[0025] Figure 2 Schematic diagram illustrating the active area defining the localized SOZ (LSOZ) structure.
[0026] Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B Yes Description Figure 1B Schematic diagram of .
[0027] Figure 7 The flowchart is a method for manufacturing a partial SOZ structure disclosed in the second embodiment of the present invention.
[0028] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 Yes Description Figure 7 Schematic diagram of .
[0029] Fig.13 The flowchart of a method for manufacturing a partial SOZ structure disclosed in the third embodiment of the present invention.
[0030] Fig.14 , Fig.15 and Fig.16 Yes Description Fig.13 Schematic diagram of .
[0031] The reference numerals are described as follows:
[0032] 200 p-type substrate
[0033] 201 P-type well
[0034] 202 Active Zone
[0035] 204 Pad Oxide Layer
[0036] 206 liner nitride layer
[0037] 208 Shallow Trench Isolation Area
[0038] 302 Shallow Trench Isolation Oxide 2 Layer
[0039] 304 Photoresist
[0040] 402, 802, 1302 oxide spacer
[0041] 404, 804, 1304 Nitride spacer
[0042] 502 Silicon Surface
[0043] 602, 1102, 1402 horizontal cavity
[0044] 604, 1202, 1404 thermal oxide
[0045] 606, 1502 Z material
[0046] 1101 Silicon Column
[0047] 1201 First buried insulating layer
[0048] 1203, 1504 Spin-on dielectric
[0049] 1204 Silicon Island
[0050] 1206 Vertically Extended Dielectric Layer
[0051] 1506 Second buried layer
[0052] L1, L2 length
[0053] OSS Original Semiconductor Surface
[0054] t1, t2, t3, t4, t5 depth
[0055] VSOS Vertical Silicon Oxide Seed
[0056] W1 Width
[0057] 10-40, 102-108, 20', 30', 702-714, steps
[0058] 30” DETAILED DESCRIPTION
[0059] Please refer to Figure 1A , Figure 1A This is a flow chart of a method for manufacturing a localized SOZ (LSOZ) structure disclosed in the first embodiment of the present invention. The detailed steps are as follows:
[0060] Step 10: Start;
[0061] Step 20: Based on a semiconductor substrate, an active region of the local SOZ structure is defined by patterning a liner oxide layer 204 and a liner nitride layer 206 on the semiconductor substrate.
[0062] Then, a shallow trench isolation (STI) region 208 is formed. Figure 2 );
[0063] Step 30: forming a first buried layer below the active region of the local SOZ structure;
[0064] Step 40: End.
[0065] Please refer to Figure 1B , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , step 30 may include: step 102: depositing a shallow trench isolation oxide 2 layer 302, polishing the shallow trench isolation oxide 2 layer 302 using a chemical-mechanical planarization (CMP) technique, depositing a photoresist 304, and then patterning the photoresist 304 ( Figure 3 );
[0066] Step 104: Use anisotropic etching technique to remove the exposed pad nitride layer 206, the pad oxide layer 204 and the silicon material below the exposed pad nitride layer 206, remove the photoresist 304 and use spacer technique.
[0067] A thin oxide spacer 402 and a thin nitride spacer 404 are formed ( Figure 4 );
[0068] Step 106: Use the oxide spacer 402 and the nitride spacer 404 as necessary covers, and use the anisotropic etching technology to remove the exposed silicon surface so that the existing trench has a deeper depth ( Figure 5 );
[0069] Step 108: Form the horizontal cavity 602 and perform thermal oxidation to produce thermal oxide 604, and then deposit Z material 606 in the horizontal cavity 602 and the deeper trench ( Fig. 6A ).
[0070] First embodiment:
[0071] The following describes the manufacturing process of the LSOZ structure. In step 20, as Figure 2 As shown in (a), a typical silicon wafer (p-type or n-type) is used as the entire substrate, wherein the manufacturing method starts with a well-designed doped p-type well 201, and the p-type well 201 is set in the p-type substrate 200 (wherein in another embodiment of the present invention, the manufacturing method can start from the p-type substrate 200 instead of the p-type well 201). Then a rectangular active (single crystal silicon) region 202 (length L1×width W1) is created using a well-known process, wherein the active region 202 is covered by a liner oxide layer 204, and then the liner oxide layer 204 is covered by a liner nitride layer 206. Outside the active region 202, a shallow trench isolation (STI) region 208 surrounding the active region 202 is formed using well-known technology, wherein the shallow trench isolation region 208 has a depth t1. In addition, Figure 2 (b) corresponds to Figure 2 (a) is a top view, where Figure 2 (a) is along the Figure 2 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0072] Then, in step 102, as Figure 3 As shown in (a), a shallow trench isolation oxide 2 layer 302 is deposited so that the top surface of the shallow trench isolation oxide 2 layer 302 is flush with the top surface of the liner nitride layer 206 (this is an embodiment of the present invention). Then, a carefully designed area with a length L2 is defined using a photolithography technique and a photoresist 304, wherein the length L2 is shorter than the length L1 so that the liner nitride layer 206 on the left and right sides of the carefully designed area are exposed. In addition, Figure 3 (b) corresponds to Figure 3 (a) is a top view, where Figure 3 (a) is along the Figure 3 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0073] Then, in step 104, Figure 4As shown in (a), the anisotropic etching technology (such as reactive ion etching (RIE) technology) is used to remove the exposed pad nitride layer 206, the pad oxide layer 204 under the exposed pad nitride layer 206, and the silicon material to form a trench in the silicon substrate, wherein the trench in the silicon substrate has a depth t2, and the depth t2 is less than the depth t1. Then the photoresist 304 is removed and the spacer technology is used to create an oxide spacer 402 and a nitride spacer 404 on the vertical edge of the exposed silicon surface (corresponding to the depth t2) and the vertical edge of the shallow trench isolation (including the shallow trench isolation region 208 and the shallow trench isolation oxide 2 layer 302). In addition, Figure 4 (b) is related to Figure 4 (a) The corresponding top view, where Figure 4 (a) is along the Figure 4 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0074] Then, in step 106, if Figure 5 As shown in (a), these spacers (oxide spacer 402 and nitride spacer 404) are used as necessary covers and the anisotropic etching technology is used to remove the exposed silicon surface, so that the existing trench has a deeper depth (depth t3), wherein the sum of depth t2 and depth t3 is still less than depth t1. Figure 5 As shown in (a), the exposed silicon surface 502 will be used to form the local SOZ structure later. Figure 5 (b) is related to Figure 5 (a) The corresponding top view, where Figure 5 (a) is along the Figure 5 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0075] Then, in step 108, Fig. 6A As shown in (a), a horizontal cavity 602 is formed by thermally oxidizing the exposed silicon surface 502 and then etching the thermal oxide so that the horizontal cavity 602 surrounds the remaining silicon. Thermal oxidation is then performed to convert all the remaining silicon into thermal oxide 604 (hereinafter referred to as a neck thermal oxide). In addition, how to form the horizontal cavity 602 will be described later. In addition, FIG. Fig. 6A (b) is related to Fig. 6A (a) The corresponding top view, where Fig. 6A (a) is along the Fig. 6A (b) is a cross-sectional view of the cutting line in the X direction. Figure 6B As shown in (a), Z material 606 is deposited in the horizontal cavity 602 and the deeper trench, where Figure 6B (b) is related to Figure 6B (a) The corresponding top view, and Figure 6B (a) is along the Figure 6B (b) is a cross-sectional view taken along the cutting line in the X direction.
[0076] Second embodiment:
[0077] The following description will elaborate more engineering techniques to form another exposed silicon surface structure, which may be to make the local SOZ structure have any desired pattern. The detailed steps are as follows:
[0078] Step 10: Get Started.
[0079] Step 20': Based on the semiconductor substrate, an active region of the local SOZ structure is defined by patterning a liner oxide layer 204 and a liner nitride layer 206 on the semiconductor substrate, and then a shallow trench isolation region 208 is formed ( Figure 2 );
[0080] Step 30': forming a first buried layer ( Figure 7 to Figure 12 ); Step 40: End.
[0081] Step 20' is the same as the aforementioned step 20 and will not be described again here.
[0082] Please refer to step 30' and Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 . Figure 7 FIG. 1 is a flow chart of a method for manufacturing a partial SOZ structure disclosed in a second embodiment of the present invention, wherein Figure 7 Step 30' in may include:
[0083] Step 702: Use the anisotropic etching technique to remove the oxide material exposed in the shallow trench isolation region 208, and then use the spacer technique to create a thin oxide spacer 802 and a thin nitride spacer 804 ( Figure 8 );
[0084] Step 704: Use isotropic etching technique to further etch the exposed shallow trench isolation region 208 ( Fig. 9 );
[0085] Step 706: Form a horizontal cavity 1102 around the remaining silicon and perform thermal oxidation to produce thermal oxide 1202 ( Fig.10 , Fig.11 and Fig.12 );
[0086] Step 708: Deposit the desired Z material (i.e., spin-on dielectric (SOD) 1203) using chemical vapor deposition (CVD) technology, and then planarize the desired Z material ( Fig.12 ).
[0087] Continue Figure 2 In step 702, if Figure 8 As shown in (a), the anisotropic etching technology (e.g., reactive ion etching technology) is then used to remove the exposed oxide material at a depth t4 from the original semiconductor surface OSS in the shallow trench isolation region 208. Then, the spacer technology is used to create an oxide spacer 802 and a nitride spacer 804 on the vertical edges of the pad nitride layer 206, the pad oxide layer 204, and the active region. In addition, Figure 8 (b) is related to Figure 8 (a) The corresponding top view, where Figure 8 (a) is along the Figure 8 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0088] Step 704, as Fig. 9 As shown in (a), the isotropic etching technology (dry or wet) is then used to further etch the exposed shallow trench isolation region 208 so that the surface of the shallow trench isolation region 208 is at a depth of t5 from the original semiconductor surface OSS. The key to this new design technology is to expose the sidewalls of the single crystal silicon region below the oxide spacer 802 and the nitride spacer 804 and above the surface of the shallow trench isolation region 208, that is, the vertical silicon sidewall with a depth (t5-t4) (called the vertical silicon oxidation seed (VSOS) region) is fully exposed as a seed for the subsequent oxidation process. The rest of the wafer is covered by the liner nitride layer 206 or the shallow trench isolation region 208 on the flat surface and is protected by the liner nitride layer 206. Fig. 9 The exposed silicon structure shown in (a) is Figure 5 The exposed silicon structure shown in (a) is the same and will be used to form the local SOZ later. Fig. 9 (b) is related to Fig. 9 (a) The corresponding top view, where Fig. 9 (a) is along the Fig. 9 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0089] A method for forming a horizontal cavity to facilitate the formation of the local SOZ is described below. In step 706, Fig.10 As shown, the vertical silicon oxide seed crystal region is subjected to repeated oxidation / etching processes through a special design to remove most of the vertical silicon oxide seed crystal region. Fig.10 As shown, Fig.10 It is based on Sentaurus's computer-aided design technology (Technology Computer-Aided Design, TCAD) to simulate the corresponding Fig. 9 The vertical silicon oxidation seed region exposed within the dotted rectangular structure in (a) is subjected to repeated oxidation / etching processes. At time = 0, a thin thermal oxide is grown on the vertical silicon sidewalls of the vertical silicon oxidation seed region at 800 degrees, and at time = 1, the thermal oxide previously grown at time = 0 is etched to expose the silicon surface of the vertical silicon oxidation seed region. Similarly, at time = 2, a thin thermal oxide is again grown on the vertical silicon sidewalls of the vertical silicon oxidation seed region at 800 degrees, and at time = 3, the thermal oxide previously grown at time = 2 is etched to expose the silicon surface of the vertical silicon oxidation seed region. Thereafter, such oxidation / etching processes are repeated at time = 4 to time = 9 until most of the vertical silicon oxidation seed region is removed and only residual silicon pillars 1101 (such as Fig.11 (a) shows that a horizontal cavity 1102 is formed and surrounds the silicon pillar 1101. Fig.12 As shown, thermal oxidation is then performed on the silicon pillar 1101 to transform the silicon pillar 1101 into a thermal oxide 1202 (hereinafter referred to as a thermal oxide neck). Figure 5 The silicon surface structure exposed in (a) can also be Fig.10 , Fig.11 , Fig.12 The horizontal cavity 602 is formed based on the process described. In addition, Fig.11 (b) is related to Fig.11 (a) The corresponding top view, where Fig.11 (a) is along the Fig.11 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0090] Then, in step 708, Fig.12 As shown in (a), the chemical vapor deposition technique is used to form the required Z material to completely fill the horizontal cavity 1102. For example, a chemical vapor deposition oxide filling process (many Z materials are available, such as high-density deposited oxide, spin-on dielectric, etc.) is used to fill the horizontal cavity 1102 and wrap the thermal oxide 1202 around the thermal oxide 1202. Then, as shown in FIG. Fig.12As shown in (a), a planarization technique such as chemical mechanical planarization, etch back, etc. is used to create a flat surface flush with the surface of the pad nitride layer 206 or the pad oxide layer 204 (assuming that the pad nitride layer 206 has been stripped). Therefore, a subsurface oxide layer (with a thermal oxide neck and a spin-on dielectric) is constructed below the active region, and the expected silicon island 1204 (that is, a single-crystalline silicon island on insulator (SC-SIOI)) is formed. Fig.12 As shown in (a), the first buried insulating layer 1201 includes a thermal oxide 1202 (the thermal oxide neck) and a spin-on dielectric 1203, and a vertically extending dielectric layer (also a spin-on dielectric) 1206 surrounds the sidewalls of the silicon island 1208. In addition, Fig.12 (b) is related to Fig.12 (a) The corresponding top view, where Fig.12 (a) is along the Fig.12 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0091] Therefore, the present invention discloses a novel substrate material structure: there can be many single crystal silicon islands on insulating layers (SC-SIOI) regions, which are surrounded by oxide isolation layers on 6 surfaces surrounding the single crystal silicon islands (such as silicon island 1204), wherein the single crystal silicon islands can be used as a starting material based on a bulk silicon substrate wafer, without using a more expensive entire silicon on insulator (SOI) wafer. The structure of the single crystal silicon islands on insulating layers can be well used as a substrate for accommodating silicon transistors or other components. Metal oxide semiconductor field effect transistors (MOSFETs) can then be built into the single crystal silicon islands on insulating layers, just like forming the most advanced silicon on insulating layers devices, but without using expensive entire silicon on insulating layers wafers, but such silicon on insulating layers devices can be realized by using bulk silicon substrate wafers.
[0092] Of course, as long as the horizontal cavity can be filled by chemical vapor deposition technology or other processes, the local SOI can also be other Z materials (such as nitride) different from oxide / spin-on dielectric. Of course, in another embodiment of the present invention, the local SOI can be made of a Z material other than oxide / spin-on dielectric. Fig.12 The thermal oxide 1202 (the thermal oxide neck) of the silicon pillar 1101 in the first buried insulating layer 1201 of (a) may be etched and then replaced by other insulating materials (eg, nitride) during a chemical vapor deposition technique.
[0093] Third embodiment:
[0094] Please refer to the following Fig.13 , Fig.14 , Fig.15 and Fig.16 . Fig.13 FIG. 1 is a flow chart of a method for manufacturing a partial SOZ structure disclosed in the third embodiment of the present invention, wherein Fig.13 Step 30" in the above may include step 702, step 704, step 706, step 708, step 710, step 712 and step 714, wherein step 702, step 704, step 706, step 708 may refer to the above corresponding description and Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , so I will not go into details here.
[0095] Step 710: Use the anisotropic etching technique to remove the spin-on dielectric and portions of the shallow trench isolation region 208, use the spacer technique to create a thin oxide spacer 1302 and a thin nitride spacer 1304, and then further etch the shallow trench isolation region 208 to expose another vertical silicon oxidation seed (VSOS) region ( Fig.14 ); Step 712: Based on the vertical silicon oxidation seed crystal region, a horizontal cavity 1402 is formed and thermal oxidation is performed to produce a thermal oxide 1404 ( Fig.15 );
[0096] Step 714: Using chemical vapor deposition technology to form another desired Z material (ie, tungsten 1502),
[0097] A spin-on dielectric 1504 is then deposited and chemically mechanically planarized over the desired Z material ( Fig.16 ).
[0098] In step 710 after step 708, if Fig.14 As shown in (a), in the formation Fig.12 After the first buried insulating layer 1201 in the substrate, the spin-on dielectric (including the spin-on dielectric 1203 and the vertically extended dielectric layer 1206) and the exposed shallow trench isolation region 208 are removed using the anisotropic etching technique, wherein the anisotropic etching technique removes the exposed shallow trench isolation region 208 by a well-measured depth. The spacer technique is then used to create an oxide spacer 1302 and a nitride spacer 1304 on the exposed vertical edges. Then, as shown in FIG. Fig.14As shown in (a), the exposed shallow trench isolation region 208 is further etched downward to expose the vertical silicon oxidation seed crystal region, that is, the vertical silicon sidewall of a certain depth is well exposed to serve as a seed crystal for the subsequent oxidation process. In addition, Fig.14 (b) is related to Fig.14 (a) The corresponding top view, where Fig.14 (a) is along Fig.14 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0099] Then, in step 712, as Fig.15 (a) shows, with Fig.10 As in the steps described in the above, repeated oxidation / etching processes are performed on the vertical silicon oxide seed crystal regions to remove most of the silicon material. Such oxidation / etching processes are repeated until most of the silicon material is removed and only residual silicon pillars are left. Fig.15 As shown in (a), a horizontal cavity 1402 is formed. Thereafter, thermal oxidation is performed to convert all remaining silicon pillars into thermal oxide 1404 (hereinafter referred to as thermal oxide neck). In addition, Fig.15 (b) is related to Fig.15 (a) The corresponding top view, where Fig.15 (a) is along Fig.15 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0100] Then, in step 716, if Fig.16 As shown in (a), tungsten (or other suitable high thermal conductivity material) is deposited to obtain tungsten 1502 above the etched shallow trench isolation region 208. For example, after forming the thermal oxide 1404 (that is, the thermal oxide neck), tungsten (or other suitable high thermal conductivity material) is directly deposited using chemical vapor deposition technology to completely fill the horizontal cavity 1402, and then additional spin-on dielectric 1504 is deposited and planarized. Therefore, a second buried layer 1506 (including thermal oxide 1404 and tungsten 1502) is formed below the first buried insulating layer 1201. Fig.16 As shown in (a), compared with the traditional semiconductor substrate, below the silicon island 1204, the first buried insulating layer 1201 is an insulating layer for isolating the silicon island 1204, and the second buried layer 1506 having a metal (such as tungsten) provides better heat dissipation. In this way, a heterogeneous wafer substrate with a double buried layer is completed. In addition, the back side of the semiconductor substrate can be polished by chemical mechanical planarization to expose the second buried layer 1506, wherein the second buried layer 1506 can serve as a supporting substrate. That is, a thinned wafer with a strong support structure can be made from the back side of the semiconductor substrate using chemical mechanical planarization technology, so that the wafer thickness is thinner than 50 microns or even thinner. In addition, Fig.16 (b) is related to Fig.16(a) The corresponding top view, where Fig.16 (a) is along Fig.16 (b) is a cross-sectional view taken along the cutting line in the X direction.
[0101] Afterwards, the well-known processes can be continued to complete the flat surface of the active region in various ways, and various embodiments can be used to manufacture different types of transistors with various gate structures, such as planar gate transistors, fin field effect transistors (FinFETs), tri-gate transistors, gate-all-around (GAA) gate transistors, sheet-channels or tube-channels, etc. can be realized according to the needs and their respective formation processes. Therefore, compared with the prior art, the single-crystalline silicon island on insulator (SC-SIOI) element provided by the present invention has shown the feasibility and implementation method by using a cheaper bulk silicon wafer substrate instead of a more expensive wafer with silicon on an entire insulating layer.
[0102] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A semiconductor structure, characterized in that Include: A semiconductor substrate having an original surface; a semiconductor island formed based on the semiconductor substrate; a shallow trench isolation region surrounding the semiconductor island; a first buried layer, wherein the first buried layer is a local layer below the semiconductor island, and a material of the first buried layer is different from a material of the semiconductor substrate; and a second buried layer, wherein the second buried layer is a local layer below the first buried layer, and a material of the second buried layer is different from a material of the semiconductor substrate.
2. The semiconductor structure according to claim 1, characterized in that A material of the second buried layer is different from a material of the first buried layer.
3. The semiconductor structure according to claim 2, characterized in that The first buried layer is a buried insulating layer, and the second buried layer is a metal-containing layer.
4. The semiconductor structure according to claim 3, characterized in that The first buried insulating layer includes a thermal oxide layer and a deposited dielectric layer, and the bottom surface of the semiconductor island is completely isolated by the first buried insulating layer.
5. The semiconductor structure according to claim 4, further comprising a vertically extended dielectric layer, characterized in that The vertically extending dielectric layer surrounds sidewalls of the semiconductor island.
6. The semiconductor structure according to claim 1, characterized in that The thermal conductivity of the second buried layer is higher than the thermal conductivity of the semiconductor substrate.
7. A semiconductor structure, characterized in that Include: A semiconductor substrate having an original surface; a semiconductor island formed based on the semiconductor substrate; a shallow trench isolation region surrounding the semiconductor island; and A buried layer is provided below the semiconductor island, wherein the thermal conductivity of the buried layer is higher than the thermal conductivity of the semiconductor substrate.
8. The semiconductor structure according to claim 7, characterized in that The buried layer is a metal-containing layer.
9. The semiconductor structure according to claim 7, characterized in that The buried layer includes a first portion extending into the shallow trench isolation region.
10. The semiconductor structure according to claim 9, characterized in that The shallow trench isolation region includes an oxide layer below the first portion of the buried layer.
11. The semiconductor structure according to claim 10, characterized in that The shallow trench isolation region includes a dielectric layer over a first portion of the buried layer.
12. A semiconductor structure, characterized in that Include: A semiconductor substrate having an original surface; a semiconductor island formed based on the semiconductor substrate; a shallow trench isolation region surrounding the semiconductor island; and A buried layer is provided in the shallow trench isolation region and below the original surface, wherein the buried layer is distributed along the periphery of the semiconductor island and has a thermal conductivity higher than that of the semiconductor substrate.
13. The semiconductor structure according to claim 12, characterized in that The top surface of the buried layer is lower than the bottom of the semiconductor island.
14. The semiconductor structure according to claim 12, characterized in that The buried layer includes a first portion directly below the semiconductor island.
15. The semiconductor structure according to claim 14, characterized in that A local insulating layer is below the semiconductor island and above the buried layer.