Mitigating threshold voltage offsets in backside power delivery using backside passivation layers

Abstract

Described herein are devices, transistor structures, systems, and techniques relating to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between the source structure and the drain structure, and the gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulating layer on the backside of the semiconductor material, and then treated using ozone / UV curing to remove trapped charges from the semiconductor material.

Description

Background Art

[0001] Higher performance, lower cost, increased miniaturization and greater density of integrated circuits (ICs) are ongoing goals for the electronics industry. Backside interconnects are an important aspect of the semiconductor industry's progress toward these goals. For example, backside interconnects can provide power from the back side of a transistor device. This provides advantages including lower resistance paths for powering transistor devices, open space on the front side of transistor device layouts, etc. This in turn improves transistor device performance metrics in both per power terms and per area terms.

[0002] However, there are still difficulties in the deployment of backside power delivery, such as the introduction of threshold voltage (Vt) shift when the transistor is exposed from the backside. The techniques and structures discussed herein provide backside metallization and power delivery with reduced (e.g., zero or near zero) Vt shift. As the desire to deploy advanced transistor structures becomes more widespread, such improvements may become critical. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The materials described herein are illustrated in the accompanying drawings by way of example and not limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, where considered appropriate, reference numerals are repeated between the drawings to indicate corresponding or similar elements. In the drawings:

[0004] Figure 1 is a flow chart illustrating a method for mitigating or eliminating a threshold voltage shift due to backside semiconductor material etching using a passivation layer;

[0005] Figure 2A , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9A With practice Figure 1 A cross-sectional view of a transistor structure developed by forming a back passivation layer on the transistor semiconductor structure using a method;

[0006] Figure 2B and Fig. 9B yes Figure 2A and Fig. 9A A cross-sectional top view or plan view of a transistor structure;

[0007] Fig.10 shows a similar Fig. 9A and Fig. 9B A cross-sectional side view of an integrated circuit device structure of a transistor structure;

[0008] Fig.11 An exemplary system employing a transistor structure having a field effect transistor with a backside passivation layer is shown; and

[0009] Fig.12 is a functional block diagram of an electronic computing device in accordance with some embodiments. DETAILED DESCRIPTION

[0010] One or more embodiments or implementations are now described with reference to the accompanying drawings. Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be employed without departing from the spirit and scope of the present description. It will be apparent to those skilled in the relevant art that the techniques and / or arrangements described herein may also be employed in various other systems and applications in addition to the systems and applications described herein.

[0011] In the following detailed description, reference is made to the accompanying drawings forming a part thereof, wherein similar reference numerals may always represent similar parts to indicate corresponding or similar elements. It should be understood that, for the sake of simplicity and / or clarity of explanation, the elements shown in the figures are not necessarily drawn to scale. For example, for the sake of clarity, the sizes of some elements may be exaggerated relative to other elements. In addition, it should be understood that other embodiments may be utilized without departing from the scope of the claimed subject matter, and structural and / or logical changes may be made. It should also be noted that directions and references (e.g., up, down, top, bottom, above, below, etc.) may be used to facilitate discussion of the drawings and embodiments, and are not intended to limit the application of the claimed subject matter. Therefore, the following detailed description should not be considered to have a limiting meaning, and the scope of the claimed subject matter is defined by the appended claims and their equivalents.

[0012] In the following description, many details are set forth. However, it will be apparent to those skilled in the art that the present invention can be practiced without these specific details. In some cases, known methods and apparatus are shown in block diagram form rather than in detail to avoid making the present invention difficult to understand. References throughout this specification to "embodiment" or "one embodiment" mean that the specific features, structures, functions or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in an embodiment" or "in an embodiment" that appear in various places throughout this specification do not necessarily refer to the same embodiment of the present invention. In addition, specific features, structures, functions or characteristics can be combined in any suitable manner in one or more embodiments. For example, the first embodiment can be combined with the second embodiment, as long as the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0013] As used in the description of the invention and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. As used herein, the term "primarily" means not less than 50% of a particular material or component, while the term "substantially pure" means not less than 99% of a particular material or component, and the term "pure" means not less than 99.9% of a particular material or component. Unless otherwise stated, these material percentages are based on atomic percentages. As used herein, the terms concentration and material percentage are used interchangeably and also mean atomic percentages, unless otherwise stated.

[0014] The terms "coupled" and "connected" and their derivatives may be used herein to describe the structural relationship between components. It should be understood that these terms are not intended to be synonymous with each other. On the contrary, in a particular embodiment, "connected" may be used to represent that two or more elements are in direct physical or electrical contact with each other. "Coupled" may be used to represent that two or more elements are in direct or indirect (with other intermediate elements between them) physical or electrical contact with each other, and / or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship, an electrical relationship, a functional relationship, etc.).

[0015] As used herein, the terms "above", "below", "between", "on", etc. refer to the relative position of a material layer or component relative to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intermediate layers. In addition, a layer disposed between two layers may be in direct contact with the two layers, or may have one or more intermediate layers. In contrast, a first layer "on" a second layer is in direct contact with the second layer. Similarly, unless otherwise expressly stated, a feature disposed between two features may be in direct contact with an adjacent feature, or may have one or more intermediate features. The term "adjacent" means that these features are in direct contact. In addition, the terms "substantially", "close", "approximately", "nearby", and "approximately" generally refer to within + / -10% of a target value. The term layer as used herein may include a single material or multiple materials. As used throughout this description and claims, a list of items combined by the terms "at least one of" or "one or more of" may represent any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C. The terms "lateral," "laterally adjacent," and similar terms indicate that two or more components are aligned along a plane that is orthogonal to a vertical direction of the overall structure. As used herein, the terms "monolithic," "monolithically integrated," and similar terms indicate that the components of a monolithic overall structure form an inseparable whole that cannot be reasonably separated.

[0016] The devices, transistor structures, integrated circuit dies, apparatus, systems and techniques described herein involve a passivation layer applied to the back side of the transistor semiconductor material when the transistor semiconductor material is exposed for deployment of back side power delivery. For example, the present disclosure provides for mitigation of threshold voltage shift in architectures deploying back side power delivery.

[0017] As discussed, the backside interconnect or backside metallization layer is an important aspect of progress in the semiconductor industry. This backside interconnect is vertically opposite to the front side metallization layer relative to the device layer therebetween. For example, the front side metallization layer is above the device layer including the transistor, and the back side metallization layer is below the transistor. During the front side processing (e.g., before the front side metallization), the bridging via is manufactured so that the bridging via extends vertically across the device layer. After manufacturing the front side metallization layer (which may contact the bridging via), the back side metallization layer may be formed by attaching the wafer to a carrier, removing the substrate on which the transistor and the front side metallization layer are formed, forming the back side metallization layer, and removing the carrier. In addition, as discussed herein, this back side processing may include etching the transistor semiconductor material of the device layer. It is noteworthy that this etching and exposure of the transistor semiconductor material introduces trapped charge into the transistor semiconductor material of the field effect (FE) transistor. For example, the back side power delivery process may introduce additional trapped charge into the FE transistor, which results in a larger line-in-line to line-end threshold voltage (Vt) shift, which is undesirable in the Vt target. Furthermore, these trapped charges may have local layout dependencies and cause problems with Vt centering of all transistors.It is desirable to reduce (eg, have zero or near zero) the intra-line to end-of-line threshold voltage Vt shift.

[0018] As discussed herein, a passivation layer is introduced after back etching, and back etching exposes the back of the FE transistor semiconductor material. The passivation layer can be any thickness and / or material discussed herein, such as a 5nm SiN (silicon nitride) passivation layer (e.g., a layer including silicon and nitrogen). After applying the passivation layer, an ozone / ultraviolet (e.g., O3 / UV) anneal is performed. The passivation layer and ozone / UV annealing or treatment removes trapped charge from the transistor semiconductor material previously exposed to the passivation layer to reduce trapped charge and mitigate or eliminate the Vt shift discussed. After the ozone / UV annealing or treatment, a second insulating layer is formed on the passivation layer (or conformal insulating layer), and planarization is performed to flatten the second insulating layer and expose the bridge via discussed from the back. For example, the second insulating layer (or insulating fill layer) can be a silicon oxide insulating fill layer (e.g., a layer including silicon and oxygen). The passivation layer and ozone / UV annealing or treatment discussed mitigate or eliminate the Vt shift. For example, the Vt shift can be reduced by about 15 to 20mV. On devices that are more sensitive to the Vt shift of the threshold voltage from within the line to the end of the line, the Vt shift can be reduced by a larger amount.

[0019] The back metallization layer and the front metallization layer in question can be interconnected by metal vias that extend vertically across or across the transistors of the device layer. The metal vias can be characterized as vias, deep vias, bridge vias, cross-transistor vias, interconnect vias, etc. In some contexts, the vias can be characterized as power vias as a means of delivering power from the back metallization layer to the transistor device. However, the metal vias can deliver signal routing, ground routing, or provide any suitable interconnection. It is noteworthy that the vias bridge the front and back metallization layer interconnections.

[0020] Figure 1 is a flow chart illustrating a method 100 for mitigating or eliminating threshold voltage shift due to backside semiconductor material etching using a passivation layer, arranged in accordance with at least some embodiments of the present disclosure. Figure 2A , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9A is a cross-sectional view of a transistor structure evolving as method 100 is practiced to form a backside passivation layer on the transistor semiconductor structure, arranged in accordance with some embodiments of the present disclosure. Figure 2B and Fig. 9B Arranged according to some embodiments of the present disclosure Figure 2A and Fig. 9A A cross-sectional top view or plan view of a transistor structure of FIG. 1 is a cross-sectional top view or plan view of a transistor structure of FIG. 1. As discussed herein, a passivation layer or insulating layer is formed on the back side of the exposed transistor semiconductor structure, and an ozone / UV cure is performed to remove trapped charge from the transistor semiconductor structure, thereby mitigating or eliminating threshold voltage shift. Although illustrated with respect to forming a bridging via within a gate trace of a transistor structure, the bridging via may be formed at any suitable location, such as within a source / drain contact trace of a transistor structure.

[0021] Method 100 begins with an input operation 101, in which a workpiece including an at least partially formed transistor structure is received for processing. For example, a substrate may be received for processing so that a transistor or transistor structure is manufactured above the substrate. In some embodiments, the transistor or transistor structure includes a semiconductor structure extending between a source structure and a drain structure. A gate structure (e.g., a gate dielectric and a gate electrode) is between the source structure and the drain structure so that the gate structure is adjacent to a channel region of one or more semiconductor structures. In addition, the source structure and the drain structure may be contacted by a source contact and a drain contact, respectively. For example, the transistor may be part of a transistor layer or a device layer formed above the substrate.

[0022] Any number of metallization layers may be formed over the front side transistors of the device layer to interconnect the transistors, provide signal routing, etc. As used herein, the term front side of a transistor structure refers to the side (or direction of that side) that is typically built over a wafer substrate during front end of line (FEOL) processing of the transistor structure, according to the recognized use of the front side. The back side is then opposite the front side and is the side opposite to the build direction (e.g., negative z direction). The received workpiece may also include a bridging via that contacts the front side metallization and extends vertically across the transistors of the device layer to extend below the transistors of the device layer. The bridging via may then be contacted from the back side during back side exposure, as discussed below.

[0023] Figure 2A A cross-sectional side view of a transistor structure 200 is shown, the transistor structure 200 including a metal via 212 extending across a device layer 215 to extend below the device layer 215. As shown, the transistor structure 200 includes a plurality of semiconductor structures 208 including semiconductor material. Each or several of the semiconductor structures 208 corresponds to a functional transistor that can be implemented in an integrated circuit. The semiconductor structures 208 can also be characterized as fins. Figure 2A In the context of Figure 2B The gate cutout shown is taken.

[0024] Figure 2B A top view or plan view of the transistor structure 200 is provided, which shows that the semiconductor structure 208 extends between and contacts the source structure 221 and the drain structure 222. In addition, the gate structure 205 is between the source structure 221 and the drain structure 222 and is connected to the channel region 225 of the semiconductor structure 208 (at Figure 2B is obscured in the middle).

[0025] Continue to refer Figure 2A and Figure 2B, transistor structure 200 may include substrate 201 and be formed over substrate 201. In some embodiments, as shown, semiconductor structure 208 may be continuous with substrate 201. However, semiconductor structure 208 may also be formed over substrate 201 but not continuous with substrate 201. Substrate 201 may include any suitable material or materials. For example, substrate 201 may be substantially oriented along a predetermined crystal orientation (e.g., <100> , <111> , <110> In some embodiments, substrate 201 is a semiconductor material such as single crystal silicon (Si), germanium (Ge), silicon germanium (SiGe), III-V materials (e.g., gallium arsenide (GaAs)), silicon carbide (SiC), sapphire (Al2O3), or any combination thereof. In some embodiments, substrate 201 is a semiconductor material having <111> Crystalline oriented silicon. Semiconductor structure 208 can be any suitable one or more semiconductor materials, such as silicon, germanium, silicon germanium, III-V materials, any material discussed with respect to substrate 201, or other materials. In some embodiments, semiconductor structure 208 is formed as a fin from substrate 201. In some embodiments, a portion of semiconductor structure 208 (e.g., a sub-fin) is buried in an insulating material or insulating layer 203. In some embodiments, insulating layer 203 is silicon oxide (e.g., a layer including silicon and oxygen). However, other insulating materials may be used. As used herein, the term insulating material refers to a material in which current cannot flow freely.

[0026] As shown, the channel region 225 of each semiconductor structure 208 is surrounded by a gate structure 205. The gate structure 205 includes, for example, a gate dielectric 206 on at least a portion of each semiconductor structure 208 and a gate electrode 209 on the gate dielectric 206. As used herein, the term channel region indicates a region or portion of a material or structure that is manipulated by a gate to operate a transistor. It is noteworthy that for the region that will become the channel region, the transistor does not need to be in operation. The gate dielectric 206 can be silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. For example, the gate dielectric 206 can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, or zinc.

[0027] As shown, the gate structure includes a gate dielectric 206 and a gate electrode 209. The gate electrode 209 may include any suitable work function metal for transistor gate control (e.g., tantalum, titanium, aluminum, ruthenium, or alloys of these materials), and a fill metal (e.g., tungsten). As shown, the semiconductor structure 208 extends between a source structure 221 (or source) and a drain structure 222 (or drain). The gate dielectric 206 and gate electrode 209 of the gate structure 205 are adjacent to the channel region 225 of the semiconductor structure 208 to form a three-terminal transistor device. Although described herein with respect to a FinFET transistor architecture, these structures and techniques may be deployed with respect to any suitable FET transistor architecture (such as a tri-gate or dual-gate transistor architecture or a planar transistor architecture).

[0028] As shown, in some embodiments, the gate electrode 209 has a depth, vertical height, or thickness t1 (e.g., in the z direction) that can be in the range of about 50nm to 90nm. In some embodiments, the thickness t1 is in the range of 60 to 80nm. In some embodiments, the thickness t1 is in the range of 50 to 60nm. Other thicknesses can be used. In addition, the gate electrode can extend a depth, vertical height, or thickness t2 (e.g., in the z direction) of about 10 to 30nm above the top surface or vertex of the semiconductor structure 208. In some embodiments, the thickness t2 is in the range of 15 to 25nm. In some embodiments, the thickness t2 is in the range of 10 to 15nm. Other thicknesses can be used.

[0029] The transistor structure 200 also includes a metal via 212 formed within the insulating liner layer 211. The metal via 212 contacts a metallization feature 213 of a metallization layer 217 such that the metallization feature 213 is embedded in the insulating material 214. The metallization layer 217 can be one of any number of metallization layers, such as seven to ten such layers, which include metal lines and metal vias that interconnect the metal lines. As shown, the metal via 212 (e.g., a bridging via) contacts the metallization feature 213 and extends from the metallization layer 217 above the transistor of the device layer 215 to below the transistor of the device layer 215. That is, the metal via 212 bridges between the front side 224 of the transistor structure 200 and the back side 223 of the transistor structure 200. As discussed, the term front side of the transistor structure refers to a side (or direction of the side) that is constructed during FEOL processing of the transistor structure 200 according to the recognized use of the front side (e.g., the positive z-direction), which is a process performed on or above the received substrate 201. Thus, the back side is opposite the front side, and is the side opposite to the build direction (eg, the negative z-direction).

[0030] As shown, the insulating liner layer 211 laterally surrounds the metal via 212 and is between the metal via 212 and other components of the transistor structure 200. The insulating liner layer 211 provides electrical isolation between the metal via 212 and other components of the transistor. The insulating liner layer 211 can be any suitable material, such as silicon nitride (e.g., including silicon and nitrogen), silicon oxide (e.g., including silicon and oxygen), or other insulating materials. The metal via 212 can be any suitable metal. In some embodiments, the metal via 212 is tungsten or includes tungsten. However, other metals such as copper, aluminum, or others can be deployed. Figure 2B As shown in the top view of , the transistor structure 200 may include a metal via 212 and an insulating liner layer 211 extending through or adjacent to the gate structure 205. However, the metal via 212 and the insulating liner layer 211 may be formed through or adjacent to the source structure 221, the drain structure 222, or any other suitable component of the transistor structure 200.

[0031] return Figure 1 , processing continues at operation 102, where the front side of the workpiece received at operation 102 is attached to a carrier and the back side of the transistor structure is exposed. In some embodiments, the partially manufactured workpiece is mounted to a carrier, such as a carrier wafer, by its front side, and the bridging vias and transistor semiconductor structures discussed are exposed by the back side of the substrate of the workpiece. The workpiece may be mounted to the carrier using any suitable one or more techniques, such as applying an adhesive film between the workpiece and the carrier. The bridging vias are then exposed using any suitable one or more techniques, such as a back side substrate removal process, including back side grinding, back side etching, etc., to thin the substrate.

[0032] Figure 3 A cross-sectional side view of a transistor structure 300 similar to transistor structure 200 is shown after a carrier 315 is attached to front side 224 and material removal 301 is performed on back side material 302 to expose semiconductor structure 208. As shown, carrier 315 is attached over front side 224 of transistor structure 300. Carrier 315 may be attached over a metallization layer or level similar to metallization layer 217. For example, carrier 315 may be coupled to a passivation layer formed on or over a top metallization layer of transistor structure 300. In some embodiments, a carrier (such as a carrier wafer) is attached using an adhesive film between the workpiece and carrier 315, although other techniques may be used.

[0033] After being attached to the carrier 315, material is removed from the back side 223 of the transistor structure 300 via material removal 301 to expose the back sides of the semiconductor structure 208, the metal via 212, the insulating liner layer 211, and the insulating layer 203. The material removal 301 may be performed using any suitable technique or techniques, such as a chemical mechanical polishing (CMP) technique, to remove material from the back side 223. As shown, the material removal 301 may provide a substantially planar back side surface 303 such that the back side surfaces of each of the semiconductor structure 208, the metal via 212, the insulating liner layer 211, and the insulating layer 203 are substantially coplanar (e.g., in the xy plane).

[0034] return Figure 1 , processing continues at operation 103, where an etch removal of the fill material is performed to etch back material from the semiconductor structure (e.g., the back side of the fin) and the insulating material laterally adjacent to the fin. For example, a portion of the back side of the sub-fin and a portion of the insulating material laterally adjacent to the sub-fin may be removed. This etching process is selective to the sub-fin material and the laterally adjacent insulating material, so that the sub-fin material and the laterally adjacent insulating material are etched, while other structures such as metal vias and via liners are substantially not etched. The etch removal discussed may be performed using any suitable one or more techniques, such as selective plasma etching techniques. As discussed, these etching techniques reduce the thickness of the semiconductor structure and introduce trapped charge into the semiconductor structure, which may adversely cause Vt shift. For example, plasma etching of the back side of the fill material and the semiconductor structure bombards the remaining fill material and semiconductor structure portions with charge. In addition, the work function metal of the gate dielectric 206 and the gate electrode 209 may also introduce trapped charge. Without the mitigation techniques discussed below, this introduction of trapped charge can result in undesirable Vt shifts in the range of approximately 40 to 60 mV.

[0035] Figure 4 A cross-sectional side view of a transistor structure 400 similar to transistor structure 300 is shown after selective etching 401 of semiconductor structure 208 and portion 402 of insulating layer 203. As discussed, selective etching 401 may be a plasma etch. In some embodiments, semiconductor structure 208 is or includes silicon, and insulating layer 203 is or includes silicon oxide, while insulating liner layer 211 is or includes silicon nitride, and metal via 212 is or includes tungsten. In some embodiments, selective etching 401 is a plasma etch that selectively etches silicon and silicon oxide while substantially not etching silicon nitride and tungsten.

[0036] As shown, the selective etch 401 may provide a substantially flat back surface 404 such that the back surfaces of each of the semiconductor structure 208 and the insulating layer 203 are substantially coplanar (e.g., in the xy plane). Also as shown, the selective etch 401 may not substantially etch the metal vias 212 and the insulating liner layer 211. For example, the selective etch 401 may not substantially change the previously discussed flat back surface 303 such that the back surfaces of each of the metal vias 212 and the insulating liner layer 211 are substantially coplanar (e.g., in the xy plane) at the substantially flat back surface 303.

[0037] As shown, in some embodiments, the semiconductor structure 208 is etched back to a depth, vertical height, or thickness t4 (e.g., in the z direction) that may be in the range of about 80 to 120 nm. In some embodiments, the thickness t4 is in the range of 90 to 110 nm. In some embodiments, the thickness t4 is in the range of 80 to 100 nm. Other thicknesses may be used. In addition, the insulating layer 203 may be etched back to a depth, vertical height, or thickness t5 (e.g., in the z direction) of about 30 to 70 nm. In some embodiments, the thickness t5 is in the range of 40 to 60 nm. In some embodiments, the thickness t5 is in the range of 30 to 50 nm. Other thicknesses may be used. In some embodiments, a portion of the semiconductor structure 208 that is laterally adjacent to the insulating layer 203 (e.g., the thickness t5 of the semiconductor structure 208) may be defined as a sub-fin portion of the semiconductor structure 208. The upper portion of the semiconductor structure 208 (e.g., the thickness t4-t5 of the semiconductor structure 208) may be characterized as an active fin portion of the semiconductor structure 208.

[0038] return Figure 1 , processing continues at operation 104, where a conformal insulating layer or passivation layer is formed or deposited on the back surface of the exposed semiconductor structure, insulating layer, metal via, and insulating liner layer. The conformal insulating layer or passivation layer can be deposited using any suitable one or more techniques, such as chemical vapor deposition (CVD), including low pressure chemical vapor deposition (LPCVD). The conformal insulating layer can be any suitable insulating material deposited to any suitable thickness.

[0039] In some embodiments, the insulating layer formed at operation 104 is a silicon nitride layer (e.g., a layer including silicon and nitrogen) having a thickness of about 5 nm. In some embodiments, the insulating layer or passivation layer includes one or more of silicon, carbon, oxygen, and nitrogen. In some embodiments, the insulating layer or passivation layer is silicon nitride (e.g., including silicon and nitrogen). In some embodiments, the insulating layer or passivation layer is aluminum oxide (e.g., including aluminum and oxygen). In some embodiments, the insulating layer or passivation layer is silicon carbide (e.g., including silicon and carbon). In some embodiments, the insulating layer or passivation layer is silicon oxynitride (e.g., including silicon, oxygen, and nitrogen). In some embodiments, the insulating layer or passivation layer is silicon oxynitride carbon SiCON (e.g., including silicon, carbon, oxygen, and nitrogen). In some embodiments, the insulating layer or passivation layer is SiCO (e.g., including silicon, carbon, and oxygen). Other materials may be used.

[0040] As discussed, the insulating or passivation layer can be deposited to any suitable thickness, such as a thickness in the range of 3 to 10 nm, a thickness no greater than 10 nm, a thickness of about 5 nm, or a thickness no greater than 5 nm. Other thicknesses can be used.

[0041] Figure 5 A cross-sectional side view of a transistor structure 500 similar to transistor structure 400 is shown after depositing a conformal insulating layer 501. As discussed, conformal insulating layer 501 may be deposited using CVD, LPCVD, or other suitable deposition techniques. In some embodiments, conformal insulating layer 501 is conformal such that it has substantially the same thickness t6 on back surface 502 of semiconductor structure 208, back surface 503 of insulating layer 203, sidewall surface 505 of insulating liner layer 211, back surface 504 of insulating liner layer 211, and back surface 506 of metal via 212. As shown, conformal insulating layer 501 is formed on back surface 502 of semiconductor structure 208 and back surface 503 of insulating layer 203 formed at operation 103. The conformal insulating layer 501 is also formed on the sidewall surface 505 of the insulating liner layer 211 exposed at operation 103 , and on the back surface 504 of the insulating liner layer 211 and the back surface 506 of the metal via 212 formed at operation 102 .

[0042] Thickness t6 can be any suitable thickness. In some embodiments, thickness t6 is in the range of 3 to 10 nm. In some embodiments, thickness t6 is in the range of 4 to 6 nm. In some embodiments, thickness t6 is in the range of 3 to 5 nm. In some embodiments, thickness t6 is no greater than 10 nm. In some embodiments, thickness t6 is no greater than 5 nm. Other thicknesses may be used. Conformal insulating layer 501 may be any of the materials discussed above, such as SiN, SiON, SiC, AlO, SiCON, or SiCO.

[0043] return Figure 1 , the process continues at operation 105, where an ozone / ultraviolet light (e.g., O3 / UV) treatment is performed to remove the trapped charge introduced at operation 103 from the semiconductor structure of the transistor. The ozone / UV treatment can be characterized as ozone / UV curing, ozone / UV annealing, etc. In some embodiments, the ozone / UV treatment applies UV light (e.g., a wavelength in the range of 100 to 400 nm, where a wavelength in the range of 180 to 300 nm is particularly advantageous) in an ozone-rich or pure ozone environment. In some embodiments, the ozone / UV treatment can be provided at an elevated temperature. The ozone / UV treatment applied to the back side of the passivation layer removes trapped charge from the semiconductor structure to the passivation layer to reduce the trapped charge and mitigate or eliminate Vt shift.

[0044] Figure 6 A cross-sectional side view of a transistor structure 600 similar to transistor structure 500 is shown during an ozone / UV treatment 601 to remove trapped charge from semiconductor structure 208 and / or other components of transistor structure 600. In some embodiments, ozone / UV treatment 601 applies UV light in an ozone-rich or pure ozone environment to remove trapped charge, as shown with respect to trapped charge removal 602. Although illustrated with respect to trapped charge removal 602 using downward arrows for clarity of presentation, any suitable mechanism (such as removal, restoration, migration, decomposition, etc. of lattice defects and / or bonds in semiconductor structure 208) may be used to mitigate or decompose trapped charge. In some embodiments, ozone / UV treatment may be provided at an elevated temperature. As discussed, such trapped charge removal 602 mitigates or eliminates Vt shifts, such as in-line to line-end Vt shifts.

[0045] return Figure 1 , processing continues at operation 106, where an insulating fill material is deposited and planarized. The insulating fill material may be deposited using any suitable technique or techniques, such as CVD, and planarized using any suitable technique or techniques, such as a CMP process. For example, the insulating fill material may be bulk deposited and then polished back to expose the back surface of the bridge via and the bridge via insulator liner while covering the previously exposed semiconductor structure, such that the conformal insulating layer formed at operation 104 is between the back surface of the semiconductor structure and the insulating fill material. The insulating fill material may be any insulator material, such as silicon oxide.

[0046] Figure 7 A cross-sectional side view of a transistor structure 700 similar to transistor structure 600 is shown after forming an insulating layer 701. As shown, insulating layer 701 is formed on the Figure 42. The etching removal is shown in the recess defined. The insulating layer 701 can be any suitable material, such as silicon dioxide, and can be formed by bulk deposition and planarization techniques to provide a substantially flat back surface 704. As shown, the transistor structure 700 includes a conformal insulating layer 501 (e.g., a first insulating layer) on the back surface 502 (e.g., the back side) of the semiconductor structure 208, and an insulating layer 701 (e.g., a second insulating layer or an insulating fill layer) on the conformal insulating layer 501. In some embodiments, the conformal insulating layer 501 and the insulating layer 701 are different materials, wherein the material of the conformal insulating layer 501 helps passivate and remove trapped charges, while the insulating layer 701 provides a bulk or fill material. In some embodiments, the conformal insulating layer 501 is one of silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, silicon oxynitride carbon, or silicon oxycarbide.

[0047] return Figure 1 , processing continues at operation 107, where any number of back metallization levels are formed opposite to the front metallization layer relative to the transistor or device layer. As discussed, the partially manufactured workpiece is mounted to a carrier such as a carrier wafer by its front side, and the bridging vias are exposed through the back side of the substrate of the workpiece. A back metallization layer is then manufactured above the exposed bridging vias (and opposite to the transistor layer relative to the front metallization layer). In some embodiments, one of the back metallization layers is such that the metallization features of one of the back metallization layers contact the bridging vias. The back metallization layer can be formed using any suitable one or more techniques, such as dual inlay techniques, single inlay techniques, subtractive metallization patterning techniques, etc. For example, power delivery can be provided by the back metallization layer to the bridging vias to power the transistors of the device layer. Although power delivery has been discussed, interconnection, signal routing, ground plane, or other functions can be provided by the back metallization layer.

[0048] Figure 8A cross-sectional side view of a transistor structure 800 similar to transistor structure 700 is shown after a metallization layer 817 is formed above the back side 223 of the transistor structure 800. The metallization layer 817 may include any number of metallization features, such as metallization features 801 (e.g., metal lines, metal vias, metal contacts, etc.) embedded in the insulating material 802. As discussed, the metallization layer 817 and any additional layers extending below the metallization layer 817 may be formed using any suitable one or more techniques. The metallization layer 817 may be one of any number of metallization layers (such as two to five such layers including metal vias of metal lines and interconnecting metal lines). As shown, a metal via 212 (e.g., a bridge via) contacts the metallization feature 801 so that the metal via 212 extends from the metallization layer 217 to the metallization layer 817, and thereby bridges the device layer 215 from the front side 224 of the transistor structure 800 to the back side 223 of the transistor structure 800.

[0049] return Figure 1 , processing continues at operation 108, where the carrier attached at operation 102 can be removed, and continues at operation 109, where continued processing is performed as known in the art to cut, package and output the integrated circuit (IC) die, package or device including the features discussed. In operation, any suitable one or more techniques (such as delamination, UV curing, etc.) can be used to remove the carrier. At operation 109, continued processing can include cutting, packaging, assembling, etc. The resulting device (e.g., IC die, IC package, IC assembly, etc.) can then be implemented in any suitable form factor device, such as laptop computers, netbooks, notebooks, ultrabooks, smart phones, tablet computers, personal digital assistants, super mobile PCs, mobile phones, desktop computers, servers, printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, portable music players, digital video recorders, etc.

[0050] Fig. 9A A cross-sectional side view of a transistor structure 900 similar to transistor structure 800 is shown after removal of carrier 315 via delamination, UV curing, etc. Fig. 9A and Fig. 9B, transistor structure 900 includes one or more transistors, such as transistor 901. Transistor 901 includes one or more semiconductor structures, such as semiconductor structure 208 extending between source structure 221 and drain structure 222, and gate structure 205 over channel region 225 of semiconductor structure 208. In some embodiments, semiconductor structure 208 can be characterized as a semiconductor material, source structure 221 and drain structure 222 can be characterized as a source and a drain, and gate structure 205 can be characterized as a gate. As discussed, gate structure 205 includes gate dielectric 206 and gate electrode 209, which can include a work function metal on gate dielectric 206 and a bulk metal on the work function metal.

[0051] As also shown, the transistor structure 900 includes a metal via 212 (e.g., a bridge via, a power via, a deep power via, or simply a via) extending from a metallization layer 217 (e.g., a front metallization or a front metallization layer) above the transistor 901 to a metallization layer 817 (e.g., a back metallization or a back metallization layer) below the transistor 901. For example, the metal via 212 spans the device layer 215 and contacts the metallization feature 213 of the metallization layer 217 and contacts the metallization feature 801 of the metallization layer 817. A conformal insulating layer 501 (e.g., a first insulating layer) is on the back surface 502 (e.g., the back side) of the semiconductor structure 208. As discussed, the conformal insulating layer 501 provides passivation and trapped charge removal. The conformal insulating layer 501 can be characterized as a passivation layer, an insulating layer, or an insulating material. In addition, an insulating material 802 such as an insulating fill layer (e.g., a second insulating layer) is on the first insulating layer. The insulating material 802 may provide a fill material beneath the semiconductor structure 208 and laterally adjacent to a portion of the metal via 212 and a portion of the insulating liner layer 211 .

[0052] Conformal insulating layer 501 and insulating material 802 can be any material and have any of the properties discussed above. In some embodiments, conformal insulating layer 501 includes one or more of silicon, carbon, oxygen, and nitrogen. In some embodiments, conformal insulating layer 501 includes silicon and nitrogen (e.g., pure or substantially pure silicon nitride), or aluminum and oxygen (e.g., pure or substantially pure aluminum oxide). In some embodiments, conformal insulating layer 501 includes silicon and nitrogen (e.g., pure or substantially pure silicon nitride), and insulating material 802 includes silicon and oxygen (e.g., pure or substantially pure silicon dioxide). In some embodiments, conformal insulating layer 501 has a thickness of no more than 10 nm. In some embodiments, conformal insulating layer 501 has a thickness of no more than 5 nm. In some embodiments, conformal insulating layer 501 has a thickness in the range of 1 to 5 nm.

[0053] Other components of the transistor structure 900 may also be any material and have any of the properties discussed above. In some embodiments, the semiconductor structure 208 has a thickness t4 of no greater than 100 nm between the back side 223 of the semiconductor structure 208 and the front side 224 of the semiconductor structure 208. As shown, the transistor structure 900 also includes an insulating liner layer 211 (e.g., an insulating liner) adjacent to the metal via 212, such that a portion 905 of the conformal insulating layer 501 is on a sidewall surface 505 of the insulating liner layer 211. In some embodiments, a bottom surface 906 of the insulating material 802 is substantially coplanar with a back side surface 506 of the metal via 212 and a back side surface 504 of the insulating liner layer 211.

[0054] In addition, the gate structure 205 is on the first portion 911 of the semiconductor structure 208, the insulating layer 203 (e.g., the third insulating layer) is on the second portion 912 of the semiconductor structure 208, and the gate structure 205 is on the insulating layer 203 at the interface 913 therebetween. In some embodiments, the bottom surface 914 of the insulating layer 203 is substantially coplanar with the back surface 502 of the semiconductor structure 208. In some embodiments, the conformal insulating layer 501 is on the bottom surface 914 of the insulating layer 203. In some embodiments, the metallization feature 801 of the metallization layer 817 is a power delivery metallization feature (e.g., a backside power delivery feature) in contact with the metal via 212.

[0055] Fig.10 A cross-sectional side view of an integrated circuit device structure 1000 similar to transistor structure 900 after incorporation of transistor structure 900 into an integrated circuit die 1016 is shown, arranged in accordance with some embodiments of the present disclosure. Fig.10 , the transistor structure 900 is shown in an expanded view 1019. As shown, any number of front metallization layers 1091, including metallization layer 217, can be formed above the device layer 215. For example, interconnection, signal routing, optional power delivery, etc. can be provided by the front metallization layer 1091. As used herein, the term metallization layer represents a metal interconnect or wire that provides electrical routing. Adjacent metallization layers (such as metallization interconnects 1092) are interconnected by vias (such as vias 1093), and vias 1093 can be characterized as a part of a metallization layer or between metallization layers. As shown, in some embodiments, the front metallization layer 1091 is formed above the transistor structure 900 and is adjacent to the transistor structure 900. In the example shown, the front metallization layer 1091 includes M0, V0, M1, M2 / V1, M3 / V2, and M4 / V3. However, the front metallization layer 1091 can include any number of metallization layers, such as six, eight or more metallization layers.

[0056] In addition, a back metallization layer 1001 including a metallization layer 817 can be formed below the device layer 215. For example, power delivery, optional additional interconnections, and wiring to external devices (not shown) can be provided by the back metallization layer 1001. As shown, in some embodiments, the back metallization layer 1001 is formed above the transistor structure 900 and is adjacent to the transistor structure 900. In the example shown, the back metallization layer 1001 includes BM0, BM1, and BM2 with an intermediate via layer. However, the back metallization layer 1001 can include any number of metallization layers, such as three, four, or more metallization layers. In the example shown, a package-level interconnect 1006 is provided on or below the back side 223 as a bump above the passivation layer 1005. However, any suitable interconnect structure (such as a bonding pad, a solder bump, etc.) can be used to provide a package-level interconnect 1006. In some embodiments, the integrated circuit die 1016 includes any transistor structure discussed herein, and the integrated circuit die 1016 is coupled to a power source / battery 1015, which can be any suitable power supply device or component. Additionally or alternatively, the integrated circuit die 1016 can be coupled to other devices, such as a display, a peripheral device, or the like. For example, the integrated circuit die 1016 can be coupled to any of the components discussed below.

[0057] Fig.11An exemplary system using a transistor structure with a field effect transistor with a back passivation layer according to some embodiments is shown. For example, the system can be a mobile computing platform 1105 and / or a data server machine 1106. Either can use a monolithic IC die, for example, with a field effect transistor with a back passivation layer, as described elsewhere herein. The server machine 1106 can be any commercial server (for example, including any number of high-performance computing platforms that are arranged in a rack and networked together for electronic data processing), which in an exemplary embodiment includes an IC die assembly 1150 with a field effect transistor with a back passivation layer for removing trapped charge, as described elsewhere herein. The mobile computing platform 1105 can be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, etc. For example, the mobile computing platform 1105 can be any of a tablet computer, a smart phone, a laptop computer, etc., and can include a display screen (for example, a capacitive, inductive, resistive, or optical touch screen), a chip-level or package-level integrated system 1110, and a battery / power supply 1115. Although shown with respect to a mobile computing platform 1105 , in other examples, the chip-level or package-level integrated system 1110 and the battery / power supply 1115 may be implemented in a desktop computing platform, an automotive computing platform, an Internet of Things platform, etc. As discussed below, in some examples, the disclosed system may include a subsystem 1160 , such as a system on a chip (SOC) or an integrated system of multiple ICs, which is shown with respect to a mobile computing platform 1105 .

[0058] Whether disposed within the integrated system 1110 shown in the expanded view 1120 or as a stand-alone packaged device within the data server machine 1106, the subsystem 1160 may include a memory circuit system and / or a processor circuit system 1140 (e.g., RAM, a microprocessor, a multi-core microprocessor, a graphics processor, etc.), a power management integrated circuit (PMIC) 1130, a controller 1135, and a radio frequency integrated circuit (RFIC) 1125 (e.g., including a broadband RF transmitter and / or receiver (TX / RX)). As shown, one or more IC dies (such as the memory circuit system and / or the processor circuit system 1140) may be assembled and implemented so that one or more IC dies have a back passivation layer for removing trapped charge, as described herein. In some embodiments, the RFIC 1125 includes a digital baseband and an analog front end module, which also includes a power amplifier on the transmit path and a low noise amplifier on the receive path. Functionally, PMIC 1130 may perform battery power regulation, DC to DC conversion, etc., and thus has an input coupled to battery / power source 1115, and an output that provides current supply to other functional modules. Fig.11As further shown in the , in an exemplary embodiment, the RFIC 1125 has an output coupled to an antenna (not shown) to implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The memory circuit system and / or the processor circuit system 1140 can provide memory functions for the subsystem 1160, provide high-level control for the subsystem 1160, data processing, etc. In an alternative embodiment, each of the SoC modules can be integrated into a separate IC coupled to a package substrate, interposer, or board.

[0059] Fig.12 1 is a functional block diagram of an electronic computing device 1200 according to some embodiments. For example, the device 1200 may implement a field effect transistor and a back passivation layer for removing trapped charge, as discussed herein, via any suitable components therein. For example, one or more IC dies of the electronic computing device 1200 may deploy a field effect transistor and a back passivation layer for removing trapped charge from the semiconductor structure of the field effect transistor. The device 1200 also includes a motherboard or packaging substrate 1202 that hosts multiple components, such as, but not limited to, a processor 1204 (e.g., an application processor). The processor 1204 may be physically and / or electrically coupled to the packaging substrate 1202. In some examples, the processor 1204 is within an IC assembly. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that may be further stored in registers and / or memory.

[0060] In various examples, one or more communication chips 1206 may also be physically and / or electrically coupled to the packaging substrate 1202. In further implementations, the communication chip 1206 may be part of the processor 1204. The computing device 1200 may include other components that may or may not be physically and electrically coupled to the packaging substrate 1202, depending on its application. These other components include, but are not limited to, volatile memory (e.g., DRAM 1232), non-volatile memory (e.g., ROM 1235), flash memory (e.g., NAND or NOR), magnetic memory (MRAM 1230), graphics processor 1222, digital signal processor, cryptographic processor, chipset 1212, antenna 1225, touch screen display 1215, touch screen controller 1265, battery / power supply 1216, audio codec, video codec, power amplifier 1221, global positioning system (GPS) device 1240, compass 1245, accelerometer, gyroscope, speaker 1220, camera 1241, and mass storage devices (such as hard disk drives, solid-state drives (SSDs), compact disks (CDs), digital versatile disks (DVDs), etc.), etc.

[0061] The communication chip 1206 can implement wireless communications for transmitting data to and from the computing device 1200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data via non-solid media using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 1206 can implement any of a plurality of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, the computing device 1200 may include multiple communication chips 1206. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc. The battery / power supply 1216 may include any suitable power supply circuit system, and optionally a battery source to provide power to the components of the electronic computing device 1200.

[0062] Although certain features set forth herein have been described with reference to various embodiments, this description is not intended to be interpreted in a limiting sense. Therefore, various modifications of the embodiments described herein and other embodiments that are obvious to those skilled in the art to which the present disclosure belongs are deemed to be within the spirit and scope of the present disclosure.

[0063] It will be appreciated that the invention is not limited to the embodiments thus described but may be practiced with modifications and alterations without departing from the scope of the appended claims.For example, the embodiments described above may include specific combinations of features as further provided below.

[0064] The following relates to exemplary embodiments.

[0065] In one or more first embodiments, a device includes: a transistor, the transistor including a semiconductor structure extending between a source structure and a drain structure, and a gate structure above a channel region of the semiconductor structure; a via extending from front metallization above the transistor to back metallization below the transistor; a first insulating layer on the back side of the semiconductor structure, and a second insulating layer on the first insulating layer.

[0066] In one or more second embodiments, further with respect to the first embodiment, the first insulating layer includes one or more of silicon, carbon, oxygen and nitrogen.

[0067] In one or more third embodiments, further with respect to the first or second embodiment, the first insulating layer includes silicon and nitrogen, or aluminum and oxygen.

[0068] In one or more fourth embodiments, further with respect to the first to third embodiments, the first insulating layer includes silicon and nitrogen, and the second insulating layer includes silicon and oxygen, so that the first insulating layer has a thickness of no greater than 10 nm.

[0069] In one or more fifth embodiments, further with respect to the first to fourth embodiments, a thickness of the semiconductor structure between a back surface of the semiconductor structure and a front surface of the semiconductor structure is not greater than 100 nm.

[0070] In one or more sixth embodiments, further with respect to the first to fifth embodiments, the device further includes an insulating pad adjacent to the via hole, wherein a portion of the first insulating layer is on a sidewall of the insulating pad.

[0071] In one or more seventh embodiments, further with respect to the first to sixth embodiments, a bottom surface of the second insulating layer is substantially coplanar with a bottom surface of the via.

[0072] In one or more eighth embodiments, further with respect to the first to seventh embodiments, the gate structure is on a first portion of the semiconductor structure, a third insulating layer is on a second portion of the semiconductor structure, and the gate structure is on the third insulating layer, and a bottom surface of the third insulating layer is substantially coplanar with a bottom surface of the semiconductor structure, and the first insulating layer is on a bottom surface of the third insulating layer.

[0073] In one or more ninth embodiments, further to the first to eighth embodiments, the back side metallization includes a power delivery metallization feature in contact with the via.

[0074] In one or more tenth embodiments, a system includes an IC die including the device according to any one of the first to ninth embodiments, and a power source and / or a display coupled to the IC die.

[0075] In one or more eleventh embodiments, a system includes an integrated circuit (IC) die, the integrated circuit die including a transistor, the transistor including a semiconductor structure extending between a source and a drain, and a gate on the front side of the semiconductor structure; a bridging via, the bridging via extending from the front side metal above the transistor to the back side metal below the transistor; a conformal insulating layer, the conformal insulating layer on the back side of the semiconductor structure; and an insulating fill layer, the insulating fill layer on the conformal insulating layer; and a power supply and / or display coupled to the IC die.

[0076] In one or more twelfth embodiments, further with respect to the eleventh embodiment, the conformal insulating layer includes silicon and nitrogen, and the insulating filling layer includes silicon and oxygen, so that the conformal insulating layer has a thickness of no greater than 10 nm.

[0077] In one or more thirteenth embodiments, further directed to the eleventh or twelfth embodiment, a thickness of the semiconductor structure between the front side of the semiconductor structure and the back side of the semiconductor structure is not greater than 100 nm.

[0078] In one or more fourteenth embodiments, further with respect to the eleventh to thirteenth embodiments, the system also includes an insulating pad adjacent to the bridging via, wherein a portion of the conformal insulating layer is on a sidewall of the insulating pad, and a bottom surface of the insulating filling layer is substantially coplanar with a bottom surface of the bridging via.

[0079] In one or more fifteenth embodiments, further with respect to the eleventh to fourteenth embodiments, the gate is on a first portion of the semiconductor structure, a second insulating filling layer is on a second portion of the semiconductor structure, and the gate is on the second insulating filling layer, and a bottom surface of the second insulating filling layer is substantially coplanar with a bottom surface of the semiconductor structure, and the conformal insulating layer is on a bottom surface of the second insulating filling layer.

[0080] In one or more sixteenth embodiments, a method includes: exposing a back side of a semiconductor structure, wherein the semiconductor structure extends between a source structure and a drain structure, and a gate structure is coupled to the semiconductor structure; etching at least a portion of the semiconductor structure through the exposed back side of the semiconductor structure to form a surface of the semiconductor structure; forming a first insulating layer on the surface of the semiconductor structure; performing ozone and ultraviolet annealing on the first insulating layer; and forming a second insulating layer above the first insulating layer.

[0081] In one or more seventeenth embodiments, further directed to the sixteenth embodiment, the first insulating layer includes one or more of silicon, carbon, oxygen, and nitrogen.

[0082] In one or more eighteenth embodiments, further with respect to the sixteenth or seventeenth embodiment, the first insulating layer includes silicon and nitrogen, and the second insulating layer includes silicon and oxygen, so that the first insulating layer has a thickness of no more than 10 nm.

[0083] In one or more nineteenth embodiments, further with respect to the sixteenth to eighteenth embodiments, the first insulating layer has a thickness not greater than 5 nm.

[0084] In one or more twentieth embodiments, further with respect to the sixteenth to nineteenth embodiments, a via extends from the front metallization above the semiconductor structure to a back surface of the via, and etching at least a portion of the semiconductor structure provides a back etch of the semiconductor structure such that the back surface of the via is below the surface of the semiconductor structure.

[0085] In one or more twenty-first embodiments, further with respect to the sixteenth to twentieth embodiments, forming a first insulating layer on the surface of the semiconductor structure further forms the first insulating layer on a sidewall of an insulating liner adjacent to the via hole.

[0086] It will be appreciated that the present invention is not limited to the embodiments described above, but can be practiced by modification and change without departing from the scope of the appended claims. For example, the above-described embodiments may include a specific combination of features. However, the above-described embodiments are not limited in this regard, and in various embodiments, the above-described embodiments may include only a subset of these features, a different order of these features, a different combination of these features, and / or additional features other than those features explicitly listed. Therefore, the scope of the present invention should be determined with reference to the full scope of the equivalent schemes enjoyed by the appended claims and these claims.

Claims

1. A device comprising: a transistor comprising a semiconductor structure extending between a source structure and a drain structure, and a gate structure over a channel region of the semiconductor structure; a via extending from the front metallization above the transistor to the back metallization below the transistor; a first insulating layer, the first insulating layer being on a back side of the semiconductor structure; as well as A second insulating layer is on the first insulating layer.

2. The device according to claim 1, wherein: The first insulating layer includes one or more of silicon, carbon, oxygen and nitrogen.

3. The device according to claim 1, wherein: The first insulating layer includes silicon and nitrogen, or aluminum and oxygen.

4. The device according to claim 1, wherein: The first insulating layer includes silicon and nitrogen, and the second insulating layer includes silicon and oxygen, wherein the first insulating layer has a thickness of not more than 10 nm.

5. The device according to claim 4, wherein: The thickness of the semiconductor structure between the back surface of the semiconductor structure and the front surface of the semiconductor structure is no greater than 100 nm.

6. The device according to any one of claims 1 to 5, further comprising an insulating pad adjacent to the via, wherein: A portion of the first insulating layer is on a sidewall of the insulating liner.

7. The device according to claim 6, wherein: A bottom surface of the insulating layer is substantially coplanar with a bottom surface of the via hole.

8. The device according to any one of claims 1 to 5, wherein: The gate structure is on a first portion of the semiconductor structure, a third insulating layer is on a second portion of the semiconductor structure, and the gate structure is on the third insulating layer, wherein a bottom surface of the third insulating layer is substantially coplanar with a bottom surface of the semiconductor structure, and the first insulating layer is on the bottom surface of the third insulating layer.

9. The device according to any one of claims 1 to 5, wherein: The backside metallization includes a power delivery metallization feature in contact with the via.

10. A system comprising: An integrated circuit (IC) die, the integrated circuit die comprising: a transistor comprising a semiconductor structure extending between a source and a drain, and a gate on a front side of the semiconductor structure; a bridging via extending from a front metal above the transistor to a back metal below the transistor; a conformal insulating layer on a back side of the semiconductor structure; and an insulating filling layer, the insulating filling layer being on the conformal insulating layer; and A power source is coupled to the IC die.

11. The system according to claim 10, wherein: The conformal insulating layer includes one or more of silicon, carbon, oxygen and nitrogen.

12. The system according to claim 10, wherein: The conformal insulating layer includes silicon and nitrogen, or aluminum and oxygen.

13. The system according to claim 10, wherein: The conformal insulating layer includes silicon and nitrogen, and the insulating filling layer includes silicon and oxygen, wherein the conformal insulating layer has a thickness of no greater than 10 nm.

14. The system according to claim 13, wherein: A thickness of the semiconductor structure between the front surface of the semiconductor structure and the back surface of the semiconductor structure is no greater than 100 nm.

15. The system of any one of claims 10 to 14, further comprising an insulating pad adjacent to the bridging via, wherein: A portion of the conformal insulating layer is on a sidewall of the insulating liner.

16. The system of claim 15, wherein: A bottom surface of the insulating filling layer is substantially coplanar with a bottom surface of the bridging via.

17. A system according to any one of claims 10 to 14, wherein: The gate is on a first portion of the semiconductor structure, a second insulating filling layer is on a second portion of the semiconductor structure, and the gate is on the second insulating filling layer, wherein a bottom surface of the second insulating filling layer is substantially coplanar with a bottom surface of the semiconductor structure, and the conformal insulating layer is on the bottom surface of the second insulating filling layer.

18. The system according to any one of claims 10 to 14, wherein: The backside metal includes power delivery metallization features in contact with the via.

19. A method comprising: exposing a backside of a semiconductor structure, wherein the semiconductor structure extends between the source structure and the drain structure and a gate structure is coupled to the semiconductor structure; etching at least a portion of the semiconductor structure through an exposed backside of the semiconductor structure to form a surface of the semiconductor structure; forming a first insulating layer on the surface of the semiconductor structure; performing ozone and UV annealing on the first insulating layer; and A second insulating layer is formed over the first insulating layer.

20. The method according to claim 19, wherein: The first insulating layer includes one or more of silicon, carbon, oxygen and nitrogen.

21. The method according to claim 19, wherein: The first insulating layer includes silicon and nitrogen, and the second insulating layer includes silicon and oxygen, wherein the first insulating layer has a thickness of not more than 10 nm.

22. The method according to claim 21, wherein: The first insulating layer has a thickness of no greater than 5 nm.

23. The method according to any one of claims 19 to 22, wherein: A via extends from front side metallization over the semiconductor structure to a back side surface of the via, and wherein etching at least a portion of the semiconductor structure provides an etch back of the semiconductor structure such that the back side surface of the via is below the surface of the semiconductor structure.

24. The method according to claim 23, wherein: Forming the first insulating layer on the surface of the semiconductor structure further forms the first insulating layer on a sidewall of an insulating liner adjacent to the via hole.

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