Interconnect package, method of forming interconnect package, and power module

Abstract

The embodiment of the invention relates to an interconnection package, a method of forming the interconnection package and a power module. The interconnect package may include a first insulating layer, a source connection portion disposed on a surface of the first insulating layer and adapted to electrically connect the source pad to the substrate, a second insulating layer, and a gate connection portion disposed between the first insulating layer and the second insulating layer and adapted to electrically connect the gate pad to the substrate. Further, the second insulating layer has a plurality of gate openings and a plurality of source openings therethrough and wherein a first surface of the second insulating layer is configured to be attached to a surface of the first insulating layer such that a plurality of portions of the source connection portion are exposed from the plurality of source openings on a second surface of the second insulating layer opposite the first surface, and a plurality of portions of the gate connection portion are exposed from the plurality of gate openings on the second surface of the second insulating layer.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of power electronics, and more particularly, to an interconnect package, a method of forming an interconnect package, and a power module employing the interconnect package. Background Art

[0002] In recent years, the booming development of electric vehicles has driven the update and iteration of power semiconductor technology. At present, power modules based on power devices are widely used in the field of power electronics due to their advantages such as high switching speed, low loss and high thermal stability. Power devices occupy a core position in power electronic systems, and their reliability is the most important factor in determining the safe operation of the entire system.

[0003] Power devices are interconnected with external circuits through packaging. In the conventional packaging process of power modules, wire bonding and filling materials such as resin are used for interconnection and encapsulation. However, filling materials such as silicone gel may age faster over time or after cycle testing, resulting in decreased moisture and oxidation resistance and even insulation performance, which greatly reduces the interconnection reliability of the leads in the power module. Summary of the invention

[0004] In view of the above problems, an embodiment of the present disclosure aims to provide a solution for improving the reliability of interconnect packaging.

[0005] According to a first aspect of the present disclosure, an interconnect package is provided. The interconnect package includes a first insulating layer, a source connection portion disposed on a surface of the first insulating layer and adapted to electrically connect a source pad to a substrate, a second insulating layer, and a gate connection portion disposed between the first insulating layer and the second insulating layer and adapted to electrically connect a gate pad to a substrate. The second insulating layer has a plurality of gate openings and a plurality of source openings extending therethrough and wherein a first surface of the second insulating layer is configured to be attached to a surface of the first insulating layer, so that a plurality of portions of the source connection portion are exposed from the plurality of source openings on a second surface of the second insulating layer opposite to the first surface, and a plurality of portions of the gate connection portion are exposed from the plurality of gate openings on a second surface of the second insulating layer opposite to the first surface.

[0006] In some embodiments of the first aspect, a plurality of portions of a gate connection portion exposed from bottom ends of a plurality of gate openings and a conductive trace not exposed from the plurality of gate openings are formed by depositing a conductive film on a first surface of a second insulating layer, wherein the plurality of portions of the gate connection portion include a gate pad connection portion for coupling with a gate pad, and a gate substrate connection portion for coupling with a substrate, and wherein the conductive trace electrically connects the gate pad connection portion and the gate substrate connection portion.

[0007] In some embodiments of the first aspect, the source connection portion is formed by a conductive sheet, wherein the multiple portions of the source connection portion include a source pad connection portion for coupling with a source pad, and a source substrate connection portion for coupling with a substrate, and wherein the source pad connection portion is electrically connected to the source substrate connection portion via a portion of the conductive sheet that is not exposed from the multiple source openings.

[0008] In some embodiments of the first aspect, a source pad connection portion and a source substrate connection portion are formed by patterning a conductive sheet, and wherein a thickness of the source pad connection portion is less than a thickness of the source substrate connection portion and greater than a thickness of a portion of the conductive sheet.

[0009] In some embodiments of the first aspect, a thickness of the source pad connecting portion is less than a depth of the plurality of source openings.

[0010] In some embodiments of the first aspect, a thickness of the source pad connecting portion is greater than or equal to a depth of the source opening.

[0011] In some embodiments of the first aspect, the source substrate connection portion is electrically connected to the substrate through a conductive pad.

[0012] In some embodiments of the first aspect, the gate-substrate connection portion is coupled to the substrate through a conductive pad.

[0013] In some embodiments of the first aspect, the second conductive film is deposited at bottom ends of the plurality of gate openings such that a portion of the second conductive film on the gate substrate connection portion has a greater thickness than a portion of the second conductive film on the gate pad portion.

[0014] According to a second aspect of the present disclosure, a method for forming an interconnect package is provided. The method includes: forming a source connection portion on a surface of a first insulating layer, the source connection portion being suitable for electrically connecting a source pad to a substrate; forming a second insulating layer, the second insulating layer having a plurality of gate openings and a plurality of source openings extending therethrough; forming a gate connection portion between the first insulating layer and the second insulating layer, the gate connection portion being suitable for electrically connecting the gate pad to the substrate; and attaching a first surface of the second insulating layer to a surface of the first insulating layer, so that a plurality of portions of the source connection portion are exposed from the plurality of source openings on a second surface of the second insulating layer opposite to the first surface, and a plurality of portions of the gate connection portion are exposed from the plurality of gate openings on a second surface of the second insulating layer opposite to the first surface.

[0015] According to a third aspect of the present disclosure, a power module is provided. The power module comprises: a substrate; a bare die on the substrate and comprising a source pad and a gate pad; and an interconnect package according to the first aspect of the present disclosure, the interconnect package covering the bare die and used to electrically connect the source pad and the gate pad of the bare die to the substrate, respectively.

[0016] The invention summary is provided to introduce a series of concepts in a simplified form, which will be further described in the specific embodiments below. The invention summary is not intended to identify the key features or essential features of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easy to understand through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0018] Figure 1 A shows a top view of a conventional power module interconnected by wire bonding;

[0019] Figure 1 B shows Figure 1 A is a perspective view of the power module shown.

[0020] Figure 1 C shows Figure 1 A is an electron microscope image of lead defects caused by package aging of a power module.

[0021] Figure 2 A shows a perspective view of a power device without interconnect packaging.

[0022] Figure 2 B shows Figure 2 A is a perspective view of a power device with an interconnect package attached.

[0023] Figure 2 C shows a perspective view of an interconnect package according to an embodiment of the present disclosure.

[0024] Figure 3 A shows a top view of a portion of a power device with an interconnect package attached according to an embodiment of the present disclosure.

[0025] Figure 3 B shows Figure 3 A is a cross-sectional view of the interconnect package and the power device along the AA' direction.

[0026] Figure 3 C shows Figure 3 A is a cross-sectional view of the interconnect package and the power device along the BB' direction.

[0027] Figure 4 An exploded view of an interconnect package according to a first embodiment of the present disclosure is shown.

[0028] Figure 5 Shows Figure 4 An enlarged perspective view of a portion of the interconnect package is shown.

[0029] Figure 6 A scanning electron microscope (SEM) image of a conductive film according to an embodiment of the present disclosure is shown.

[0030] Figure 7 An exploded view of an interconnect package according to a second embodiment of the present disclosure is shown.

[0031] Figure 8 A and Figure 8 B respectively shows the interconnection package according to the second embodiment of the present disclosure. Figure 3 Cross-sectional views along the AA' and BB' directions in A.

[0032] Fig. 9 Shows Figure 7 An enlarged perspective view of a portion of the interconnect package is shown.

[0033] Fig.10 An exploded view of an interconnect package according to a third embodiment of the present disclosure is shown.

[0034] Fig.11 An exploded view of an interconnect package according to a fourth embodiment of the present disclosure is shown.

[0035] Fig.12 Shows Fig.11 An enlarged perspective view of a portion of the interconnect package is shown.

[0036] Fig.13 A and Fig.13 B shows Fig.12 The interconnect package is shown as a cross-sectional view along the AA' direction and the BB' direction.

[0037] Fig.14 A flow chart of a process 600 of preparing an interconnect package 20 according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0038] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0039] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0040] Directional terms (such as "top", "bottom", "above", "below", "front", "rear", "head", "tail", "above", "below", etc.) may be used with reference to the orientation of the drawings and / or elements being described. Because embodiments may be positioned in a variety of different orientations, the directional terms are used for purposes of illustration and not limitation. In some instances, directional terms may be interchanged with equivalent directional terms based on the orientation of the embodiment as long as the general directional relationship between elements and their general purpose is maintained.

[0041] In the present disclosure, statements including serial numbers (such as "first", "second", etc.) may modify various elements. However, these elements are not limited to the above statements. For example, the above statements do not limit the order and / or importance of the elements. The above statements are only used to distinguish one element from other elements.

[0042] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0043] In the embodiments described herein or illustrated in the accompanying drawings, any direct electrical connection or coupling (i.e., any connection or coupling without additional intermediate elements) may also be implemented through an indirect connection or coupling (i.e., a connection or coupling with one or more additional intermediate elements), and vice versa, as long as the general purpose of the connection or coupling is essentially maintained.

[0044] As described above, conventional power module packaging processes use wire bonding interconnection and silicone gel injection for encapsulation. However, in some cases, silicone gel ages over time, which can cause moisture and oxidation resistance to decrease, greatly reducing the interconnection reliability of the wires in the power module.

[0045] Specifically, Figure 1 A and Figure 1 B shows a top view and a three-dimensional view of a conventional power module 1' interconnected by wire bonding. Figure 1 A and Figure 1 As shown in FIG. 1B , the power module 1′ includes a power device 10 and a source pad and a gate pad of the power device 10 (hereinafter referred to as Figure 2 Description) is electrically connected to the substrate (referenced below Figure 2 The leads 20' include a source lead and a gate lead, as shown by arrows in the figure.

[0046] After interconnection through wire bonding, the power module is encapsulated with resin to isolate the external environment and enable the power chip to operate reliably. In the field of power electronics, in addition to device characteristic characterization, reliability has become the most important quality assessment method and goal of power modules. As mentioned earlier, the performance of power devices requires the support of packaging. Therefore, during the reliability test, a certain degree of accelerated aging is used to expose the weaknesses of the device packaging in advance.

[0047] Figure 1 C shows an electron microscope image of defect spots on the lead of a conventional package after a thermal cycle test, as shown in the dotted box. Figure 1 In the case shown in C, defects in the metal leads may cause problems such as lead breakage and misalignment, thereby reducing the performance of the device.

[0048] According to an embodiment of the present disclosure, an interconnection package is proposed. By adopting a multi-layer insulating film and a non-wire bonding method for interconnection packaging, it performs well in the reliability test process and greatly improves the reliability of the power module. The various embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings. It should be understood that this is only for illustrative purposes and is not intended to limit the scope of the present invention in any way.

[0049] Figure 2 A shows a perspective view of the power device 10 . Figure 2 B shows Figure 2 A is a perspective view of a portion of a power device 10 with an interconnect package 20 attached. In some embodiments, Figure 2 A and Figure 2 The power device 10 in B and Figure 1 The structures of the power devices in the same or similar. Figure 2 As shown in FIG. 1A , the power device 10 includes a substrate 12 and a plurality of dies (not shown) formed on the substrate 12 . Each die includes a plurality of source pads 14 and gate pads 16 .

[0050] exist Figure 2In B, the interconnect package 20 is covered and attached to the power device 10 through a sintering process to form a circuit loop and package and protect the power device at the same time. The sintering process is usually completed by sintering a conductive paste (also known as a sintering paste). In some embodiments, the conductive paste is divided into carbon paste (graphite conductor), metal paste (gold powder, silver powder, copper powder or silver-copper alloy) and modified ceramic paste according to the different fillers therein. It should be understood that in other embodiments, the interconnect package 20 can be attached to the power device 10 in any other way, and the present disclosure is not limited to this.

[0051] Figure 2 C shows a perspective view of an interconnect package 20 according to an embodiment of the present disclosure. Figure 2 C, the interconnect package 20 includes a source connection portion 24 suitable for connecting the source pad 14 to the substrate 12, and a gate connection portion 26 suitable for connecting the gate pad 16 to the substrate 12. The source connection portion 24 includes a source pad connection portion 241 for coupling with the source pad 14 and a source substrate connection portion 242 for coupling with the substrate. The gate connection portion 26 includes a gate pad connection portion 261 for coupling with the gate pad 16 and a gate substrate connection portion 262 for coupling with the substrate. The following reference Figure 3 and Figure 4 The structure of the interconnect package 20 will be described in detail.

[0052] Figure 3 A shows a top view of a portion of a power module 1 according to an embodiment of the present disclosure. Figure 3 B and Figure 3 C shows Figure 3 A is a cross-sectional view of a portion of the power module 1 .

[0053] A plurality of bare chips are bonded to the substrate 12. Figure 3 In the cross section along the AA' direction shown in B, the gate pad 16 of the bare chip is exposed from the upper surface and is coupled to the gate pad connection portion 261 of the interconnect package 20 using the sintering paste 31. The gate substrate connection portion 262 of the interconnect package 20 is coupled to the substrate 12, and the substrate 12 is electrically connected to the gate pad 16 via the conductive trace 263 of the gate connection portion 26.

[0054] exist Figure 3 In the cross section along the BB' direction shown in FIG. C, the source pad 14 of the die is exposed from the upper surface and is coupled to the source pad connection portion 241 of the interconnect package 20 using the sintering paste 32. The source substrate connection portion 242 of the interconnect package 20 is coupled to the substrate 12 and is connected to the substrate 12 via a portion 243 of the source connection portion 24 (see FIG. Figure 4 ) to electrically connect the substrate 12 to the source pad 14.

[0055] Figure 4 An exploded view of an interconnect package 20 according to a first embodiment of the present disclosure is shown. The interconnect package 20 includes a first insulating layer 22, a second insulating layer 28, and a source connection portion 24 and a gate connection portion 26 between the first insulating layer 28 and the second insulating layer 22. The first insulating layer 22 and the second insulating layer 28 are both made of insulating materials, including but not limited to polyimide, silicone resin, thermoplastic resin, glass fiber, or any other material with high insulation and moisture-proof properties. An insulating adhesive 23 is applied on the first insulating layer 22 to attach the first insulating layer 22 to the second insulating layer 28.

[0056] The insulating adhesive includes, but is not limited to, epoxy resin, modified phenolic, polyurethane, anaerobic adhesive, inorganic adhesive and other attachment materials with insulating electrical properties. The second insulating layer 28 has a plurality of openings extending therethrough, and the openings extending through the second insulating layer 28 include a plurality of gate openings 284 and a plurality of source openings 286. The gate openings 284 include openings corresponding to the gate pad connection portion 261 and the gate substrate connection portion 262, and the source openings 286 include openings corresponding to the source pad connection portion 241 and the source substrate connection portion 242.

[0057] The first insulating layer 22 is attached to the second insulating layer 28 via the adhesive layer 23, and a portion 243 of the source connecting portion 24 and the conductive trace 263 of the gate connecting portion 26 are sandwiched in the stacked insulating layers, so that the source pad connecting portion 241 and the source substrate connecting portion 242 of the source connecting portion 24 are exposed from multiple source openings 286, and the gate pad connecting portion 261 and the gate substrate connecting portion 262 are exposed from multiple gate openings 284.

[0058] The source connection portion 24 is formed by a conductive sheet. The conductive sheet can be a copper sheet, an aluminum sheet, or other metal sheet. The pad connection portion 241 for coupling with the pad of the bare chip and a portion 243 of the source connection portion 24 are formed by patterning the conductive sheet. In some embodiments, the conductive sheet can be patterned using photolithography and etching. It should be understood that the unetched portion of the conductive sheet can be used as a substrate connection portion 241 for coupling with the substrate of the power device. In some embodiments, the substrate connection portion 241 can be formed by etching. In other embodiments, the conductive sheet can also be patterned by other methods such as stamping, which is not limited by the present disclosure.

[0059] In some embodiments, the source pad connection portion 241 is formed to have a thickness smaller than the source substrate connection portion 242 and larger than the portion 243 of the conductive sheet. In this case, when the first insulating layer 22 and the second insulating layer 28 are attached, the portion 243 of the conductive sheet is embedded in the adhesive 23 on the first insulating layer 22. In some embodiments, the thickness of the source pad connection portion 241 is equal to the depth of the source opening 286, so that after the attachment is completed, the surface of the source solder connection portion 241 is flush with the upper surface of the second insulating layer 28, as shown in FIG. Figure 5 shown. Figure 5 A partially enlarged portion of the interconnect package 20 is shown.

[0060] Back to Figure 4 , to describe the formation of the gate connection portion 26. In some embodiments, by depositing a conductive film on the lower surface of the second insulating layer 28, a gate pad connection portion 261 and a gate substrate connection portion 262 exposed from the gate opening 284, and a conductive trace 263 not exposed from the gate opening 284 are formed. In this case, the gate pad connection portion 261 and the gate substrate connection portion 262 are exposed from the bottom end of the gate opening 284. In other embodiments, the conductive film is continuously deposited at the bottom end of the gate opening 284 on one side of the upper surface of the second insulating layer 28, and the thickness of the conductive film on the gate substrate connection portion 262 is greater than the thickness of the conductive film on the gate pad connection portion 261.

[0061] The conductive film can be a metal or metal alloy, such as aluminum, copper, platinum, gold or any combination thereof. The conductive film can be deposited using any conventional method suitable for metals, such as sputtering, electroplating, thermal evaporation, atomic layer deposition (ALD) or chemical vapor deposition (CVD). The present disclosure is not limited in this regard.

[0062] Figure 6 A scanning electron microscope (SEM) image of a conductive film according to an embodiment of the present disclosure is shown. Figure 6 In the figure, taking metal copper as an example, a cross-sectional view of a portion of a copper film formed by growing a film is shown. It can be seen that the gate connection portion formed by the copper film is dense inside and has a smooth surface, which can prevent lead defects caused by aging of the molding material and improve the breakdown voltage of the device.

[0063] Return to reference Figure 5 , the surface of the gate pad connection portion 261 is also flush with the upper surface 281 of the second insulating layer. It should be understood that in some embodiments, the surfaces of the gate pad connection portion 261 and the source pad connection portion 241 may exceed the upper surface of the second insulating layer 28. Then, the interconnection package 20 is mounted on the power device 10 via the sintering paste to realize the interconnection between the source pad 24 and the gate pad 26 and the substrate 12 respectively.

[0064] Reference below Figure 7 The interconnect package 30 of the second embodiment of the present disclosure is described in detail. Figure 2-5 The interconnect package 20 shown has the same or similar structure. Figure 2-5 The various aspects described with respect to the interconnect package 20 may be applicable to Figure 7 In some embodiments, the structure of the interconnection package 30 is similar to the interconnection package 20, except that the thickness of the source pad connection portion 341 and the gate pad connection portion 361 are respectively less than the opening depth of the source opening 386 and the gate opening 384. Figure 7 Shown by the light-medium colored line.

[0065] In this case, the sintering paste 37 is filled in the source opening corresponding to the source pad connection portion 341 in the source opening 386 and in the gate opening corresponding to the gate pad connection portion 361 in the gate opening 384 by screen printing or spraying. In addition, a conductive pad 35 is provided at the gate opening corresponding to the gate substrate connection portion 362 of the gate opening 384. The conductive pad 35 is coupled to the gate substrate connection portion 362 via the sintering paste 37, and further electrically connects the gate substrate connection portion 362 to the substrate 12. In this way, the interconnect package 30 can be efficiently mounted on the power device 10 without the need to grow a conductive film on the upper surface of the second insulating layer 28.

[0066] Figure 8 A and Figure 8 B shows Figure 7 The interconnect package 30 is shown in cross-sectional views along the AA′ direction and the BB′ direction. Figure 8 A and Figure 8 The interconnect package 30 shown in B is Figure 3 A and Figure 3 The difference of the interconnect package 20 shown in B is that the thickness of the gate pad connection portion 361 and the source pad connection portion 341 is less than the depth of the gate opening and the source opening. In other words, the surface of the gate pad connection portion 361 and the source pad connection portion 341 is not flush with the upper surface of the second insulating layer 38. Fig. 9 Shows Figure 7 The partially enlarged perspective view of the interconnect package 30 is shown. Fig. 9 The above structure can be seen more clearly in .

[0067] Fig.10 An exploded view of an interconnect package 40 according to a third embodiment of the present disclosure is shown. Fig.10 The structure of the interconnect package 40 in Figure 7The structure of the interconnect package 30 in FIG. 4 is the same or similar, and the same elements are not repeated here. The interconnect package 40 is different from the interconnect package 30 in that the source connection portion 44 is directly formed by the conductive sheet and is not etched to form a source pad connection portion and a source substrate connection portion with different thicknesses. In some embodiments, the source pad connection portion and the source substrate connection portion have the same thickness and are both exposed from the bottom end of the source opening. Fig.10 The gate connection portion 46 of the interconnect package 40 described in Figure 7 The preparation process and structure of the gate connection portion 36 of the interconnect package 30 are the same.

[0068] As reference Figure 7 As described above, the sintering paste 47 is filled in the source opening corresponding to the source pad connection portion in the source opening 486 and in the gate opening corresponding to the gate pad connection portion 461 in the gate opening 484 by screen printing or spraying. In addition, a conductive pad 45 is provided at the gate opening corresponding to the gate substrate connection portion 462 of the gate opening 484. The conductive pad 45 is coupled to the gate substrate connection portion 462 via the sintering paste 47, and further electrically connects the gate substrate connection portion 462 to the substrate 12.

[0069] Likewise, in some embodiments, an additional conductive pad (not shown) is disposed at the source opening of the source opening 486 corresponding to the source substrate connection portion for coupling with the substrate 12 via the sintering paste 47 and electrically connecting the source substrate connection portion to the substrate 12 .

[0070] In this way, by providing an additional conductive pad to couple the source-substrate connection portion of the conductive sheet to the substrate, the etching process for the conductive sheet is omitted, thereby further improving the production efficiency of the interconnect package.

[0071] Fig.11 An exploded view of an interconnect package 50 according to a fourth embodiment of the present disclosure is shown. Fig.11 The structure of the interconnect package 50 shown in FIG. Figure 7 The structure of the interconnect package 30 shown is the same or similar, and the same elements will not be described again. The interconnect package 50 is different from the interconnect package 30 in that a portion 55 of the gate connection portion 56 overlaps a portion of the source connection portion 54 in a vertical direction perpendicular to the surface of the interconnect package. In this case, in order to avoid the breakdown of the power device when a voltage is applied, a third insulating layer 59 is inserted between the first insulating layer 52 and the second insulating layer 58, so that the gate connection portion 56 is sandwiched between the second insulating layer 58 and the third insulating layer 59. Fig.11As shown, the third insulating layer 59 has a plurality of additional source openings 596 for accommodating the source pad connection portion 541 and the source substrate connection portion 542 of the source connection portion 54 .

[0072] Thus, the first insulating layer 52, the second insulating layer 58 and the third insulating layer are attached in sequence to form Fig.12 The interconnect package 50 shown. The gate pad connection portion 561 and the gate substrate connection portion 562 of the gate connection portion 56 are exposed from the gate opening 584 of the second insulating layer 58, and a portion 55 of the gate connection portion 56 that vertically overlaps with the source connection portion 54 is separated from the source connection portion 54 via the third insulating layer 59. In some embodiments, the gate connection portion 56 is formed on the upper surface of the third insulating layer 59 by growing a conductive film. It should be understood that the gate connection portion 56 can also be grown on the lower surface of the second insulating layer 58 in the same growth manner as in the aforementioned embodiment. In this way, when optimizing the wiring layout, even if the gate connection portion 56 partially overlaps with the source connection portion 54 in the vertical direction, the power module 1 can still operate with excellent performance.

[0073] Fig.13 They are shown respectively Fig.12 The interconnect package 50 is shown in cross-sectional views along the AA′ direction and the BB′ direction. Fig.13 A and Fig.13 The interconnect package 50 shown in B is Figure 8 A and Figure 8 The interconnect package 30 shown in FIG. 3 is different in that a portion 55 of the gate connection 56 vertically overlaps the source connection 54. The portion 55 of the gate connection 56 is separated from the source connection 54 by a third insulating layer 59, so that the power device is not easily broken down during operation.

[0074] Fig.14 FIG. 6 is a flowchart of a process 600 for preparing an interconnect package 20 according to an embodiment of the present disclosure. Figure 2 and Figure 4 Flow 600 will be described.

[0075] At block 602, a source connection portion 24 is formed on the first insulating layer 22 via an insulating adhesive 23. The source connection portion 24 is adapted to electrically connect the source pad to the substrate. The source connection portion 24 includes a source pad connection portion 241 for coupling with the source pad 14 and a source substrate connection portion 242 for coupling with the substrate 12. The specific formation process of the source connection portion 24 is described in detail in Figure 4 The details are introduced in the description of , so I will not repeat them here.

[0076] At block 604, a second insulating layer 28 is formed having a plurality of gate openings 284 and a plurality of source openings 288 therethrough. The gate openings 284 and source openings 286 are used to accommodate gate connections 26 (see block 606) and source connections 24, respectively.

[0077] In block 606, a conductive film is deposited on the lower surface of the second insulating layer 28 to form a gate pad connection portion 261 and a gate substrate connection portion 262 exposed from the gate opening 284, and a conductive trace 263 not exposed from the gate opening 284. In some embodiments, the conductive film is continuously deposited in the gate opening on one side of the upper surface of the second insulating layer 28, so that the thickness of the conductive film on the gate substrate connection portion 262 is greater than the thickness of the conductive film on the gate pad connection portion 261. The method and material for forming the conductive film are the same as those described in the aforementioned reference. Figure 4 The contents described are the same or similar and will not be repeated here.

[0078] In frame 608, the lower surface of the second insulating layer 208 is attached to the surface of the first insulating layer 22, so that multiple portions of the source connection portion 24 are exposed from the multiple source openings 286 on the upper surface of the second insulating layer opposite to the lower surface, and multiple portions of the gate connection portion 26 are exposed from the multiple gate openings 284 on the upper surface of the second insulating layer 28.

[0079] It should be understood that the above processes can be completed sequentially or in parallel in any reasonable order.

[0080] It should also be understood that the interconnect package produced by the above process can be used in a power module such as an automotive system electronic control unit. In some embodiments, the power module can include at least one interconnect package as described in the above embodiments and combinations thereof.

[0081] Although the subject matter has been described using language specific to structural features, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

[0082] Without prejudice to the essential principles, the details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without departing from the scope of protection.

Claims

1. An interconnect package, comprising: a first insulating layer; a source connection portion on a surface of the first insulating layer and adapted to electrically connect the source pad to a substrate; a second insulating layer having a plurality of gate openings and a plurality of source openings penetrating the second insulating layer; a gate connecting portion, adapted to electrically connect the gate pad to the substrate and located between the first insulating layer and the second insulating layer; and The first surface of the second insulating layer is configured to be attached to the surface of the first insulating layer so that multiple portions of the source connecting portion are exposed from the multiple source openings on a second surface of the second insulating layer opposite to the first surface, and multiple portions of the gate connecting portion are exposed from the multiple gate openings on the second surface of the second insulating layer.

2. The interconnect package according to claim 1 , wherein the portions of the gate connection portions exposed from bottom ends of the plurality of gate openings and the conductive traces not exposed from the plurality of gate openings are formed by depositing a conductive film on the first surface of the second insulating layer, wherein the plurality of portions of the gate connection portion include a gate pad connection portion for coupling with a gate pad, and a gate substrate connection portion for coupling with the substrate, and wherein the conductive trace electrically connects the gate pad connection portion and the gate substrate connection portion.

3. The interconnect package of claim 2 , wherein the source connection portion is formed by a conductive sheet, wherein the plurality of portions of the source connection portion include a source pad connection portion for coupling with the source pad, and a source substrate connection portion for coupling with the substrate, and The source pad connection portion is electrically connected to the source substrate connection portion via a portion of the conductive sheet that is not exposed from the plurality of source openings.

4. The interconnect package according to claim 3, wherein the source pad connection portion and the source substrate connection portion are formed by patterning the conductive sheet, and The thickness of the source pad connection portion is smaller than the thickness of the source substrate connection portion and is larger than the thickness of the portion of the conductive sheet. 5 . The interconnect package of claim 4 , wherein a thickness of the source pad connection portion is less than a depth of the plurality of source openings. 6 . The interconnect package of claim 4 , wherein a thickness of the source pad connection portion is greater than or equal to a depth of the source opening. 7 . The interconnect package of claim 3 , wherein the source substrate connection portion is electrically connected to the substrate through a conductive pad.

8. The interconnect package of claim 5 or 7, wherein the gate-substrate connection portion is coupled to the substrate through a conductive pad.

9. The interconnect package of claim 6, wherein a second conductive film is deposited at the bottom ends of the plurality of gate openings such that a portion of the second conductive film on the gate substrate connection portion has a greater thickness than a portion of the second conductive film on the gate pad portion.

10. The interconnect package according to any one of the preceding claims, wherein the interconnect package further comprises a third insulating layer located between the first insulating layer and the gate connection and comprising the plurality of source openings extending through the third insulating layer.

11. A method of forming an interconnect package, comprising: forming a source connection portion on a surface of the first insulating layer, the source connection portion being adapted to electrically connect the source pad to the substrate; forming a second insulating layer having a plurality of gate openings and a plurality of source openings extending therethrough; forming a gate connection portion between the first insulating layer and the second insulating layer, the gate connection portion being adapted to electrically connect a gate pad to the substrate; as well as The first surface of the second insulating layer is attached to the surface of the first insulating layer so that multiple portions of the source connecting portion are exposed from the multiple source openings on a second surface of the second insulating layer opposite to the first surface, and multiple portions of the gate connecting portion are exposed from the multiple gate openings on the second surface of the second insulating layer.

12. The method according to claim 11, wherein forming the gate connection portion comprises depositing a conductive film on the first surface of the second insulating layer to form the plurality of portions of the gate connection portion exposed from bottom ends of the plurality of gate openings and conductive traces not exposed from the plurality of gate openings, wherein the plurality of portions of the gate connection portion include a gate pad connection portion for coupling with a gate pad, and a gate substrate connection portion for coupling with the substrate, and wherein the conductive trace electrically connects the gate pad connection portion and the gate substrate connection portion.

13. The method of claim 12, wherein forming the source connection comprises forming the source connection from a conductive sheet, wherein the plurality of portions of the source connection portion include a source pad connection portion for coupling with the source pad, and a source substrate connection portion for coupling with the substrate, and The source pad connection portion is electrically connected to the source substrate connection portion via a portion of the conductive sheet that is not exposed from the plurality of source openings.

14. The method according to claim 13, forming the source connection portion further comprises: The source pad connection portion and the source substrate connection portion are formed by patterning the conductive sheet, and The thickness of the source pad connection portion is smaller than the thickness of the source substrate connection portion and is larger than the thickness of the portion of the conductive sheet. 15 . The method of claim 14 , wherein the source pad connection portion is formed to have a thickness smaller than a depth of the plurality of source openings. 16 . The method of claim 14 , wherein the source pad connection portion is formed to have a thickness greater than or equal to a depth of the plurality of source openings.

17. The method of claim 13, wherein the source substrate connection portion is electrically connected to the substrate through a conductive pad.

18. The method of claim 15 or 17, wherein the gate-substrate connection portion is coupled to the substrate through a conductive pad.

19. The method according to claim 16, wherein forming the gate connection portion further comprises: A second conductive film is deposited at the bottom ends of the plurality of gate openings such that a portion of the second conductive film on the gate substrate connection portion has a greater thickness than a portion of the second conductive film on the gate pad portion.

20. The method according to claim 15 further comprises filling adhesive in source openings corresponding to the source pad connection portion among the plurality of source openings and in gate openings corresponding to the gate pad connection portion among the plurality of gate openings by screen printing or spraying.

21. The method of any preceding claim, further comprising forming a third insulating layer between the first insulating layer and the gate connection, the third insulating layer comprising the plurality of source openings extending through the third insulating layer.

22. A power module comprising substrate; a bare die on the substrate and including a source pad and a gate pad; The interconnect package according to any one of claims 1 to 10, wherein the interconnect package covers the die and is used to electrically connect the source pad and the gate pad of the die to the substrate, respectively.

23. The power module of claim 22, wherein the interconnect package is attached to the substrate by an adhesive.

24. The power module of claim 22, further comprising a molding material for encapsulating the substrate, the die, and the interconnect package together.

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