Semiconductor element
By designing metal oxide semiconductor transistors, contact regions and protection diodes in semiconductor components, using doping regions and protection rings of different conductive types, the problem of the size of integrated circuits increasing in electrostatic discharge is solved, and high voltage resistance is achieved ESD protection without increasing silicon chip area.
Patent Information
- Application Number
- CN202310777424.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-28
- Publication Date
- 2024-12-31
AI Technical Summary
In deep sub-micron complementary metal oxide semi-transistor technology, integrated circuits are susceptible to electrostatic discharge damage, and existing ESD protection circuit designs require larger component sizes to withstand high voltages, resulting in an increase in silicon chip area.
A semiconductor element is designed, including a metal oxide semiconductor transistor, a contact region and a protection diode, providing a gentle breakdown voltage protection during heavy pressurization through doped regions and protection rings of different conductive types.
It effectively reduces the component size of the ESD protection circuit, reduces the area of the silicon chip, and maintains a voltage resistance of more than 2,000 volts, protecting the integrated circuit from electrostatic discharge damage.
Smart Images
Figure CN119230541A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device, and more particularly to a protection device that provides a milder breakdown voltage during heavy charging. Background Art
[0002] As the size of semiconductor integrated circuit devices continues to shrink, in the sub-micron complementary metal oxide semiconductor (CMOS) technology, shallower junction depth, thinner gate oxide thickness, lightly doped drain (LDD), shallow trench isolation (STI) and self-aligned silicide structures or manufacturing processes have become standard manufacturing processes. However, the above structures or manufacturing processes make integrated circuit products more susceptible to electrostatic discharge (ESD) damage, so ESD protection circuit design must be added to the chip to protect the integrated circuit from ESD damage. Generally, integrated circuit products on the market must have a withstand voltage of at least 2000 volts in the human body model (HBM). In order to withstand such a large ESD voltage, the ESD protection circuit must be designed to have a sufficiently large component size, thereby increasing the area occupied by the silicon chip. Summary of the invention
[0003] An embodiment of the present invention discloses a semiconductor element or more specifically a protection element that can provide a softer breakdown voltage during heavy charging, which mainly includes a first metal oxide semiconductor transistor disposed on a substrate, a pickup region disposed on one side of the first metal oxide semiconductor transistor, and a protection diode disposed on the other side of the first metal oxide semiconductor transistor, wherein the first metal oxide semiconductor transistor further includes a first gate structure disposed on the substrate and a first source / drain region disposed on both sides of the first gate structure, the protection diode is electrically connected to the first gate structure, and the pickup region and the protection diode include different conductivity types. BRIEF DESCRIPTION OF THE DRAWINGS
[0004] Figure 1 It is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention;
[0005] Figure 2 is a top view of a semiconductor device according to an embodiment of the present invention;
[0006] Figure 3 for Figure 2 A schematic cross-sectional view of a semiconductor element;
[0007] Figure 4 is a top view of a semiconductor device according to an embodiment of the present invention;
[0008] Figure 5 for Figure 4 A schematic cross-sectional view of a semiconductor element;
[0009] Figure 6 It is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention;
[0010] Figure 7 It is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention;
[0011] Figure 8 is a top view of a semiconductor device according to an embodiment of the present invention;
[0012] Fig. 9 for Figure 8 A schematic cross-sectional view of a semiconductor element;
[0013] Fig.10 is a top view of a semiconductor device according to an embodiment of the present invention;
[0014] Fig.11 for Fig.10 Schematic diagram of the cross section of a semiconductor component.
[0015] Main component symbols
[0016] 12: Base
[0017] 14: MOS transistor
[0018] 16: Contact area
[0019] 18: Protection diode
[0020] 20: Interlayer dielectric layer
[0021] 22: P trap
[0022] 24: Shallow Trench Isolation
[0023] 26: Gate structure
[0024] 28: Gate dielectric layer
[0025] 30: Gate electrode
[0026] 32: Lightly doped drain
[0027] 34: Source / Drain Region
[0028] 36: Contact plug
[0029] 38:Metal interconnect
[0030] 42: Doping area
[0031] 44: Doping area
[0032] 46: Doping area
[0033] 48: Doping area
[0034] 50: Doping area
[0035] 52: Doping area
[0036] 54: Protection ring
[0037] 56:NMOS transistor
[0038] 58:PMOS transistor
[0039] 60: N well
[0040] 62: Doping area
[0041] 64: Doping area
[0042] 66: Doping area
[0043] 68: Doping area
[0044] 70: Silicide metal barrier layer DETAILED DESCRIPTION
[0045] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the structure of a semiconductor element according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon germanium composite, silicon carbide, gallium arsenide, etc. Then, a metal-oxide semiconductor (MOS) transistor 14, a pickup region 16 on one side of the MOS transistor 14, a protection diode 18 on the other side of the MOS transistor 14, and a dielectric layer such as an interlayer dielectric (ILD) 20 covering the substrate 12 are formed, wherein the substrate further includes a well region such as a P-well 22 disposed under each MOS transistor 14, the pickup region 16, and the protection diode 18, and a shallow trench isolation (STI) 24 to separate the MOS transistor 14, the pickup region 16, and the protection diode 18.
[0046] More specifically, the substrate 12 may include planar or non-planar transistor elements (such as fin-shaped structure transistors), wherein the MOS transistor 14 may include a gate structure 26 disposed on the substrate 12, spacers (not shown) disposed on both sides of the gate structure 26, a lightly doped drain 32 and a source / drain region 34 disposed in the substrate 12 on both sides of the gate structure 26, and a selective epitaxial layer and a metal silicide disposed on the surface of the source / drain region 34. In the present embodiment, the lightly doped drain 32 preferably includes an N-type lightly doped drain or NLDD and the source / drain region 34 includes an N+ doped region.
[0047] In the present embodiment, the gate structure 26 may include a gate dielectric layer 28 and a gate electrode 30, wherein the gate dielectric layer 28 preferably includes silicon oxide and the gate electrode 30 may include polysilicon or a metal material. Although the gate structure 26 of the present embodiment takes the gate electrode 30 formed of polysilicon as an example, it is not limited thereto. According to other embodiments of the present invention, the gate structure 26 formed of polysilicon may be converted into a metal gate including a work function metal material according to a replacement metal gate (RMG) manufacturing process, and this variation also falls within the scope of the present invention. Since converting a polysilicon gate into a metal gate according to the RMG manufacturing process is a well-known technique in the art, it will not be further described here.
[0048] In addition, the spacer may include a single spacer or a composite spacer, for example, the spacer may include an offset spacer (not shown) and a main spacer (not shown), and the spacer may be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride, but is not limited thereto. The source / drain region 34 and the epitaxial layer may include different dopants or different materials according to the conductivity type of the transistor to be prepared. For example, the source / drain region 34 may include P-type dopants or N-type dopants, and the epitaxial layer may include silicon germanium, silicon carbide or silicon phosphide.
[0049] The interlayer dielectric layer 20 may be disposed on the substrate 12 and cover each MOS transistor 14, and a plurality of contact plugs 36 may be disposed in the interlayer dielectric layer 20 to electrically connect the source / drain regions 34 of the transistor. Then, a metal interconnection manufacturing process is performed to form an intermetallic dielectric layer (not shown) on the interlayer dielectric layer 20, and metal interconnections 38 are embedded in the intermetallic dielectric layer and electrically connected to the contact plugs 36. In the present embodiment, the contact plugs 36 and / or the metal interconnects 38 may be embedded in the interlayer dielectric layer 20 and / or the intermetallic dielectric layer on the interlayer dielectric layer 20 according to a single damascene process or a dual damascene process, wherein each of the contact plugs 36 and / or the metal interconnects 38 may further include a barrier layer and a metal layer, wherein the barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the metal layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but not limited thereto. Since the related manufacturing processes of planar or non-planar transistors and metal interconnects are well known in the art, they are not further described here.
[0050] In the present embodiment, the contact region 16 disposed on one side of the MOS transistor 14, such as the left side, preferably includes at least one doping region, such as a doping region 42 and a doping region 44, wherein each doping region 42, 44 and the source / drain region 34 in the MOS transistor 14 preferably include dopants of different conductive types. For example, the doping region 42 disposed on the top of the present embodiment preferably includes a P-type lightly doped drain or PLDD with a lower concentration, while the doping region 44 below includes a P+ doping region with a higher concentration, and the concentrations of both are greater than the concentration of the P-well 22. It should be noted that although the contact region 16 of the present embodiment takes two doping regions 42 and 44 as an example, it is not limited thereto. According to other embodiments of the present invention, only a single doping region, such as a P+ doping region, may be formed in the contact region 16, and this variation also falls within the scope of the present invention.
[0051] In addition, the protection diode 18 disposed on the other side of the MOS transistor 14, such as the right side, includes a doping region 46 disposed in the substrate 12 and another doping region 48 disposed on the doping region 46, wherein the doping region 46 disposed at the bottom and the doping regions 42 and 44 of the contact region 16 preferably include the same conductivity type, but the concentration of the doping region 46 is slightly higher than the concentration of the doping region 44, for example, the doping region 46 preferably includes a P++ doping region. The doping region 48 at the top includes a different conductivity type from the doping region 46 at the bottom or includes the same conductivity type as the source / drain region 34 of the MOS transistor 14, but the concentration of the doping region 48 is slightly higher than the concentration of the source / drain region 34, for example, the doping region 48 preferably includes an N++ doping region.
[0052] Please continue to refer to Figures 2 to 3 , Figures 2 to 3 FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention, wherein Figure 2 For a top view of a semiconductor device Figure 3 Then Figure 2 In order to correspond to the above embodiments, the same elements as those in the above embodiments are preferably labeled with the same reference numerals in this embodiment and the following embodiments, and in order to make the illustration more concise, the hatching lines are omitted in the top views of the following embodiments. Figures 2 to 3 As shown, compared to Figure 1 The protection diode 18 in the embodiment only includes the doping region 46 and the doping region 48. The protection diode 18 in the present embodiment further includes a protection ring 54 formed by doping regions 50 and 52 surrounding the doping regions 46 and 48, wherein the doping regions 50 and 52 preferably include the same conductivity type as the doping region 46 below, but the concentration of the doping region 50 is preferably slightly lower than the concentration of the doping region 52, and the concentration of the doping region 52 is slightly lower than the concentration of the doping region 46. For example, the doping region 50 preferably includes a PLDD doping region and the doping region 52 preferably includes a P+ doping region. Compared with the area of the contact region 16, the concentration of the doping region 52 is approximately equal to the concentration of the doping region 44 and the concentration of the doping region 50 is approximately equal to the concentration of the doping region 42.
[0053] As in the above-mentioned embodiment, although the guard ring 54 of this embodiment is exemplified by two doping regions 50 and 52, it is not limited thereto. According to other embodiments of the present invention, only a single doping region, such as a P+ doping region, may be formed in the guard ring 54, and this variation also falls within the scope of the present invention. Figure 2 As shown, doped region 48 in protection diode 18 is preferably electrically connected to gate structure 26 of MOS transistor 14 via contact plug 36 and metal interconnect 38 .
[0054] Please continue to refer to Figures 4 to 5 , Figures 4 to 5 FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention, wherein Figure 4 For a top view of a semiconductor device Figure 5 Then Figure 4 A schematic cross-sectional view of a semiconductor component. Figures 4 to 5 As shown, compared to Figure 1 Only a single MOS transistor 14 is provided on the substrate. The present invention can also selectively provide a complementary metal oxide semiconductor (CMOS) transistor between the contact region 16 and the protection diode 18, wherein the CMOS transistor preferably includes an NMOS transistor 56 and a PMOS transistor 58 and the two are preferably separated by a shallow trench isolation 24.
[0055] In detail, the lightly doped drain 32 of the NMOS transistor 56 preferably includes an N-type lightly doped drain or NLDD and the source / drain region 34 includes an N+ doped region and both are disposed in the P-well 22. Similarly, the lightly doped drain 32 of the PMOS transistor 58 preferably includes a P-type lightly doped drain or PLDD and the source / drain region 34 includes a P+ doped region and both are disposed in the N-well 60. In addition, the contact region 16 and the protection diode 18 of the present embodiment are preferably connected to the P-well 60. Figure 3 The contact region 16 and the protection diode 18 in the embodiment have the same structure. For example, the contact region 16 preferably includes at least one doped region such as a doped region 42 and a doped region 44, wherein the upper doped region 42 preferably includes a P-type lightly doped drain or PLDD and the lower doped region 44 includes a P+ doped region.
[0056] The protection diode 18 on the right side of the NMOS transistor 56 and the PMOS transistor 58 includes, in addition to the doped regions 46 and 48, a guard ring 54 formed by doped regions 50 and 52 surrounding the doped regions 50 and 52, wherein the doped region 46 preferably includes a P++ doped region, the doped region 48 preferably includes an N++ doped region, the doped region 50 includes a PLDD doped region, and the doped region 52 includes a P+ doped region. Figure 4 As shown, the doped region 48 in the protection diode 18 is preferably electrically connected to the gate structure 26 of the NMOS transistor 56 via the contact plug 36 and the metal interconnect 38 , while the guard ring 54 in the protection diode 18 is electrically connected to the contact region 16 via the contact plug 36 and the metal interconnect 38 .
[0057] Please continue to refer to Figure 6 , Figure 6 FIG. 1 is a schematic diagram of the structure of a semiconductor element according to an embodiment of the present invention. Figure 6 As shown, compared to Figure 1 The protection diode 18 includes two doped regions 46 and 48 stacked up and down. The protection diode 18 of this embodiment only includes a single doped region 48 arranged in the substrate 12, wherein the doped region 48 preferably includes an N++ doped region and the bottom surface of the doped region 48 can be slightly lower than the bottom surface of the source / drain region 34 or the bottom surface of the doped region 44 of the contact region 16.
[0058] Please continue to refer to Figure 7 , Figure 7 FIG. 1 is a schematic diagram of the structure of a semiconductor element according to an embodiment of the present invention. Figure 7 As shown, different from Figure 1The two doping regions 46 and 48 of different conductivity types in the protection diode are stacked up and down. In the protection diode 18 of the present embodiment, at least two groups of doping regions of different conductivity types can be arranged in a left-right adjacent manner. For example, in the protection diode 18, a doping region 62 and a doping region 64 with N-type conductivity type can be arranged on the left side, and a doping region 66 and a doping region 68 with P-type conductivity type can be arranged on the right side, wherein the doping region 62 on the upper left side preferably includes a NLDD doping region with a lower concentration and the doping region 64 on the lower left side includes an N+ doping region with a higher concentration. Similarly, the doping region 66 on the upper right side includes a PLDD doping region with a lower concentration and the doping region 68 on the lower right side includes a P+ doping region with a lower concentration. In terms of position, the bottom surface of the doping region 64 on the left side can be aligned with the bottom surface of the doping region 68 on the right side.
[0059] It should be noted that the N-type doped regions 62 and 64 on the left are preferably connected to the gate structure 26 via the contact plugs 36 and the metal interconnects 38, while the P-type doped regions 66 and 68 on the right are preferably provided with a silicide block (SAB) 70. In other words, the surface of the substrate 12 not covered by the silicide block includes the doped region 42, the source / drain region 34, and the surface of the doped region 62, and a silicide layer (not shown) may be formed, but no silicide layer is formed on the surface of the doped region 66, so that the P-type doped region 66 is preferably not provided with any contact plug or connected to any wire and is not exposed. In addition, although the N-type doping regions 62 and 64 are arranged slightly closer to the left side of the MOS transistor 14 and the P-type doping regions 66 and 68 are arranged on the right side away from the MOS transistor 14 in this embodiment, it is not limited to this configuration. According to other embodiments of the present invention, the left and right positions of the N-type doping regions 62 and 64 and the P-type doping regions 66 and 68 can be arbitrarily adjusted under the principle that the contact plugs 36 are connected to the N-type doping regions 62 and 64 but no contact plugs 36 are connected to the P-type doping regions 66 and 68. These are all within the scope of the present invention.
[0060] Please continue to refer to Figures 8 to 9 , Figures 8 to 9 FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention, wherein Figure 8 For a top view of a semiconductor device Fig. 9 Then Figure 8 A schematic cross-sectional view of a semiconductor component. Figures 8 to 9 As shown, this embodiment preferably Figure 7 The N-type doped regions 62 and 64 connected to the gate structure 26 are disposed on the right side, while the silicide barrier layer 70 and the P-type doped regions 66 and 68 thereunder are disposed on the left side.
[0061] In addition, the protection diode 16 is preferably Figure 4The invention also includes a guard ring 54 formed by the doped regions 50 and 52 surrounding the doped regions 62, 64, 66, and 68. Figure 4 As shown, the doped region 62 in the protection diode 18 is preferably electrically connected to the gate structure 26 of the MOS transistor 14 via the contact plug 36 and the metal interconnect 38 , while the guard ring 54 in the protection diode 18 is electrically connected to the contact region 16 via the contact plug 36 and the metal interconnect 38 .
[0062] Please continue to refer to Figure 10 to Figure 11 , Figure 10 to Figure 11 FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention, wherein Fig.10 For a top view of a semiconductor device Fig.11 Then Fig.10 A schematic cross-sectional view of a semiconductor component. Figure 10 to Figure 11 As shown, the present invention can be combined with Figures 4 to 5 The structure of the CMOS transistor and the left contact area 16 is similar to Figures 8 to 9 The right side protection diode 18 is used to generate another new protection element structure.
[0063] For example, compared to Figure 8 Only a single MOS transistor 14 is provided on the substrate 12. The present invention can optionally provide a complementary metal oxide semiconductor (CMOS) transistor between the contact region 16 and the protection diode 18, wherein the CMOS transistor preferably includes an NMOS transistor 56 and a PMOS transistor 58 and the two are preferably separated by a shallow trench isolation 24.
[0064] As in the previous embodiment, the lightly doped drain 32 of the NMOS transistor 56 preferably comprises an N-type lightly doped drain or NLDD and the source / drain region 34 comprises an N+ doped region and both are disposed in the P-well 22. Similarly, the lightly doped drain 32 of the PMOS transistor 58 preferably comprises a P-type lightly doped drain or PLDD and the source / drain region 34 comprises a P+ doped region and both are disposed in the N-well 60. In addition, the contact region 16 of the present embodiment is preferably connected to the N-well 60. Figure 5 The contact region 16 in the embodiment has the same structure. For example, the contact region 16 preferably includes at least one doped region such as a doped region 42 and a doped region 44, wherein the upper doped region 42 preferably includes a P-type lightly doped drain or PLDD and the lower doped region 44 includes a P+ doped region.
[0065] In the protection diode 18 part, this embodiment is preferably compared with Figure 7 or Fig. 9The N-type doped regions 62 and 64 connected to the gate structure 26 are arranged on the right side, while the silicided metal barrier layer 70 and the P-type doped regions 66 and 68 thereunder are arranged on the left side. In addition, the protection diode 16 further includes a guard ring 54 formed by the doped regions 50 and 52 surrounding the doped regions 62, 64, 66, and 68. The doped region 62 is preferably electrically connected to the gate structure 26 of the MOS transistor 14 via the contact plug 36 and the metal interconnect 38, and the guard ring 54 is electrically connected to the contact region 16 via the contact plug 36 and the metal interconnect 38.
[0066] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A semiconductor element, characterized in that: Include: A first metal oxide semiconductor transistor is disposed on the substrate; A contact region is disposed on one side of the first metal oxide semiconductor transistor; and The protection diode is disposed on the other side of the first metal oxide semiconductor transistor, wherein the contact region and the protection diode include different conductivity types.
2. The semiconductor device as claimed in claim 1, wherein the first metal oxide semiconductor transistor comprises: A first gate structure is disposed on the substrate; and The first source / drain region is disposed on both sides of the first gate structure. 3 . The semiconductor device as claimed in claim 2 , wherein the protection diode is electrically connected to the first gate structure. The semiconductor device as claimed in claim 2 , wherein the contact region comprises a first conductivity type.
5. The semiconductor device as claimed in claim 4, wherein the protection diode comprises: A first doped region disposed in the substrate, wherein the first doped region includes the first conductivity type; and The second doping region is disposed on the first doping region, wherein the second doping region includes a second conductive type. The semiconductor device as claimed in claim 5 , wherein the contact region concentration is less than the first doping region concentration.
7. The semiconductor device as claimed in claim 4, wherein the protection diode comprises: a well region disposed in the substrate, wherein the well region includes the first conductivity type; and The doped region is disposed on the well region, wherein the doped region includes a second conductive type. The semiconductor device as claimed in claim 7 , wherein the concentration of the well region is lower than the concentration of the contact region.
9. The semiconductor device as claimed in claim 4, wherein the protection diode comprises: A first doped region disposed in the substrate, wherein the first doped region includes the first conductivity type; and The second doping region is disposed beside the first doping region, wherein the second doping region includes a second conductive type. 10 . The semiconductor device as claimed in claim 9 , wherein the second doped region is electrically connected to the first gate structure. 11 . The semiconductor device as claimed in claim 9 , wherein a bottom surface of the first doped region is flush with a bottom surface of the second doped region. 12 . The semiconductor device as claimed in claim 9 , further comprising a silicide metal barrier layer disposed on the first doped region. 13 . The semiconductor device as claimed in claim 1 , further comprising a second metal oxide semiconductor transistor disposed between the first metal oxide semiconductor transistor and the protection diode. 14 . The semiconductor device as claimed in claim 13 , wherein the first metal oxide semiconductor transistor and the second metal oxide semiconductor transistor comprise different conductivity types.
15. The semiconductor device as claimed in claim 13, wherein the second metal oxide semiconductor transistor comprises: A second gate structure is disposed on the substrate; and The second source / drain region is disposed on both sides of the second gate structure.