Memory for image sensor and forming method thereof

Abstract

The invention discloses a memory for an image sensor and a forming method thereof. The forming method comprises the following steps: providing a substrate; etching the substrate to form a first groove and a charge storage region which are communicated with each other; forming a first trench isolation structure in the first trench; etching a part of the first trench isolation structure to form a second trench; forming a gate structure of a transfer transistor in the second groove; at least part of a channel of the transfer transistor is in the vertical direction; and reading or writing operation of the charge storage area is realized by controlling the gate structure. Based on the process compatibility of the image sensor and the memory, the image sensor and the memory are manufactured on the same wafer, and the vertical transfer gate of the transfer transistor is formed on the isolation structure, so that the storage density is improved, and the cost is remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular to a memory for an image sensor and a method for forming the memory. Background Art

[0002] The data stored in random access memory (RAM) can be read or written as needed, and the speed of reading and writing has nothing to do with the storage location of the data. This type of memory has the fastest reading and writing speed among all memories, but the stored data will be lost when the power is off, so it is mainly used to store data used for a short time. According to the different storage information, random access memory can be divided into static random access memory (Static RAM, SRAM) and dynamic random access memory (Dynamic RAM, DRAM).

[0003] For image sensors, the image data of the image sensor pixel array needs to be cached in the storage array. The existing technology usually manufactures the pixel array module, logic processing circuit and storage array module of the image sensor separately through separate silicon wafers, and then packages the three silicon wafers together by stacking. This process is not only difficult, but also significantly increases the cost. Summary of the invention

[0004] Based on the problems existing in the prior art, the present invention proposes a process method for manufacturing the pixel array, logic circuit and storage array of an image sensor on the same silicon wafer. This method is compatible with the existing manufacturing process of image sensors and has significantly reduced costs. The vertical transfer gate of the transfer transistor is formed on the isolation structure, which can improve the storage density.

[0005] An embodiment of the present invention provides a method for forming a memory for an image sensor, comprising: providing a substrate; etching the substrate to form a first trench and a charge storage area that are interconnected; forming a first trench isolation structure in the first trench; etching a portion of the first trench isolation structure to form a second trench; forming a gate structure of a transfer transistor in the second trench; at least a portion of the channel of the transfer transistor is in a vertical direction; and realizing a read or write operation on the charge storage area by controlling the gate structure.

[0006] In some embodiments, at least some of the upper portions of the charge storage regions are connected via a connection structure to prevent the charge storage regions from tipping over or breaking during etching of the substrate.

[0007] In some embodiments, providing the substrate includes: providing the substrate having a first doping type; performing ion implantation opposite to the first doping type on the substrate to form a first doping region in the middle of the substrate for forming the charge storage region.

[0008] In some embodiments, providing a substrate includes: providing a first substrate having a first doping type; epitaxially forming a first epitaxial doping layer of opposite doping type to the first doping type on the first substrate to form the charge storage region; epitaxially forming a second epitaxial doping layer of the first doping type on the first epitaxial doping layer; the substrate includes the first substrate, the first epitaxial doping layer and the second epitaxial doping layer.

[0009] In some embodiments, after etching the substrate to form interconnected first trenches and charge storage regions, the method further includes: implanting ions of a first doping type into the bottom of the first trench to form a plurality of isolated second doping regions; and laterally diffusing the doping ions of the plurality of isolated second doping regions through heat treatment to connect the plurality of isolated second doping regions.

[0010] In some embodiments, forming a first trench isolation structure in the first trench includes: forming a first dielectric layer on a surface of the first trench; and depositing a first polysilicon to fill the first trench to form the first trench isolation structure.

[0011] In some embodiments, forming a first trench isolation structure in the first trench includes: forming a first dielectric layer with doped ions on the surface of the first trench; diffusing the doped ions through heat treatment to form a lateral PN junction with the charge storage area; and depositing a first polysilicon to fill the first trench to form the first trench isolation structure.

[0012] In some embodiments, forming a first trench isolation structure in the first trench includes: forming a third doped epitaxial layer on the surface of the first trench to form a lateral PN junction with the charge storage region; forming a first dielectric layer on the surface of the third doped epitaxial layer in the first trench; and depositing a first polysilicon to fill the first trench to form the first trench isolation structure.

[0013] In some embodiments, the first polysilicon is connected to a voltage.

[0014] In some embodiments, forming the gate structure of the transfer transistor in the second trench includes: forming a second dielectric layer on the surface of the second trench; depositing second polysilicon to fill the second trench to form the gate structure of the transfer transistor with at least a portion of the channel in a vertical direction.

[0015] In some embodiments, the method further includes: forming a third doped region as a floating diffusion region on the surface of the charge storage region by ion implantation opposite to the first doping type; and realizing charge transfer between the charge storage region and the floating diffusion region by controlling the gate structure.

[0016] The present invention also provides a memory for an image sensor, comprising: a substrate; a first trench isolation structure formed in the substrate; a transfer transistor in which at least part of the channel is in a vertical direction; a gate structure of the transfer transistor is formed above the first trench isolation structure and below the surface of the substrate; a charge storage area formed between the first trench isolation structures; and a read or write operation on the charge storage area is achieved by controlling the gate structure.

[0017] In some embodiments, the first trench isolation includes a first dielectric layer formed on a surface of the first trench; and a first polysilicon for filling the first trench; and the first polysilicon is connected to a voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be further explained in the form of exemplary embodiments, which will be described in detail by means of the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same numerals represent the same structure.

[0019] Figure 1 The figure is a schematic diagram of the structure of an image sensor according to an embodiment of the present invention.

[0020] Figure 2 Schematic diagram of the structure of a pixel unit according to an embodiment of the present invention.

[0021] Figure 3 Schematic diagram of the structure of a storage unit according to an embodiment of the present invention.

[0022] Figure 4 The figure is a schematic structural diagram of a substrate according to an embodiment of the present invention.

[0023] Figure 5 FIG. 4 is a schematic structural diagram of another substrate according to an embodiment of the present invention.

[0024] Figure 6 It is a schematic diagram of the cross-sectional structure of a substrate during the process of forming a memory according to an embodiment of the present invention.

[0025] Figure 7 To correspond to Figure 6 Top view of the substrate in FIG.

[0026] Figure 8 FIG. 4 is a top view of another substrate during the process of forming a memory according to an embodiment of the present invention.

[0027] Fig. 9 To correspond to Figure 8 Schematic diagram of the cross section of the substrate along AA.

[0028] Fig.10 To correspond to Figure 8 Schematic diagram of the cross section of the substrate along BB.

[0029] Figures 11 to 17 To correspond to Figure 6 A schematic diagram of a cross-sectional structure of a substrate during a method for forming a memory device. Implementation

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present invention. For ordinary technicians in this field, the present invention can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0031] like Figure 1 As shown, the image sensor 100 includes a pixel array 110, a logic circuit 120 and a storage array 130. The pixel array 110 includes a plurality of pixel units 111, and a semiconductor device ( Figure 1 The memory array 130 may include a plurality of memory cells 131. The image data of the pixel array 110 may be cached in the memory array 130.

[0032] like Figure 2 As shown, the pixel unit 111 includes a photodiode 111a and a transfer transistor 111b connected to one end thereof. The other end of the photodiode 111a can be grounded or a fixed voltage. Figure 3 As shown, the storage unit 131 includes a capacitor 131a and a transfer transistor 131b connected to one end thereof. The other end of the capacitor 131a can be grounded or a fixed voltage. Among them, the capacitor 131a can be a plate capacitor or a diode junction capacitor. Due to the structural similarity between the pixel unit 111 and the storage unit 131, the compatibility of the image sensor and the DRAM process can be achieved, that is, the pixel array, logic circuit and storage array of the image sensor are formed on the same silicon wafer to form a non-stacked image sensor.

[0033] The following describes a method for forming a memory (storage array 130) for an image sensor in conjunction with the relevant drawings. It should be noted that due to the structural similarity between the pixel unit 111 and the storage unit 131, the processes of the pixel array 110 and the storage array 130 can be implemented simultaneously. For the convenience of description, the following only describes the structure of the storage array 130.

[0034] like Figure 4 and Figure 5 As shown, a substrate 200 is provided. For illustrative purposes only, two commonly used substrates are introduced below.

[0035] like Figure 4 As shown, the substrate 200 may be a substrate 200 having a first doping type (such as p-type doping); the substrate 200 is subjected to ion implantation opposite to the first doping type (such as n-type doping), and a middle layer of the substrate 200 forms a first doping region 202 for forming a charge storage region. The lower layer of the substrate 200 is a p-type doping region 201; the upper layer of the substrate 200 is a p-type doping region 203.

[0036] like Figure 5 As shown, the substrate 200 may include a first substrate 210 having a first doping type (e.g., p-type doping); and a first epitaxial doping layer 220 (e.g., n-type doping) opposite to the first doping type is epitaxially formed on the first substrate 210 to form a charge storage region; and a second epitaxial doping layer 230 (e.g., p-type doping) of the first doping type is epitaxially formed on the first epitaxial doping layer 220.

[0037] In addition to the two types of substrates described above, the substrate 200 may also be of other types, which will not be described in detail herein.

[0038] Furthermore, if Figure 6 and Figure 7 , etching the substrate 200, forming interconnected first trenches 300 and multiple charge storage areas 400 (i.e., single storage units) on the front side of the substrate 200; the multiple charge storage areas 400 are arranged in a dispersed array. Similarly, multiple doping regions (such as n-type doping) of photodiodes are simultaneously formed in the pixel array 110 of the image sensor.

[0039] Considering that the charge storage region 400 is a dispersed columnar structure, the charge storage region 400 may collapse or break during the etching process. Figure 8 , Fig. 9 , Fig.10A connection structure 410 may be formed between the upper portions of different charge storage regions 400, and the bottom of the connection structure 410 is hollowed out to prevent the charge storage region 400 from falling or breaking during the etching process. The process of forming the connection structure 410 is not limited here.

[0040] For the convenience of description, the connection structure 410 is not introduced in this embodiment. Figure 6 and Figure 7 The structure shown is used as a basis to form a memory.

[0041] Furthermore, if Fig.11 As shown, ions of a first doping type (such as p-type doping) are implanted into the bottom of the first trench 300 to form a plurality of isolated second doping regions 310 .

[0042] like Fig.12 As shown, through heat treatment, the doping ions of the plurality of isolated second doping regions 310 are diffused laterally, so that the plurality of isolated second doping regions 310 are connected. Fig.11 and Fig.12 The main purpose of the process step is to form better electrical isolation between different charge storage regions 400.

[0043] It should be noted that Fig.11 and Fig.12 The process step can be omitted in some cases, for example, the bottom of the first trench 300 is in the p-type substrate (such as Figure 4 The p-type doped region 201 and Figure 5 For another example, after the memory is formed, the back side of the substrate 200 may be thinned to achieve electrical isolation between the charge storage regions 400 .

[0044] Furthermore, if Fig.13 As shown, a first trench isolation structure 500 is formed in the first trench 300. Specifically, a first dielectric layer 510 and a first polysilicon 520 can be formed on the first trench surface 300 to form the first trench isolation structure 500. The first polysilicon 520, the first dielectric layer 510 and the charge storage area 400 can form a plate capacitor. The first polysilicon is connected to a voltage.

[0045] In one embodiment, the first dielectric layer 510 may be doped with ions (such as p-type doping); the doped ions are diffused by heat treatment to form a lateral PN junction with the charge storage region 400, thereby increasing a PN junction capacitance. The first dielectric layer 510 may be made of silicon nitride, silicon oxide, silicon oxynitride, and the like.

[0046] In another embodiment, a third doped epitaxial layer (e.g., p-type doping) (not shown in the figure) can be formed on the surface of the first trench 300 by epitaxy to form a lateral PN junction with the charge storage area 400, thereby increasing a PN junction capacitance; a first dielectric layer 510 is formed on the surface of the third doped epitaxial layer in the first trench 300; and a first polysilicon 520 is deposited to fill the first trench 300 to form a first trench isolation structure 500. The first dielectric layer 510 can be made of materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0047] Furthermore, if Figures 14 to 17 As shown, part of the first trench isolation structure 500 is etched to form a second trench 600; a gate structure 700 of a transfer transistor is formed in the second trench 600; at least part of the channel of the transfer transistor is in a vertical direction (i.e., perpendicular to the surface of the substrate 200); and by controlling the gate structure 700, a read or write operation on the charge storage area 400 is achieved.

[0048] Specifically, Fig.15 As shown, a second dielectric layer 710 is formed on the surface of the second trench 600; a second polysilicon 720 is deposited to fill the second trench 600; Fig.16 As shown, by ion implantation of the opposite doping type to the first doping type (such as n-type doping), a third doping region 730 is formed on the surface of the charge storage region 400 as a floating diffusion region; Fig.17 As shown, a portion of the second polysilicon 720 is etched away to form a gate structure 700 (or vertical transfer gate) of a transfer transistor with at least a portion of the channel in a vertical direction. By controlling the gate structure 700, the transfer of charges between the charge storage area 400 and the floating diffusion area 730 is achieved.

[0049] It should be noted that in the above-mentioned formation process, some process steps are omitted, such as chemical mechanical polishing.

[0050] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention.

[0051] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as examples and not limitations, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A method for forming a memory for an image sensor, characterized in that: include: providing a substrate; Etching the substrate to form a first trench and a charge storage area that are interconnected; forming a first trench isolation structure in the first trench; Etching a portion of the first trench isolation structure to form a second trench; A gate structure of a transfer transistor is formed in the second trench; at least a portion of the channel of the transfer transistor is in a vertical direction; By controlling the gate structure, a read or write operation on the charge storage area is achieved.

2. The method according to claim 1, characterized in that At least some of the upper portions of the charge storage regions are connected via a connection structure to prevent the charge storage regions from tipping over or breaking during etching of the substrate.

3. The method according to claim 1, characterized in that The providing of the substrate comprises: providing the substrate having a first doping type; Ions of opposite doping type to the first are implanted into the substrate to form a first doping region in the middle of the substrate for forming the charge storage region.

4. The method according to claim 1, characterized in that The providing of the substrate comprises: providing a first substrate having a first doping type; epitaxially forming a first epitaxial doping layer having a doping type opposite to the first doping type on the first substrate, so as to form the charge storage region; epitaxially growing a second epitaxial doped layer of the first doping type on the first epitaxial doped layer; The substrate includes the first substrate, the first epitaxial doping layer and the second epitaxial doping layer.

5. The method according to claim 1, characterized in that After etching the substrate to form the first trench and the charge storage area interconnected with each other, the method further comprises: Performing ion implantation of a first doping type into the bottom of the first trench to form a plurality of isolated second doping regions; Through heat treatment, doping ions of the plurality of isolated second doping regions are laterally diffused, so that the plurality of isolated second doping regions are connected.

6. The method according to claim 1, characterized in that The forming of a first trench isolation structure in the first trench comprises: forming a first dielectric layer on the surface of the first trench; A first polysilicon is deposited to fill the first trench to form the first trench isolation structure.

7. The method according to claim 1, characterized in that The forming of a first trench isolation structure in the first trench comprises: forming a first dielectric layer with doped ions on the surface of the first trench; By heat treatment, the doping ions are diffused to form a lateral PN junction with the charge storage region; A first polysilicon is deposited to fill the first trench to form the first trench isolation structure.

8. The method according to claim 1, characterized in that The forming of a first trench isolation structure in the first trench comprises: forming a third doped epitaxial layer on the surface of the first trench to form a lateral PN junction with the charge storage region; forming a first dielectric layer on the surface of the third doped epitaxial layer in the first trench; A first polysilicon is deposited to fill the first trench to form the first trench isolation structure.

9. The method according to any one of claims 6 to 8, characterized in that The first polysilicon is connected to a voltage.

10. The method according to claim 1, characterized in that The gate structure of the transfer transistor formed in the second trench includes: forming a second dielectric layer on the surface of the second trench; A second polysilicon is deposited to fill the second trench to form a gate structure of the transfer transistor in which at least a portion of the channel is in a vertical direction.

11. The method according to claim 1, characterized in that Also includes: By ion implantation opposite to the first doping type, a third doping region is formed on the surface of the charge storage region as a floating diffusion region; By controlling the gate structure, the charge transfer between the charge storage area and the floating diffusion area is achieved.

12. The method according to claim 1, characterized in that The pixel array and the storage array of the image sensor are formed on the substrate.

13. A memory for an image sensor, characterized in that: include: substrate; a first trench isolation structure formed in the substrate; A transfer transistor having at least a portion of its channel oriented vertically; The gate structure of the transfer transistor is formed above the first trench isolation structure and below the surface of the substrate; a charge storage region formed between the first trench isolation structures; By controlling the gate structure, a read or write operation on the charge storage area is achieved.

14. The memory for an image sensor according to claim 13, wherein: The first trench isolation includes a first dielectric layer formed on the surface of the first trench; and a first polysilicon for filling the first trench; the first polysilicon is connected to a voltage.

Images