Image sensor

Abstract

An image sensor is provided. The image sensor comprises a semiconductor substrate which comprises a first surface and a second surface opposite to the first surface, and the semiconductor substrate further comprises a photoelectric conversion area; a transfer gate disposed on the first surface of the semiconductor substrate; a buried insulating layer disposed on the first surface of the semiconductor substrate to cover the transfer gate; and a pixel isolation structure disposed in the pixel isolation trench, the pixel isolation trench extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, the pixel isolation trench passing through the buried insulating layer, the pixel isolation structure defining a plurality of pixels in the semiconductor substrate, a portion of the pixel isolation structure being covered by the buried insulating layer.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0084509 filed on June 29, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0128490 filed on September 25, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The disclosed example embodiments relate to image sensors, and more particularly, to image sensors including a deep trench isolation structure. Background Art

[0003] An image sensor is a device that converts an optical image signal into an electrical signal. The image sensor includes a plurality of pixels, and each of the plurality of pixels includes a photodiode region, the photodiode region receives incident light and converts the received light into an electrical signal, and a pixel circuit that outputs a pixel signal by using charges generated by the photodiode region. As the integration of image sensors increases, the size of each pixel is reduced, and thus, there is a problem that it is difficult to reduce or prevent dark current. Summary of the invention

[0004] The disclosed example embodiments provide an image sensor that can reduce dark current and can reduce or prevent optical crosstalk.

[0005] According to one aspect of an example embodiment, an image sensor includes: a semiconductor substrate including a first surface and a second surface opposite to the first surface, the semiconductor substrate also including a photoelectric conversion region; a transfer gate disposed on the first surface of the semiconductor substrate; a buried insulating layer disposed on the first surface of the semiconductor substrate to cover the transfer gate; and a pixel isolation structure disposed in a pixel isolation trench, the pixel isolation trench extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, the pixel isolation trench passing through the buried insulating layer, the pixel isolation structure defining a plurality of pixels in the semiconductor substrate, and a portion of the pixel isolation structure being covered by the buried insulating layer.

[0006] According to one aspect of an example embodiment, an image sensor includes: a semiconductor substrate including a first surface and a second surface opposite to the first surface, the semiconductor substrate also including a photoelectric conversion region; a transfer gate disposed on the first surface of the semiconductor substrate; an etch stop layer disposed on the first surface of the semiconductor substrate to cover the transfer gate; and a pixel isolation structure disposed in a pixel isolation trench, the pixel isolation trench extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, the pixel isolation structure including a conductive layer, the conductive layer including a reflective metal material, wherein an end of the etch stop layer is disposed on the conductive layer, and the pixel isolation structure and the etch stop layer do not vertically overlap each other.

[0007] According to one aspect of an example embodiment, an image sensor includes: a semiconductor substrate including a first surface and a second surface opposite to the first surface, the semiconductor substrate also including a photoelectric conversion region; a transfer gate disposed on the first surface of the semiconductor substrate; and a pixel isolation structure disposed in a pixel isolation trench, the pixel isolation trench extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate, wherein the pixel isolation structure includes a conductive layer, a blocking conductive layer, a pixel isolation insulating layer and an insulating liner, the conductive layer being disposed in the pixel isolation trench, the conductive layer extending in a vertical direction perpendicular to the first surface of the semiconductor substrate, the blocking conductive layer being disposed on a side wall of the conductive layer in the pixel isolation trench, the pixel isolation insulating layer being disposed on the conductive layer and the blocking conductive layer in the pixel isolation trench, the insulating liner extending in a vertical direction on an inner wall of the pixel isolation trench, the insulating liner covering the side walls of the pixel isolation insulating layer and the side walls of the blocking conductive layer, and the upper surface of the pixel isolation insulating layer being disposed at a level higher than the first surface of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram showing a configuration of an image sensor according to an embodiment; Figure 2 is a block diagram showing a configuration of an image sensor according to an embodiment; Figure 3 is a readout circuit diagram of an image sensor according to an example embodiment; Figure 4 is a layout diagram illustrating an image sensor according to example embodiments; Figure 5 It is along Figure 4 A cross-sectional view taken along line A1-A1'; Figure 6 is Figure 5 a plan view at a first vertical level of; Figure 7 is Figure 5 a plan view at a second vertical level of; Figure 8 is a cross-sectional view illustrating an image sensor according to example embodiments; Fig. 9 is Figure 8 a plan view at a second vertical level of; Fig.10 is a cross-sectional view illustrating an image sensor according to example embodiments; Fig.11 is a cross-sectional view illustrating an image sensor according to example embodiments; Fig.12 is Fig.12 a plan view at a second vertical level of; Fig.13 is a cross-sectional view illustrating an image sensor according to example embodiments; Fig.14 is a cross-sectional view illustrating an image sensor according to example embodiments; Fig.15 is a cross-sectional view illustrating an image sensor according to example embodiments; and Fig.16 is a cross-sectional view illustrating an image sensor according to example embodiments. DETAILED DESCRIPTION

[0009] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram showing a configuration of an image sensor 1100 according to an embodiment.

[0011] Reference Figure 1 , the image sensor 1100 may include a pixel array 1110 , a controller 1130 , a row driver 1120 , and a pixel signal processor 1140 .

[0012] The pixel array 1110 may include a plurality of unit pixels arranged two-dimensionally, and each of the plurality of unit pixels may include a photoelectric conversion device. The photoelectric conversion device may absorb light (e.g., light provided from an external object) to generate charges, and an electrical signal (or output voltage) based on the generated charges may be supplied to the pixel signal processor 1140 through a vertical signal line. The unit pixels included in the pixel array 1110 may supply output voltages one at a time in units of rows, and thus, the unit pixels included in a row of the pixel array 1110 may be simultaneously activated by a selection signal output from the row driver 1120. The unit pixels included in the selected row may supply output voltages based on the absorbed light to the output lines of the corresponding column lines.

[0013] The controller 1130 may control the row driver 1120 so that the pixel array 1110 absorbs light to accumulate charges, or temporarily stores the accumulated charges, or outputs an electric signal based on the stored charges to the outside of the pixel array 1110. In addition, the controller 1130 may control the pixel signal processor 1140 to detect an output voltage provided by the pixel array 1110.

[0014] The pixel signal processor 1140 may include a correlated double sampler (CDS) 1142, an analog-to-digital converter (ADC) 1144, and a buffer 1146. The CDS 1142 may sample the output voltage provided by the pixel array 1110 and hold the output voltage provided by the pixel array 1110. The CDS 1142 may sample twice a specific noise level and a level based on the generated output voltage to output a level corresponding to “a difference between the specific noise level and the level based on the generated output voltage.” In addition, the CDS 1142 may receive and compare a ramp signal generated by a ramp signal generator 1148 to output a comparison result.

[0015] The ADC 1144 may convert an analog signal corresponding to a level received from the CDS 1142 into a digital signal. The buffer 1146 may latch the digital signal, and the latched signal may be sequentially output to the outside of the image sensor 1100 and may be transmitted to an image processor (not shown).

[0016] Figure 2 is a block diagram showing a configuration of an image sensor 2000 according to an embodiment.

[0017] Reference Figure 2 , the image sensor 2000 may include a pixel unit 2200 and a peripheral circuit unit. In the pixel unit 2200, a plurality of unit pixels 2100 may be regularly arranged (eg, at regular intervals) in a two-dimensional (2D) array structure, and each of the plurality of unit pixels 2100 includes a photoelectric conversion layer.

[0018] The peripheral circuit unit may be disposed at the periphery of the pixel unit 2200 , and may include a vertical driving circuit 2400 , a column signal processing circuit 2500 , a horizontal driving circuit 2600 , an output circuit 2700 , a control circuit 2800 , and input and output terminals 2900 .

[0019] The control circuit 2800 may control the vertical driving circuit 2400, the column signal processing circuit 2500, and the horizontal driving circuit 2600. For example, the control circuit 2800 may generate a clock signal or a control signal to be used in the operation of the vertical driving circuit 2400, the column signal processing circuit 2500, and the horizontal driving circuit 2600 based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock. In addition, the control circuit 2800 may input the clock signal or the control signal to the vertical driving circuit 2400, the column signal processing circuit 2500, and the horizontal driving circuit 2600.

[0020] The vertical driving circuit 2400 may be configured with, for example, a shift register. The vertical driving circuit 2400 may select a pixel driving wiring, and may supply a pulse for driving a plurality of unit pixels 2100 to the selected pixel driving wiring in a row unit. For example, the vertical driving circuit 2400 may sequentially and selectively scan a pulse to each unit pixel 2100 of the pixel unit 2200 in a vertical direction in a row unit. In addition, the vertical driving circuit 2400 may apply a pixel signal based on the charge generated by the photoelectric conversion layer of each unit pixel 2100 to the column signal processing circuit 2500 through the vertical signal line 2320.

[0021] The column signal processing circuit 2500 may be provided in each column of the plurality of unit pixels 2100, and may perform signal processing (such as noise removal) on a signal output from each unit pixel 2100 for each unit pixel of a row. For example, the column signal processing circuit 2500 may perform signal processing (such as correlated double sampling (CDS), signal amplification, or analog-to-digital conversion) for removing noise unique to the unit pixel 2100. A horizontal selection switch (not shown) may be provided at an output terminal of the column signal processing circuit 2500.

[0022] The horizontal driving circuit 2600 may be configured with, for example, a shift register and may sequentially output horizontal scanning pulses to sequentially select each of the plurality of column signal processing circuits 2500 and may cause a pixel signal of each column signal processing circuit 2500 to be output to the horizontal signal line 2340 .

[0023] The output circuit 2700 may process and output a signal sequentially supplied from each column signal processing circuit 2500 through the horizontal signal line 2340. For example, the output circuit 2700 may perform only buffering, or may perform black level adjustment, column non-uniformity correction, and various digital signal processing. In addition, the input and output terminal 2900 may exchange signals with the outside (e.g., transmit signals and / or receive signals).

[0024] Figure 3 is a readout circuit diagram of an image sensor according to example embodiments.

[0025] Reference Figure 3 , a plurality of pixels PX may be arranged in a matrix form (e.g., in columns and rows), and each of the plurality of pixels PX may include a transfer transistor TX and a logic transistor. Here, the logic transistor may include a reset transistor RX, a select transistor SX, and a source follower transistor (or drive transistor) SFX. The reset transistor RX may include a reset gate RG, the select transistor SX may include a select gate SEL, the source follower transistor SFX may include a source follower gate SF, and the transfer transistor TX may include a transfer gate TG.

[0026] Each of the plurality of pixels PX may further include a photoelectric conversion region PD and a floating diffusion region FD. The photoelectric conversion region PD may generate and accumulate photocharges in proportion to the amount of light incident on the photoelectric conversion region PD from the outside, and may use a photodiode, a phototransistor, a photogate, a clamped photodiode (PPD), and / or any combination thereof.

[0027] The transfer gate TG may transfer the charges generated by the photoelectric conversion region PD to the floating diffusion region FD. The floating diffusion region FD may receive, accumulate, and store the photoelectric charges generated by the photoelectric conversion region PD. The source follower gate SF of the source follower transistor SFX may be connected to the floating diffusion region FD, and the source follower transistor SFX may be controlled based on the amount of photocharges accumulated in the floating diffusion region FD.

[0028] The reset transistor RX may periodically reset the photocharge accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode of the reset transistor RX may be connected to a source voltage V DD When the reset transistor RX is turned on, the source voltage V connected to the source electrode of the reset transistor RX DD may be transferred to the floating diffusion region FD. When the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD may be released, and thus, the floating diffusion region FD may be reset.

[0029] The source follower transistor SFX may be connected to a current source (not shown) provided outside the plurality of pixels PX to function as a source follower buffer amplifier, and may amplify a potential change in the floating diffusion region FD to output the amplified value to the output line V OUT .

[0030] The selection transistor SX may select a plurality of pixels PX in units of columns, and when the selection transistor SX is turned on, an output voltage generated by the source follower transistor SFX may be transmitted to the output line V OUT .

[0031] Figure 4 is a layout diagram illustrating an image sensor 100 according to example embodiments. Figure 5 It is along Figure 4 A cross-sectional view taken along line A1-A1'. Figure 6 is Figure 5 A plan view of the image sensor 100 at a first vertical level LV1, and Figure 7 is Figure 5 FIG. 1 is a plan view of the image sensor 100 at a second vertical level LV2 .

[0032] Reference Figure 4 and Figure 5 , the image sensor 100 may include a semiconductor substrate 110 , and the semiconductor substrate 110 includes a plurality of pixels PX.

[0033] The semiconductor substrate 110 may include a first surface 110F1 and a second surface 110F2 facing each other. In example embodiments, the semiconductor substrate 110 may include a P-type semiconductor substrate. For example, the semiconductor substrate 110 may include a P-type silicon substrate. In example embodiments, the semiconductor substrate 110 may include a P-type body substrate, and a P-type epitaxial layer or an N-type epitaxial layer grown on the P-type body substrate. In other example embodiments, the semiconductor substrate 110 may include an N-type body substrate, and a P-type epitaxial layer or an N-type epitaxial layer grown on the N-type body substrate.

[0034] A plurality of pixels PX may be arranged in a matrix form in the semiconductor substrate 110, and a plurality of photoelectric conversion regions PD may be respectively disposed in the plurality of pixels PX. The photoelectric conversion region PD may be a region doped with n-type impurities. For example, the photoelectric conversion region PD may have an impurity concentration difference between its upper and lower portions, and thus may have a potential slope. Alternatively, the photoelectric conversion region PD may be formed in a type in which a plurality of impurity regions are stacked in a vertical direction. A p-well region (not shown) may be disposed in a partial region adjacent to the first surface 110F1 of the semiconductor substrate 110. The p-well region may be disposed adjacent to the photoelectric conversion region PD, and may be a region doped with p-type impurities.

[0035] A device isolation layer 115 defining an active area ACT may be formed on the first surface 110F1 of the semiconductor substrate 110. The device isolation layer 115 may be disposed in a device isolation trench 150T formed to have a specific depth in the first surface 110F1 of the semiconductor substrate 110. The device isolation layer 115 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. An interface insulating layer 115I may be further disposed on an inner wall of the device isolation trench 150T and may be conformally disposed between the semiconductor substrate 110 and the device isolation layer 115.

[0036] The transistors configuring the pixel circuit PXT may be disposed on the active region ACT. For example, the active region ACT may be a portion of the semiconductor substrate 110, and the transmission gate TG, the source follower gate SF, the selection gate SEL, and the reset gate RG are disposed at an upper portion of the portion of the semiconductor substrate 110. The floating diffusion region FD may be disposed, for example, in a portion of the active region ACT (e.g., a portion of the active region ACT adjacent to the transmission gate TG).

[0037] In example embodiments, the transmission gate TG may constitute the transmission transistor TX (see Figure 3 ), and the transfer transistor TX may be configured to transfer the charge generated by the photoelectric conversion region PD to the floating diffusion region FD. The reset gate RG may configure the reset transistor RX (see Figure 3 ), and the reset transistor RX may be configured to periodically reset the charge stored in the floating diffusion region FD. The source follower gate SF may construct a source follower transistor SFX (see Figure 3 ), and the source follower transistor SFX can be used as a source follower buffer amplifier and can be configured to buffer a signal based on the charge charged into the floating diffusion region FD. The select gate SEL can construct the select transistor SX (see Figure 3 ), and the selection transistor SX may perform switching and addressing functions for selecting the pixel PX.

[0038] The transfer gate TG, the reset gate RG, the source follower gate SF, and the selection gate SEL each include a gate electrode 120. For example, the gate electrode 120 may be disposed in a buried gate trench 120T, or may be disposed on the first surface 110F1 of the semiconductor substrate 110.

[0039] In example embodiments, the gate electrode 120 may include at least one of doped polysilicon, metal, metal silicide, metal nitride, and a metal-containing film. A gate insulating layer 122 may be disposed between the gate electrode 120 and the first surface 110F1 of the semiconductor substrate 110 and on the inner wall of the buried gate trench 120T. A gate spacer 124 may be disposed on the sidewall of the gate electrode 120.

[0040] The floating diffusion region FD may be disposed in the semiconductor substrate 110 adjacent to or on one side of the gate electrode 120 (e.g., the transfer gate TG). In example embodiments, the floating diffusion region FD may be a region doped with a first impurity, and, for example, the first impurity may be an n-type impurity. In some example embodiments, the first impurity may include phosphorus or arsenic.

[0041] An etch stop layer 130 covering the gate electrode 120 may be formed on the first surface 110F1 of the semiconductor substrate 110. The etch stop layer 130 may conformally cover the upper surface of the gate electrode 120 and the upper surface and sidewalls of the gate spacer 124, and further, the etch stop layer 130 may be disposed on the upper surface of the device isolation layer 115. The etch stop layer 130 may include silicon nitride or silicon oxynitride, and may be configured as a single layer or a double layer.

[0042] The buried insulating layer 132 may be disposed on the etch stop layer 130. The buried insulating layer 132 may be disposed on the etch stop layer 130 to have a sufficiently large height and completely cover the gate electrode 120, and an upper surface of the buried insulating layer 132 may have a flat profile. In example embodiments, the buried insulating layer 132 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k dielectric material.

[0043] The pixel isolation structure 140 may be disposed in at least a portion of the semiconductor substrate 110, and a plurality of pixels PX may be defined by the pixel isolation structure 140. The pixel isolation structure 140 may be disposed between one photoelectric conversion region among a plurality of photoelectric conversion regions PD and a photoelectric conversion region PD adjacent thereto. One photoelectric conversion region PD and another photoelectric conversion region PD adjacent thereto may be physically and electrically isolated by the pixel isolation structure 140. The pixel isolation structure 140 may be disposed between two adjacent photoelectric conversion regions PD among a plurality of photoelectric conversion regions PD arranged in a matrix form, and may have a grid shape or a mesh shape in a plan view.

[0044] The pixel isolation structure 140 may be formed in a pixel isolation trench 140T. The pixel isolation trench 140T may pass through the semiconductor substrate 110 from the first surface 110F1 of the semiconductor substrate 110 to the second surface 110F2 of the semiconductor substrate 110, extend through the first surface 110F1 of the semiconductor substrate 110 in the vertical direction Z, and pass through the buried insulating layer 132.

[0045] The pixel isolation trench 140T may include a first portion P1 and a second portion P2, the first portion P1 passing through the semiconductor substrate 110 from the first surface 110F1 of the semiconductor substrate 110 to the second surface 110F2 of the semiconductor substrate 110, and the second portion P2 passing through the buried insulating layer 132 and disposed at a vertical level higher than that of the first portion P1 (e.g., a vertical level along the Z direction). Here, disposed at a high vertical level may mean disposed farther away from the second surface 110F2 of the semiconductor substrate 110. For example, the second portion P2 of the pixel isolation trench 140T may be disposed at a vertical level higher than the first surface 110F1 of the semiconductor substrate 110, and the first portion P1 of the pixel isolation trench 140T may be disposed at a vertical level equal to or lower than the first surface 110F1 of the semiconductor substrate 110 and equal to or higher than the second surface 110F2 of the semiconductor substrate 110.

[0046] In example embodiments, the gate electrode 120 may be formed on the first surface 110F1 of the semiconductor substrate 110, and an etch stop layer 130 and a buried insulating layer 132 each covering an upper surface of the gate electrode 120 may be formed, and then the pixel isolation trench 140T may be formed by removing a portion of the buried insulating layer 132 and a portion of the semiconductor substrate 110. Therefore, the first portion P1 and the second portion P2 of the pixel isolation trench 140T may include sidewalls that are continuously connected and aligned with each other.

[0047] In example embodiments, the pixel isolation structure 140 may include an insulating liner 142 , a conductive layer 144 , a blocking conductive layer 146 , and a pixel isolation insulating layer 148 .

[0048] The insulating liner 142 may be disposed on the inner wall of the pixel isolation trench 140T. For example, the insulating liner 142 may be disposed over the inner wall of each of the first portion P1 and the second portion P2 of the pixel isolation trench 140T. The insulating liner 142 may extend from the second surface 110F2 of the semiconductor substrate 110 to the first surface 110F1 of the semiconductor substrate 110, and further extend through the first surface 110F1 of the semiconductor substrate 110 to the upper side of the sidewall of the buried insulating layer 132. The insulating liner 142 may extend so that a portion of the insulating liner 142 is disposed at the same vertical level as the upper surface of the buried insulating layer 132. In some example embodiments, the insulating liner 142 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In example embodiments, the insulating liner 142 may include a metal oxide such as hafnium oxide, aluminum oxide, or tantalum oxide.

[0049] The conductive layer 144 may be disposed in the first portion P1 of the pixel isolation trench 140T, and may extend in the vertical direction Z. In example embodiments, the conductive layer 144 may include a reflective metal material. The conductive layer 144 may include at least one of aluminum (Al), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), platinum (Pt), gold (Au), chromium (Cr), titanium (Ti), nickel (Ni), molybdenum (Mo), iron (Fe), magnesium (Mg), iridium (Ir), palladium (Pd), and ruthenium (Ru). However, the material included in the conductive layer 144 is not limited to the types of materials described above, and the conductive layer 144 may include another metal material not described herein.

[0050] In example embodiments, the conductive layer 144 may include an upper surface disposed at a level lower than a bottom surface of the device isolation layer 115. The conductive layer 144 may include a reflective metal material and thus may reflect light incident toward the pixel isolation structure 140 at an oblique angle to the inside of the pixel PX.

[0051] The blocking conductive layer 146 may be disposed in the first portion P1 of the pixel isolation trench 140T and may extend in the vertical direction Z. The blocking conductive layer 146 may be disposed between the conductive layer 144 and the insulating liner 142, and thus, the conductive layer 144 may not directly contact the insulating liner 142. In example embodiments, the blocking conductive layer 146 may include at least one of titanium, titanium nitride, titanium aluminum, titanium silicon, cobalt, and cobalt silicon.

[0052] The pixel isolation insulating layer 148 may be disposed on the conductive layer 144 and the blocking conductive layer 146 in the pixel isolation trench 140T. For example, the pixel isolation insulating layer 148 may be disposed in the upper portion of the first portion P1 of the pixel isolation trench 140T and in the second portion P2 of the pixel isolation trench 140T. Both sidewalls of the pixel isolation insulating layer 148 may be covered by the insulating liner 142.

[0053] In example embodiments, the pixel isolation insulating layer 148 may include an upper surface disposed at the same level as an upper surface of the buried insulating layer 132, and the insulating liner 142 may be disposed between the pixel isolation insulating layer 148 and the buried insulating layer 132. A bottom surface of the pixel isolation insulating layer 148 may be disposed at a level lower than a bottom surface of the device isolation layer 115. In example embodiments, the pixel isolation insulating layer 148 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k dielectric material.

[0054] In an example embodiment, because the pixel isolation structure 140 is disposed in the first portion P1 and the second portion P2 of the pixel isolation trench 140T, the lower side of the pixel isolation structure 140 may be disposed to pass through the interior of the semiconductor substrate 110 , and the upper side of the pixel isolation structure 140 may be disposed to pass through the buried insulating layer 132 .

[0055] For example, Figure 6 1 shows a plan view of the image sensor 100 at a first vertical level LV1, which is lower than the first surface 110F1 of the semiconductor substrate 110 and higher than the second surface 110F2 of the semiconductor substrate 110. Figure 6 As shown in FIG. 1 , in a plan view, the lower side of the pixel isolation structure 140 disposed in the first portion P1 of the pixel isolation trench 140T (e.g., the insulating liner 142, the conductive layer 144, and the blocking conductive layer 146 of the pixel isolation structure 140) may be disposed to surround a plurality of pixels PX of the semiconductor substrate 110. In addition, Figure 7 FIG. 4 shows a plan view of the image sensor 100 at a second vertical level LV2, which is higher than the first surface 110F1 of the semiconductor substrate 110. Figure 7 As shown in the figure, in a plan view, the upper side of the pixel isolation structure 140 (e.g., the insulating liner 142 and the pixel isolation insulating layer 148 of the pixel isolation structure 140) disposed in the second portion P2 of the pixel isolation trench 140T may be disposed to surround the buried insulating layer 132 at a position corresponding to each of the plurality of pixels PX.

[0056] like Figure 5 As shown in , the upper side of the sidewall of the pixel isolation structure 140 may contact the sidewall of the buried insulating layer 132 and may be covered by the buried insulating layer 132. A portion of the sidewall of the pixel isolation structure 140 may contact the device isolation layer 115 and the etch stop layer 130. In example embodiments, the etch stop layer 130 may include an end portion 130CE extending on the upper surface of the semiconductor substrate 110 and disposed at a point contacting the second portion P2 of the pixel isolation trench 140T. For example, the insulating liner 142 may be disposed to contact the sidewall 115S of the device isolation layer 115 and to contact the end portion 130CE of the etch stop layer 130.

[0057] In addition, the upper surface of the pixel isolation structure 140 may be disposed at a level higher than the first surface 110F1 of the semiconductor substrate 110, and may be disposed at the same level as the upper surface of the buried insulating layer 132. A sidewall of the pixel isolation structure 140 may contact an end portion 130CE of the etch stop layer 130, and the pixel isolation structure 140 may be disposed at a position that does not overlap the etch stop layer 130 along the vertical direction Z.

[0058] In an example embodiment, because the insulating liner 142 is disposed in the first portion P1 and the second portion P2 of the pixel isolation trench 140T, a portion of the insulating liner 142 (e.g., a portion of the insulating liner 142 disposed in the second portion P2 of the pixel isolation trench 140T) may be disposed between the buried insulating layer 132 and the pixel isolation insulating layer 148, another portion of the insulating liner 142 (e.g., another portion of the insulating liner 142 disposed in the second portion P2 of the pixel isolation trench 140T) may be disposed between the etch stop layer 130 and the pixel isolation insulating layer 148, another portion of the insulating liner 142 (e.g., a portion of the insulating liner 142 disposed in the first portion P1 of the pixel isolation trench 140T) may be disposed between the device isolation layer 115 and the pixel isolation insulating layer 148, and another portion of the insulating liner 142 (e.g., another portion of the insulating liner 142 disposed in the first portion P1 of the pixel isolation trench 140T) may be disposed between the semiconductor substrate 110 and the blocking conductive layer 144.

[0059] In example embodiments, the semiconductor substrate 110 may have a first height h1 in the vertical direction Z. The first height h1 may correspond to a distance from a first surface 110F1 of the semiconductor substrate 110 to a second surface 110F2 of the semiconductor substrate 110 in the vertical direction Z. The pixel isolation structure 140 may have a second height h2 greater than the first height h1 in the vertical direction Z. In some example embodiments, the second height h2 may be about 105% to about 200% of the first height h1, and a ratio of the second height h2 to the first height h1 may be changed based on the size of the pixel PX and the layout of the pixel PX.

[0060] The blocking impurity region 110D may be disposed in an inner region of the semiconductor substrate 110 disposed adjacent to the pixel isolation trench 140T. In a plan view, in each pixel PX, the blocking impurity region 110D may be surrounded by the pixel isolation structure 140. The blocking impurity region 110D may be a region doped with p-type impurities disposed in the semiconductor substrate 110, and the p-type impurities may include boron (B).

[0061] The contact 150 may be disposed in a contact hole 150H passing through the buried insulating layer 132, and may be electrically connected to the semiconductor substrate 110 and the gate electrode 120. The contact 150 may include a barrier layer 150M and a buried conductive layer 150F, the barrier layer 150M may be disposed on the inner wall of the contact hole 150H, and the buried conductive layer 150F may fill the inside of the contact hole 150H. For example, the barrier layer 150M may be disposed on the sidewall and bottom surface of the buried conductive layer 150F.

[0062] In example embodiments, the buried conductive layer 150F may include at least one of impurity-doped or undoped polysilicon, a metal, a metal silicide, a metal nitride, and a metal-containing layer, and may include, for example, tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, or doped polysilicon. The barrier layer 150M may include titanium nitride, tungsten nitride, tungsten silicide, or titanium silicide.

[0063] A wiring layer 152 electrically connected to the contact 150 may be disposed on the buried insulating layer 132 , and an interlayer insulating layer 154 covering the wiring layer 152 may be disposed on the buried insulating layer 132 .

[0064] The back insulating layer 162 may be disposed on the second surface 110F2 of the semiconductor substrate 110. In example embodiments, the back insulating layer 162 may include a metal oxide such as hafnium oxide, aluminum oxide, or tantalum oxide. In example embodiments, the back insulating layer 162 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0065] A passivation layer 164 may be disposed on the backside insulating layer 162 , and a color filter 166 and a microlens 168 may be disposed on the passivation layer 164 .

[0066] Generally, a pixel isolation structure may be formed in a pixel isolation trench by using polysilicon, and a negative bias may be applied to the pixel isolation structure, thereby preventing the occurrence of dark current. However, as the pixel size is miniaturized, there may be a problem in that optical crosstalk occurs when light passes through the pixel isolation structure and is transmitted to or incident on an adjacent pixel.

[0067] According to example embodiments, the pixel isolation structure 140 may be disposed to pass through the buried insulating layer 132 and extend in the vertical direction Z, and the pixel isolation structure 140 includes a conductive layer 144 including a reflective metal material, thereby reducing or preventing optical crosstalk that may occur when light is transmitted to or incident on adjacent pixels.

[0068] Figure 8 is a cross-sectional view illustrating an image sensor 100A according to example embodiments. Fig. 9 The image sensor 100A is Figure 8 A plan view of the second vertical level LV2. Figure 8 and Fig. 9 In, with Figures 1 to 7 The same reference numerals as those in the accompanying drawings represent the same elements.

[0069] Reference Figure 8 and Fig. 9, the pixel isolation insulating layer 148 of the pixel isolation structure 140 may include a void 148V. The void 148V may represent an air space in which an insulating material layer configuring the pixel isolation insulating layer 148 is not formed and the air space is empty.

[0070] In example embodiments, the void 148V may extend a relatively large height in the vertical direction Z from a vertical level lower than the first surface 110F1 of the semiconductor substrate 110 to a vertical level higher than the first surface 110F1 of the semiconductor substrate 110. Figure 8 As shown in FIG. 1 , the void 148V may be disposed at a level lower than the upper surface of the buried insulating layer 132 and may not be exposed to the outside of the pixel isolation structure 140. In other example embodiments, the void 148V may be disposed to extend up to the same level as the upper surface of the buried insulating layer 132.

[0071] In example embodiments, the pixel isolation insulating layer 148 may include a material with poor step coverage. In a process of forming the pixel isolation insulating layer 148 in the second portion P2 of the pixel isolation trench 140T, the pixel isolation insulating layer 148 may not completely fill the second portion P2 of the pixel isolation trench 140T, and therefore, the void 148V may remain in the pixel isolation insulating layer 148. The void 148V may include an air space, and the air space may have a relatively low dielectric constant. Because the void 148V is included in the pixel isolation insulating layer 148, the conversion gain characteristics of the image sensor 100A may be enhanced.

[0072] Fig.10 is a cross-sectional view showing an image sensor 100B according to an example embodiment. Fig.10 In, with Figures 1 to 9 The same reference numerals as those in the accompanying drawings represent the same elements.

[0073] Reference Fig.10 , the upper surfaces of the conductive layer 144 and the blocking conductive layer 146 of the pixel isolation structure 140 may be disposed at a level higher than the bottom surface of the device isolation layer 115, and may be disposed at a level lower than the upper surface of the device isolation layer 115. The pixel isolation insulating layer 148 of the pixel isolation structure 140 may be formed on the conductive layer 144 and the blocking conductive layer 146, and the bottom surface of the pixel isolation insulating layer 148 may be disposed at a level lower than the upper surface of the device isolation layer 115, or may be disposed at a level lower than the first surface 110F1 of the semiconductor substrate 110.

[0074] Fig.11 is a cross-sectional view illustrating an image sensor 100C according to example embodiments. Fig.12 is Fig.11 A plan view of the second vertical level LV2. Fig.11and Fig.12 In, with Figures 1 to 10 The same reference numerals as those in the accompanying drawings represent the same elements.

[0075] Reference Fig.11 and Fig.12 , the upper surfaces of the conductive layer 144 and the blocking conductive layer 146 of the pixel isolation structure 140 may be disposed at a level higher than the upper surface of the device isolation layer 115, and may be disposed at a level lower than the upper surface of the buried insulating layer 132. For example, the conductive layer 144 and the blocking conductive layer 146 may be disposed in a portion or the entire portion of the first portion P1 and / or the second portion P2 of the pixel isolation trench 140T. A portion of the blocking conductive layer 146 and a portion of the insulating liner 142 may be disposed between the conductive layer 144 and the buried insulating layer 132 at a vertical level higher than the first surface 110F1 of the semiconductor substrate 110.

[0076] For example, as shown in the plan view at the second vertical level LV2 higher than the first surface 110F1 of the semiconductor substrate 110 Fig.12 As shown in the figure, in a plan view, the upper side of the pixel isolation structure 140 (e.g., the insulating liner 142, the conductive layer 144, and the blocking conductive layer 146 of the pixel isolation structure 140) disposed in the second portion P2 of the pixel isolation trench 140T may be disposed to surround the buried insulating layer 132 at a position corresponding to each pixel PX.

[0077] In some example embodiments, the pixel isolation insulating layer 148 may be omitted, and the conductive layer 144 and the blocking conductive layer 146 may be disposed within the total height of the pixel isolation trench 140T (e.g., the total height of the first portion P1 and the second portion P2). In this case, the upper surfaces of the conductive layer 144 and the blocking conductive layer 146 may be disposed at the same level as the upper surface of the buried insulating layer 132.

[0078] According to an example embodiment, a conductive layer 144 including a reflective metal material may extend in a vertical direction Z on the first surface 110F1 of the semiconductor substrate 110, and thus, the pixel isolation structure 140 may reflect light incident from one pixel PX toward an adjacent pixel PX at an oblique angle, thereby reducing or preventing optical crosstalk of the image sensor 100C.

[0079] Fig.13 is a cross-sectional view showing an image sensor 100D according to an example embodiment. Fig.13 In, with Figures 1 to 12 The same reference numerals as those in the accompanying drawings represent the same elements.

[0080] Reference Fig.13, the contact 150 may be disposed in a contact hole 150H passing through the buried insulating layer 132, and may be electrically connected to the semiconductor substrate 110 and the gate electrode 120. The contact 150 may include a barrier layer 150M and a buried conductive layer 150F. The barrier layer 150M may include the same material as the barrier conductive layer 146 of the pixel isolation structure 140, and the buried conductive layer 150F may include the same material as the conductive layer 144 of the pixel isolation structure 140.

[0081] In example embodiments, the buried conductive layer 150F and the conductive layer 144 may include a reflective metal material. For example, the buried conductive layer 150F and the conductive layer 144 may include at least one of Al, Cu, Ag, Co, W, Pt, Au, Cr, Ti, Ni, Mo, Fe, Mg, Ir, Pd, and Ru. In example embodiments, the barrier layer 150M and the blocking conductive layer 146 may include at least one of titanium, titanium nitride, titanium aluminum, titanium silicon, cobalt, and cobalt silicon.

[0082] In example embodiments, the gate electrode 120 may be formed on the semiconductor substrate 110, and the buried insulating layer 132 may be formed to cover the gate electrode 120. Subsequently, a contact hole 150H passing through the buried insulating layer 132 and a pixel isolation trench 140T passing through the buried insulating layer 132 and the semiconductor substrate 110 may be formed. Subsequently, a process of forming a blocking layer 150M in the contact hole 150H and a process of forming a blocking conductive layer 146 in the pixel isolation trench 140T may be performed in the same process step, and a process of forming a buried conductive layer 150F in the contact hole 150H and a process of forming a conductive layer 144 in the pixel isolation trench 140T may be performed by the same process in the same process step.

[0083] Fig.14 is a cross-sectional view showing an image sensor 100E according to an example embodiment. Fig.14 In, with Figures 1 to 13 The same reference numerals as in the drawings represent the same elements.

[0084] Reference Fig.14 , the pixel isolation structure 140 may further include a buried conductive layer 149 disposed on the conductive layer 144. For example, the conductive layer 144 may be formed to have a relatively thin thickness that does not completely fill the inside of the pixel isolation trench 140T, and the buried conductive layer 149 may be formed on the conductive layer 144. In example embodiments, the conductive layer 144 may include a reflective metal material, and the buried conductive layer 149 may include silicon germanium (SiGe), polysilicon, a metal, a metal nitride, or a metal silicide.

[0085] Fig.15 is a cross-sectional view showing an image sensor 100F according to an example embodiment. Fig.15 In, with Figures 1 to 14 The same reference numerals as in the drawings represent the same elements.

[0086] Reference Fig.15 The pixel isolation trench 140T may include an inclined sidewall, so that the width of the second portion P2 of the pixel isolation trench 140T in the horizontal direction (for example, the X direction or the Y direction) is greater than the width of the first portion P1 of the pixel isolation trench 140T in the horizontal direction, and the horizontal width of the pixel isolation trench 140T at the same level as the upper surface of the buried insulating layer 132 is greater than the horizontal width of the pixel isolation trench 140T at the same level as the second surface 110F2 of the semiconductor substrate 110.

[0087] In the above reference Figures 4 to 15 In the described embodiment, it is shown that one pixel PX can be disposed separately from an adjacent pixel PX, and in a plan view, each of the plurality of pixels PX is surrounded by a pixel isolation structure 140. However, in other example embodiments, the pixel isolation structure 140 may not be disposed in at least a partial region between at least one pixel PX among the plurality of pixels PX and an adjacent pixel PX. For example, in a structure in which two pixels PX share a floating diffusion region FD, an isolation region or a cut region of the pixel isolation structure 140 may be disposed between two adjacent pixels PX. Alternatively, in a structure in which four pixels PX share a floating diffusion region FD, an isolation region or a cut region of the pixel isolation structure 140 may be disposed between four adjacent pixels PX arranged in a matrix form.

[0088] In the above reference Figures 4 to 15 In the described embodiment, it is shown that in one pixel PX, at least two gate electrodes 120 are separated from each other on the first surface 110F1 of the semiconductor substrate 110. However, in other example embodiments, only the transmission gate TG may be disposed on the first surface 110F1 of the semiconductor substrate 110, and the gate electrodes 120 (e.g., the selection gate SEL, the reset gate RG, and the source follower gate SF) configuring the pixel circuit PXT may be disposed on an additional semiconductor substrate, the semiconductor substrate 110 may be bonded to the additional semiconductor substrate, and the semiconductor substrate 110 may be electrically connected to the additional semiconductor substrate through a bonding pad and / or a through via between the semiconductor substrate 110 and the additional semiconductor substrate.

[0089] Fig.16 is a cross-sectional view illustrating an image sensor 100G according to example embodiments.

[0090] Reference Fig.16In the image sensor 100G, the buried insulating layer 132, the insulating liner 142, and the pixel isolation insulating layer 148 may include the same material, and therefore, a boundary between the buried insulating layer 132 and the insulating liner 142 and a boundary between the insulating liner 142 and the pixel isolation insulating layer 148 may not be clearly recognized. In example embodiments, the etch stop layer 130 may include an end portion 130CE extending on the upper surface of the semiconductor substrate 110 and disposed at a point contacting the second portion P2 of the pixel isolation trench 140T. The end portion 130CE of the etch stop layer 130 may extend in the first horizontal direction X and the second horizontal direction Y to correspond to a planar shape of the pixel isolation trench 140T.

[0091] The end portion 130CE of the etch stop layer 130 may be aligned with the sidewall of the device isolation layer 115. For example, the sidewall of the device isolation layer 115 may refer to a surface of the device isolation layer 115 connected to the pixel isolation trench 140T, and the end portion 130CE of the etch stop layer 130 may be aligned with the sidewall of the device isolation layer 115 in the vertical direction Z and disposed at the sidewall of the device isolation layer 115.

[0092] In example embodiments, the buried insulating layer 132, the insulating liner 142, and the pixel isolation insulating layer 148 may include an insulating material (such as silicon oxide), and in this case, the space on the upper surfaces of the conductive layer 144 and the blocking conductive layer 146, both of which are disposed at the first portion P1 of the pixel isolation trench 140T, may be filled with an insulating material (such as silicon oxide).

[0093] In example embodiments, in a process of forming the pixel isolation trench 140T, a portion of the etch stop layer 130 may be removed and an end portion 130CE of the etch stop layer 130 may be formed, and thus the conductive layer 144 and the blocking conductive layer 146 may be disposed not to vertically overlap the etch stop layer 130 .

[0094] According to the embodiments described above, the image sensor may include a pixel isolation structure extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate and passing through the buried insulating layer, and the pixel isolation structure may include a conductive layer containing a reflective metal material. The conductive layer may reflect light incident toward the pixel isolation structure to the inside of the pixel. Therefore, even when the pixel size may be reduced, the optical crosstalk of the image sensor may be reduced or prevented.

[0095] In the above, example embodiments have been described in the drawings and the specification. The embodiments have been described by using the terms described herein, but this is only used to describe the inventive concept and is not used to limit the meaning or scope of the inventive concept defined in the attached claims and their equivalents. Therefore, it will be understood by those of ordinary skill in the art that various modifications and other equivalent embodiments can be implemented according to the inventive concept. Therefore, the spirit and scope of the inventive concept can be defined based on the spirit and scope of the attached claims and their equivalents.

[0096] While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims and their equivalents.

Claims

1. An image sensor, comprising: A semiconductor substrate, comprising a first surface and a second surface opposite to the first surface, and the semiconductor substrate further comprising a photoelectric conversion region; A transmission gate is disposed on the first surface of the semiconductor substrate; A buried insulating layer is disposed on the first surface of the semiconductor substrate to cover the transmission gate; as well as A pixel isolation structure is arranged in a pixel isolation groove, the pixel isolation groove extends from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, the pixel isolation groove passes through the buried insulating layer, the pixel isolation structure defines a plurality of pixels in the semiconductor substrate, and a portion of the pixel isolation structure is covered by the buried insulating layer.

2. The image sensor according to claim 1, wherein: The pixel isolation structure includes: An insulating liner, disposed on an inner wall of the pixel isolation trench; A conductive layer is disposed in the pixel isolation groove; a pixel isolation insulating layer, disposed in the pixel isolation trench and on the conductive layer; and The barrier conductive layer is arranged between the conductive layer and the insulating liner.

3. The image sensor according to claim 2, wherein: The pixel isolation trench includes a first portion passing through the semiconductor substrate and a second portion passing through the buried insulating layer, and an insulating liner is disposed on an inner wall of each of the first portion and the second portion of the pixel isolation trench, wherein a first portion of the insulating liner disposed in the second portion of the pixel isolation trench contacts the buried insulating layer, and The second portion of the insulating liner disposed in the first portion of the pixel isolation trench contacts the blocking conductive layer.

4. The image sensor according to claim 2, wherein: An upper surface of the pixel isolation structure is disposed at the same level as an upper surface of the buried insulating layer.

5. The image sensor according to claim 2, wherein: The conductive layer includes a reflective metallic material.

6. The image sensor according to claim 2, wherein: The conductive layer includes at least one of aluminum, copper, silver, cobalt, tungsten, platinum, gold, chromium, titanium, nickel, molybdenum, iron, magnesium, iridium, palladium, and ruthenium.

7. The image sensor according to claim 2, further comprising: A device isolation layer is disposed in the device isolation trench, and the device isolation layer defines an active area of ​​the semiconductor substrate; as well as an etch stop layer, disposed between the first surface of the semiconductor substrate and the buried insulating layer, between the transmission gate and the buried insulating layer, and between the upper surface of the device isolation layer and the buried insulating layer, Wherein, the sidewall of the pixel isolation structure contacts the device isolation layer and the etching stop layer.

8. The image sensor according to claim 7, wherein: An upper surface of the conductive layer is disposed at a lower level than a bottom surface of the device isolation layer.

9. The image sensor according to claim 7, wherein: An upper surface of the conductive layer is disposed at a level higher than a bottom surface of the device isolation layer and lower than an upper surface of the device isolation layer.

10. The image sensor according to claim 7, wherein: An upper surface of the conductive layer is disposed at a higher level than an upper surface of the device isolation layer.

11. The image sensor according to claim 2, wherein: The pixel isolation insulating layer includes a void in the pixel isolation insulating layer.

12. The image sensor according to any one of claims 1 to 11, wherein: The semiconductor substrate has a first height in a vertical direction, and The pixel isolation structure has a second height in the vertical direction that is higher than the first height.

13. An image sensor, comprising: A semiconductor substrate, comprising a first surface and a second surface opposite to the first surface, and the semiconductor substrate further comprising a photoelectric conversion region; A transmission gate is disposed on the first surface of the semiconductor substrate; an etch stop layer disposed on the first surface of the semiconductor substrate to cover the transmission gate; as well as A pixel isolation structure is arranged in a pixel isolation trench, the pixel isolation trench extends from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, the pixel isolation structure includes a conductive layer, the conductive layer includes a reflective metal material, The end of the etching stop layer contacts the side wall of the pixel isolation structure, and the pixel isolation structure and the etching stop layer do not vertically overlap each other.

14. The image sensor according to claim 13, wherein: The pixel isolation structure also includes: A blocking conductive layer is disposed on a side wall of the conductive layer; a pixel isolation insulating layer disposed in a second portion of the pixel isolation trench, the second portion being disposed at a higher level than the first portion of the pixel isolation trench; and The insulating liner is arranged between the semiconductor substrate and the blocking conductive layer, and the insulating liner extends on the inner wall of the pixel isolation groove along a vertical direction perpendicular to the first surface of the semiconductor substrate.

15. The image sensor according to claim 14, further comprising: a buried insulating layer disposed on the etch stop layer to cover the transmission gate; as well as A device isolation layer is disposed in the device isolation trench, and the device isolation layer defines an active area of ​​the semiconductor substrate. The pixel isolation trench passes through the buried insulating layer and extends in a vertical direction.

16. The image sensor according to claim 15, wherein: The end of the etch stop layer is aligned with the sidewall of the device isolation layer, and The insulating liner contacts the sidewall of the device isolation layer and the end of the etching stop layer.

17. The image sensor according to claim 16, wherein: An insulating liner is disposed on the entire inner wall of the pixel isolation trench, and Wherein, the upper surface of the conductive layer is arranged at a level lower than the bottom surface of the device isolation layer.

18. The image sensor according to any one of claims 13 to 17, wherein: The conductive layer includes at least one of aluminum, copper, silver, cobalt, tungsten, platinum, gold, chromium, titanium, nickel, molybdenum, iron, magnesium, iridium, palladium, and ruthenium.

19. An image sensor, comprising: A semiconductor substrate, comprising a first surface and a second surface opposite to the first surface, and the semiconductor substrate further comprising a photoelectric conversion region; A transmission gate is disposed on the first surface of the semiconductor substrate; as well as A pixel isolation structure is arranged in a pixel isolation trench, wherein the pixel isolation trench extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate, Wherein, the pixel isolation structure includes: A conductive layer is disposed in the pixel isolation trench, and the conductive layer extends in a vertical direction perpendicular to the first surface of the semiconductor substrate; a blocking conductive layer, disposed on a side wall of the conductive layer in the pixel isolation trench; a pixel isolation insulating layer disposed on the conductive layer and the blocking conductive layer in the pixel isolation trench; and An insulating liner extends vertically on the inner wall of the pixel isolation trench, the insulating liner covers the side wall of the pixel isolation insulating layer and the side wall of the blocking conductive layer, and The upper surface of the pixel isolation insulating layer is arranged at a level higher than the first surface of the semiconductor substrate.

20. The image sensor according to claim 19, further comprising: A device isolation layer is disposed in the device isolation trench, and the device isolation layer defines an active area of ​​the semiconductor substrate; An etch stop layer is disposed on the first surface of the semiconductor substrate and the device isolation layer to cover the upper surface of the transmission gate; as well as a buried insulating layer disposed on an upper surface of the etch stop layer, The pixel isolation trench passes through the buried insulating layer and extends in a vertical direction, and an upper surface of the pixel isolation structure is arranged at the same level as an upper surface of the buried insulating layer.

Images