Terminal structure of super junction device and manufacturing method thereof

Abstract

The invention discloses a terminal structure of a super junction device. A protection epoxy film covers the surface of the super junction structure of a transition region and a terminal region. Each P-type column has a first surface region, and a portion of P-type impurities in the first surface region are thermally segregated into the protective epoxy film. The second P-type injection impurity is located in a second surface region of the super junction structure of the terminal region, the second surface region and the first surface region have an overlapping region, and the second P-type injection impurity is used for compensating the reduction amount of the P-type impurity in the first surface region, so that the PN balance of the super junction structure in the terminal region is improved; and the second P-type injection impurity enables the N-type net doping amount of the second surface area of the N-type column of the terminal area to be reduced at the same time. The invention further discloses a manufacturing method of the terminal structure of the super junction device. The PN balance of the terminal structure can be improved, the withstand voltage of the device can be improved, the process window of the P-type column of the device can be expanded, and the breakdown voltage consistency and reliability of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a terminal structure of a super junction device; the present invention also relates to a method for manufacturing the terminal structure of a super junction device. Background Art

[0002] Existing superjunction devices include a current flow region, which is usually also called a charge flow region, and a terminal region that withstands voltage, and a transition region is also included between the current flow region and the terminal region. In the current flow region, there are alternatingly arranged P-type columns and N-type columns, namely PN columns, and the PN columns form a superjunction structure. Usually, the P-type columns are usually composed of a P-type epitaxial layer filled in a trench, namely a superjunction trench, and the N-type columns are composed of an N-type epitaxial layer between the P-type columns. Taking the structure of a strip-shaped PN column as an example, there is a gate structure above each N-column, and the gate structure includes a planar gate structure and a trench gate structure. For the planar gate structure, the gate structure can partially cover the surrounding P-type columns or not. There is a P-type well above each P-type column, and there is a source region composed of an N+ region in the P-type well; a contact hole is formed on the top of the source region, and the source region is connected to the source electrode composed of the front metal layer, namely the metal source electrode, through the contact hole on the top; at the same time, the bottom of the contact hole in the source region is also connected to the P-type well through a high-concentration P+ contact region.

[0003] There is a P-type ring area in the transition area that is connected to the P-type well in the current flow area. There is a contact hole on the P-type area, and there is also a high-concentration P+ contact area under the contact hole; therefore, the P-type ring contacts the top contact hole through the P+ contact area and is connected to the source composed of the front metal layer through the top contact hole; in this way, the P-type ring and the P-type well in the current flow area and the source area are all connected to the source.

[0004] The terminal region is used to withstand the voltage between the source region and the drain region in the lateral direction. In general superjunction MOSFET devices, the terminal region is mainly composed of alternately arranged PN columns, or outside the alternately arranged PN columns, there is a cutoff region composed of N+ regions. When the alternately arranged PN columns are reverse biased between the source region and the drain region, the carriers therein deplete each other, forming a depletion region for bearing the lateral voltage. In order to improve the competitiveness of the device, the smallest terminal size is required, so that the lateral electric field strength of the PN column will increase, making the design of the device terminal more important, especially the design of the terminal can improve the relationship between the source-drain breakdown voltage (BVdss) Vs PN balance of the device, affecting the consistency of the process window and the product BVdss. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a terminal structure of a super junction device, which can improve the PN balance of the terminal structure, improve the voltage resistance of the terminal structure and thus improve the voltage resistance of the entire super junction device, and can also expand the process window of the P-type column of the device, and can improve the breakdown voltage consistency and reliability of the device. To this end, the present invention also provides a method for manufacturing the terminal structure of a super junction device.

[0006] To solve the above technical problems, in the terminal structure of the super junction device provided by the present invention, the middle area of ​​the super junction device is the current flow area, the terminal area surrounds the periphery of the current flow area, and the transition area is located between the current flow area and the terminal area.

[0007] A super junction structure is formed in the current flow region, the transition region and the terminal region; the super junction structure is formed in a semiconductor substrate and is composed of N-type columns and P-type columns arranged alternately, each of the P-type columns has a first initial P-type impurity, each of the N-type columns has a first initial N-type impurity, and a super junction unit is composed of one N-type column and an adjacent P-type column.

[0008] A terminal structure is formed in the transition region and the terminal region, and the terminal structure includes: the super junction structure, a protective epoxy film and a second P-type implanted impurity.

[0009] The protective epoxy film covers the surface of the super junction structure in the transition region and the termination region.

[0010] Each of the P-type pillars has a first surface region, and part of the P-type impurities in the first surface region are thermally segregated into the protective epoxy film, thereby reducing the amount of the P-type impurities in the first surface region of each of the P-type pillars.

[0011] The second P-type injection impurity is located in the second surface area of ​​the super junction structure in the terminal area, and there is no second P-type injection impurity in the current flow area; in the P-type column in the terminal area, the second surface area and the first surface area have an overlapping area, and the second P-type injection impurity is used to compensate for the reduction in the P-type impurity in the first surface area, thereby improving the PN balance of the super junction structure in the terminal area, and the second P-type injection impurity simultaneously reduces the N-type net doping amount in the second surface area of ​​the N-type column in the terminal area, so as to improve the voltage resistance of the super junction structure in the terminal area and improve the process window of the P-type column.

[0012] A further improvement is that the constituent film of the protective epoxy film includes a thermal oxidation film.

[0013] A further improvement is that the first initial P-type impurity includes boron or boron fluoride.

[0014] A further improvement is that, in the current flow region, a P-type well is formed on the surface of each of the P-type pillars, and the P-type well also extends to the surface of the adjacent N-type pillar.

[0015] A P-type ring is formed in the transition region, and the P-type ring covers the surface of each of the super junction units in the transition region.

[0016] The doping concentration of the P-type well is 1 to 2 orders of magnitude higher than the doping concentration of the P-type column, and the doping concentration of the P-type ring is 1 to 2 orders of magnitude higher than the doping concentration of the P-type column.

[0017] A further improvement is that the second P-type implanted impurity includes boron or boron fluoride, and the implantation conditions of the second P-type implanted impurity include 2E11cm -2 ~8E11cm -2 .

[0018] A further improvement is that by adjusting the second P-type injected impurity, the voltage resistance of the super junction structure in the terminal area is adjusted to be greater than the voltage resistance of the super junction structure in the current flow area, so that the voltage resistance of the super junction device is determined by the voltage resistance of the super junction structure in the current flow area.

[0019] A further improvement is that the process window of the P-type column is a variation window of the doping concentration of the first initial P-type impurity in the P-type column, the minimum doping concentration of the P-type column takes the optimal balanced doping concentration, and the maximum doping concentration of the P-type column ensures that the withstand voltage of the super junction device meets the minimum withstand voltage requirement value. The withstand voltage of the super junction structure in the terminal region is improved, so that the withstand voltage of the super junction device is improved, the maximum doping concentration of the P-type column is also increased, and the process window of the P-type column is expanded.

[0020] A further improvement is that a first epitaxial layer is formed on the surface of the semiconductor substrate, and the super junction structure is formed in the first epitaxial layer.

[0021] The first epitaxial layer is a single epitaxial layer with a single resistivity.

[0022] Alternatively, the first epitaxial layer is formed by stacking a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, and the resistivity of the second epitaxial sublayer is lower than the resistivity of the first epitaxial sublayer.

[0023] A further improvement is that the first epitaxial layer is N-type doped, the components of the P-type pillars include a P-type doped second epitaxial layer filled in the trenches, and the N-type pillars are composed of the first epitaxial layer between the P-type pillars;

[0024] The fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type column.

[0025] In order to solve the above technical problems, the present invention provides a method for manufacturing a terminal structure of a super junction device, comprising the following steps:

[0026] Step 1: Divide the formation area of ​​the super junction device into a current flow area, a transition area and a terminal area, wherein the middle area of ​​the super junction device is the current flow area, the terminal area surrounds the periphery of the current flow area, and the transition area is located between the current flow area and the terminal area.

[0027] A super junction structure is formed in the current flow region, the transition region and the terminal region; the super junction structure is formed in a semiconductor substrate and is composed of N-type columns and P-type columns arranged alternately, each of the P-type columns has a first initial P-type impurity, each of the N-type columns has a first initial N-type impurity, and a super junction unit is composed of one N-type column and an adjacent P-type column.

[0028] Step 2: Perform selective P-type ion implantation to form second P-type implanted impurities in the second surface region of the super junction structure in the terminal region; and the second P-type implanted impurities are absent in the current flow region.

[0029] Step three: forming a protective epoxy film and performing pattern etching on the protective epoxy film, wherein the pattern etching makes the protective epoxy film only on the surface of the super junction structure in the transition region and the terminal region.

[0030] During the formation of the protective epoxy film, part of the P-type impurities in the first surface region of each of the P-type pillars may be thermally segregated into the protective epoxy film, thereby reducing the amount of the P-type impurities.

[0031] In the P-type column in the terminal area, the second surface area and the first surface area have an overlapping area, and the second P-type injected impurities are used to compensate for the reduced amount of P-type impurities in the first surface area, thereby improving the PN balance of the super junction structure in the terminal area. The second P-type injected impurities simultaneously reduce the N-type net doping amount in the second surface area of ​​the N-type column in the terminal area, so as to improve the voltage resistance of the super junction structure in the terminal area and improve the process window of the P-type column.

[0032] A further improvement is that in step three, the constituent film of the protective epoxy film includes a thermal oxidation film formed by a thermal oxidation process.

[0033] A further improvement is that the first initial P-type impurity includes boron or boron fluoride.

[0034] A further improvement is that before step 3, the following steps are also included:

[0035] A P-type well is formed in the current flow region, the P-type well being located on a surface of each of the P-type pillars and also extending onto a surface of an adjacent N-type pillar.

[0036] A P-type ring is formed in the transition region, and the P-type ring covers the surface of each of the super junction units in the transition region.

[0037] The doping concentration of the P-type well is 1 to 2 orders of magnitude higher than the doping concentration of the P-type column, and the doping concentration of the P-type ring is 1 to 2 orders of magnitude higher than the doping concentration of the P-type column.

[0038] A further improvement is that the second P-type implanted impurity includes boron or boron fluoride, and the implantation conditions of the second P-type implanted impurity include 2E11cm -2 ~8E11cm -2 .

[0039] A further improvement is that by adjusting the second P-type injected impurity, the voltage resistance of the super junction structure in the terminal area is adjusted to be greater than the voltage resistance of the super junction structure in the current flow area, so that the voltage resistance of the super junction device is determined by the voltage resistance of the super junction structure in the current flow area.

[0040] A further improvement is that the process window of the P-type column is a variation window of the doping concentration of the first initial P-type impurity in the P-type column, the minimum doping concentration of the P-type column takes the optimal balanced doping concentration, and the maximum doping concentration of the P-type column ensures that the withstand voltage of the super junction device meets the minimum withstand voltage requirement value. The withstand voltage of the super junction structure in the terminal region is improved, so that the withstand voltage of the super junction device is improved, the maximum doping concentration of the P-type column is also increased, and the process window of the P-type column is expanded.

[0041] A further improvement is that a first epitaxial layer is formed on the surface of the semiconductor substrate, and the super junction structure is formed in the first epitaxial layer.

[0042] The first epitaxial layer is a single epitaxial layer with a single resistivity.

[0043] Alternatively, the first epitaxial layer is formed by stacking a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, and the resistivity of the second epitaxial sublayer is lower than the resistivity of the first epitaxial sublayer.

[0044] A further improvement is that the first epitaxial layer is N-type doped, and step 1 includes the following sub-steps:

[0045] A plurality of trenches are formed in the first epitaxial layer.

[0046] Filling the trench with a P-type doped second epitaxial layer, the P-type doped second epitaxial layer filled in the trench is used as a component of the P-type column, and the N-type column is composed of the first epitaxial layer between the P-type columns;

[0047] The fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type column.

[0048] The present invention adds a second P-type injection impurity to the second surface area of ​​the super junction structure in the terminal area. The second P-type injection impurity is injected into both the P-type column and the N-type column. In the P-type column, the second P-type injection impurity can compensate for the reduction of the P-type impurity in the first surface area of ​​the P-type column due to the thermal segregation of the P-type impurity between the semiconductor substrate and the protective epoxy film, thereby improving the PN balance between the P-type column and the N-type column in the first surface area of ​​the terminal area; the second P-type injection impurity can also reduce the N-type net doping amount in the second surface area of ​​the N-type column at the same time. The reduction of the N-type net doping amount is more conducive to the depletion of the surface area of ​​the N-type column, and the electric field intensity of the surface area of ​​the N-type column changes more slowly. Combined with the improvement of PN balance, the withstand voltage capability of the super junction structure in the terminal area can be improved. Since the terminal structure is mainly used to withstand lateral voltage, it can also improve the ability of the device terminal to withstand lateral voltage. Finally, the withstand voltage capability of the entire super junction structure can be improved. When the corresponding super junction device is a super junction MOSFET, the source-drain breakdown voltage (BVdss) of the device can be improved.

[0049] Corresponding to super junction devices, the P-type column in the super junction structure is usually formed by a P-type epitaxial layer filled in the groove, so expanding the process window of the P-type column is the most critical technology of the super junction device. The present invention can expand the process window of the P-type column by adding a second P-type injected impurity, thereby optimizing the performance of the device. The main reasons are: the second P-type injected impurity of the present invention can increase the voltage resistance of the super junction structure in the terminal area. Through optimization, the voltage resistance of the device can be determined by the voltage resistance of the super junction structure in the current flow area. Compared with the voltage resistance of the super junction structure in the terminal area, which is very sensitive to the concentration of the P-type column, the voltage resistance of the super junction structure in the current flow area is less sensitive to the concentration of the P-type column, so the process window of the P-type column can be expanded.

[0050] When the process window of the P-type column is expanded, the adjustment range of the concentration of the P-type column will increase, which will be more conducive to improving the performance of the super junction device. For example, by increasing the doping concentration of the P-type column, the single pulse avalanche energy (EAS) performance of the device can be further improved.

[0051] In addition, the present invention improves the voltage resistance of the super junction structure in the terminal area, and it is easy to set the super junction device to be the active area, that is, the current flow area, which breaks down first. Compared with the characteristic that the breakdown of the terminal area is located at the interface between the semiconductor substrate and the protective epoxy layer, which makes the breakdown voltage unstable, the breakdown of the current flow area can be ensured to be located inside the semiconductor substrate, so the breakdown voltage is stable, thereby improving the consistency and stability of the breakdown voltage of the super junction device, such as the BVdss of the super junction MOSFET.

[0052] In addition, the second P-type implanted impurity of the present invention is implemented by selective implantation and will not be formed in the current flow region, so it will not affect the on-resistance of the device in the current flow region.

[0053] In addition, during the reverse recovery of the body diode of a superjunction device such as a superjunction MOSFET, the second P-type impurity injection of the present invention causes the holes in the terminal region to be more inclined to be pumped during the P-type ring pumping process toward the transition region, i.e., it is conducive to hole pumping, thereby reducing the possibility of damage to the body diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0055] Figure 1 is a top view of a super junction device according to an embodiment of the present invention;

[0056] Figure 2 is a cross-sectional schematic diagram of a super junction device according to an embodiment of the present invention;

[0057] Figure 3A-Figure 3I Schematic cross-sectional view of the device in each step of the method for manufacturing a super junction device according to an embodiment of the present invention;

[0058] Figure 4 is a flow chart of a method for manufacturing a super junction device according to an embodiment of the present invention;

[0059] Figure 5 It is a test diagram of the relationship between BVdss and the doping concentration of the P-type column of the super junction device according to the embodiment of the present invention and the existing super junction device. DETAILED DESCRIPTION

[0060] like Figure 2 As shown is a cross-sectional schematic diagram of a super junction device according to an embodiment of the present invention; in the terminal structure of the super junction device according to the embodiment of the present invention, the middle region of the super junction device is a current flow region, the terminal region surrounds the periphery of the current flow region, and the transition region is located between the current flow region and the terminal region. Figure 2 In the embodiment, the current flow area is area 1, namely, the active area; the transition area is area 2, and the terminal area is area 3.

[0061] A super junction structure is formed in the current flow region, the transition region and the terminal region; the super junction structure is formed in a semiconductor substrate 1 and includes alternatingly arranged N-type columns and P-type columns, each of the P-type columns has a first initial P-type impurity, each of the N-type columns has a first initial N-type impurity, and a super junction unit includes one of the N-type columns and an adjacent P-type column.

[0062] In the embodiment of the present invention, a first epitaxial layer 2 is formed on the surface of the semiconductor substrate 1, and the super junction structure is formed in the first epitaxial layer 2. The first epitaxial layer 2 is N-type doped, the components of the P-type column include a P-type doped second epitaxial layer filled in the trench, and the N-type column is composed of the first epitaxial layer 2 between the P-type columns.

[0063] In some embodiments, the semiconductor substrate 1 is a silicon substrate. The first epitaxial layer 2 is a silicon epitaxial layer.

[0064] Figure 2 In the figure, the grooves in zone 1 are individually marked with mark 41, the grooves in zone 2 are individually marked with mark 42, and the grooves in zone 3 are individually marked with mark 43; the P-type columns in zone 1 are individually marked with mark 51, the P-type columns in zone 2 are individually marked with mark 52, and the P-type columns in zone 3 are individually marked with mark 53. Figure 2 In the figure, Wp1 represents the width of the groove 41, which is also the width of the P-type column 51; Wp2 represents the width of the groove 42, which is also the width of the P-type column 52; Wp3 represents the width of the groove 43, which is also the width of the P-type column 53; Wn1 represents the width of the N-type column in zone 1, Wn2 represents the width of the N-type column in zone 2, and Wn3 represents the width of the N-type column in zone 3.

[0065] Figure 2 In the embodiment, the P-type column is composed of the P-type doped second epitaxial layer filled in the trench. In other embodiments, the P-type column can also be composed of the P-type doped second epitaxial layer filled in the trench and the P-type injection layer at the bottom of the trench.

[0066] In some embodiments, the first epitaxial layer 2 is a single epitaxial layer with a single resistivity. In other embodiments, the first epitaxial layer 2 is formed by stacking a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, and the resistivity of the second epitaxial sublayer is lower than the resistivity of the first epitaxial sublayer.

[0067] The terminal structure is formed in the transition region and the terminal region, and the terminal structure includes: the super junction structure, a protective epoxy film 7 and a second P-type implanted impurity 61 .

[0068] The protective epoxy film 7 covers the surface of the super junction structure in the transition region and the terminal region.

[0069] Each of the P-type pillars 53 in the terminal region has a first surface region, and part of the P-type impurities in the first surface region may be thermally segregated into the protective epoxy film 7 so as to reduce the amount of the P-type impurities in the first surface region of each of the P-type pillars.

[0070] The second P-type injection impurity 61 is located in the second surface area of ​​the super junction structure in the terminal area; in the P-type column in the terminal area, the second surface area and the first surface area have an overlapping area, and the second P-type injection impurity 61 is used to compensate for the reduction in the P-type impurity in the first surface area, thereby improving the PN balance of the super junction structure in the terminal area. The second P-type injection impurity 61 simultaneously reduces the N-type net doping amount in the second surface area of ​​the N-type column in the terminal area, so as to improve the voltage resistance of the super junction structure in the terminal area and improve the process window of the P-type column.

[0071] There is no second P-type implanted impurity 61 in the current flow region, thus preventing the second P-type implanted impurity 61 from having an adverse effect on the on-resistance of the device.

[0072] In the embodiment of the present invention, the constituent film of the protective epoxy film 7 includes a thermal oxidation film.

[0073] The first initial P-type impurity includes boron or boron fluoride.

[0074] During the thermal oxidation process of the thermal oxide film, the boron element in the first surface region of the P-type column is easily adsorbed into the thermal oxide film at the Si-SiO2 interface between the semiconductor substrate 1 and the protective epoxy film 7, thereby reducing the P-type doping concentration in the first surface region of the P-type column.

[0075] In the current flow region, a P-type well 6 is formed on the surface of each P-type column, and the P-type well 6 also extends to the surface of the adjacent N-type column.

[0076] A P-type ring 6a is formed in the transition region, and the P-type ring 6a covers the surface of each super junction unit in the transition region. The doping concentration of the P-type well 6 is 1 to 2 orders of magnitude higher than the doping concentration of the P-type column, and the doping concentration of the P-type ring 6a is 1 to 2 orders of magnitude higher than the doping concentration of the P-type column.

[0077] Figure 2In the embodiment, the P-type well 6 is also represented by P, and the P-type ring 6a is also represented by P'. In some embodiments, the P-type well 6 and the P-type ring 6a are formed simultaneously using the same process.

[0078] In the current flow area and the transition area, although the amount of P-type impurities in the first surface area of ​​each of the P-type columns 51 and 52 will be reduced due to thermal segregation into the protective epoxide film 7, since the P-type well 6 and the P-type ring 6a both cover the first surface area of ​​the corresponding P-type columns 51 and 52, the amount of P-type impurities reduced by thermal segregation is much smaller than the P-type doping amount of the P-type well 6 and the P-type ring 6a, and the influence on the P-type doping concentration of the P-type well 6 and the P-type ring 6a can be basically ignored, so it will not have an adverse effect on the performance of the device. In the present invention, only the reduction of the amount of P-type impurities in the first surface area of ​​the P-type column 53 in the terminal area will bring adverse effects, that is, it will have an adverse effect on the PN balance of the P-type column 53 and the top area of ​​the N-type column and further affect the voltage resistance of the device, that is, the source-drain breakdown voltage will become smaller.

[0079] In some embodiments, the second P-type implanted impurity 61 includes boron or boron fluoride, and the implantation conditions of the second P-type implanted impurity 61 include 2E11cm -2 ~8E11cm -2 .

[0080] In an embodiment of the present invention, by adjusting the second P-type injected impurity 61, the voltage resistance of the super junction structure in the terminal area is adjusted to be greater than the voltage resistance of the super junction structure in the current flow area, so that the voltage resistance of the super junction device is determined by the voltage resistance of the super junction structure in the current flow area.

[0081] The process window of the P-type column is a variation window of the doping concentration of the first initial P-type impurity in the P-type column. The minimum doping concentration of the P-type column takes the optimal balanced doping concentration, and the maximum doping concentration of the P-type column ensures that the voltage resistance of the super junction device meets the minimum voltage resistance requirement value. The fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type column. The process window of the P-type column is the most critical feature of the super junction device, and expanding the process window of the P-type column is the most critical process technology of the super junction device. In the embodiment method of the present invention, since the voltage resistance of the super junction structure in the terminal area is improved, the voltage resistance of the entire device is also improved. Therefore, the maximum doping concentration of the process window of the P-type column is also improved, so the process window of the P-type column is expanded.

[0082] In addition, by setting the process window of the P-type column to between the optimal balanced doping concentration and the maximum doping concentration, the doping concentration of the P-type column will be greater than or equal to the doping concentration of the N-type column, which is beneficial to improving the EAS performance of the device while ensuring the withstand voltage.

[0083] like Figure 2 As shown, in the embodiment of the present invention, in the current flow area, it also includes:

[0084] The gate structure adopts a planar gate, which is formed by stacking a gate oxide film 8 and a polysilicon gate 9.

[0085] Each of the polysilicon gates 9 covers the corresponding P-type well 6 and extends to the surface of the N-type pillars between the P-type wells 6 . The surface of the P-type well 6 covered by the polysilicon gates 9 is used to form a channel.

[0086] In some embodiments, a JFET region is further formed on the surface of the N-type pillar between the P-type wells 6 in the current flow region.

[0087] A source region 10 composed of an N+ region is formed on the surface of the P-type well 6 and the source region 10 is self-aligned with the side of the polysilicon gate 9. The outermost periphery of the terminal region includes an N+ doped cut-off region 10a. Figure 1 The cut-off region corresponding to the mark 21 in FIG. 1 has the same structure.

[0088] In some embodiments, the thickness of the protective epoxy film 7 is The thermal oxidation process temperature of the protective epoxy film 7 is above 800°C.

[0089] For a 500V to 700V MOSFET, i.e., a super junction MOSFET, the thickness of the gate oxide film 8 is The thickness of the polysilicon gate 9 is

[0090] The process conditions of the P-type well 6 need to meet the threshold voltage requirements. For a device with a threshold voltage of 2-4V, the process conditions of the ion implantation of the P-type well 6 can be B 30-100keV, that is, the implanted impurity is boron and the implantation dose is 3E13cm -2 ~1E14cm -2 The implantation energy is 30keV to 100keV. The P-type ring 6a is formed simultaneously with the P-type well 6 by using the same process.

[0091] The process conditions for ion implantation of the source region 10 are as follows: the implanted impurities are phosphorus or arsenic, and the implantation dose is 3E15 cm -2 ~5E15cm-2 The implantation energy is 30keV to 100keV. The process conditions of the cut-off region 10a are the same as those of the source region 10 and they are formed simultaneously.

[0092] like Figure 2 As shown, in the current flow region, the super junction device further includes the following front structure:

[0093] Interlayer film 11, contact hole 12a, source electrode 14 and gate electrode (not shown) composed of a front metal layer.

[0094] The contact hole 12a passes through the interlayer film 11. The source region 10 is connected to the source electrode 14 through the corresponding contact hole 12a at the top, and the polysilicon gate 9 is connected to the gate electrode through the corresponding contact hole 12a at the top.

[0095] The thickness of the interlayer film 11 is 8000 angstroms to 10000 angstroms.

[0096] The contact hole 12 a corresponding to the top of the source region 10 also passes through the source region 10 and contacts the P-type well 6 at the bottom, and a P+ doped well contact region 13 is formed at the bottom of the contact hole 12 a corresponding to the source region 10 .

[0097] The super junction device further includes the following back side structure:

[0098] The N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1. The semiconductor substrate 1 adopts an N-type heavily doped structure and directly forms a drain region of the super junction device after the semiconductor substrate 1 is thinned. A drain composed of a back metal layer 15 is formed on the back of the drain region.

[0099] In the transition region, the P-type ring 6a is connected to the source 14 through a contact hole 12b.

[0100] In the terminal region, a polysilicon field plate 9a is further formed on the surface of the protective epoxy film 7. The polysilicon field plate 9a is connected to an electrode 14b composed of a front metal layer through a contact hole. The electrode 14b can be a gate.

[0101] In the embodiment of the present invention, a second P-type injection impurity 61 is added to the second surface region of the super junction structure in the terminal region. The second P-type injection impurity 61 is injected into both the P-type column and the N-type column. In the P-type column, the second P-type injection impurity 61 can compensate for the reduction of the P-type impurities in the first surface region of the P-type column due to the thermal segregation of the P-type impurities between the semiconductor substrate 1 and the protective epoxy film 7, thereby improving the PN balance between the P-type column and the N-type column in the first surface region of the terminal region. The second P-type injection impurity 61 can also simultaneously reduce the N-type net doping amount in the second surface region of the N-type column. The reduction of the N-type net doping amount is more conducive to the depletion of the surface region of the N-type column, and the electric field strength of the surface region of the N-type column changes more slowly. Combined with the improvement of PN balance, the withstand voltage capability of the super junction structure in the terminal region can be improved. Since the terminal structure is mainly used to withstand lateral voltage, it can also improve the ability of the device terminal to withstand lateral voltage. Finally, the withstand voltage capability of the entire super junction structure can be improved. When the corresponding super junction device is a super junction MOSFET, the source-drain breakdown voltage (BVdss) of the device can be improved.

[0102] Corresponding to super junction devices, the P-type column in the super junction structure is usually formed by a P-type epitaxial layer filled in the groove, so expanding the process window of the P-type column is the most critical technology of the super junction device. The embodiment of the present invention can expand the process window of the P-type column by adding a second P-type injection impurity 61, thereby optimizing the performance of the device. The main reasons are: the second P-type injection impurity 61 of the present invention can increase the voltage resistance of the super junction structure in the terminal area. Through optimization, the voltage resistance of the device can be determined by the voltage resistance of the super junction structure in the current flow area. Compared with the voltage resistance of the super junction structure in the terminal area, which is very sensitive to the concentration of the P-type column, the voltage resistance of the super junction structure in the current flow area is less sensitive to the concentration of the P-type column, so the process window of the P-type column can be expanded.

[0103] When the process window of the P-type column is expanded, the adjustment range of the concentration of the P-type column will increase, which will be more conducive to improving the performance of the super junction device. For example, by increasing the doping concentration of the P-type column, the single pulse avalanche energy (EAS) performance of the device can be further improved.

[0104] In addition, the embodiment of the present invention improves the voltage resistance of the super junction structure in the terminal area, and it is easy to set the super junction device to be the active area, that is, the current flow area, to break down first. Compared with the characteristic that the breakdown of the terminal area is located at the interface between the semiconductor substrate 1 and the protective epoxy layer, which makes the breakdown voltage unstable, when the current flow area breaks down, it can be ensured that the breakdown is located inside the semiconductor substrate 1, so the breakdown voltage is stable, thereby improving the consistency and stability of the breakdown voltage of the super junction device, such as the BVdss of the super junction MOSFET.

[0105] In addition, the second P-type implanted impurities 61 of the embodiment of the present invention are implemented by selective implantation and will not be formed in the current flow region, so they will not affect the on-resistance of the device in the current flow region.

[0106] In addition, during the reverse recovery of the body diode of a super junction device such as a super junction MOSFET, the second P-type injected impurity 61 in the embodiment of the present invention is more inclined to pump the holes in the terminal region toward the P-type ring 6a in the transition region, which is conducive to hole pumping, thereby reducing the possibility of damage to the body diode.

[0107] Compared with the existing technology, the embodiment of the present invention is to inject a certain concentration of P-type impurities into the upper part of the P-type column and the upper part of the N-type epitaxial layer in the terminal area, so that the reduction of P-type impurities caused by the segregation of B to oxide in the thermal oxide film formation process after the formation of the PN column at the top of the P-type column is compensated, and at the same time, the concentration at the top of the N-type epitaxial layer is reduced, so that PN depletion is easier to develop in the top area, and the distribution of the electric field strength in the N area is more uniform, thereby improving the ability of the terminal area to withstand reverse bias and improving the source-drain breakdown ability of the device. At the same time, the increase in the concentration of the P-type column at the top of the terminal area also reduces the sensitivity of the device terminal BVdss to the deviation of the impurity concentration of the P column-N column, thereby expanding the process window of the P-type impurity concentration and improving the consistency of the device.

[0108] In the manufacturing process of existing devices, after the epitaxial formation of the P-type column, Pwell will be formed. Pwell is mainly formed in the active area and transition area of ​​the device. Generally, Pwell will cover the area at the top of the P-type column. Generally, the impurity concentration of Pwell is 1-2 orders of magnitude higher than that of the P-type column. When the device is reverse biased, the Pwell of the device is connected to the source through the P+ layer injected through the contact hole and is at 0 potential.

[0109] After the Pwell is formed, the prior art needs to form a field oxide layer (Field OX), which is the protective ring oxide layer. Field oxide is generally formed by thermal oxidation and has a thickness of 6000-10000 angstroms. During the thermal oxidation process, the P-type impurities B or BF2 (B is used in general processes) on the top of the P-type column will be adsorbed into the thermal oxide film during the thermal process, causing the P-type impurity concentration in SI to decrease. This problem, in the area where Pwell is injected, because the P-type impurity concentration of PWell is much higher than that of the P-type column, the general Pwell surface concentration is about E17 / cm 3 , and the P-type impurity concentration of the P-type column including its top is about E15 / cm 3. Therefore, in the active area or transition area, the loss of B in Si during the formation of the thermal oxide film has no obvious effect on the performance of the device. However, in the terminal area that bears voltage, since there are only P-type impurities doped in the P-type epitaxial filling, the loss of B during the formation of the thermal oxide film will cause a net reduction of P-type impurities at the top of the P-type column, causing the balance of P-type impurities and N-type impurities at the top of the terminal area to be affected, thereby affecting the BVdss of the terminal and the BVdss of the device.

[0110] In the embodiment of the present invention, by introducing photolithography to open the terminal region and then performing ion implantation in the terminal region, the P-type impurities reduced in the thermal oxidation film process are compensated, the PN balance of the terminal region can be improved, and the BVdss of the device can be increased.

[0111] Experiments have confirmed that under this manufacturing process, the window of P-type column concentration can be expanded, improving the manufacturability of the device and the consistency of BVdss.

[0112] One advantage of increasing the P-type impurity concentration at the top of the P column through ion implantation in the terminal region is that during the reverse recovery of the body diode, the holes in the terminal region are more inclined to be pumped toward the transition region (usually with a Pwell injection ring), which can reduce the possibility of damage to the body diode.

[0113] like FIG. 3A to FIG. 3I , which is a schematic cross-sectional view of a device in each step of a method for manufacturing a super junction device according to an embodiment of the present invention; the method for manufacturing a terminal structure of a super junction device according to an embodiment of the present invention comprises the following steps:

[0114] Step 1: Divide the formation area of ​​the super junction device into a current flow area, a transition area and a terminal area, wherein the middle area of ​​the super junction device is the current flow area, the terminal area surrounds the periphery of the current flow area, and the transition area is located between the current flow area and the terminal area.

[0115] A super junction structure is formed in the current flow region, the transition region and the terminal region; the super junction structure is formed in a semiconductor substrate 1 and is composed of N-type columns and P-type columns arranged alternately, each of the P-type columns has a first initial P-type impurity, each of the N-type columns has a first initial N-type impurity, and a super junction unit is composed of one N-type column and an adjacent P-type column.

[0116] In the embodiment method of the present invention, a first epitaxial layer 2 is formed on the surface of the semiconductor substrate 1, and the super junction structure is formed in the first epitaxial layer 2. In some embodiment methods, the first epitaxial layer 2 is a single epitaxial layer with a single resistivity. In other embodiment methods, the first epitaxial layer 2 is formed by stacking a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, and the resistivity of the second epitaxial sublayer is lower than the resistivity of the first epitaxial sublayer.

[0117] The semiconductor substrate 1 is a silicon substrate. The first epitaxial layer 2 is a silicon epitaxial layer.

[0118] The first initial P-type impurity includes boron or boron fluoride.

[0119] The first epitaxial layer 2 is N-type doped, and step 1 includes the following sub-steps:

[0120] like Figure 3A As shown, a hard mask layer 3 is formed.

[0121] The hard mask layer 3 is patterned to define the formation area of ​​the trench.

[0122] The first epitaxial layer 2 is etched using the hard mask layer 3 as a mask to form a plurality of trenches in the first epitaxial layer 2 . Figure 3A In the figure, the grooves in zone 1, zone 2 and zone 3 are marked with reference numerals 41, 42 and 43, respectively, and have widths Wp1, Wp2 and Wp3, respectively.

[0123] like Figure 3B As shown, a P-type doped second epitaxial layer is filled in the trench, the P-type column is composed of the P-type doped second epitaxial layer filled in the trench, and the N-type column is composed of the first epitaxial layer 2 between the P-type columns. Figure 3B , the P-type columns in area 1, area 2 and area 3 are marked with marks 51, 52 and 53 respectively. In other embodiments, before filling the second epitaxial layer, a P-type ion implantation region is formed at the bottom of the trench, and the P-type ion implantation region and the second epitaxial layer filled in the trench are stacked together to form the P-type column, and the P-type ion implantation region at the bottom of the P-type column can eliminate the problem of reduced consistency caused by inconsistent trench depth.

[0124] The method of the embodiment of the present invention further includes:

[0125] like Figure 3C As shown, a P-type well 6 is formed in the current flow region. The P-type well 6 is located on the surface of each of the P-type pillars and also extends to the surface of the adjacent N-type pillars.

[0126] A P-type ring 6a is formed in the transition region, and the P-type ring 6a covers the surface of each super junction unit in the transition region. In some embodiments, the P-type ring 6a and the P-type well 6 are formed simultaneously using the same process; in other embodiments, the P-type ring 6a can also be formed using a separate photolithography definition plus ion implantation.

[0127] The doping concentration of the P-type well 6 is 1 to 2 orders of magnitude higher than that of the P-type column, and the doping concentration of the P-type ring 6 a is 1 to 2 orders of magnitude higher than that of the P-type column.

[0128] Step 2: Figure 3D As shown, selective P-type ion implantation is performed to form a second P-type implant impurity 61 in the second surface region of the super junction structure in the terminal region; there is no second P-type implant impurity 61 in the current flow region. Figure 3D In the figure, the selective P-type ion implantation is indicated by the arrow line corresponding to the mark 102 , and the selected implantation area is defined by the pattern of the photoresist 101 .

[0129] In some embodiments, the second P-type implanted impurity 61 includes boron or boron fluoride, and the implantation conditions of the second P-type implanted impurity 61 include 2E11cm -2 ~8E11cm -2 .

[0130] Step 3: Figure 3E As shown, a protective epoxy film 7 is formed and the protective epoxy film 7 is patterned and etched, and the patterned etching makes the protective epoxy film 7 only on the surface of the super junction structure in the transition area and the terminal area.

[0131] During the process of forming the protective epoxy film 7 , part of the P-type impurities in the first surface region of each of the P-type pillars will be thermally segregated into the protective epoxy film 7 , thereby reducing the amount of the P-type impurities.

[0132] In the P-type column in the terminal area, the second surface area and the first surface area have an overlapping area, and the second P-type injected impurity 61 is used to compensate for the reduced amount of P-type impurities in the first surface area, thereby improving the PN balance of the super junction structure in the terminal area. The second P-type injected impurity 61 simultaneously reduces the N-type net doping amount in the second surface area of ​​the N-type column in the terminal area, so as to improve the voltage resistance of the super junction structure in the terminal area and improve the process window of the P-type column.

[0133] In the method of the embodiment of the present invention, the protective epoxy film 7 is formed by patterning a thermal oxide film formed by a thermal oxidation process, that is, the thermal oxide film, that is, a thick field oxide film, is first formed, and then the thermal oxide film is patterned and etched to form the protective epoxy film 7.

[0134] In the method of the embodiment of the present invention, by adjusting the second P-type injected impurity 61, the voltage resistance of the super junction structure in the terminal area is adjusted to be greater than the voltage resistance of the super junction structure in the current flow area, so that the voltage resistance of the super junction device is determined by the voltage resistance of the super junction structure in the current flow area.

[0135] The process window of the P-type column is a variation window of the doping concentration of the first initial P-type impurity in the P-type column. The minimum doping concentration of the P-type column takes the optimal balanced doping concentration, and the maximum doping concentration of the P-type column ensures that the withstand voltage of the super junction device meets the minimum withstand voltage requirement. The withstand voltage of the super junction structure in the terminal region is improved, so that the withstand voltage of the super junction device is improved, the maximum doping concentration of the P-type column is also increased, and the process window of the P-type column is expanded.

[0136] In step 1, the fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type column. It can be seen that the larger the process window of the P-type column, the lower the control accuracy requirement for the doping concentration of the second epitaxial layer, and thus the more conducive to the formation of the second epitaxial layer.

[0137] The method of the embodiment of the present invention also includes the following steps:

[0138] Step 4: Figure 3F As shown, a gate oxide film 8 is formed by a thermal oxidation process, and then a polysilicon gate 9 is formed.

[0139] In the method of the embodiment of the present invention, for a 500V to 700V super junction MOSFET, the thickness of the gate oxide film 8 is The thickness of the polysilicon gate 9 is

[0140] Step 5: Figure 3F As shown, the polysilicon gate 9 and the gate oxide film 8 are etched in sequence by photolithography definition and etching process to form the planar gate structure formed by the etched gate oxide film 8 and the polysilicon gate 9. While forming the polysilicon gate 9, a polysilicon field plate 9a is formed on the surface of the protective epoxy film 7.

[0141] The planar gate structure is located in the current flow region, and is composed of an N-type column 2 and an adjacent P-type column 51 to form a super junction unit; the polysilicon gate 9 corresponding to each of the split-gate planar gate structures covers the corresponding P-type well 6 and extends to the top of the N-type column between the adjacent P-type wells 6. The surface of the P-type well 6 covered by the polysilicon gate 9 is used to form a channel.

[0142] Step 6: Figure 3G As shown, photolithography plus N+ ion implantation is used to form a source region 10 composed of N+ regions on the surface of the P-type well 6 in the current flow area, and the cut-off region 10a is formed at the outermost side of the terminal area. The source region 10 and the side of the polysilicon gate 9 are self-aligned.

[0143] The process conditions for ion implantation of the source region 10 are as follows: the implanted impurities are phosphorus or arsenic, and the implantation dose is 3E15 cm -2 ~5E15cm -2 , the injection energy is 30keV~100keV.

[0144] Step 7: Figure 3H As shown, an interlayer film 11 is deposited, and a contact hole opening is formed through the interlayer film 11 by using a photolithography and etching process. Figure 3F The openings of the middle contact holes are marked with reference numerals 121a and 121b, respectively.

[0145] The interlayer film 11 is a combination of an undoped oxide film and a BPSG film. The thickness of the interlayer film 11 is

[0146] In the etching of the contact hole 121a in the current flow area, the N+ at the bottom, i.e. the source area 10, needs to be etched away, i.e. silicon over-etching is required. The amount of silicon over-etching can be between 2000 angstroms and 4000 angstroms, which is specifically determined according to the injection conditions of the ion injection corresponding to the source area 10, i.e. the injection dose and the injection energy.

[0147] like Fig. 3I As shown, after the opening of the contact hole is formed and before the metal is filled, the step of performing P+ ion implantation at the bottom of the openings 121a and 121b of the contact hole to form a well contact region 13 is also included. Preferably, the P-type implanted impurity of the well contact region 13 here is B, BF2, or a combination of B and BF2, generally with an implantation energy of 30keV to 80keV and an implantation dose of 1E15cm -2 ~3E15cm -2, the device's ability to resist current shock can be improved by optimizing the injection conditions. In order to better improve the softness of the reverse recovery process of the body diode, the energy and dose of the P-type injection of the well contact area 13 can also be reduced. For example, the energy can be BF2, 5keV~40KEV, 5E14cm -2 ~2E15 cm -2 ,The selection of dose can ensure the minimum dose for forming ohmic contact, and the selection of energy mainly considers the ,capacity of ion implantation equipment.

[0148] like Figure 2 As shown, after the contact hole etching and the P+ ion implantation at the bottom are completed, a blocking layer formed by stacking Ti and TiN is deposited, and then metal tungsten (W) is deposited to fill the opening of the contact hole and form the contact holes 12a and 12b. For the opening of the contact hole with a width of 0.6 microns, the W thickness can be set to 4000 angstroms, and then plasma dry etching is performed to completely remove the metal on the surface. When the size of all contact holes is relatively large, for example, the aspect ratio is less than or equal to 0.5, and can be completely filled with AlCu or AlSiCu, only Ti-TiN needs to be deposited, and W deposition and corresponding etching are not required.

[0149] Step 8: Figure 2 As shown, a front metal deposition is performed to form a front metal layer, and a photolithography plus metal etching process is used to form the gate and the source 14 and the electrode 14a composed of the front metal layer. Each source region 18 and the corresponding P-type well 6 are connected to the source 14 through the same contact hole 12a at the top; the polysilicon gate 9 is connected to the gate through the corresponding contact hole (not shown) at the top. The polysilicon field plate 9a is connected to the electrode 14b through the contact hole, and the electrode 14b can be a gate.

[0150] The material of the front metal layer can be AlSi, AlSiCu, and can have a barrier layer, and the barrier layer can be Ti / TiN, that is, a stacked layer of Ti and TiN, or TiN. The total thickness of the front metal layer is generally 4 μm to 6 μm.

[0151] Then, the semiconductor substrate 1 is thinned on the back side and the drain region is formed by the N+ region formed in the semiconductor substrate 1 after thinning. The drain region can be directly formed by the heavily doped semiconductor substrate 1, or by the semiconductor substrate 1 plus N-type heavily doped ion implantation. Then, a back metal layer 15 is deposited on the back side of the semiconductor substrate 1, i.e., the drain region 11, to form a drain electrode.

[0152] The following takes a 650V super junction MOSFET as an example to further explain in detail the parameters used in the method of the embodiment of the present invention:

[0153] The thickness of the first epitaxial layer 2 can be 50 microns, divided into two layers, the top layer has a resistivity of 1.25 ohm.cm, phosphorus doping, and a thickness of 20 microns; the bottom layer has a resistivity of 1.5 ohm.cm, phosphorus doping, and a thickness of 30 microns. The groove width is set to 4.5 microns, and the distance between the grooves is 4.5 microns.

[0154] Figure 2 This is the device structure of the embodiment of the present invention. Compared with the existing device, this structure has a P-type implantation at the top of the terminal region of the device, that is, a second P-type implantation impurity 61 is formed, so that the P-type impurity amount at the top of the P-type column increases, the concentration of the top N region of the terminal region becomes lower, and the impurity at the top of the P-type column increases. This manufacturing process may include the following steps:

[0155] Step 1:

[0156] A dielectric film, namely the hard mask layer 3, is deposited on the first epitaxial layer 2, and the area where the groove is required is defined by trench photolithography, and then the groove is formed by dry etching. The semiconductor substrate 1 is a silicon substrate. The first epitaxial layer 2 is a silicon epitaxial layer.

[0157] After the trench is formed, a P-type epitaxial layer, i.e., the second epitaxial layer, is deposited in the trench. The second epitaxial layer is also a silicon epitaxial layer. Then, the silicon on the surface of the silicon wafer is removed by chemical mechanical polishing, so that a P-type column is formed in the trench. Then, the oxide film on the surface is removed or retained.

[0158] The trench depth is generally 42 microns, and a P-type ion implantation can be performed at the bottom of the trench, such as 120-180 keV, B, 1.0E12-2.0E12 / cm 2 The dielectric film here, i.e., the hard mask layer 3, can be a single oxide film, for example, an oxide film with a thickness of more than 1 micron, which can be used as a hard mask during trench etching. After the trench is formed, there is still an oxide film of a certain thickness left, for example, an oxide film with a thickness of 0.1-0.2 microns. During the CMP process after the epitaxial filling is completed, the oxide film serves as a protective layer for N-type epitaxy during CMP, so that the Si at this location will not be defective in the CMP process, causing leakage or quality problems.

[0159] The dielectric film here can also be composed of an oxide film with a thickness of 0.1-0.15 microns, a SIN film with a thickness of 0.1-0.2 microns and an oxide film with a thickness greater than 1 micron on the top. This can better control the uniformity during the manufacturing process: for example, after the trench etching is completed, at least part of the SiN is retained on the oxide film underneath, and the SIN is removed before epitaxial growth. In this way, the uniformity of the oxide film before epitaxial growth is good, and the uniformity of CMP in the outer eye can also be improved.

[0160] A further improvement to the above multi-layer film structure is that the first oxide film is formed by thermal oxidation, which further improves uniformity.

[0161] The step of forming the P-type well 6 includes:

[0162] like Figure 3C As shown, PWell regions 6 and 6a are formed in the current flow region and transition region of the device by Pwell lithography, and then Pwell 6 and P-type ring 6a are formed by ion implantation.

[0163] The process conditions of Pwell need to meet the requirements of device threshold voltage. For devices with threshold voltage requirements of 2-4 volts, B, 30-100keV, 3-10E13 / cm 2 At the same time, it is necessary to ensure that when the device reaches the breakdown voltage, no punch-through occurs in the channel, otherwise the device will have large leakage and the breakdown voltage will be lowered.

[0164] In products that are irradiated with electrons, the device threshold voltage (Vth) decreases due to the trapping of holes in the gate oxide layer (Gox) of the device caused by electron irradiation. Therefore, to achieve a Vth of 3.5-4.5V, the Pwell dose needs to be increased to 1.4E14-2.3E14 / cm 2 .

[0165] In step 2, if Figure 3D As shown, the terminal region is subjected to photolithography and ion implantation of P-type ion implantation. Here, the impurity of the P-type ion implantation, i.e., the second P-type implantation impurity 61, can be B or BF2. The energy of the ion implantation is 5-100keV, and the dose is designed according to the impurity concentration and process of the N-type epitaxy. A further improvement is that the ion implantation is B, 60keV-120keV, and the dose is 2E11 / cm 2 ~8E11 / cm 2 More preferably, B 60keV5E11 / cm 2 .

[0166] Then, through high temperature annealing, the impurities injected into Pwell, the implanted impurities of the P-type impurities in the terminal region, that is, the second P-type implanted impurities 61 are pushed to the required position.

[0167] In step three, Figure 3E As shown, a certain thick field oxide film, namely a protective epoxy film 7, is formed on the surface of the silicon wafer, and then the oxide film in the current flow area is etched away by photolithography and etching of the protective epoxy film 7, and the remaining oxide film covers the transition area and most or all of the terminal area.

[0168] In an improved embodiment, the protective epoxy film 7 is formed by a thermal oxidation process at a temperature higher than 800°C, so as to reduce dangling bonds and unstable interface states at the Si-SiO2 interface, further improve the voltage-bearing capacity of the terminal region, and improve the consistency of the device's breakdown voltage. The thickness of the oxide film needs to be set according to the size of the device's BVds. Generally, the larger the BVds, the thicker the oxide film needs to be. Generally, the oxide film thickness required for devices above 600V exceeds 8000 angstroms.

[0169] In some embodiments, the method further includes: after the pattern of the protective epoxy film 7 is formed, a JFET region is formed in the current flow region of the silicon wafer by ion implantation.

[0170] Since the transition zone and the terminal zone are protected by the protective epoxy film 7, JFET injection can be performed without photolithography, saving the cost of the photolithography process. If JFET is injected into the terminal area, it will obviously cause the device BVds to decrease. If JFET is injected into the transition zone, the device's ability to resist current shock will be reduced.

[0171] In some embodiments, the JFET implantation conditions are phosphorus (phos), 30-100 keV, 1-4E12 / cm 2 In other embodiments, it can also be a combination of a 30-60keV injection and a 1-1.5MEV injection. The high-energy injection can further reduce the device's specific on-resistance and improve the charge balance around Pwell to increase the device's Bvds. The experimental results show that for a 600V device, it can increase by 10-20V.

[0172] In steps 4 and 5, if Figure 3F As shown, a gate oxide film 8 is formed by thermal oxidation. Then, N-type high-concentration polysilicon 9 is deposited, and a polycrystalline electrode, namely the polysilicon gate 9, is formed by photolithography and etching of the polysilicon gate 9.

[0173] The gate oxide film is a thermal oxide film. Generally, the gate oxide thickness of a 500-700V MOSFET is The thickness of polysilicon is

[0174] After the polysilicon gate 9 is photolithographically etched, a polysilicon gate 9 is formed in the current flow area, and a polysilicon gate bus (gate BUS) surrounding the chip is formed on the periphery of the chip, and the gate BUS is connected to the polysilicon gate 9 in the current flow area. The size of the polysilicon at the connection can be smaller than the size of the polysilicon in the current flow area, so that the size of the contact hole in the transition area can be easily increased without causing gate and source metal leakage. The gate bus can also cover or partially cover the protection ring dielectric film in the transition area, and there can also be isolated polysilicon in the terminal area to serve as a field plate 9a for the terminal smooth electric field.

[0175] In step six, after the polycrystalline electrode is formed, a source region 10 is formed in the current flow area by photolithography and ion implantation. At the same time, a cutoff region 10a can also be formed in the outermost area of ​​the terminal. The cutoff region 10a can be used to prevent the surface inversion of the terminal region, thereby better improving the stability of the breakdown characteristics of the device.

[0176] The source region 10 can be formed by As or Phos implantation, or a combination thereof. The implantation conditions for As and Phos are generally 30-100 keV and 3-5E15 / cm 2 .

[0177] In step seven, an interlayer film 11 is deposited. The interlayer film 11 can be a combination of an undoped oxide film and a BPSG film. Then, the opening of the contact hole is formed by contact hole photolithography and etching. Figure 3H The openings 121a and 121b are shown in FIG. 1 ; after forming the opening of the contact hole, high concentration P is implanted to form the well contact region 13 to ensure good ohmic contact between the metal and Pwell.

[0178] Here, in the etching of the opening of the contact hole, in the device current flow area, the contact hole needs to etch away the silicon of the source region 10 in the contact hole area, so the etching amount can be between 2000 angstroms and 4000 angstroms, which is determined by the injection conditions of the source region 10, i.e. the injection energy and dosage. In the transition area, the opening of the contact hole only needs to pass through the interlayer film 11 and the protective epoxy film 7, and the etching amount of silicon in this area can be greater than or equal to 0, or in other words, only the oxide film in the contact hole area can be completely removed. Generally, the SI etching amount is set at 0-500 angstroms.

[0179] Generally, the thickness of the interlayer film 11 is 8000-10000 angstroms.

[0180] Since the contact hole realizes the connection between the source metal and the Pwell region of the guard ring, ie, the P-type ring 6a in the transition region, it is ensured that the device terminal structure of the same size can withstand the same voltage as the existing process in the process of the embodiment of the present invention.

[0181] Since the contact hole in the current flow area penetrates the N+ region, namely the source region 10, there will be no contact problem between Pwell and metal due to the full injection of the N+ region outside the polysilicon gate 9, thus ensuring normal electrical characteristics.

[0182] The high concentration P-type implantation here, i.e., the implanted impurities of the well contact region 13, can be B, BF2, or a combination thereof, generally with an energy of 30-80keV and a dosage of 1-3E15 / cm2. By optimizing the implantation conditions, the device's resistance to current shocks can be improved. In order to better improve the softness of the reverse recovery process of the body diode, the energy and dosage of the P-type implantation can also be reduced. For example, the energy can be BF2, 5-40keV, 5E14-2E15 / cm2. The dosage can be selected to ensure the minimum dosage for forming an ohmic contact. The selection of energy mainly depends on the capability of the ion implantation equipment.

[0183] After the contact hole etching and ion implantation are completed, a Ti-TiN blocking layer is deposited and annealed. The general process conditions are rapid annealing at 630-720°C, followed by the deposition of metal tungsten (W) to fill the contact holes (for an opening of 0.6 microns, the W thickness can be set to 4000 angstroms), followed by plasma dry etching to completely remove the metal on the surface. When all contact holes are relatively large in size, such as when the aspect ratio is less than or equal to 0.5 and can be completely filled with AlCu or AlSiCu, only Ti-TiN needs to be deposited, without W deposition and corresponding etching.

[0184] In step eight, a front metal is deposited on the front of the silicon wafer, and then the gate electrode, i.e., the gate and the source metal of the device, is formed by front metal lithography and etching. The metal on the front of the silicon wafer can be AlSi, AlSiCu, and can have a barrier layer, which can be Ti / TIN, or TIN. The total thickness of the metal is generally 4-6 microns.

[0185] In some improved embodiments, the method may further include: depositing a dielectric film, i.e., a passivation layer, on the front side of the silicon wafer, and then opening the gate region and the source region by photolithography and etching, while protecting the terminal region, the transition region, etc. with a dielectric film.

[0186] In some improved embodiments, the method may further include: coating polyimide on the front side of the silicon wafer, opening the gate region and the source region through photolithography and development, and protecting the terminal region and the transition region with a polyimide film. The thickness of the polyimide film after baking is generally 4 microns to 10 microns.

[0187] Thereafter, the back side of the silicon wafer is thinned, and a back side metal layer 15 is deposited on the back side to form a drain.

[0188] Such a super junction MOSFET device is formed.

[0189] The steps of the above production process are as follows Figure 4 As shown, Figure 4 The lithography process hierarchy is used to represent the corresponding process steps, which are:

[0190] Step S101, Trench photo & etch, refers to the photolithography and etching of the trench of the P-type column in step one, where trech means trench, photo means photolithography, and etch means etching.

[0191] Step S102, Pwell photo&IMP, represents the photolithography and implantation of the P-type well 6, and IMP represents implantation.

[0192] Step S103, Terminal B IMP photo&IMP, indicates the photolithography and implantation of the second P-type implant impurity 61 in step 2, terminal indicates the terminal region, and B indicates boron.

[0193] Step S104 , Gfield photo&etch, represents the photolithography and etching of the protective epoxy film 7 in step three, where Gfield is the field oxide layer, namely the protective epoxy layer 7 .

[0194] Step S105, JFET blank IMP, indicates full implantation of the JFET region. Blank indicates full implantation without the need for a mask. Step S105 will not increase the number of photolithography times.

[0195] Step S106 , poly photo&etch, represents the photolithography and etching of the polysilicon gate 9 in step five, and poly represents the polysilicon gate 9 .

[0196] Step S107 , Nplus blank IMP, indicates that the N+ of the source region 10 in step 6 is fully implanted, and Nplus indicates that the source region 10 is N-type doped.

[0197] Step S108, Cont photo&etch, represents the photolithography and etching of the contact hole in step 7. Cont represents the contact hole.

[0198] Step S109, Metal photo&etch, represents the photolithography and etching of the front metal layer in step 8. Metal represents the front metal layer.

[0199] Step S110, Passivation photo&etch, represents photolithography and etching of the passivation layer, and passivation represents the passivation layer.

[0200] Step S111, Polyimide photo&etch, represents photolithography and etching of polyimide film, and polyimide represents polyimide film.

[0201] Depend on Figure 4 As shown, a total of 10 photolithography steps were used, wherein step S105 does not require photolithography, and the super junction MOSFET device is successfully manufactured. The BVds of the device has the following advantages over the existing device that does not use terminal P-type injection:

[0202] During the device manufacturing process, the electron irradiation step S112 can be introduced before or after the polyimide process, and the appropriate dose and annealing conditions (generally 60-300KGY dose, 300-380°C annealing conditions, 30-300min) can be set to achieve minority carrier lifetime control of the device, improve the body diode reverse recovery characteristics of the device, and expand the application range of the device.

[0203] In one embodiment, electron irradiation, i.e., step S112, is performed before the polyimide process, i.e., step S111. The relationship between the BVdss and the P-type impurities of the obtained device is as follows: Figure 5 The specific data are shown in Table 1 below:

[0204] Table 1

[0205] P-type impurity concentration BVdss(V) of existing devices BVdss (V) of the device according to the embodiment of the present invention P0-0.3E 710 720 P0-0.2E 730 750 P0 760 770 P0+0.2E 740 760 P0+0.3E 700 750 P0+0.4E 680 740 P0+0.5E 650 735 P0+0.6E 700

[0206] Figure 5 In the figure, each point 201a on the curve 201 corresponds to the BVdss of the device of the embodiment of the present invention in Table 1, and each point 202a on the curve 202 corresponds to the BVdss of the conventional device in Table 1. The BVdss in Table 1 is the central value of 135 points tested on each wafer. From the above experimental data, we can see that:

[0207] 1. The maximum value of BVdss Med of the device of the embodiment of the present invention can be improved by 10V compared with the existing device. In Table 1, P0 represents the doping concentration of the P-type column when the N-type column and the P-type column are completely PN balanced. The P-type column has the highest value of BVdss Med when the doping concentration is P0.

[0208] 2. The change curve of BVdss and P-type impurity concentration of the device in the embodiment of the present invention is obviously slower than that of the existing device, which significantly improves the process window of P-type impurity concentration. Expanding this process window is the most critical technology of super junction devices.

[0209] 3. P0 is the top point. In the direction of concentration, it is obvious that the window of the device of the embodiment of the present invention is greatly expanded. In order to obtain good EAS performance, the P-type impurities of the super junction device are generally selected in the direction of concentration. According to the experimental results of this experiment, the product is a 650V super junction device. Generally, BVdss Med needs to be guaranteed at 700-710V. Considering the process window, the existing device needs to select P0+0.15E as the production condition, and the process window is only from P0 to P0+0.3E. That is, when P0+0.15E is selected as the production condition, the process fluctuation needs to be controlled from P0 to P0+0.3E. The doping concentration of the P-type column of the embodiment of the present invention can be produced at P0+0.3E, and the process window is from P0 to P0+0.6E, and the process window is significantly expanded. Moreover, the working point concentration of the embodiment of the present invention is 0.15E higher than that of the existing device, and the EAS capability of the device can be significantly improved.

[0210] 4. The P epitaxial layer (epi) concentration window of the device of the embodiment of the present invention is expanded due to the optimization of the P-type injection conditions set in the terminal area. This optimized condition enables the concentration at the top of the N region and the concentration at the top of the P-type column to obtain better BVdss and BVdss stability under the terminal design, which is significantly better than the existing devices. One explanation is that the BVdss of the optimized terminal is higher than the BVdss of the active area, i.e., the current flow area. Therefore, the BVdss of the tested device is determined by the BVdss of the active area. In the prior art, due to the existing design of the terminal area, the BVdss of the terminal area is lower than the BVdss of the active area, resulting in the BVdss of the device being determined by the BVdss of the terminal area. In the prior art, the BVdss of the terminal area is very sensitive to the concentration of the P-type column, resulting in a small process window.

[0211] 5. Since ion implantation is only performed in the device terminal area, it has no effect on the device active area, so the device on-resistance is not affected.

[0212] 6. The consistency of device BVds is significantly improved: Due to the improvement of the ability of the device terminal to withstand breakdown, the device can be easily designed so that the breakdown voltage of the terminal is higher than the breakdown voltage of the charge flow area, thereby greatly improving the consistency of the device Bvds and the device's ability to resist current shock. The reason is: when the terminal breakdown voltage is lower than the breakdown voltage of the charge flow area, the breakdown of the device often occurs in the area close to the Si / SiO2 interface, so that carriers are easily gathered at the interface, making the breakdown voltage of the device unstable and the EAS capability poor; when the breakdown of the terminal is higher than the charge flow area, since the super junction MOSFET can be designed to ensure that the breakdown of the device in the charge flow area occurs in the SI body, the stability of the device BVdss can be greatly improved, and it is easy to obtain good EAS capability.

[0213] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A terminal structure of a super junction device, characterized in that: The middle area of ​​the super junction device is a current flow area, the terminal area surrounds the periphery of the current flow area, and the transition area is located between the current flow area and the terminal area; A super junction structure is formed in the current flow region, the transition region and the terminal region; the super junction structure is formed in a semiconductor substrate and comprises N-type columns and P-type columns arranged alternately, each of the P-type columns has a first initial P-type impurity, each of the N-type columns has a first initial N-type impurity, and a super junction unit comprises one of the N-type columns and an adjacent P-type column; A terminal structure is formed in the transition region and the terminal region, the terminal structure comprising: the super junction structure, a protective epoxy film and a second P-type implanted impurity; The protective epoxy film covers the surface of the super junction structure in the transition region and the terminal region; Each of the P-type pillars has a first surface region, and part of the P-type impurities in the first surface region are thermally segregated into the protective epoxy film so as to reduce the amount of the P-type impurities in the first surface region of each of the P-type pillars; The second P-type injection impurity is located in the second surface area of ​​the super junction structure in the terminal area, and there is no second P-type injection impurity in the current flow area; in the P-type column in the terminal area, the second surface area and the first surface area have an overlapping area.

2. The terminal structure of the super junction device according to claim 1, characterized in that: The constituent film of the protective epoxy film includes a thermal oxide film.

3. The terminal structure of the super junction device according to claim 1, characterized in that: The first initial P-type impurity includes boron or boron fluoride.

4. The terminal structure of the super junction device according to claim 1, characterized in that: In the current flow region, a P-type well is formed on the surface of each P-type column, and the P-type well also extends to the surface of the adjacent N-type column; A P-type ring is formed in the transition region, and the P-type ring covers the surface of each super junction unit in the transition region; The doping concentration of the P-type well is 1 to 2 orders of magnitude higher than the doping concentration of the P-type column, and the doping concentration of the P-type ring is 1 to 2 orders of magnitude higher than the doping concentration of the P-type column.

5. The terminal structure of the super junction device according to claim 1, characterized in that: The second P-type implanted impurity includes boron or boron fluoride, and the implantation conditions of the second P-type implanted impurity include 2E11cm -2 ~8E11cm -2 .

6. The terminal structure of the super junction device according to claim 1, characterized in that: By adjusting the second P-type injected impurity, the voltage resistance of the super junction structure in the terminal area is adjusted to be greater than the voltage resistance of the super junction structure in the current flow area, so that the voltage resistance of the super junction device is determined by the voltage resistance of the super junction structure in the current flow area.

7. The terminal structure of the super junction device according to claim 1, characterized in that: The process window of the P-type column is a variation window of the doping concentration of the first initial P-type impurity in the P-type column. The minimum doping concentration of the P-type column takes the optimal balanced doping concentration. The maximum doping concentration of the P-type column ensures that the voltage resistance of the super junction device meets the minimum voltage resistance requirement value. The voltage resistance of the super junction structure in the terminal area is improved, which improves the voltage resistance of the super junction device. The maximum doping concentration of the P-type column is also increased, and the process window of the P-type column is expanded.

8. The terminal structure of the super junction device according to claim 7, characterized in that: A first epitaxial layer is formed on the surface of the semiconductor substrate, and the super junction structure is formed in the first epitaxial layer; The first epitaxial layer is a single epitaxial layer having a single resistivity; Alternatively, the first epitaxial layer is formed by stacking a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, and the resistivity of the second epitaxial sublayer is lower than the resistivity of the first epitaxial sublayer.

9. The terminal structure of the super junction device according to claim 8, characterized in that: The first epitaxial layer is N-type doped, the components of the P-type pillars include a P-type doped second epitaxial layer filled in the trenches, and the N-type pillars are composed of the first epitaxial layer between the P-type pillars; The fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type column.

10. A method for manufacturing a terminal structure of a super junction device, characterized in that: The steps include: Step 1, dividing the formation area of ​​the super junction device into a current flow area, a transition area and a terminal area, wherein the middle area of ​​the super junction device is the current flow area, the terminal area surrounds the outer periphery of the current flow area, and the transition area is located between the current flow area and the terminal area; A super junction structure is formed in the current flow region, the transition region and the terminal region; the super junction structure is formed in a semiconductor substrate and comprises alternately arranged N-type columns and P-type columns, each of the P-type columns has a first initial P-type impurity, each of the N-type columns has a first initial N-type impurity, and a super junction unit comprises an N-type column and an adjacent P-type column. Step 2: Performing selective P-type ion implantation to form a second P-type implanted impurity in a second surface region of the super junction structure in the terminal region; The second P-type implanted impurity is absent in the current flow region; Step 3, forming a protective epoxy film and performing pattern etching on the protective epoxy film, wherein the pattern etching makes the protective epoxy film only on the surface of the super junction structure in the transition region and the terminal region; During the process of forming the protective epoxy film, part of the P-type impurities in the first surface region of each of the P-type pillars will be thermally segregated into the protective epoxy film, thereby reducing the amount of the P-type impurities; In the P-type column in the terminal area, the second surface area and the first surface area have an overlapping area, and the second P-type injected impurities are used to compensate for the reduced amount of P-type impurities in the first surface area, thereby improving the PN balance of the super junction structure in the terminal area. The second P-type injected impurities simultaneously reduce the N-type net doping amount in the second surface area of ​​the N-type column in the terminal area, so as to improve the voltage resistance of the super junction structure in the terminal area and improve the process window of the P-type column.

11. The method for manufacturing a terminal structure of a super junction device according to claim 10, characterized in that: In step three, the constituent film of the protective epoxy film includes a thermal oxidation film formed by a thermal oxidation process.

12. The method for manufacturing a terminal structure of a super junction device according to claim 10, characterized in that: The first initial P-type impurity includes boron or boron fluoride.

13. The method for manufacturing a terminal structure of a super junction device according to claim 10, characterized in that: Before step 3, it also includes: forming a P-type well in the current flow region, the P-type well being located on the surface of each of the P-type pillars and also extending to the surface of the adjacent N-type pillars; forming a P-type ring in the transition region, wherein the P-type ring covers the surface of each of the super junction units in the transition region; The doping concentration of the P-type well is 1 to 2 orders of magnitude higher than the doping concentration of the P-type column, and the doping concentration of the P-type ring is 1 to 2 orders of magnitude higher than the doping concentration of the P-type column.

14. The method for manufacturing a terminal structure of a super junction device according to claim 10, characterized in that: The second P-type implanted impurity includes boron or boron fluoride, and the implantation conditions of the second P-type implanted impurity include 2E11cm -2 ~8E11cm -2 .

15. The method for manufacturing a terminal structure of a super junction device according to claim 10, characterized in that: By adjusting the second P-type injected impurity, the voltage resistance of the super junction structure in the terminal area is adjusted to be greater than the voltage resistance of the super junction structure in the current flow area, so that the voltage resistance of the super junction device is determined by the voltage resistance of the super junction structure in the current flow area.

16. The method for manufacturing a terminal structure of a super junction device according to claim 10, characterized in that: The process window of the P-type column is a variation window of the doping concentration of the first initial P-type impurity in the P-type column. The minimum doping concentration of the P-type column takes the optimal balanced doping concentration. The maximum doping concentration of the P-type column ensures that the voltage resistance of the super junction device meets the minimum voltage resistance requirement value. The voltage resistance of the super junction structure in the terminal area is improved, which improves the voltage resistance of the super junction device. The maximum doping concentration of the P-type column is also increased, and the process window of the P-type column is expanded.

17. The method for manufacturing a terminal structure of a super junction device according to claim 16, characterized in that: A first epitaxial layer is formed on the surface of the semiconductor substrate, and the super junction structure is formed in the first epitaxial layer; The first epitaxial layer is a single epitaxial layer having a single resistivity; Alternatively, the first epitaxial layer is formed by stacking a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, and the resistivity of the second epitaxial sublayer is lower than the resistivity of the first epitaxial sublayer.

18. The method for manufacturing a terminal structure of a super junction device according to claim 17, characterized in that: The first epitaxial layer is N-type doped, and step 1 includes the following sub-steps: forming a plurality of trenches in the first epitaxial layer; Filling the trench with a P-type doped second epitaxial layer, the P-type doped second epitaxial layer filled in the trench is used as a component of the P-type column, and the N-type column is composed of the first epitaxial layer between the P-type columns; The fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type column.

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