Semiconductor structure and forming method thereof
By introducing isolation side walls into the semiconductor structure, the leakage current problem between the source-drain doped layer and the substrate is solved, and the performance of the semiconductor structure is improved.
Patent Information
- Application Number
- CN202310787757.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-29
- Publication Date
- 2024-12-31
AI Technical Summary
There is a leakage current problem in semiconductor structures, especially between the source-drain doped layer and the substrate, which affects the performance of the device.
The isolation side wall is introduced into the semiconductor structure, which is located between the side wall of the source-drain doped layer and the substrate side wall at the bottom of the channel structure layer. The source-drain doped layer and the substrate side wall are isolated through the isolation side wall to prevent leakage flow channel and prevent doped ions from diffusion.
It effectively reduces the leakage current between the source-drain doped layer and the substrate, and improves the performance and stability of the semiconductor structure.
Smart Images
Figure CN119230589A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistor size is getting smaller and smaller, and Fin-type field-effect transistor (FinFET) came into being. However, to maintain the original driving current performance, this structure is no longer suitable for smaller nodes. So the all-around gate transistor (Gate-All-Around, GAAFET) appeared. Its control of short channel effects and superior electrical performance make it replace FinFET and become the mainstream at smaller process nodes.
[0003] GAAFET is a four-sided ring gate structure that can better suppress the short channel effect and achieve better electrical performance.
[0004] However, current semiconductor structures still have the problem of leakage current. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, improve the leakage current problem between the source-drain doping layer and the substrate, and enhance the performance of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a channel structure layer suspended on the substrate, the channel structure layer comprising one or more channel layers spaced in sequence from bottom to top; a gate structure spanning the channel structure layer, the gate structure filling between the channel layer and the substrate and between adjacent channel layers; the gate structure surrounding the channel layer; a source-drain doping layer located in the channel structure layer on both sides of the gate structure and in a partial thickness of the substrate; and an isolation sidewall located between the sidewall of the source-drain doping layer and the sidewall of the substrate at the bottom of the channel structure layer.
[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a base, comprising a substrate and one or more channel stacks stacked in sequence on the substrate, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a pseudo-gate structure spanning the channel stack; forming source-drain grooves in the channel stack and a partial thickness substrate on both sides of the pseudo-gate structure; forming isolation sidewalls on the sidewalls of the substrate exposed by the source-drain grooves; forming source-drain doping layers in the source-drain grooves, the source-drain doping layers being in contact with the sidewalls of the isolation sidewalls.
[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0009] The semiconductor structure provided by the embodiment of the present invention is also provided with an isolation sidewall, which is located between the sidewall of the source and drain doping layer and the sidewall of the substrate at the bottom of the channel structure layer. Compared with the solution in which the source and drain doping layer and the exposed substrate sidewall of the source and drain groove are in contact, the source and drain doping layer and the substrate sidewall are isolated by the isolation sidewall in the embodiment of the present invention. The isolation sidewall can block the leakage current channel between the source and drain doping layer and the substrate at the bottom of the channel stack. Moreover, the isolation sidewall can also block the diffusion of doped ions in the source and drain doping layer into the substrate at the bottom of the channel stack, which is beneficial to improve the leakage current problem between the source and drain doping layer and the substrate, and improves the performance of the semiconductor structure.
[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming the source-drain groove and before forming the source-drain doping layer in the source-drain groove, an isolation sidewall is further formed on the substrate sidewall exposed by the source-drain groove. Accordingly, in the step of forming the source-drain doping layer, the source-drain doping layer contacts the sidewall of the isolation sidewall. Compared with the scheme in which the source-drain doping layer contacts the substrate sidewall exposed by the source-drain groove, in the embodiment of the present invention, the source-drain doping layer is isolated from the substrate sidewall by the isolation sidewall. The isolation sidewall can block the leakage current channel between the source-drain doping layer and the substrate at the bottom of the channel stack. Moreover, the isolation sidewall can also block the diffusion of doped ions in the source-drain doping layer into the substrate at the bottom of the channel stack, which is beneficial to improve the leakage current problem between the source-drain doping layer and the substrate, and improves the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0012] Figure 4 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;
[0013] Figures 5 to 13It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0014] As can be seen from the background technology, the performance of the current semiconductor structure needs to be improved. Now, in combination with a method for forming a semiconductor structure, the reason why the performance of the semiconductor structure needs to be improved is analyzed. Figures 1 to 3 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.
[0015] refer to Figure 1 , providing a base (not shown), including a substrate 10 and one or more channel stacks 11 stacked in sequence on the substrate 10 , each channel stack 11 including a sacrificial layer 12 and a channel layer 13 located on the sacrificial layer 12 .
[0016] refer to Figure 2 , forming a dummy gate structure 15 across the channel stack 11 ; forming source and drain grooves 14 in the channel stack 11 and a partial thickness of the substrate 10 on both sides of the dummy gate structure 15 .
[0017] refer to Figure 3 , a source-drain doping layer 18 is formed in the source-drain groove 14 .
[0018] Among them, the source-drain doped layer 18 is in direct contact with the substrate 10 on the sidewall 19, resulting in a serious leakage current problem between the source-drain doped layer 18 and the substrate 10. In addition, an etching process is usually used to etch the channel stack 11 and a portion of the thickness of the substrate 10 on both sides of the dummy gate structure to form the source-drain groove 14. Defects are easily generated on the substrate surface exposed by the source-drain groove 14, and then in the step of forming the source-drain doped layer 18 in the source-drain groove 14, stacking faults are easily generated in the source-drain doped layer 18, resulting in more serious leakage current.
[0019] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a channel structure layer suspended on the substrate, the channel structure layer including one or more channel layers spaced apart from bottom to top; a gate structure spanning the channel structure layer, the gate structure filling between the channel layer and the substrate and between adjacent channel layers; the gate structure surrounding the channel layer; a source-drain doped layer located in the channel structure layer on both sides of the gate structure and in a partial thickness of the substrate; an isolation sidewall located between the sidewall of the source-drain doped layer and the sidewall of the substrate at the bottom of the channel structure layer.
[0020] The semiconductor structure provided by the embodiment of the present invention is provided with an isolation sidewall, which is located between the sidewall of the source-drain doped layer and the sidewall of the substrate at the bottom of the channel structure layer. In the embodiment of the present invention, the source-drain doped layer and the substrate sidewall are isolated by the isolation sidewall. The isolation sidewall can block the leakage current channel between the source-drain doped layer and the substrate at the bottom of the channel stack. Moreover, the isolation sidewall can also block the diffusion of doped ions in the source-drain doped layer into the substrate at the bottom of the channel stack, which is beneficial to improve the leakage current problem between the source-drain doped layer and the substrate, and improve the performance of the semiconductor structure.
[0021] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 4 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.
[0022] like Figure 4 As shown, in this embodiment, the semiconductor structure includes: a substrate 100; a channel structure layer 600, suspended on the substrate 100, the channel structure layer 600 includes one or more channel layers 106 arranged in sequence from bottom to top; a gate structure 500, spanning the channel structure layer 600, the gate structure 500 is filled between the channel layer 106 and the substrate 100 and between adjacent channel layers 106; the gate structure 500 surrounds the channel layer 106; the source-drain doping layer 400, located in the channel structure layer 600 on both sides of the gate structure 500 and a partial thickness of the substrate 100; and the isolation sidewall 200, located between the sidewall of the source-drain doping layer 400 and the sidewall of the substrate 100 at the bottom of the channel structure layer 600.
[0023] The substrate 100 is used to provide a process platform for forming a semiconductor structure.
[0024] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be one or more of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium arsenide, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0025] In this embodiment, the channel structure layer 600 includes a plurality of channel layers 106 as an example for description, and the plurality of channel layers 106 are stacked and arranged on the substrate 100 in a direction perpendicular to the surface of the substrate 100. In other embodiments, based on actual process requirements, the number of the channel layer may also be one.
[0026] Specifically, the channel layer 106 is used to form a conductive channel of a MOS transistor.
[0027] In this embodiment, an NMOS transistor is formed, and the material of the channel layer 106 is the same as that of the substrate 100 , both of which are silicon.
[0028] In other embodiments, when forming a PMOS transistor, in order to improve the performance of the PMOS transistor, a silicon germanium channel technology may be used, that is, the material of the channel layer is silicon germanium.
[0029] In other embodiments, based on actual process requirements, other materials may be selected for the channel layer.
[0030] It should be noted that, in this embodiment, a well region is also formed in the substrate 100 and the channel layer 106. When an NMOS transistor is formed, the well region is doped with P-type ions; when a PMOS transistor is formed, the well region is doped with N-type ions.
[0031] In this embodiment, the gate structure 500 spans the channel structure layer 600 , the gate structure 500 is filled between the channel layer 106 and the substrate 100 and between adjacent channel layers 106 , and the gate structure 500 surrounds the channel layer 106 .
[0032] When the device is operating, the gate structure 500 is used to control the opening and closing of the conductive channel.
[0033] In this embodiment, the gate structure 500 is a metal gate structure, and the gate structure 500 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filled between the substrate 100 and the channel layer 106 and between adjacent channel layers 106.
[0034] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.
[0035] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.
[0036] The work function layer is used to adjust the work function of the gate structure 500, and then adjust the threshold voltage of the field effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.
[0037] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 500 to an external circuit. The material of the gate electrode layer is a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.
[0038] In this embodiment, the gate structure 500 is located between the substrate 100 and the channel layer 106, or between adjacent channel layers 106, as the first portion (not labeled); the gate structure 500 crosses the channel structure layer 600 as the second portion (not labeled).
[0039] In this embodiment, the semiconductor structure further includes: a gate spacer 113 located on the sidewall of the second portion and used to protect the sidewall of the gate structure 500 .
[0040] In this embodiment, the material of the gate spacer 113 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric or ultra-low-k dielectric material, and the gate spacer 113 is a single-layer or stacked structure. As an example, the gate spacer 113 is a single-layer structure, and the material of the gate spacer 113 is silicon nitride.
[0041] In this embodiment, the semiconductor structure further includes: an inner sidewall 300 , which is located between the second portion and the source-drain doped layer 400 along the extension direction of the channel layer 106 .
[0042] In this embodiment, the inner sidewall 300 is used to achieve isolation between the source-drain doped layer 400 and the gate structure 500 , and also increases the distance between the source-drain doped layer 400 and the gate structure 500 , which is beneficial to reduce the parasitic capacitance between the source-drain doped layer 400 and the gate structure 500 .
[0043] In this embodiment, the material of the inner sidewall 300 is an insulating material to achieve isolation between the source-drain doped layer 400 and the gate structure 500, thereby reducing the parasitic capacitance between the source-drain doped layer 400 and the gate structure 500. In this embodiment, the material of the inner sidewall 300 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.
[0044] The source-drain doped layer 400 is used as a source or a drain of the MOS transistor. When the MOS transistor is working, the source-drain doped layer 400 is used to provide a carrier source.
[0045] In this embodiment, the material of the source / drain doping layer 400 includes a stress layer doped with ions.
[0046] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 400 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doped ions in the source and drain doping layer 400 are N-type ions.
[0047] The isolation sidewall 200 is used to isolate the source-drain doped layer 400 from the sidewall of the substrate 100. The isolation sidewall 200 can block the leakage current channel between the source-drain doped layer 400 and the substrate 100 at the bottom of the channel structure layer 600. In addition, the isolation sidewall 200 can also block the diffusion of doped ions in the source-drain doped layer 400 into the substrate 100 at the bottom of the channel structure layer 600, thereby improving the leakage current problem between the source-drain doped layer 400 and the substrate 100 and improving the performance of the semiconductor structure.
[0048] In this embodiment, the side wall of the substrate 100 contacting the isolation spacer 200 is indented relative to the side wall of the channel structure layer 600 on the same side, which facilitates the formation of the isolation spacer 200 and reduces the process difficulty of forming the isolation spacer 200 .
[0049] In this embodiment, the isolation spacer 200 is a triangle, that is, there is an angle between the sidewall of the substrate 100 in contact with the isolation spacer 200 and the normal of the substrate 100. In other embodiments, based on actual processes, the shape of the isolation spacer may also be other shapes, including: rectangle, etc.
[0050] In other embodiments, based on actual process requirements, the substrate sidewall in contact with the isolation spacer may also be flush with the sidewall on the same side of the channel stack.
[0051] In this embodiment, the isolation spacer 200 is made of an insulating dielectric material, thereby ensuring that the isolation spacer 200 can isolate the source / drain doped layer 400 from the sidewall of the substrate 100 .
[0052] Specifically, in this embodiment, the material of the isolation spacer 200 includes one of silicon oxide, silicon nitride or silicon carbonitride, low-k dielectric material or ultra-low-k dielectric material. As an example, the material of the isolation spacer 200 is silicon nitride.
[0053] It should be noted that the width d of the isolation sidewall 200 should not be too small or too large along the direction parallel to the substrate 100. If the width d of the isolation sidewall 200 is too small, it is easy to reduce the isolation effect of the isolation sidewall 200 on the source-drain doped layer 400 and the substrate 100; if the width d of the isolation sidewall 200 is too large, the distance between the source-drain doped layer 400 on both sides of the channel structure layer 600 is too small, which is easy to aggravate the short channel effect and also easy to cause the isolation sidewall 200 to improve the leakage current not significantly. For this reason, in this embodiment, along the direction parallel to the substrate 100, the width d of the isolation sidewall 200 is 2 nanometers to 4 nanometers.
[0054] It should also be noted that the thickness h of the substrate 100 in contact with the isolation sidewall 200 should not be too small or too large. If the thickness h of the substrate 100 in contact with the isolation sidewall 200 is too small, it is easy to cause insufficient epitaxial growth of the source-drain doped layer 400; if the thickness h of the substrate 100 in contact with the isolation sidewall 200 is too large, it is easy to cause the height of the source-drain doped layer 400 in the substrate 100 to be too large, which is easy to increase the probability of leakage current between the source-drain doped layer 400 and the substrate 100. For this reason, in this embodiment, the thickness h of the substrate 100 in contact with the isolation sidewall 200 is 10 nanometers to 40 nanometers.
[0055] In this embodiment, the semiconductor structure is used to form a MOS transistor; the semiconductor structure also includes: an inversion doped region (not shown) located in the substrate 100 at the bottom of the source and drain doped layer 400, and the doping ion type is different from the channel conductivity type of the MOS transistor.
[0056] Specifically, the doping type of the inversion doping region is different from the channel conductivity type of the MOS transistor, that is, the doping type of the inversion doping region is different from that of the source-drain doping layer 400, which is beneficial to improving the potential barrier of the substrate 100 at the bottom of the source-drain doping layer 400, thereby inhibiting the diffusion of doped ions in the source-drain doping layer 400 into the substrate 100, thereby improving the leakage current between the source-drain doping layer 400 and the substrate 100.
[0057] In this embodiment, when an NMOS transistor is formed, the doping ions in the inversion doping process are P-type ions; when a PMOS transistor is formed, the doping ions in the inversion doping process are N-type ions.
[0058] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 410 , which is located on the substrate 100 at the side of the gate structure 500 and covers the source-drain doped layer 400 .
[0059] The interlayer dielectric layer 410 is used to cover the source-drain doped layer 400 and protect the source-drain doped layer 400 . The interlayer dielectric layer 410 is also used to achieve electrical isolation between adjacent gate structures 500 .
[0060] In this embodiment, the material of the interlayer dielectric layer 410 includes one or more of silicon oxide and silicon nitride. As an example, the material of the interlayer dielectric layer 410 is silicon nitride.
[0061] The semiconductor structure may be formed by the method for forming a semiconductor structure provided by an embodiment of the present invention, or may be formed by other methods.
[0062] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 5 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0063] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.
[0064] refer to Figure 5 , providing a base (not shown), including a substrate 100 and one or more sequentially stacked channel stacks 108 located on the substrate 100 , each channel stack 108 including a sacrificial layer 105 and a channel layer 106 located on the sacrificial layer 105 .
[0065] The substrate is used to provide a process platform for subsequent process steps.
[0066] In this embodiment, the formation of a gate-all-around (GAA) transistor is used as an example for description. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field effect transistor (CFET).
[0067] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be one or more of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium arsenide, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0068] In this embodiment, the channel stack 108 provides a process basis for subsequently forming the channel layer 106 with suspended spacing. In this embodiment, the number of the channel stacks 108 is multiple as an example for description, and the stacking direction of the multiple channel stacks 108 on the substrate 100 is perpendicular to the surface of the substrate 100. In other embodiments, based on actual process requirements, the number of the channel stack can also be one.
[0069] Specifically, the channel layer 106 is used to form a conductive channel of the MOS transistor, and the sacrificial layer 105 is used to support the channel layer 106, thereby providing a process basis for the subsequent realization of the spaced-apart suspended arrangement of the channel layer 106, and also for occupying a spatial position for the subsequent formation of a gate structure.
[0070] In this embodiment, an NMOS transistor is formed, and the material of the channel layer 106 is the same as that of the substrate 100, both of which are silicon. The material of the sacrificial layer 105 is silicon germanium. In the subsequent process of removing the sacrificial layer 105, the etching selectivity of silicon germanium and silicon is relatively high, so by setting the material of the sacrificial layer 105 to silicon germanium and the material of the channel layer 106 to silicon, the effect of the removal process of the sacrificial layer 105 on the channel layer 106 can be effectively reduced, thereby improving the quality of the channel layer 106, and further facilitating the improvement of device performance.
[0071] In other embodiments, when forming a PMOS transistor, in order to improve the performance of the PMOS transistor, a silicon germanium channel technology may be used, that is, the material of the channel layer 106 is silicon germanium, and the material of the sacrificial layer 105 is silicon.
[0072] In other embodiments, based on actual process requirements, other materials may be selected for the channel layer and the sacrificial layer.
[0073] It should be noted that, in this embodiment, a well region is also formed in the substrate 100 and the channel layer 106. When an NMOS transistor is formed, the well region is doped with P-type ions; when a PMOS transistor is formed, the well region is doped with N-type ions.
[0074] refer to Figure 6 , forming a dummy gate structure 111 across the channel stack 108 .
[0075] The dummy gate structure 111 is used to pre-occupy a space position for the subsequent formation of a gate structure.
[0076] In this embodiment, the dummy gate structure 111 includes a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) located on the dummy gate oxide layer.
[0077] In this embodiment, the material of the dummy gate oxide layer includes one or more of silicon oxide and silicon oxynitride.
[0078] In this embodiment, the material of the dummy gate layer (not shown) includes polysilicon.
[0079] In this embodiment, a dummy gate mask layer 112 is further formed on the top of the dummy gate layer (not shown). The dummy gate mask layer 112 is used as an etching mask for patterning the dummy gate material layer to form the dummy gate structure 111.
[0080] As an example, the material of the dummy gate mask layer 112 is silicon nitride.
[0081] In this embodiment, a gate sidewall 113 is further formed on the sidewalls of the dummy gate layer (not shown) and the dummy gate mask layer 112. The gate sidewall 113 is used together with the dummy gate layer (not shown) and the dummy gate mask layer 112 as an etching mask for subsequent formation of source and drain grooves to define the formation position of the source and drain doping layer. The gate sidewall 113 is also used to protect the dummy gate layer (not shown) and the dummy gate mask layer 112 and the sidewalls of the subsequent gate structure.
[0082] In this embodiment, the material of the gate spacer 113 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric or ultra-low-k dielectric material, and the gate spacer 113 is a single-layer or stacked structure. As an example, the gate spacer 113 is a single-layer structure, and the material of the gate spacer 113 is silicon nitride.
[0083] refer to Figure 6 , source and drain grooves 120 are formed in the channel stack 108 on both sides of the dummy gate structure 111 and in a partial thickness of the substrate 100 .
[0084] The source-drain grooves 120 provide space for the subsequent formation of source-drain doping layers, and also provide space for the subsequent formation of isolation sidewalls.
[0085] In the present embodiment, in the step of forming the source-drain groove 120, the side wall of the substrate 100 exposed by the source-drain groove 120 is indented relative to the side wall on the same side of the channel stack 108, that is, the side wall of the substrate 100 exposed by the source-drain groove 120 and the bottom of the channel stack 108 form a groove 121, and the groove 121 is used to provide a spatial position for the subsequent formation of an isolation sidewall. Moreover, by making the side wall of the substrate 100 exposed by the source-drain groove 120 indented relative to the side wall on the same side of the channel stack 108, it is convenient to form a deposition layer on the bottom and side walls of the source-drain groove 120 and on the side walls and top surface of the dummy gate structure 111 in the subsequent step of forming the isolation sidewall. In the process of removing the deposition layer located at the bottom of the source-drain groove 120, the side walls of the channel stack 108, and the side walls and top of the dummy gate structure 111, the deposition layer located in the groove 121 can be retained, thereby facilitating the formation of an isolation sidewall in the groove 121, thereby reducing the process difficulty of forming the isolation sidewall.
[0086] In this embodiment, the groove 121 is a triangular groove, that is, there is an angle between the sidewall of the substrate 100 exposed by the source and drain groove 120 and the normal line of the substrate 100. In other embodiments, based on the actual process of forming the source and drain grooves, the shape of the groove may also be other shapes, including: rectangle, etc.
[0087] In other embodiments, based on actual process requirements, the substrate sidewall exposed by the source / drain grooves may also be flush with the sidewall on the same side of the channel stack.
[0088] It should be noted that, along the direction parallel to the substrate, the sidewall of the substrate 100 exposed by the source-drain groove 120 should not be too small or too large indented relative to the sidewall of the same side of the channel stack 108. If the indented distance d is too small, the depth of the groove 121 is too small, and the space provided for the subsequent formation of the isolation sidewall is too small, which is easy to increase the difficulty of forming the isolation sidewall in the groove 121, and it is easy to cause the width of the isolation sidewall formed subsequently to be too small, and then it is easy to reduce the isolation effect of the isolation sidewall on the source-drain doped layer and the substrate 100; if the indented distance d is too large, after the source-drain doped layer is formed in the source-drain groove 120, the distance between the source-drain doped layers on both sides of the dummy gate structure 111 is too small, which is easy to aggravate the short channel effect, and it is also easy to cause the subsequent formation of the isolation sidewall in the groove 121, and the improvement of the leakage current is not obvious. To this end, in this embodiment, along a direction parallel to the substrate 100 , the sidewall of the substrate 100 exposed by the source / drain groove 120 is retracted by a distance d of 2 nm to 4 nm relative to the sidewall of the channel stack 108 on the same side.
[0089] It should also be noted that the depth h of the source-drain groove 120 in the substrate 100 should not be too small or too large. If the depth h of the source-drain groove 120 in the substrate 100 is too small, in the subsequent step of forming the source-drain doped layer in the source-drain groove 120, the source-drain groove 120 provides insufficient epitaxial growth space for the source-drain doped layer; if the depth h of the source-drain groove 120 in the substrate 100 is too large, the height of the source-drain doped layer subsequently formed in the source-drain groove 120 in the substrate 100 is too large, which easily increases the probability of leakage current between the source-drain doped layer and the substrate 100, and also easily increases the difficulty of the subsequent process of forming the isolation sidewall in the groove 121. For this reason, in the present embodiment, the depth h of the source-drain groove 120 in the substrate 100 is 10 nanometers to 40 nanometers.
[0090] In this embodiment, the step of forming the source-drain groove 120 includes: etching the channel stack 108 and a portion of the thickness of the substrate 100 on both sides of the dummy gate structure 111 to form the source-drain groove 120. Specifically, the channel stack 108 and a portion of the thickness of the substrate 100 exposed by the dummy gate mask layer 112 and the gate sidewall 113 are etched to form the source-drain groove 120.
[0091] Specifically, in this embodiment, an anisotropic etching process is used to etch the channel stack 108 on both sides of the pseudo-gate structure 111 and a partial thickness of the substrate 100 to form an initial groove (not shown); an isotropic etching process is used to etch the substrate 100 in a direction parallel to the substrate 100, so that the side wall of the substrate 100 is retracted relative to the side wall on the same side of the channel stack 108 to form a groove 121, thereby forming a source and drain groove 120.
[0092] Specifically, an anisotropic etching process is first used to etch the channel stack 108 and a partial thickness of the substrate 100 on both sides of the pseudo-gate structure 111 to form a rough morphology of the source and drain grooves 120, and then an isotropic etching process is used to etch a portion of the substrate 100 in a direction parallel to the substrate 100, so that the side walls of the substrate 100 exposed by the source and drain grooves 120 can be retracted relative to the side walls on the same side of the channel stack 108 to form a groove 121.
[0093] In this embodiment, the anisotropic etching process includes a dry etching process. The anisotropic dry etching process has a high profile controllability, which is beneficial to improving the profile morphology quality of the source-drain groove 120. In addition, the selected anisotropic dry etching process is beneficial to achieving a high etching selectivity, thereby reducing the probability of mis-etching other film layers.
[0094] In this embodiment, the isotropic etching process includes a wet etching process. The isotropic wet etching process can etch in directions parallel to and perpendicular to the substrate 100, and the wet etching process is easy to achieve a large etching selectivity, which is conducive to reducing the difficulty of etching the substrate in a direction parallel to the substrate, and is convenient for forming the groove 121.
[0095] refer to Figures 7 and 8 , an isolation spacer 200 is formed on the sidewall of the substrate 100 exposed by the source / drain groove 120 .
[0096] The isolation sidewall 200 isolates the subsequent source-drain doped layer from the sidewall of the substrate 100. The isolation sidewall 200 can block the leakage current channel between the source-drain doped layer and the substrate 100 at the bottom of the channel stack 108. In addition, the isolation sidewall 200 can also block the diffusion of doped ions in the source-drain doped layer into the substrate 100 at the bottom of the channel stack 108, thereby improving the leakage current problem between the source-drain doped layer and the substrate 100 and improving the performance of the semiconductor structure.
[0097] Specifically, in this embodiment, the isolation spacer 200 is formed in the trench 121 and covers the sidewall of the substrate 100 exposed by the trench 121 .
[0098] In this embodiment, the isolation spacer 200 is made of an insulating dielectric material, thereby ensuring that the isolation spacer 200 can isolate the source / drain doping layer from the sidewall of the substrate 100 .
[0099] Specifically, in this embodiment, the material of the isolation spacer 200 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material. As an example, the material of the isolation spacer 200 is silicon nitride.
[0100] The following combination Figures 7 and 8, the steps of forming the isolation sidewall 200 in this embodiment are described in detail.
[0101] like Figure 7 As shown, a deposition layer 130 is formed on the bottom and sidewalls of the source / drain groove 120 and the sidewalls and top surface of the dummy gate structure 111 , and the deposition layer 130 fills the trench.
[0102] The deposition layer 130 is used to provide materials for subsequently forming isolation spacers.
[0103] Specifically, the deposition layer 130 conformally covers the bottom and sidewalls of the source / drain grooves 120 , the top of the dummy gate mask layer 112 , and the sidewalls of the gate spacer 113 .
[0104] In this embodiment, the process of forming the deposition layer 130 includes a chemical vapor deposition process.
[0105] Specifically, the chemical vapor deposition process has the characteristics of good filling performance and high step coverage. The chemical vapor deposition process is used to form the deposition layer 130, which is beneficial to improve the isolation sidewall 200 in the groove 121 (such as Figure 7 The filling capacity and filling quality within the structure (as shown) can improve the isolation effect of the isolation spacer 200 after the isolation spacer 200 is subsequently formed, and the chemical vapor deposition process has low cost and high process compatibility.
[0106] In other embodiments, the process of forming the deposition layer 130 further includes an atomic deposition process.
[0107] like Figure 8 As shown, the deposition layer 130 located at the bottom of the source / drain groove 120 , the sidewall of the channel stack 108 , and the sidewall and top of the dummy gate structure 111 is removed, and the remaining deposition layer 130 located in the trench is retained as the isolation spacer 200 .
[0108] Among them, since the deposition layer 130 is also filled in the groove, the deposition layer 130 filled in the groove is thicker. Therefore, in the process of etching the deposition layer 130, while the deposition layer 130 located on the bottom substrate 100 of the source and drain groove 120, on the side wall of the channel stack 108, and on the side wall and top of the pseudo gate structure 111 is removed, the deposition layer 130 located in the groove can be retained to serve as an isolation sidewall 200.
[0109] In this embodiment, the process steps of removing the deposition layer 130 located at the bottom of the source and drain groove 120, the sidewalls of the channel stack 108, and the sidewalls and top of the dummy gate structure 111 include: using an anisotropic etching process to etch and remove the deposition layer 130 located at the bottom of the source and drain groove 120 and the top of the dummy gate structure 111; after the anisotropic etching process, using an isotropic etching process to etch and remove the deposition layer 130 located at the sidewalls of the channel stack 108 and the dummy gate structure 111.
[0110] Specifically, by first adopting an anisotropic etching process to etch away the deposition layer 130 located at the bottom of the source-drain groove 120 and the top of the dummy gate structure 111, it is beneficial to improve the etching efficiency. Then, an isotropic etching process is adopted to utilize the isotropic etching characteristics of the isotropic etching process to etch away the deposition layer 130 located at the side walls of the channel stack 108 and the dummy gate structure 111 to expose the side wall surface of the channel layer 106, thereby facilitating the subsequent step of forming the source-drain doping layer in the source-drain groove 120, so that the source-drain doping layer can contact the channel layer 106.
[0111] In this embodiment, the anisotropic etching process includes a dry etching process. The anisotropic dry etching process has better profile controllability, which is beneficial to improving the profile morphology quality of the source-drain groove 120 after removing the deposition layer 130. In addition, the selected anisotropic dry etching process is beneficial to achieving a higher etching selectivity, thereby reducing the probability of mis-etching other film layers.
[0112] In this embodiment, the isotropic etching process includes a wet etching process. The isotropic wet etching process can etch in a direction parallel to and perpendicular to the channel layer 106, and the wet etching process is easy to achieve a large etching selectivity, which is conducive to reducing the difficulty of etching the deposition layer 130 located on the sidewall of the channel stack 108 and reducing the probability of damage to other film structures.
[0113] In this embodiment, the step of forming the isolation sidewall 200 also includes: after forming the deposition layer 130 and before removing the deposition layer 130 located at the bottom of the source and drain groove 120, the sidewall of the channel stack 108, and the sidewall and top of the pseudo gate structure 111, modifying the deposition layer 130 to improve the density of the deposition layer 130.
[0114] By modifying the deposition layer, the density of the deposition layer 130 is improved, thereby improving the isolation capability of the isolation sidewall 200, so that the isolation sidewall 200 has a stronger ability to block leakage current between the source-drain doping layer and the bottom substrate 100 of the channel stack 108, which is beneficial to improving the improvement effect of the leakage current problem.
[0115] In this embodiment, the step of modifying the deposition layer 130 includes: performing ion doping treatment on the deposition layer 130, wherein the doped ions include group IV element ions; and performing heat treatment on the deposition layer doped with group IV element ions.
[0116] After the ion doping treatment and heat treatment are carried out successively, the group IV element ions can form a process from amorphization to recrystallization, so that by doping the group IV element ions in the deposition layer 130 and heat treating the deposition layer doped with the group IV element ions, the group IV element ions can move and fill into the lattice vacancies in the deposition layer 130 material during the heat treatment, thereby realizing the modification of the deposition layer 130 material, and facilitating the elimination of defects in the deposition layer 130, improving the density of the deposition layer 130 material, and the group IV element ions have little effect on the performance of the device.
[0117] Moreover, in this embodiment, the modification treatment is carried out by means of ion doping treatment and heat treatment, which is beneficial to combining with the existing process flow, thereby helping to improve process compatibility, reduce process risks and costs, and ensure the effect of the modification treatment.
[0118] In this embodiment, during the ion doping process, the IV group element ions include carbon ions. Since the carbon ions are relatively small in size, it is helpful to reduce the difficulty of filling the lattice vacancies, and by introducing carbon elements into the deposition layer 130 material, it is also helpful to reduce the dielectric constant of the deposition layer 130 material, thereby helping to improve the isolation effect of the isolation sidewall 200 on the source-drain doping layer and the sidewall of the substrate 100.
[0119] In other embodiments, the group IV element ions may also include silicon ions or germanium ions.
[0120] In this embodiment, an ion implantation process is used to perform ion doping. The ion implantation process has the characteristics of fast process rate and high process controllability. The ion implantation process is used to dope the deposition layer 130, and the formation position of the ion doping region and the depth of the ion doping region in the deposition layer 130 can be accurately controlled, so that the isolation sidewall 200 formed subsequently can play a better isolation role, which is beneficial to improve the leakage current problem.
[0121] It should be noted that the temperature of the heat treatment should not be too high or too low. If the temperature of the heat treatment is too high, it is easy to cause the diffusion speed of the group IV element ions to be too fast, which will increase the difficulty of increasing the density of the deposited layer, and easily damage the deposited layer 130 material, and also increase the probability of impurity ion loss in the well region, and also increase the probability of impurity ion concentration on the surface of the substrate 100 and the channel layer 106 being reduced and not conducive to the redistribution of impurity ions; if the temperature of the heat treatment is too low, it is easy to cause the group IV element ions to be unable to form the required repair effect. Therefore, the temperature range of the heat treatment is 400 degrees Celsius to 700 degrees Celsius.
[0122] It should also be noted that the process time of the heat treatment should not be too long or too short. If the process time of the heat treatment is too long, it is easy to cause excessive diffusion of the ions of the group IV elements, and it is also easy to increase the probability of impurity ion loss in the well region, and it is also easy to increase the probability of impurity ion concentration on the surface of the substrate 100 and the channel layer 106 being reduced, which is not conducive to the redistribution of impurity ions, and it is easy to cause damage to the deposition layer 130 material and other film layer structures; if the process time of the heat treatment is too short, the required repair effect cannot be formed. Therefore, the process time of the heat treatment is 1 minute to 30 minutes.
[0123] In this embodiment, the process of heat treating the ion-implanted deposition layer 130 includes an annealing process.
[0124] Specifically, the annealing process has the characteristics of low process cost and high controllability of annealing temperature. The annealing process is used to perform heat treatment on the ion-doped area, which can repair the lattice defects caused by the doping treatment.
[0125] In this embodiment, the annealing process includes a rapid thermal annealing process (RTA).
[0126] It should be noted that, in this embodiment, the modification treatment of the deposition layer 130 is described by performing ion doping treatment on the deposition layer 130 and performing heat treatment, and the modification treatment method is not limited to this.
[0127] In this embodiment, the step of forming the isolation sidewall 200 also includes: after forming the deposition layer 130 and before removing the deposition layer 130 located at the bottom of the source and drain groove 120, the sidewall of the channel stack 108, and the sidewall and top of the pseudo gate structure 111, performing a first interface repair treatment on the bottom and sidewall of the source and drain groove 120 to repair the interface state of the substrate 100 in contact with the deposition layer 130.
[0128] Specifically, the interface state of the surface of the substrate 100 exposed at the bottom of the source-drain groove 120 is repaired, thereby providing a good interface state for the subsequent formation of a source-drain doped layer in the source-drain groove 120, which is correspondingly beneficial to the epitaxial growth quality of the source-drain doped layer, and repairing the defects in the lattice at the bottom of the source-drain doped layer, which is beneficial to improving the problem of stacking fault defects in the source-drain doped layer, and further improving the leakage current problem between the source-drain doped layer and the substrate 100.
[0129] In this embodiment, the step of performing a first interface repair treatment on the bottom and sidewalls of the source / drain groove 120 includes: treating the bottom and sidewalls of the source / drain groove 120 with an inert gas.
[0130] By treating the bottom and side walls of the source-drain groove 120 with an inert gas, the interface state between the deposited layer and the bottom and side walls of the source-drain groove 120 can be passivated, thereby repairing the interface state of the bottom and side walls of the source-drain groove 120.
[0131] Specifically, the specific steps of using the inert gas to process the bottom and sidewalls of the source / drain groove 120 include: introducing the inert gas into the reaction chamber so that the inert gas contacts the bottom and sidewalls of the source / drain groove 120 .
[0132] Specifically, the inert gas includes helium (He), neon (Ne), or argon (Ar).
[0133] It should be noted that the temperature of treating the bottom and sidewalls of the source-drain groove 120 with an inert gas should not be too high or too low. If the temperature is too high, the process risk will increase; if the temperature is too low, the effect of the first interface repair treatment will not be obvious. Therefore, the temperature range of treating the bottom and sidewalls of the source-drain groove 120 with an inert gas is 200 degrees Celsius to 400 degrees Celsius.
[0134] It should also be noted that the process time for treating the bottom and sidewalls of the source-drain groove 120 with an inert gas should not be too long or too short. If the process time is too long, it is easy to increase the risk of process damage; if the process time is too short, the required repair effect cannot be achieved. Therefore, the process time for treating the bottom and sidewalls of the source-drain groove 120 with an inert gas is 10 minutes to 30 minutes.
[0135] In the present embodiment, the method for forming a semiconductor structure is used to form a MOS transistor; after forming the isolation sidewall 200 and before forming the source-drain doping layer, the method for forming the semiconductor structure further includes: performing an inversion doping treatment on the bottom of the source-drain groove 120, wherein the doping type of the inversion doping treatment is different from the channel conductivity type of the MOS transistor, and an inversion doping region is formed in the substrate 100 at the bottom of the source-drain groove 120 (not shown).
[0136] Specifically, the doping type of the inversion doping region is different from the channel conductivity type of the MOS transistor, that is, the doping type of the inversion doping region is different from that of the source and drain doping layer, which is beneficial to improving the potential barrier of the substrate 100 at the bottom of the source and drain groove 120, so that after the source and drain doping layer is subsequently formed in the source and drain groove 120, it can inhibit the diffusion of doped ions in the source and drain doping layer into the substrate, thereby improving the leakage current between the source and drain doping layer and the substrate 100.
[0137] Specifically, in this embodiment, the step of performing inversion doping treatment on the bottom of the source-drain groove 120 includes: using an ion implantation process to dope the substrate 100 at the bottom of the source-drain groove 120 .
[0138] In this embodiment, when an NMOS transistor is formed, the doping ions in the inversion doping process are P-type ions; when a PMOS transistor is formed, the doping ions in the inversion doping process are N-type ions.
[0139] In this embodiment, after performing an inversion doping treatment on the bottom of the source / drain groove 120 and before forming a source / drain doping layer, the method for forming a semiconductor structure also includes: performing a second interface repair treatment on the surface of the substrate 100 at the bottom of the source / drain groove 120 to repair the interface state of the surface of the substrate 100 exposed at the bottom of the source / drain groove 120.
[0140] Specifically, the interface state of the surface of the substrate 100 exposed at the bottom of the source-drain groove 120 is repaired, thereby providing a good interface state for the subsequent formation of a source-drain doped layer in the source-drain groove 120, which is correspondingly beneficial to the epitaxial growth quality of the source-drain doped layer, and repairing the defects in the lattice at the bottom of the source-drain doped layer, which is beneficial to improving the problem of stacking fault defects in the source-drain doped layer, and further improving the leakage current problem between the source-drain doped layer and the substrate 100.
[0141] In this embodiment, the step of performing a second interface repair treatment on the bottom of the source / drain groove 120 includes: performing a gas treatment on the surface of the substrate 100 at the bottom of the source / drain groove 120 using one or both of deuterium and an inert gas.
[0142] Deuterium or inert gas combines more stably with the interface dangling bonds, thereby inhibiting the formation of unstable chemical bonds with hydrogen, and further passivating the interface state. Therefore, by using one or both of deuterium and inert gas to perform gas treatment on the surface of the substrate 100 at the bottom of the source and drain groove 120, the interface state of the surface of the substrate 100 at the bottom of the source and drain groove 120 can be repaired.
[0143] Specifically, in this embodiment, one or both of deuterium and inert gas are introduced into the reaction chamber to perform gas treatment on the surface of the substrate 100 at the bottom of the source / drain groove 120 .
[0144] It should be noted that the flow rate of deuterium or inert gas should not be too fast or too slow. If the flow rate of deuterium or inert gas is too fast, it is easy to increase the probability of uneven interface repair; if the flow rate of deuterium or inert gas is too slow, it is easy to reduce the efficiency of interface repair. Therefore, the flow rate of deuterium or inert gas is 2slm (standard litre per minute, 1L / min flow rate under standard conditions) to 20slm.
[0145] refer to Fig. 9, along a direction parallel to the substrate 100 and perpendicular to the extension direction of the pseudo gate structure 111, a portion of the sacrificial layer 105 exposed on the sidewall of the source / drain groove 120 is laterally etched to form an inner trench 210, wherein the inner trench 210 is surrounded by the adjacent channel layer 106 and the remaining sacrificial layer 105, or the inner trench 210 is surrounded by the isolation sidewall 200, the channel layer 106 adjacent to the substrate 100, and the remaining sacrificial layer 105.
[0146] Specifically, the inner groove 210 provides a space for subsequently forming an inner spacer.
[0147] In this embodiment, the process of laterally etching the portion of the sacrificial layer 105 exposed on the sidewalls of the source / drain grooves 120 includes an isotropic etching process.
[0148] The isotropic etching process has the characteristic of isotropic etching, and it is easy to achieve a larger etching selectivity ratio, so that the portion of the sacrificial layer 105 exposed along the side wall of the source / drain groove 120 can be laterally etched, which is beneficial to reduce the difficulty of etching the sacrificial layer 105 and reduce the probability of damage to other film layer structures.
[0149] refer to Fig.10 , an inner sidewall 300 is formed in the inner trench 210 .
[0150] Subsequently, a source-drain doped layer is formed in the source-drain groove 120, and a gate structure is formed at the position of the pseudo-gate structure 111 and the sacrificial layer 105. The inner sidewall 300 is used to achieve isolation between the source-drain doped layer and the gate structure, and also to increase the distance between the source-drain doped layer and the gate structure, which is beneficial to reducing the parasitic capacitance between the source-drain doped layer and the gate structure.
[0151] In this embodiment, the material of the inner sidewall 300 is an insulating material to achieve isolation between the source and drain doping layers and the gate structure. In this embodiment, the material of the inner sidewall 300 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.
[0152] refer to Fig.11 , a source-drain doped layer 400 is formed in the source-drain groove 120 , and the source-drain doped layer 400 is in contact with the sidewall of the isolation spacer 200 .
[0153] The source-drain doped layer 400 is used as a source or a drain of the MOS transistor. When the MOS transistor is working, the source-drain doped layer 400 is used to provide a carrier source.
[0154] In this embodiment, the source-drain doped layer 400 is in contact with the side wall of the isolation sidewall 200, and the isolation sidewall 200 acts as a barrier between the source-drain doped layer 400 and the substrate 100 at the bottom of the channel stack 108, thereby blocking the leakage current and the diffusion of doped ions in the source-drain doped layer 400 into the substrate 100 at the bottom of the channel stack 108, thereby improving the leakage current problem between the source-drain doped layer 400 and the substrate 100.
[0155] In the present embodiment, after forming the deposition layer 130 and performing ion doping and heat treatment on the deposition layer 130 and before removing the deposition layer 130, the bottom and side walls of the source-drain groove 120 are subjected to a first interface repair treatment, and after performing inversion doping treatment on the bottom of the source-drain groove 120 and before forming the source-drain doping layer 400, the surface of the substrate 100 at the bottom of the source-drain groove 120 is subjected to a second interface repair treatment, thereby repairing the surface of the substrate 100 exposed at the bottom of the source-drain groove 120, and further, in the step of forming the source-drain groove doping layer 400, the quality of the source-drain epitaxial growth can be improved, and the leakage current problem between the source-drain doping layer 400 and the substrate 100 can be correspondingly improved.
[0156] In this embodiment, an epitaxial process is adopted to form the stress layer, and ions are self-doped in situ during the process of forming the stress layer. The stress layer doped with ions is used as the source-drain doping layer 400 .
[0157] Specifically, based on the substrate 100 at the bottom of the source-drain groove 120 and the channel layer 106 exposed by the source-drain groove 120, epitaxial growth is performed on the substrate 100 at the bottom of the source-drain groove 120 to form a source-drain doped layer 400. The interface state on the surface of the substrate is repaired, so that the epitaxial quality of the source-drain doped layer is good, and the leakage current problem between the source-drain doped layer 400 and the substrate 100 is improved.
[0158] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 400 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SIC, and the doped ions in the source and drain doping layer 400 are N-type ions.
[0159] refer to Fig.12 The method for forming a semiconductor structure also includes: after forming a source-drain doping layer 400, forming an interlayer dielectric layer 410 on the substrate at the side of the dummy gate structure 111, the interlayer dielectric layer 410 covers the source-drain doping layer and exposes the top of the dummy gate structure 111; removing the dummy gate structure 111, forming a gate opening 420 in the interlayer dielectric layer, exposing the channel stack 108; removing the sacrificial layer 105 exposed by the gate opening 420, forming a through groove 430, and the through groove 430 is connected to the gate opening 420.
[0160] The interlayer dielectric layer 410 is used to cover the source-drain doped layer 400 , and plays a role in protecting the source-drain doped layer 400 when a gate opening 420 is subsequently formed.
[0161] The material of the interlayer dielectric layer 410 includes one or more of silicon oxide and silicon nitride. As an example, the material of the interlayer dielectric layer 410 is silicon nitride.
[0162] The gate opening 420 and the through-slot 430 are used to provide a space for forming a gate structure.
[0163] After removing the sacrificial layer 105, one or more channel layers 106 are suspended and arranged at intervals, so that the subsequent gate structure can surround the channel layer 106. The one or more channel layers 106 that are suspended and arranged at intervals in sequence are used to form the channel structure layer 600.
[0164] refer to Fig.13 , a gate structure 500 is filled in the gate opening 420 and the through groove 430 , and the gate structure 500 surrounds the channel layer 106 .
[0165] When the device is operating, the gate structure 500 is used to control the opening and closing of the conductive channel.
[0166] In this embodiment, the gate structure 500 is a metal gate structure, and the gate structure 500 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through groove 430 and the gate opening 420.
[0167] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.
[0168] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.
[0169] The work function layer is used to adjust the work function of the gate structure 500, and then adjust the threshold voltage of the field effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.
[0170] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 500 to an external circuit. The material of the gate electrode layer is a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.
[0171] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: substrate; A channel structure layer is suspended on the substrate, and the channel structure layer includes one or more channel layers sequentially arranged from bottom to top; A gate structure, spanning the channel structure layer, the gate structure is filled between the channel layer and the substrate and between adjacent channel layers; the gate structure surrounds the channel layer; Source and drain doping layers are located in the channel structure layer on both sides of the gate structure and in a portion of the thickness of the substrate; The isolation sidewall is located between the sidewall of the source-drain doping layer and the substrate sidewall at the bottom of the channel structure layer.
2. The semiconductor structure according to claim 1, wherein: The substrate sidewall contacting the isolation spacer is retracted relative to the same sidewall of the channel structure layer.
3. The semiconductor structure according to claim 1, wherein: The material of the isolation sidewalls includes one of silicon oxide, silicon nitride or silicon carbonitride.
4. The semiconductor structure according to claim 1, wherein: The thickness of the substrate in contact with the isolation sidewall is 10 nanometers to 40 nanometers.
5. The semiconductor structure according to claim 1 or 2, characterized in that: Along a direction parallel to the substrate, the width of the isolation sidewall is 2 nanometers to 4 nanometers.
6. The semiconductor structure according to claim 1, wherein: The semiconductor structure is used to form a MOS transistor; The semiconductor structure further includes: an inversion doping region located in the substrate at the bottom of the source-drain doping layer, wherein the doping ion type is different from the channel conductivity type of the MOS transistor.
7. A method for forming a semiconductor structure, characterized in that: include: Providing a base, including a substrate and one or more sequentially stacked channel stacks located on the substrate, each of the channel stacks including a sacrificial layer and a channel layer located on the sacrificial layer; forming a dummy gate structure across the channel stack; Forming source and drain grooves in the channel stack on both sides of the dummy gate structure and in a partial thickness of the substrate; forming an isolation sidewall on the sidewall of the substrate exposed by the source / drain groove; A source-drain doping layer is formed in the source-drain groove, and the source-drain doping layer is in contact with the side wall of the isolation spacer.
8. The method for forming a semiconductor structure according to claim 7, wherein: In the step of forming the source / drain grooves, the exposed substrate sidewalls of the source / drain grooves are retracted relative to the same sidewalls of the channel stack.
9. The method for forming a semiconductor structure according to claim 8, wherein: The exposed sidewalls of the substrate of the source / drain grooves and the bottom of the channel stack form a groove; The step of forming the isolation sidewall comprises: forming a deposition layer on the bottom and sidewall of the source / drain groove, the sidewall and top surface of the dummy gate structure, wherein the deposition layer fills the groove; The deposition layer at the bottom of the source / drain groove, the sidewall of the channel stack, and the sidewall and top of the dummy gate structure is removed, and the remaining deposition layer in the trench is retained as the isolation sidewall.
10. The method for forming a semiconductor structure according to claim 9, wherein: The process of forming the deposition layer includes a chemical vapor deposition process.
11. The method for forming a semiconductor structure according to claim 9, wherein: The process of removing the deposition layer located at the bottom of the source and drain grooves, the sidewalls of the channel stack, and the sidewalls and top of the dummy gate structure includes: using an anisotropic etching process to etch and remove the deposition layer located at the bottom of the source and drain grooves and the top of the dummy gate structure; after the anisotropic etching process, using an isotropic etching process to etch and remove the deposition layer located at the sidewalls of the channel stack and the dummy gate structure.
12. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming the isolation sidewall also includes: after forming the deposition layer and before removing the deposition layer located at the bottom of the source and drain groove, the sidewall of the channel stack, and the sidewall and top of the pseudo gate structure, modifying the deposition layer to improve the density of the deposition layer.
13. The method for forming a semiconductor structure according to claim 12, wherein: The step of modifying the deposited layer comprises: performing ion doping on the deposited layer, wherein the doped ions include group IV element ions; and performing heat treatment on the deposited layer doped with group IV element ions.
14. The method for forming a semiconductor structure according to claim 13, wherein: The group IV element ions include carbon ions, silicon ions or germanium ions.
15. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming the isolation sidewall also includes: after forming the deposition layer and before removing the deposition layer located at the bottom of the source and drain groove, the sidewall of the channel stack, and the sidewall and top of the pseudo gate structure, performing a first interface repair treatment on the bottom and sidewall of the source and drain groove to repair the interface state of the substrate in contact with the deposition layer.
16. The method for forming a semiconductor structure according to claim 15, wherein: The step of performing a first interface repair treatment on the bottom and side walls of the source / drain groove comprises: using an inert gas to treat the bottom and side walls of the source / drain groove.
17. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the semiconductor structure is used to form a MOS transistor; After forming the isolation side wall and before forming the source-drain doping layer, the method for forming the semiconductor structure also includes: performing an inversion doping treatment on the bottom of the source-drain groove, wherein the doping type of the inversion doping treatment is different from the channel conductivity type of the MOS transistor, and an inversion doping region is formed in the substrate at the bottom of the source-drain groove.
18. The method for forming a semiconductor structure according to claim 17, wherein: After performing an inversion doping treatment on the bottom of the source / drain groove and before forming the source / drain doping layer, the method for forming the semiconductor structure further includes: performing a second interface repair treatment on the substrate surface at the bottom of the source / drain groove to repair the interface state of the substrate surface exposed at the bottom of the source / drain groove.
19. The method for forming a semiconductor structure according to claim 18, wherein: The step of performing a second interface repair treatment on the bottom of the source-drain groove comprises: using one or both of deuterium and inert gas to perform gas treatment on the substrate surface at the bottom of the source-drain groove.
20. The method for forming a semiconductor structure according to claim 19, wherein: The method for forming the semiconductor structure further comprises: after forming the source-drain doping layer, removing the dummy gate structure to form a gate opening to expose the channel stack; Removing the sacrificial layer exposed by the gate opening to form a through groove, wherein the through groove is connected to the gate opening; A gate structure is filled in the gate opening and the through groove, and the gate structure surrounds the channel layer.