A unidirectional low voltage transient suppression diode and its preparation method

Abstract

A unidirectional low-voltage transient suppression diode disclosed in the present invention comprises an N++ single crystal, an epitaxial P-region and a P-region formed in sequence on the surface of the N++ single crystal, an Nb+ buried layer region, an N+ region and a P+ region arranged in the P-region, a dielectric layer arranged above the P-region, a first metal layer arranged above the dielectric layer, a second metal layer and a deep groove arranged below the N++ single crystal, wherein the deep groove extends downward from the dielectric layer to the N++ single crystal. The unidirectional low-voltage transient suppression diode of the present invention introduces a low-voltage triode NPN composed of an N++ single crystal, a P-region and an Nb+ buried layer region to obtain a low breakdown voltage. Under the condition that the chip area remains unchanged, a lower breakdown voltage and a lower leakage current are obtained through a new structure and process design.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and mainly relates to a unidirectional low-voltage transient suppression diode and a preparation method thereof. Background Art

[0002] Figure 4 The figure shows a structural diagram of a unidirectional low-voltage transient suppression diode of a conventional process. Above the N++ single crystal wafer 111 are the P++ buried layer region 113 and the P- region 112. Above the P- region 114a is the N+ region 116. Above the P- region 114b is the P+ region 117. 120 and 119 are metal regions, representing the cathode and anode of the diode, respectively. 118a, 118b, and 118c are dielectric layers. 115a, 115b, and 115c are deep trenches, which mainly serve the isolation and protection functions. Figure 5 The figure shows an equivalent circuit diagram of a unidirectional low-voltage transient suppression diode of a conventional process, which is equivalent to D1 connected in series with TVS and then connected in parallel with D2. Among them, D1 is a low-capacitance diode composed of P--region 114a and N+ region 116, TVS is a low-voltage diode composed of N++ single crystal 111 and P++ buried layer region 113, and D2 is a low-capacitance diode composed of N++ single crystal 111 and P-region 112, P--region 114b, and P+ region 117.

[0003] Figure 2 The middle curve a shows an IV characteristic curve of a unidirectional low-voltage transient suppression diode of a conventional process. When 119 is at a high potential and 120 is grounded, the current flows from the P+ region 117 through the P-- region 114b, the P-- region 112, and the N++ single crystal 111, showing the forward conduction characteristic of the diode. When 120 is at a high potential and 119 is grounded, the current flows from the N++ single crystal 111 through the P++ buried layer region 113, the P-- region 114a, and the N+ region 116, showing the low-voltage breakdown characteristic of the diode. The breakdown voltage of the diode is determined by the NP junction composed of the N++ single crystal 111 and the P++ buried layer 113. The product parameters that can be obtained with this structure are: VRWM=5V, VBR(IT=1mA)=6.0~8.0V, IR(VR=5V)≤0.1μA, IPP(tp=8 / 20μs)≥4A, Cj(f=1MHz, VR=0V)=0.4~0.7pF, VESD(Contact Mode)≥20kV.

[0004] A conventional process unidirectional low voltage transient suppression diode is on an N++ single crystal wafer 111 of 0.002-0.006Ω.cm, epitaxially grows a P- region 112, front-side photolithography of a P++ buried region pattern, boron implantation, and advancement to form a P++ buried region 113, epitaxially grows P-- regions 114a and 114b, front-side photolithography of an N+ region 116 pattern, phosphorus implantation and advancement to form an N+ region 116, front-side photolithography of a P+ region 117 pattern, boron implantation and advancement to form a P+ region 117, front-side photolithography of a groove pattern to form deep grooves 115a, 115b, and 115c.

[0005] The breakdown voltage of a conventional unidirectional low-voltage transient suppression diode is determined by the NP junction formed by the heavily doped N++ single crystal 111 and the high-concentration P++ buried layer 113, which is an avalanche breakdown voltage and can reach 6.0~8.0V. If the voltage is increased to 4.0-5.0V, the concentration of the N++ single crystal 111 and the P++ buried layer 113 needs to be further increased, but the high concentration will increase the leakage current exponentially to more than 1μA.

[0006] The present invention provides a new technical solution, which can provide a unidirectional low-voltage transient suppression diode, and can obtain lower breakdown voltage and lower leakage current through new structure and process design under the condition of unchanged chip area. Summary of the invention

[0007] In view of this, the purpose of the present invention is to provide a new technical solution, which can provide a unidirectional low-voltage transient suppression diode. Under the condition of unchanged chip area, a lower breakdown voltage and lower leakage current can be obtained through a new structure and process design.

[0008] To achieve the above-mentioned purpose, on the one hand, a unidirectional low-voltage transient suppression diode of the present invention comprises an N++ single crystal wafer, an epitaxial P-region and a P--region sequentially formed on the surface of the N++ single crystal wafer, an Nb+ buried layer region, an N+ region and a P+ region arranged in the P--region, a dielectric layer arranged above the P--region, a first metal layer arranged above the dielectric layer, a second metal layer arranged below the N++ single crystal wafer and a deep trench, wherein the deep trench extends downward from the dielectric layer to the N++ single crystal wafer.

[0009] On the other hand, the technical solution adopted by the present invention is a method for preparing a unidirectional low-voltage transient suppression diode, comprising the following steps:

[0010] Step 01, prepare N++ single crystal wafer and grow P- region;

[0011] Step 02, grow a sacrificial oxide layer, photolithography Nb+ buried layer pattern on the front side, implant arsenic on the front side, and push forward to form Nb+ buried layer area;

[0012] Step 03, epitaxial growth of P-- region;

[0013] Step 04: Photolithography of the N+ region pattern on the front side, phosphorus implantation on the front side, and advancement to form the N+ region;

[0014] Step 05: Photolithography of the P+ region pattern on the front side, front boron implantation, advancement, forming the P+ region;

[0015] Step 06: Photolithography of deep groove patterns on the front side, trenching on the front side, and filling with TEOS to form deep grooves;

[0016] Step 07, deposit dielectric layer, perform front contact hole photolithography to form contact hole, evaporate metal on the front side, perform front metal photolithography, alloy to form metal area;

[0017] Step 08: Thin the back side and evaporate metal on the back side to form a metal area.

[0018] In some embodiments, the crystal orientation of the N++ single crystal in step 01 is <100> The impurity is arsenic, the resistivity is 0.002~0.006Ω·cm, the resistivity of the P-region 102 is 1~10Ω·cm, and the thickness is 5~10μm.

[0019] In some embodiments, the thickness of the sacrificial oxide layer in step 02 is 600-1000Å, and the dose of arsenic implanted on the front side is 5E15-1E16cm -2 The energy is 60~180keV, the temperature condition of arsenic advancement is 1050~1150℃, and the time is 60~180min to form a Nb+ buried layer area.

[0020] In some embodiments, the resistivity of the P-- region in step 03 is 100-300 Ω·cm, and the thickness is 10-15 μm.

[0021] In some embodiments, the phosphorus implantation dosage in step 04 is 2E15-5E15cm -2 , the energy is 40~100keV, the temperature condition of phosphorus advancement is 1000~1100℃, the time is 60~180min, and the N+ region 106 is formed.

[0022] In some embodiments, the boron implantation dose in step 05 is 4E15-8E15cm -2 , energy is 40~120KeV, temperature conditions of boron advancement are 900~1050℃, time is 30~120min, and P+ region 107 is formed.

[0023] In some embodiments, the deep grooves in step 06 have a depth of 20-25 μm, a width of 1-3 μm, and a spacing between grooves of 2-4 μm.

[0024] In some embodiments, the dielectric layer in step 07 is tetraethoxysilane TEOS with a thickness of 5000~10000Å, the metal evaporated on the front side is aluminum or aluminum copper or aluminum silicon copper with a thickness of 2~5μm, the temperature of the alloy is 360~430℃, and the time is 25~45min.

[0025] In some embodiments, the back surface in step 08 is thinned to a thickness of 150-200 μm, and the back surface evaporated metal is Ti / Ni / Ag with a thickness of 0.1-0.3 μm, 0.2-0.5 μm, or 1.0-1.5 μm.

[0026] The advantages of the present invention are:

[0027] 1. The present invention provides a new technical solution, which can provide a unidirectional low-voltage transient suppression diode. Under the condition of unchanged chip area, a lower breakdown voltage and lower leakage current can be obtained through a new structure and process design.

[0028] 2. A unidirectional low-voltage transient suppression diode of the present invention is introduced into a low-voltage triode NPN composed of an N++ single crystal 101, a P-region 102a, and Nb+ buried regions 103a and 103b to obtain a low breakdown voltage. By controlling the effective thickness T of the P-region 102a between the N++ single crystal 101 and the Nb+ buried regions 103a and 103b, a low-value BVCEO of the punch-through triode structure can be obtained. When T is in the range of 0.3-0.5μm, the BVCEO of the NPN triode is 3.0-5.0V. At the same time, due to the low concentration of the P-region 102a, the leakage current is effectively reduced, and the product parameters that can be obtained by the structure of the present invention can be: VRWM=3.3V, VBR(IT=1mA)=4.0~5.0V, IR(VR=3.3V)≤0.1μA, IPP(tp=8 / 20μs)≥4A, Cj(f=1MHz, VR=0V)=0.4~0.7pF, VESD(Contact Mode)≥20kV. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly understand the purpose and advantages of the present invention, the following will be described in detail with reference to the accompanying drawings, in which:

[0030] Figure 1 The structure diagram of a unidirectional low-voltage transient suppression diode of the present invention.

[0031] Figure 2 The IV characteristic curve diagram is a unidirectional low-voltage transient suppression diode of the present invention and a unidirectional low-voltage transient suppression diode of a conventional process.

[0032] Figure 3The figure is an equivalent circuit diagram of a unidirectional low-voltage transient suppression diode of the present invention.

[0033] Figure 4 The figure is a structural diagram of a unidirectional low voltage transient suppression diode of a conventional process.

[0034] Figure 5 The equivalent circuit diagram of a unidirectional low voltage transient suppression diode of a conventional process.

[0035] Figure 6 This is the first step of the process of a unidirectional low-voltage transient suppression diode of the present invention, namely preparing an N++ single crystal wafer 101 and epitaxially growing a P-region 102.

[0036] Figure 7 This is the second step process of a unidirectional low voltage transient suppression diode of the present invention, namely growing a sacrificial oxide layer, photolithography of a Nb+ buried layer pattern on the front side, and implanting and advancing arsenic on the front side to form Nb+ buried layer regions 103a and 103b.

[0037] Figure 8 This is the third step of the process of the unidirectional low voltage transient suppression diode of the present invention, namely, epitaxially growing the P-- region 104 .

[0038] Fig. 9 This is the fourth step of the process of the unidirectional low voltage transient suppression diode of the present invention, namely, front photolithography of the N+ region 106 pattern, front phosphorus implantation, and advancement to form the N+ region 106.

[0039] Fig.10 This is the fifth step of the process of the unidirectional low voltage transient suppression diode of the present invention, namely, front photolithography of the P+ region 107 pattern, front boron implantation, and advancement to form the P+ region 107.

[0040] Fig.11 This is the sixth step of the process of the unidirectional low voltage transient suppression diode of the present invention, namely, photolithography of deep groove patterns on the front side, trenching on the front side, and filling with TEOS to form deep grooves 105a, 105b, and 105c.

[0041] Fig.12 This is the seventh step of the process of a unidirectional low-voltage transient suppression diode of the present invention, namely, depositing dielectric layers 108a, 108b, 108c, photolithography of the front contact hole to form the contact hole, evaporating metal on the front side, photolithography of the front metal, alloying, and forming the metal area 109.

[0042] Fig.13 This is the eighth step of the process of the unidirectional low-voltage transient suppression diode of the present invention, namely, thinning the back side and evaporating metal on the back side to form the metal area 110 . DETAILED DESCRIPTION

[0043] The present invention is further described in detail below in conjunction with the accompanying drawings and implementation modes. A detailed description is given by taking the 3.3V voltage level as an example.

[0044] This implementation case uses a 3.3V voltage level for detailed explanation.

[0045] Figures 6 to 13 A process for producing a unidirectional low voltage transient suppression diode according to the present invention is provided.

[0046] First, the crystal orientation of the N++ single crystal wafer 101 is <111> The impurity is arsenic, and the resistivity is 0.003~0.006Ω·cm. The P-layer 102 is epitaxially grown, and the resistivity of the P-layer 102 is 3~5Ω·cm and the thickness is 5~7μm.

[0047] Grow a sacrificial oxide layer 121 with a thickness of 600-800Å, photolithography the Nb+ buried layer pattern on the front side, and implant arsenic at a dose of 8E15-1E16cm -2 The energy is 120~180KeV, the temperature condition of arsenic advancement is 1100~1150℃, and the time is 120~180min to form Nb+ buried layer regions 103a and 103b.

[0048] The P--region 104 is epitaxially grown, and the resistivity of the P--region 104 is 100-200Ω·cm and the thickness is 10-12μm.

[0049] The front side photolithography N+ region 106 pattern, phosphorus implantation dose is 3E15~5E15cm -2 , energy is 60~100KeV, temperature condition of phosphorus advancement is 1050~1100℃, time is 60~120min, and N+ region 106 is formed.

[0050] Front lithography P+ region 107 pattern, boron implantation dose 5E15~8E15cm -2 , energy is 60~120KeV, temperature condition of boron advancement is 1000~1050℃, time is 60~90min, and P+ region 107 is formed.

[0051] The front side is photolithographically patterned with deep grooves, and grooves are dug on the front side and filled with TEOS to form deep grooves 105a, 105b, and 105c. The depth of the deep grooves is 20-22 μm, the width is 1-2 μm, and the spacing between the grooves is 2-3 μm.

[0052] Deposit dielectric layers 108a, 108b, and 108c, perform front contact hole photolithography to form contact holes, evaporate metal on the front, perform front metal photolithography, and alloy to form metal region 109. Dielectric layers 108a, 108b, and 108c are tetraethoxysilane TEOS with a thickness of 5000 to 8000Å. The metal evaporated on the front is aluminum or aluminum copper or aluminum silicon copper with a thickness of 3 to 5μm. The temperature of the alloy is 400 to 430°C and the time is 25 to 45 minutes.

[0053] The back side is thinned and metal is evaporated on the back side to form a metal region 110. The back side is thinned to a thickness of 180-200 μm, and the evaporated metal on the back side is Ti / Ni / Ag with a thickness of 0.1 μm / 0.2 μm / 1.0 μm.

[0054] Figure 1 The structure diagram of a unidirectional low-voltage transient suppression diode of the present invention is shown. P-regions 102a and 102b are epitaxially grown on an N++ single crystal wafer 101. Above the P-region 102a are Nb+ buried layer regions 103a and 103b. Above the P-region 104a is an N+ region 106. Above the P-region 104b is a P+ region 107. 110 and 109 are metal regions, representing the cathode and anode of the diode, 108a, 108b, and 108c are dielectric layers, and 105a, 105b, and 105c are deep trenches, which mainly serve the function of isolation protection. Figure 3 The figure shows an equivalent circuit diagram of a unidirectional low-voltage transient suppression diode of the present invention, which is equivalent to D3 being connected in parallel with NPN, then connected in series with D1, and finally connected in parallel with D2. Among them, D1 is a low-capacitance diode composed of P--region 104a and N+ region 106, D3 is a diode composed of N++ single crystal 101 and P-region 102a, NPN is a low-voltage triode composed of N++ single crystal 101 and P-region 102a, Nb+ buried layer regions 103a and 103b, and D2 is a low-capacitance diode composed of N++ single crystal 101 and P-region 102b, P--region 104b, and P+ region 107.

[0055] Figure 2 The curve b in the middle shows the IV characteristic curve of a unidirectional low-voltage transient suppression diode of the present invention. When 109 is at a high potential and 110 is grounded, the current flows from the P+ region 107 through the P-- region 104b, the P-- region 102b, and the N++ single crystal 101, showing the forward conduction characteristic of the diode. When 110 is at a high potential and 109 is grounded, the current flows from the N++ single crystal 101 through the P-- region 102a, the Nb+ buried layer regions 102a, 102b, the P-- region 104a, and the N+ region 106, showing the low-voltage breakdown characteristic of the triode.

[0056] Figures 6 to 13 The invention discloses a process flow of a unidirectional low-voltage transient suppression diode. Figure 6 The P-layer 102 is epitaxially grown on the N++ single crystal wafer 101. Figure 7 The sacrificial oxide layer is grown, the Nb+ buried layer pattern is photolithographically formed on the front side, and arsenic is implanted on the front side to form Nb+ buried layer regions 103a and 103b. Figure 8 It is an epitaxially grown P-- region 104, Fig. 9 The N+ region 106 pattern is photolithographically processed on the front side, and phosphorus is implanted and pushed forward to form the N+ region 106. Fig.10 The front side photolithography P+ region 107 pattern, the front side boron implantation, advancement, forming the P+ region 107, Fig.11 The front side is photolithographically processed into deep groove patterns, the front side is grooved, and TEOS is filled to form deep grooves 105a, 105b, and 105c. Fig.12 The dielectric layers 108a, 108b, and 108c are deposited, the front contact holes are photolithographically formed, the metal is evaporated on the front side, the front metal is photolithographically formed, and the alloy is formed to form the metal area 109. Fig.13 The back side is thinned and metal is evaporated on the back side to form a metal region 110 .

[0057] Different from conventional structures, a unidirectional low-voltage transient suppression diode of the present invention introduces a low-voltage triode NPN composed of an N++ single crystal 101, a P-region 102a, and Nb+ buried regions 103a and 103b to obtain a low breakdown voltage. By controlling the effective thickness T of the P-region 102a between the N++ single crystal 101 and the Nb+ buried regions 103a and 103b, a low-value BVCEO of the punch-through triode structure can be obtained. When T is in the range of 0.3-0.5μm, the BVCEO of the NPN triode is 3.0-5.0V. At the same time, due to the low concentration of the P-region 102a, the leakage current is effectively reduced. The product parameters that can be obtained by the structure of the present invention can be: VRWM=3.3V, VBR(IT=1mA)=4.0~5.0V, IR(VR=3.3V)≤0.1μA, IPP(tp=8 / 20us)≥4A, Cj(f=1MHz, VR=0V)=0.4~0.7pF, VESD(Contact Mode)≥20kV.

[0058] Finally, it should be noted that: technicians in this industry should understand that the present invention is not limited to the above-mentioned implementation cases. The above-mentioned embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which shall fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A unidirectional low voltage transient suppression diode, characterized in that: The invention comprises an N++ single crystal wafer (101), an epitaxial P-region (102) and a P-region (104) sequentially formed on the surface of the N++ single crystal wafer (101), Nb+ buried layer regions (103a) and (103b) formed in the epitaxial P-region (102), an N+ region (106) and a P+ region (107) arranged in the P-region (104), dielectric layers (108a), (108b) and (108c) arranged above the P-region (104), a first metal layer (109) arranged above the dielectric layer, and a second metal layer (110) arranged below the N++ single crystal wafer (101). ) and deep trenches (105a), (105b), (105c), wherein the deep trenches (105a), (105b), (105c) extend downward from the dielectric layer (108a), (108b), (108c) to the N++ single crystal (101), wherein the Nb+ buried layer regions (103a), (103b) are formed in a partial region of the epitaxial P-region (102) close to the deep trenches and are located below the N+ region (106), the deep trenches (105a), (105b), (105c) are 20-25μm deep, 1-3μm wide, and the spacing between the trenches is 2-4μm.

2. A method for preparing a unidirectional low-voltage transient suppression diode, characterized in that: The following steps are involved: Step 01, preparing an N++ single crystal wafer (101), and epitaxially growing a P-region (102); Step 02, growing a sacrificial oxide layer, photolithography of a Nb+ buried layer pattern on the front side, implanting arsenic on the front side, and advancing to form Nb+ buried layer regions (103a) and (103b); Step 03, epitaxially growing a P-- region (104); Step 04, photolithography of the N+ region (106) pattern on the front side, phosphorus implantation on the front side, and advancement to form the N+ region (106); Step 05, photolithography of the P+ region (107) pattern on the front side, front boron implantation, advancement, forming the P+ region (107); Step 06, photolithography of deep groove patterns on the front side, trenching on the front side, and filling with TEOS to form deep grooves (105a), (105b), and (105c); Step 07, deposit dielectric layers (108a), (108b), (108c), perform front contact hole photolithography to form contact holes, evaporate metal on the front side, perform front metal photolithography, alloy, and form metal regions (109); Step 08: Thinning the back side and evaporating metal on the back side to form a metal area (110).

3. The preparation method according to claim 2, characterized in that: The crystal orientation of the N++ single crystal wafer (101) in step 01 is <100> The impurity is arsenic, the resistivity is 0.002~0.006Ω·cm, the resistivity of the P-region (102) is 1~10Ω·cm, and the thickness is 5~10μm.

4. The preparation method according to claim 2, characterized in that: The thickness of the sacrificial oxide layer (121) in step 02 is 600-1000Å, and the dose of arsenic implanted on the front side is 5E15-1E16cm -2 The energy is 60~180keV, the temperature condition of arsenic advancement is 1050~1150℃, and the time is 60~180min to form Nb+ buried layer regions (103a) and (103b).

5. The preparation method according to claim 2, characterized in that: The resistivity of the P-- region (104) in step 03 is 100-300Ω·cm, and the thickness is 10-15μm.

6. The preparation method according to claim 2, characterized in that: The phosphorus implantation dosage in step 04 is 2E15~5E15cm -2 The energy is 40~100keV, the temperature condition of phosphorus advancement is 1000~1100℃, and the time is 60~180min to form an N+ region (106).

7. The preparation method according to claim 2, characterized in that: The boron implantation dose in step 05 is 4E15~8E15cm -2 , the energy is 40~120KeV, the temperature condition of boron advancement is 900~1050℃, the time is 30~120min, and a P+ region (107) is formed.

8. The preparation method according to claim 2, characterized in that: The deep grooves in step 06 have a depth of 20-25 μm, a width of 1-3 μm, and a spacing between grooves of 2-4 μm.

9. The preparation method according to claim 2, characterized in that: The dielectric layers (108a), (108b), and (108c) in step 07 are tetraethoxysilane TEOS with a thickness of 5000~10000Å. The metal evaporated on the front side is aluminum or aluminum copper or aluminum silicon copper with a thickness of 2~5μm. The temperature of the alloy is 360~430℃ and the time is 25~45min.

10. The preparation method according to claim 2, characterized in that: The back surface in step 08 is thinned to a thickness of 150-200 μm, and the evaporated metal on the back surface is Ti / Ni / Ag with a thickness of 0.1-0.3 μm or 0.2-0.5 μm or 1.0-1.5 μm.

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