Micro LED chip and preparation method thereof

Abstract

The invention provides a Micro-LED (Light Emitting Diode) chip and a preparation method thereof. The method for preparing the Micro-LED chip comprises the following steps: forming a buffer layer on the surface of a substrate; forming a blue light pixel column, a green light pixel column and a red light pixel column on one side of the buffer layer, wherein the method for forming the pixel columns comprises the following steps: epitaxially growing a plurality of first n-type doped GaN layers which are arranged at intervals on one side of the buffer layer; growing a first barrier layer on the surface of the first n-type doped GaN layer; growing a quantum well structure layer on the surface of the first barrier layer; sequentially growing a blue light quantum well light-emitting layer, a green light quantum well light-emitting layer and a red light quantum well light-emitting layer on the surface of the quantum well structure layer; etching and removing the red light quantum well light-emitting layer and the green light quantum well light-emitting layer used for forming the blue light pixel column; and etching and removing the red light quantum well light-emitting layer used for forming the green light pixel column. Through epitaxial growth of the RGB Micro LED pixel columns, on one hand, monolithic integration can be realized, full color can be realized, and on the other hand, the luminescence performance of the chip can be improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and more specifically, to a Micro LED chip and a method for preparing the same. Background Art

[0002] Compared with LCD and OLED, micro-LED uses self-luminous mechanism, has great advantages in inherent brightness and device stability, and is a strong competitor for AR technology. However, the electro-optical conversion efficiency of red light Micro-LED based on AlGaInP material decreases significantly when it is small (<10μm), which limits the development of full-color Micro-LED display technology.

[0003] In the process of making red light Micro-LED arrays, due to the high surface recombination velocity and long minority carrier diffusion length of the AlGaInP material system, small-size etching and cutting will lead to serious carrier leakage and cause the quantum efficiency to drop by more than 90% at the expected Micro-LED size; secondly, when integrating the three primary color tube cores in the Micro-LED full-color display, due to the different material systems, the current mainstream blue and green light InGaN-based Micro-LED chips and AlGaInP red light cannot be directly integrated, resulting in a complex circuit structure, a significantly reduced transfer yield, and a large amount of additional costs. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, one object of the present invention is to propose a method for preparing a Micro-LED chip, which can achieve monolithic integration and full colorization, or can reduce the damage to the side wall of the pixel column caused by etching during the chip preparation process to a certain extent.

[0005] In one aspect of the present invention, the present invention provides a method for preparing a Micro-LED chip. According to an embodiment of the present invention, the method for preparing a Micro-LED chip includes: providing a substrate; forming a buffer layer on the surface of the substrate; forming a plurality of spaced pixel columns on the side of the buffer layer away from the substrate, the pixel columns including blue light pixel columns, green light pixel columns and red light pixel columns, and the method for forming the pixel columns includes: epitaxially growing a plurality of spaced first n-type doped GaN layers on the side of the buffer layer away from the substrate; growing a first barrier layer on the surface of the first n-type doped GaN layer away from the substrate; growing a quantum well structure layer on the surface of the first barrier layer away from the substrate; sequentially growing a blue light quantum well light-emitting layer, a green light quantum well light-emitting layer and a red light quantum well light-emitting layer on the surface of the quantum well structure layer away from the substrate to obtain the red light pixel column; etching and removing the red light quantum well light-emitting layer and the green light quantum well light-emitting layer used to form the blue light pixel column to obtain the blue light pixel column; etching and removing the red light quantum well light-emitting layer used to form the green light pixel column to obtain the green light pixel column. Therefore, by epitaxially growing RGB Micro LED pixel columns, on the one hand, monolithic integration can be achieved and full colorization can be realized. On the other hand, the damage to the side walls of the pixel columns caused by etching during the chip preparation process can be reduced to a certain extent, thereby improving the luminescence performance of the chip.

[0006] According to an embodiment of the present invention, the method for preparing a Micro-LED chip also includes: depositing a first isolation layer in the gap between the blue light pixel column, the green light pixel column and the red light pixel column, and the first isolation layer covers the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column; etching and removing the first isolation layer corresponding to the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column to expose the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column; growing a protective layer, an electron blocking layer and a first partial hole injection layer on the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column, so that the first partial hole injection layer is flush with the surface of the first isolation layer away from the substrate; growing a second partial hole injection layer on the surfaces of the first partial hole injection layer and the first isolation layer away from the substrate; and depositing an ohmic contact layer on the surface of the second partial hole injection layer away from the substrate.

[0007] According to an embodiment of the present invention, the method for preparing a Micro-LED chip also includes: S1: growing a first undoped GaN layer on the surface of the buffer layer away from the substrate, the thickness of the first undoped GaN layer is 0.5 to 1 μm; S2: forming a first inorganic layer on the surface of the first undoped GaN layer away from the substrate, the first inorganic layer having a plurality of openings arranged at intervals, and the thickness of the first inorganic layer is 10 to 30 nm; S3: growing a second undoped GaN layer on the surface of the first undoped GaN layer not covered by the first inorganic layer, and the second undoped GaN layer covers the surface of the first inorganic layer, and the thickness of the second undoped GaN layer is 0.5 to 1 μm; S4: repeating steps S2 and S3 until the total thickness of the undoped GaN layer is 3.5 to 4 μm, wherein the orthographic projection of the pixel column on the substrate is located within the orthographic projection of the first inorganic layer on the substrate.

[0008] According to an embodiment of the present invention, the method for preparing a Micro-LED chip also includes: etching a first groove and a second groove on the surface of the undoped GaN layer, the orthographic projection of the first groove on the substrate overlaps with the orthographic projection of the green light pixel column on the substrate, the orthographic projection of the second groove on the substrate overlaps with the orthographic projection of the red light pixel column on the substrate, and the depth of the second groove is greater than the depth of the first groove; depositing a second inorganic layer on the surface of the undoped GaN layer away from the substrate, and the second inorganic layer has a first through hole, a second through hole and a third through hole that penetrate the second inorganic layer, the first through hole exposes the first groove, the second through hole exposes the second groove, and the third through hole exposes a predetermined area of ​​the undoped GaN layer, wherein the orthographic projection of the predetermined area on the substrate overlaps with the orthographic projection of the blue light pixel column on the substrate, wherein the blue light pixel column is arranged in the third through hole, the green light pixel column is arranged in the first through hole, and the red light pixel column is arranged in the second through hole.

[0009] According to an embodiment of the present invention, the depth of the first groove is 28 to 145 nm, the depth of the second groove is 50 to 300 nm, and optionally, the thickness of the second inorganic layer is 100 to 300 nm.

[0010] According to an embodiment of the present invention, the step of growing the first n-type doped GaN layer comprises sequentially growing an n-type heavily doped GaN layer and an n-type lightly doped GaN layer, wherein the doping concentration of the n-type heavily doped GaN layer is 5×10 18 ~1×10 19 cm -3The thickness of the n-type heavily doped GaN layer is 1.5 to 2.5 μm, and the doping concentration of the n-type lightly doped GaN layer is 3×10 17 ~6×10 17 cm -3 The thickness of the n-type lightly doped GaN layer is 0.3-0.5 μm; the first barrier layer is non-doped GaN, and the thickness of the first barrier layer is 20-60 nm; the step of growing the quantum well structure layer includes sequentially growing the first quantum well structure layer and the second quantum well structure layer, and the first quantum well structure layer includes a stacked In x Ga 1-x N potential well layer and GaN barrier layer, x is 0.01 to 0.03, the In x Ga 1-x The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the GaN barrier layer is 5 to 15 nm; the second quantum well structure layer includes a stacked In y Ga 1-y N potential well layer and the second n-type doped GaN barrier layer, y is 0.03 to 0.05, the In y Ga 1-y The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 .

[0011] According to an embodiment of the present invention, the blue light quantum well light emitting layer comprises a first non-doped GaN film layer, an In a Ga 1-a N potential well layer, second non-doped GaN film layer and In b Ga 1-b N barrier layer, wherein a is 0.18-0.21, b is 0.01-0.05; the green light quantum well light-emitting layer comprises a third non-doped GaN film layer, In c Ga 1-c N potential well layer, a fourth non-doped GaN film layer and a first n-type doped GaN barrier layer, a fifth non-doped GaN film layer, In d Ga 1-d N potential well layer, a sixth non-doped GaN film layer and a second n-type doped GaN barrier layer, wherein c is 0.24-0.25, and d is 0.25-0.28; the red light quantum well light-emitting layer includes a seventh non-doped GaN film layer, an In layer, and a second n-type doped GaN barrier layer. e Ga 1-e N potential well layer, eighth non-doped GaN film layer, p-type doped GaN barrier layer and Alh Ga 1-h N layer, wherein e is 0.35 to 0.38 and h is 0.10 to 0.30.

[0012] According to an embodiment of the present invention, the blue light quantum well light emitting layer, the green light quantum well light emitting layer and the red light quantum well light emitting layer further satisfy at least one of the following conditions: the thickness of the first non-doped GaN film layer to the eighth non-doped GaN film layer is 2 to 8 nm respectively; a Ga 1-a The thickness of the N potential well layer is 2.5 to 3.5 nm. b Ga 1-b The thickness of the N barrier layer is 5 to 15 nm; c Ga 1-c The thickness of the N-type doped GaN barrier layer is 2.5 to 3.5 nm, the thickness of the first n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the first n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 , the In d Ga 1-d The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 ; The In e Ga 1-e The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the p-type doped GaN barrier layer is 5 to 15 nm, and the thickness of the Al h Ga 1-h The thickness of the N layer is 1 to 2 nm.

[0013] According to an embodiment of the present invention, the total thickness of the protective layer, the electron blocking layer and the first portion of the hole injection layer is 120-180 nm.

[0014] According to an embodiment of the present invention, the substrate is a sapphire substrate, and the buffer layer is an aluminum nitride layer; or, the substrate is a silicon substrate, and the buffer layer is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in a direction away from the substrate; or, the substrate is an n-type doped silicon carbide substrate, and the buffer layer is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in a direction away from the substrate.

[0015] According to an embodiment of the present invention, the substrate is an n-type doped silicon carbide substrate, the buffer layer is an n-type doped aluminum gallium nitride layer, and the pixel column is directly formed on the surface of the buffer layer away from the substrate; or, the substrate is an n-type doped gallium nitride substrate, the buffer layer is an aluminum nitride layer, and the pixel column is directly formed on the surface of the buffer layer away from the substrate.

[0016] According to an embodiment of the present invention, the method for preparing a Micro-LED chip also includes: depositing a first conductive film layer, a reflector, and a binding metal layer in sequence on the surface of the ohmic contact layer away from the substrate; binding a pixel driving circuit on the surface of the binding metal layer away from the substrate; peeling off the substrate; etching the layer structure between the pixel column and the substrate and a portion of the n-type heavily doped GaN layer in the pixel column using an etching method until the surface of the blue light pixel column away from the first conductive film layer, the surface of the green light pixel column away from the first conductive film layer, and the surface of the red light pixel column away from the first conductive film layer are located in the same plane; removing the first isolation layer between the blue light pixel column, the green light pixel column, and the red light pixel column ; forming a sidewall passivation layer and a reflective film layer in sequence on the surface of the pixel column; etching and removing parts of the sidewall passivation layer, the reflective film layer, the second part of the hole injection layer, the ohmic contact layer and the first conductive film layer between different pixel columns to form an isolation groove; depositing a second isolation layer in the isolation groove; removing at least part of the sidewall passivation layer and the reflective film layer on the table of the pixel column to expose the surface of the n-type heavily doped GaN layer; forming a second conductive film layer on the table of the pixel column, on the sidewall of the reflective film layer and on the surface of the second isolation layer; depositing a third isolation layer on the sidewall and bottom wall of the second conductive film layer; forming a high-reflection electrode in the third isolation layer, and the high-reflection electrode is arranged in contact with the second conductive film layer.

[0017] In another aspect of the present invention, the present invention provides a Micro LED chip. According to an embodiment of the present invention, the Micro LED chip is prepared using the method described above. As a result, the Micro LED chip can better achieve monolithic integration, achieve full color, and further improve the luminous performance of the chip. Those skilled in the art can understand that the Micro LED chip has all the features and advantages of the method for preparing the Micro LED chip described above, and no further elaboration is given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0019] Figure 1 is a flow chart of a partial structure of preparing a Micro-LED chip in one embodiment of the present invention;

[0020] Figure 2 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention;

[0021] Figure 3 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention;

[0022] Figure 4 is a structural diagram of a blue light quantum well light-emitting layer in another embodiment of the present invention;

[0023] Figure 5 is a structural diagram of a green light quantum well light-emitting layer in another embodiment of the present invention;

[0024] Figure 6 is a structural diagram of a red light quantum well light-emitting layer in another embodiment of the present invention;

[0025] Figure 7 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention;

[0026] Figure 8 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention;

[0027] Fig. 9 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention;

[0028] Fig.10 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention;

[0029] Fig.11 This is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention. DETAILED DESCRIPTION

[0030] The scheme of the present invention will be explained below in conjunction with embodiments. It will be appreciated by those skilled in the art that the following embodiments are only used to illustrate the present invention and should not be considered as limiting the scope of the present invention. Where specific techniques or conditions are not indicated in the embodiments, the techniques or conditions described in the literature in this area or the product specifications are followed. The present invention will be described below with reference to specific embodiments, it should be noted that these embodiments are merely illustrative and do not limit the present invention in any way.

[0031] In one aspect of the present invention, the present invention provides a method for preparing a Micro-LED chip. According to an embodiment of the present invention, referring to Figures 1 to 11 , the method for preparing a Micro-LED chip includes:

[0032] S100 : providing a substrate 10 .

[0033] Among them, the specific type of the substrate can be a sapphire substrate, a silicon substrate, an n-type doped silicon carbide substrate or an n-type doped gallium nitride substrate. Those skilled in the art can flexibly select a suitable substrate type according to the specific structural type of the Micro-LED chip.

[0034] S200: forming a buffer layer 20 on the surface of the substrate 10. The buffer layer may be deposited by physical vapor deposition (PVD), and the thickness of the buffer layer is 10-100 nm.

[0035] Among them, those skilled in the art can select a suitable buffer layer structure according to the specific type of substrate. In some embodiments, the substrate 10 is a sapphire substrate, and the buffer layer 20 is an aluminum nitride layer with a thickness of 10 to 100 nm; in other embodiments, the substrate 10 is a silicon substrate, and the buffer layer 20 is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in the direction away from the substrate 10; in other embodiments, the substrate 10 is an n-type doped silicon carbide substrate, and the buffer layer 20 is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in the direction away from the substrate 10; in other embodiments, the substrate 10 is an n-type doped silicon carbide substrate, and the buffer layer 20 is an n-type doped aluminum gallium nitride layer; in some other embodiments, the substrate is an n-type doped gallium nitride substrate, and the n-GaN layer is directly grown.

[0036] According to some embodiments of the present invention, when the substrate 10 is an n-type doped silicon carbide substrate and the buffer layer 20 is an n-type doped aluminum gallium nitride layer (vertical structure epitaxial wafer (Epi-Wafer)), and when the substrate is an n-type doped gallium nitride substrate and the buffer layer is an aluminum nitride layer, subsequent pixel columns can be directly formed on the surface of the buffer layer.

[0037] According to other embodiments of the present invention, when the substrate 10 is a sapphire substrate, the buffer layer 20 is an aluminum nitride layer, when the substrate 10 is a silicon substrate, the buffer layer 20 is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in the direction away from the substrate 10, and when the substrate 10 is an n-type doped silicon carbide substrate, the buffer layer 20 is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in the direction away from the substrate 10 (epi-wafer with a horizontal structure), refer to Figure 1, the method for preparing a Micro-LED chip further includes:

[0038] S1: A first non-doped GaN layer 31 is grown on the surface of the buffer layer 10 away from the substrate 10, and the thickness of the first non-doped GaN layer 31 is 0.5-1 μm (e.g., 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm). Specifically, the first non-doped GaN layer 31 can be epitaxially grown using a MOCVD (Metal Organic Chemical Vapor Deposition) device, which is a high-purity chemical vapor deposition technology used to prepare semiconductor materials and devices.

[0039] S2: forming a first inorganic layer 32 on a surface of the first undoped GaN layer 31 away from the substrate 10, wherein the first inorganic layer 32 has a plurality of openings 322 arranged at intervals, and the thickness of the first inorganic layer 32 is 10 to 30 nm (e.g., 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 23 nm, 25 nm, 28 nm, 30 nm), such as Figure 1 (a) and (b) in the figure. By depositing the first inorganic layer 32, the dislocation density in the first non-doped GaN layer 31 can be reduced. The first inorganic layer 32 can be formed by the following method: using PECVD (Plasma Enhanced Chemical Vapor Deposition) to deposit an inorganic film layer 321, and then etching the inorganic film layer into a first inorganic layer 32 with a strip structure or a mesh structure through processes such as coating photoresist, exposure, development, etching, degumming and cleaning. The size and shape of the openings of the first inorganic layer 32 need to be set according to the size and shape of the pixel. In addition, the first inorganic layer of the above thickness can effectively reduce the dislocation density in the first non-doped GaN layer 31, and will not make the thickness of the first inorganic layer too thick, resulting in a waste of material. The material of the first inorganic layer can be silicon nitride or silicon oxide, etc.

[0040] S3: growing a second non-doped GaN layer 33 on the surface of the first non-doped GaN layer 31 not covered by the first inorganic layer 32, and the second non-doped GaN layer 33 covers the surface of the first inorganic layer 32, such as Figure 1In (c), the thickness of the second non-doped GaN layer 33 is 0.5 to 1 μm (e.g., 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm). Specifically, the second non-doped GaN layer 33 can be grown epitaxially using MOCVD equipment. Since non-doped GaN material cannot grow directly on the surface of the inorganic layer, the surface of the first non-doped GaN layer 31 exposed by the first inorganic layer continues to nucleate, and non-doped GaN is gradually grown epitaxially laterally after the thickness exceeds 10 to 30 nm. At this time, the first inorganic layer 32 can act as a good mask to prevent further extension of dislocations.

[0041] S4: Repeat steps S2 and S3 at least once until the total thickness of the undoped GaN layer (including the first undoped GaN layer 31, the second undoped GaN layer 33, and the second undoped GaN layer 33 repeatedly grown in step S4) is 3.5-4 μm, wherein the orthographic projection of the pixel column prepared subsequently on the substrate is within the orthographic projection of the first inorganic layer 32 on the substrate, such as Figure 1 Through the above steps, the first inorganic layer 32 is formed multiple times, which can effectively reduce the further extension of dislocations in the non-doped GaN layer corresponding to the pixel column, so that the penetration dislocation density in this area is low, that is, the non-radiative recombination center is reduced, which is conducive to obtaining a high-performance Micro LED pixel array and improving the luminescence performance of the Micro LED chip to a certain extent.

[0042] Further, such as Figure 1 As shown, the orthographic projections of different first inorganic layers 32 on the substrate are substantially overlapped, so that in steps S1 to S4, the same mask can be used when preparing different first inorganic layers 32, saving the number of masks and reducing the preparation cost. Among them, the first inorganic layers of different layers can be the same or different, as long as they are between 10 and 30 nm.

[0043] According to an embodiment of the present invention, in order to better grow pixel columns later, refer to Figure 2 , the method for preparing a Micro-LED chip further includes:

[0044] S5: Etching a first groove 331 and a second groove 332 on the surface of the undoped GaN layer (i.e., the top second undoped GaN layer 33 in step S4), the orthographic projection of the first groove 331 on the substrate 10 overlaps with the orthographic projection of the green light pixel column on the substrate, the orthographic projection of the second groove 332 on the substrate 10 overlaps with the orthographic projection of the red light pixel column on the substrate, and the depth of the second groove 332 is greater than the depth of the first groove 331.

[0045] Among them, another mask plate can be used to etch the first groove 331 and the second groove 332 by applying photoresist, exposing, developing, etching, degumming, cleaning and other processes. In addition, the depth of the first groove is 28-145nm (for example, 28nm, 35nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 145nm), and the depth of the second groove is 50-300nm (for example, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 150nm, 180nm, 200nm, 230nm, 250nm, 280nm, 300nm).

[0046] S6: depositing a second inorganic layer 34 on the surface of the non-doped GaN layer away from the substrate 10, and the second inorganic layer 34 has a first through hole 341, a second through hole 342 and a third through hole 343 penetrating the second inorganic layer 34, the first through hole 341 exposes the first groove 331, the second through hole 342 exposes the second groove 332, and the third through hole 343 exposes a predetermined area of ​​the non-doped GaN layer (i.e., the uppermost second non-doped GaN layer 33 in step S4), wherein the orthographic projection of the predetermined area on the substrate 10 overlaps with the orthographic projection of the blue light pixel column on the substrate, wherein the blue light pixel column is arranged in the third through hole 343, the green light pixel column is arranged in the first through hole 341, and the red light pixel column is arranged in the second through hole 342, i.e., the first through hole 341, the second through hole 342 and the third through hole 343 expose the growth surfaces of the green light pixel column, the red light pixel column and the blue light pixel column respectively. The thickness of the second inorganic layer 34 is 100-300 nm, such as 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm. The material of the second inorganic layer may be silicon nitride or silicon oxide.

[0047] In some examples, the method for forming the second inorganic layer 34 can be: depositing an inorganic thin film on the surface of the non-doped GaN layer away from the substrate 10 and in the first groove and the second groove, and then using another mask to etch through exposure, development, etching, degumming, cleaning and other processes to obtain a patterned second inorganic layer 34.

[0048] S300: Reference Figure 3 , a plurality of pixel columns ( Figure 3 In the predetermined area, the first groove and the second groove, a blue pixel column, a green pixel column and a red pixel column are respectively grown, the pixel column includes a blue pixel column B, a green pixel column G and a red pixel column R, and the method for forming the pixel column includes:

[0049] S310: epitaxially grow a plurality of first n-type doped GaN layers 41 ( Figure 3 In the process of growing a plurality of first n-type doped GaN layers 41) spaced apart on the surface of the non-doped GaN layer exposed in the predetermined area, the first groove and the second groove, referring to Figure 3 .

[0050] In some examples, the step of growing the first n-type doped GaN layer 41 includes sequentially growing an n-type heavily doped GaN layer 411 and an n-type lightly doped GaN layer 412, wherein the n-type heavily doped GaN layer 411 can be grown by a vapor phase epitaxial growth technique (MOCVD), the growth temperature is 1040° C. to 1060° C., SiH4 is used as an n-type dopant, and the doping concentration of the n-type heavily doped GaN layer 411 is 5×10 18 ~1×10 19 cm -3 The thickness of the n-type heavily doped GaN layer 411 is 1.5 to 2.5 μm; the n-type lightly doped GaN layer 412 can be grown by vapor phase epitaxial growth technology (MOCVD) at a growth temperature of 1040°C to 1060°C, SiH4 is used as an n-type dopant, and the doping concentration of the n-type lightly doped GaN layer 412 is 3×10 17 ~6×10 17 cm -3 The thickness of the n-type lightly doped GaN layer 412 is 0.3-0.5 μm.

[0051] S320: growing a first barrier layer 42 on the surface of the first n-type doped GaN layer 41 away from the substrate, Figure 3 The thickness of the first barrier layer 42 is 20-60 nm, and the material of the first barrier layer 42 is non-doped GaN.

[0052] S330: growing a quantum well structure layer 43 on the surface of the first barrier layer 42 away from the substrate 10, refer to Figure 3 .

[0053] In some embodiments of the present invention, the step of growing the quantum well structure layer 43 includes sequentially growing a first quantum well structure layer 431 and a second quantum well structure layer 432, wherein the first quantum well structure layer 431 grows 3 to 5 cycles, and the first quantum well structure layer 431 includes a stacked arrangement In x Ga 1-x N potential well layer and GaN barrier layer, x is 0.01 to 0.03, that is, In x Ga 1-x The In content in the N potential well layer is 1% to 3%. x Ga1-x The N potential well layer is disposed close to the first barrier layer (First barrier) 42, and the GaN potential well layer is disposed away from the first barrier layer (First barrier) 42. x Ga 1-x The thickness of the N potential well layer is 2.5 to 3.5 nm, and the thickness of the GaN barrier layer is 5 to 15 nm; the second quantum well structure layer includes a stacked In y Ga 1-y N potential well layer and the second n-type doped GaN barrier layer, y is 0.03-0.05, that is, In y Ga 1-y The In content of N is 3% to 5%. y Ga 1-y The N potential well layer is disposed close to the first barrier layer (First barrier) 42, and the second n-type doped GaN barrier layer is disposed away from the first barrier layer (First barrier) 42. y Ga 1-y The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 .

[0054] In the process of growing the first quantum well structure layer 431, x Ga 1-x A non-doped GaN layer is pre-grown before the N potential well layer, and a non-doped GaN layer is pre-grown before the GaN layer is grown. The thickness of these two non-doped GaN layers is 1 to 5 microns, and the growth temperature is the same as that of the growth In x Ga 1-x The temperature of the N potential well layer is the same, both at 1040~1060℃.

[0055] S340: A blue light quantum well light emitting layer 44, a green light quantum well light emitting layer 45 and a red light quantum well light emitting layer 46 are sequentially grown on the surface of the quantum well structure layer 43 away from the substrate 10 to obtain a red light pixel column R, referring to Figure 3 (a) in which the blue light quantum well light emitting layer has a light emission wavelength of 455 to 465 nm, the green light quantum well light emitting layer has a light emission wavelength of 520 to 535 nm, and the red light quantum well light emitting layer has a light emission wavelength of 620 to 635 nm.

[0056] According to an embodiment of the present invention, since the subsequent steps S350 and S360 enter the etching stage (hydrogen atmosphere), the blue light quantum well light-emitting layer 44, the green light quantum well light-emitting layer 45 and the red light quantum well light-emitting layer 46 formed in step S340 are formed in a nitrogen atmosphere. Because there is a more serious etching phenomenon when the nitrogen film-forming atmosphere is switched to a hydrogen atmosphere, a 30-60 nm thick protective layer (whose material can be non-doped GaN) can be pre-formed before the product obtained in step S340 is removed from the nitrogen atmosphere to prevent the formed blue light quantum well light-emitting layer 44, the green light quantum well light-emitting layer 45 and the red light quantum well light-emitting layer 46 from being damaged.

[0057] S350: etching and removing the red light quantum well light emitting layer 46 and the green light quantum well light emitting layer 45 used to form the blue light pixel column B to obtain the blue light pixel column B. Figure 3 (b) in .

[0058] S360: Etching and removing the red light quantum well light emitting layer 46 used to form the green light pixel column G to obtain the green light pixel column G. Figure 3 (c) in .

[0059] In some embodiments of the present invention, reference Figure 4 The blue light quantum well light emitting layer 44 includes a first non-doped GaN film layer 441, an In a Ga 1-a N potential well layer 442, second non-doped GaN film layer 443 and In b Ga 1-b N barrier layer 444, where a is 0.18-0.21, b is 0.01-0.05, i.e., In a Ga 1-a The composition of In in the N potential well layer 4812 is 18% to 21%. b Ga 1- b The In content of the N barrier layer 4814 is 1% to 5%. Among them, the blue light quantum well light emitting layer 44 contains a relatively high amount of In. a Ga 1-a Growing a first non-doped GaN film layer 441 before the N potential well layer 442 can effectively improve the surface flatness of the film layer and increase the In a Ga 1-a The growth quality of the N potential well layer 442 is beneficial to the improvement of the device's luminous brightness; b Ga 1-b A second non-doped GaN film layer 443 is grown before the N barrier layer 444 to prevent In a Ga 1-aThe precipitation of In in the N potential well layer is beneficial to the improvement of the device's luminous brightness. The thickness of the first non-doped GaN film layer 441 and the second non-doped GaN film layer 443 are 1 to 8 nm respectively, and the growth temperature of the first non-doped GaN film layer 441 is related to the growth temperature of In. a Ga 1-a The growth temperature of the N potential well layer 442 is the same as that of the second non-doped GaN film layer 443. b Ga 1-b The growth temperature of the N barrier layer 444 is the same, which can effectively alleviate the problem of wave shift under large current injection; a Ga 1-a The thickness of the N potential well layer is 2.5 to 3.5 nm, and In b Ga 1-b The thickness of the N barrier layer is 5-15 nm, thus ensuring good luminescence properties of the blue light quantum well light emitting layer 44.

[0060] In some embodiments of the present invention, reference Figure 5 The green light quantum well light emitting layer 45 includes a third non-doped GaN film layer 451, In c Ga 1-c N potential well layer 452, fourth non-doped GaN film layer 453 and first n-type doped GaN barrier layer 454, fifth non-doped GaN film layer 455, In d Ga 1-d N potential well layer 456, sixth non-doped GaN film layer 457 and second n-type doped GaN barrier layer 458, wherein c is 0.24-0.25, d is 0.25-0.28, that is, In c Ga 1-c The composition of In in the N452 potential well layer is 24% to 25%. d Ga 1-d The In content of the N potential well layer 456 is 25% to 28%. Among them, the green light quantum well light emitting layer 45 contains a relatively high amount of In. c Ga 1-c Growing a third non-doped GaN film layer 451 before the N potential well layer 452 can effectively improve the surface flatness of the film layer and increase the In c Ga 1-c The growth quality of the N potential well layer 452 is beneficial to the improvement of the luminous brightness of the device; before growing the first n-type doped GaN barrier layer 454, a fourth non-doped GaN film layer 453 is grown to prevent In c Ga 1-c The precipitation of In in the N potential well layer is beneficial to the improvement of the device's luminescence brightness; d Ga 1-dGrowing a fifth non-doped GaN film layer 455 before the N potential well layer 456 can effectively improve the surface flatness of the film layer and increase the In d Ga 1-d The growth quality of the N potential well layer 456 is beneficial to the improvement of the luminous brightness of the device; before growing the second n-type doped GaN barrier layer 458, a sixth non-doped GaN film layer 457 is grown to prevent In d Ga 1-d The precipitation of In in the N potential well layer 456 is beneficial to improving the luminance of the device.

[0061] The thicknesses of the third to sixth non-doped GaN film layers are 2 to 8 nm respectively, and the growth temperature of the third non-doped GaN film layer 451 is about 100 nm. c Ga 1-c The growth temperature of the fourth non-doped GaN film layer 453 is the same as the growth temperature of the first n-type doped GaN barrier layer 454, and the growth temperature of the fifth non-doped GaN film layer 455 is the same as the growth temperature of the In d Ga 1-d The growth temperature of the N-type potential well layer 456 is the same, and the growth temperature of the sixth non-doped GaN film layer 457 is the same as the growth temperature of the second n-type doped GaN barrier layer 458, thereby effectively alleviating the problem of wave shift under large current injection. c Ga 1-c The thickness of the N-type well layer is 2.5 to 3.5 nm, the thickness of the first n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the first n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 ,In d Ga 1-d The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 In this way, the green light quantum well light-emitting layer 45 has good light-emitting properties.

[0062] In some embodiments of the present invention, reference Figure 6 The red light quantum well light emitting layer 46 includes a seventh non-doped GaN film layer 461, an In e Ga 1-e N potential well layer 462, eighth non-doped GaN film layer 463, p-type doped GaN barrier layer 464 and Al h Ga 1-hN layer 465, where e is 0.35 to 0.38, h is 0.10 to 0.30, i.e. In e Ga 1-e The composition of In in the N potential well layer 462 is 35% to 38%, and the composition of Al h Ga 1-h The Al content in the N layer 465 is 10% to 30%. The red light quantum well light emitting layer 46 contains a relatively high amount of indium. e Ga 1-e Growing a seventh non-doped GaN film layer 461 before the N potential well layer 462 can effectively improve the surface flatness of the film layer and increase the In e Ga 1-e The growth quality of the N potential well layer 462 is beneficial to the improvement of the luminous brightness of the device; growing an eighth non-doped GaN film layer 463 before growing the p-type doped GaN barrier layer 464 is beneficial to the improvement of the luminous brightness of the device.

[0063] The thickness of the seventh non-doped GaN film layer and the eighth non-doped GaN film layer are 2-8 nm, respectively. e Ga 1-e The thickness of the N-type well layer is 2.5 to 3.5 nm, the thickness of the p-type doped GaN barrier layer is 5 to 15 nm, and the thickness of the Al h Ga 1-h The thickness of the N layer is 1-2 nm, thus ensuring good luminescence characteristics of the red light quantum well light emitting layer 46. In addition, the growth temperature of the seventh non-doped GaN film layer 461 is similar to that of the In e Ga 1-e The growth temperature of the N potential well layer 462 is the same as that of the eighth non-doped GaN film layer 463 and the growth temperature of the p-type doped GaN barrier layer 464, thereby effectively alleviating the problem of wave shift under large current injection.

[0064] According to an embodiment of the present invention, referring to Figure 7 and Figure 8 , the method for preparing a Micro-LED chip further includes:

[0065] S400: Depositing a first isolation layer 51 in the gaps between the blue pixel column B, the green pixel column G, and the red pixel column R, and the first isolation layer 51 covers the surfaces of the blue pixel column B, the green pixel column G, and the red pixel column R. Figure 7 (a) The material of the first isolation layer 51 may be silicon nitride or silicon oxide, which may be prepared by vapor deposition.

[0066] S500: etching and removing the first isolation layer 51 portion corresponding to the surface of the blue pixel column B, the green pixel column G and the red pixel column R, exposing the surface of the blue pixel column B, the green pixel column G and the red pixel column R, such as Figure 7 Specifically, it can be obtained by using a mask plate, exposure, development, etching, degumming, cleaning and the like, wherein the mask plate used in this step can be the same mask plate used in step S6.

[0067] S600: growing a protective layer 52, an electron blocking layer 53 and a first portion of a hole injection layer 54 on the surface of the blue pixel column B, the green pixel column G and the red pixel column R, so that the first portion of the hole injection layer 54 is flush with the surface of the first isolation layer 51 away from the substrate, such as Figure 8 Before growing the protective layer, the product etched in step S500 is cleaned in advance with toluene, acetone, ethanol and deionized water in sequence, and blown dry with nitrogen, and then the protective layer is grown after heating in a nitrogen atmosphere.

[0068] Furthermore, in some embodiments, the total thickness of the protective layer 52, the electron blocking layer 53 and the first portion of the hole injection layer 54 is 120-180 nm, that is, the total thickness of the protective layer 52, the electron blocking layer 53 and the first portion of the hole injection layer 54 is the thickness of the first isolation layer etched away in step S500.

[0069] The thickness of the protective layer 52 is 20-40 nm, and the material of the protective layer is non-doped gallium nitride. The electron blocking layer 53 is formed by growing 4-6 pairs of p-type doped Al m Ga 1-m The hole concentration of the N layer and the first p-type doped GaN layer and the electron blocking layer is 1.5×10 18 ~2×10 18 cm -3 , p-type doped Al m Ga 1-m The thickness of the N layer is 2.5 to 3.5 nm, and the Al component is 20% to 30% (i.e., Al m Ga 1-m m in N is 0.2-0.3), and the thickness of the first p-type doped GaN layer is 5-8 nm.

[0070] S700: growing a second portion of the hole injection layer 55 on the surface of the first portion of the hole injection layer 54 and the first isolation layer 51 away from the substrate 10, such as Figure 8 (b) The hole injection layer (including the first hole injection layer and the second hole injection layer) is formed by growing 8 to 14 pairs of p-type doped Al n Ga 1-nThe hole concentration of the N layer and the second p-type doped GaN layer and the electron blocking layer is 1×10 18 ~2×10 18 cm -3 , p-type doped Al n Ga 1-n The thickness of the N layer is 2.5 to 3.5 nm, and the Al component is 10% to 20% (i.e., Al n Ga 1-n Where n in N is 0.1-0.2), and the thickness of the second p-type doped GaN layer is 5-8 nm.

[0071] S800: An ohmic contact layer 56 is formed by deposition on the surface of the second portion of the hole injection layer 55 away from the substrate 10, such as Figure 8 (b) The ohmic contact layer 56 is a p-type heavily doped GaN layer, and its thickness is 20-40 nm.

[0072] After completing step S800, the product after step S800 may be subjected to annealing treatment in a nitrogen atmosphere to complete the growth of the epitaxial structure.

[0073] According to an embodiment of the present invention, referring to Figures 9 to 11 , the method for preparing a Micro-LED chip further includes:

[0074] S900: On the surface of the ohmic contact layer 56 away from the substrate 10, a first conductive film layer 61, a reflector 62, and a binding metal layer 63 are sequentially deposited. Fig. 9 (a) in .

[0075] In some embodiments, the first conductive film layer 61 with a thickness of 30 to 120 nm may be deposited by electron beam evaporation or Sputter (magnetron sputtering), and may be further combined with a rapid annealing process to improve the transmittance of the first conductive film layer 61 and reduce the resistance of the first conductive film layer 61. The material of the first conductive film layer may be ITO.

[0076] In some embodiments, the reflector 62 with a thickness of 100-300 nm can be deposited by electron beam evaporation or Sputter (magnetron sputtering) to improve the light extraction efficiency of the Micro LED chip. The reflector 62 can be made of silver or aluminum metal.

[0077] In some embodiments, the binding metal layer 63 may be deposited by electron beam evaporation or Sputter (magnetron sputtering), and the material thereof includes but is not limited to at least one of Cr, Pt, Ni, Ti, Ni and Ag.

[0078] S1000: Binding the pixel driving circuit 64 on the surface of the binding metal layer 63 away from the substrate 10, such as Fig. 9(a) in .

[0079] In some embodiments, electron beam evaporation or Sputter (magnetron sputtering) can be used to deposit binding metal (Cr, Pt, Ag, In and other materials) on the pixel driving circuit 64, and then the binding metal layer 64 and the pixel driving circuit 64 are bound by the binding metal.

[0080] S1100: peeling off the substrate 10, such as Fig. 9 (b) in .

[0081] In some embodiments, the substrate is a sapphire substrate, and the substrate 10 can be stripped by a laser lift-off process (LLO), and the laser wavelength is 355nm, 266nm or 248nm. In other embodiments, the substrate is a silicon substrate, and the substrate 10 can be stripped by a wet etching method. In other embodiments, the substrate is an n-type doped silicon carbide substrate, and the substrate 10 can be stripped by a wet etching method or by inductively coupled plasma etching (ICP-RIE). In other embodiments, the substrate is an n-type doped gallium nitride substrate, and the substrate 10 can be stripped by inductively coupled plasma etching (ICP-RIE).

[0082] S1200: Etching the layer structure between the pixel column and the substrate and part of the n-type heavily doped GaN layer 411 in the pixel column by an etching method (ICP-RIE) until the surface of the blue light pixel column B away from the first conductive film layer 61, the surface of the green light pixel column G away from the first conductive film layer, and the surface of the red light pixel column R away from the first conductive film layer are located in the same plane, such as Fig.10 (a) in .

[0083] S1300: removing the first passivation isolation layer 51 between the blue pixel column B, the green pixel column G and the red pixel column R. Fig.10 (b) in .

[0084] In some embodiments, the method for removing the first isolation layer 51 between the blue light pixel column B, the green light pixel column G and the red light pixel column R can be: using HF solution or BOE solution (buffered oxide etching solution) to remove the first isolation layer (SiNx or SiO2 material) between the blue light pixel column B, the green light pixel column G and the red light pixel column R, and then cleaning it with deionized water.

[0085] S1400: forming a sidewall passivation layer 65 and a reflective film layer 66 on the surface of the pixel column in sequence, such as Fig.10 (c) in .

[0086] In some embodiments, before forming the sidewall passivation layer 65, after removing the first isolation layer in step S1300, a PECVD device is used to treat the defects on the sidewall of the pixel column by plasma (including hydrogen, oxygen, ammonia, etc.) before film formation, and then a sidewall passivation layer 65 with a thickness of 60 to 200 nm is deposited. In addition, a reflective film layer 66 can be grown by Sputter (magnetron sputtering) or ALD (atomic layer deposition) to further enhance the light extraction efficiency of the chip, wherein the reflective film layer 66 can be a DBR reflective film layer (distributed Bragg reflector).

[0087] S1500: etching and removing part of the sidewall passivation layer 65, the reflective film layer 66, the second part of the hole injection layer 55, the ohmic contact layer 56 and the first conductive film layer 61 between different pixel columns to form an isolation groove 67, such as Fig.11 (a) in .

[0088] In some embodiments, the isolation groove 67 may be etched by photolithography and ICP-RIE process, and acetone, ethanol and deionized water may be used for degumming and surface cleaning.

[0089] S1600: depositing a second isolation layer 68 in the isolation trench 67, such as Fig.11 (b) in .

[0090] In some embodiments, the second isolation layer 68 may further cover the bottom wall and part of the side wall of the reflective film layer 66 . Specifically, the second isolation layer 68 may be deposited by physical vapor deposition.

[0091] S1700: removing at least part of the sidewall passivation layer 65 and the reflective film layer 66 on the mesa of the pixel column to expose the surface of the n-type heavily doped GaN layer 411, such as Fig.11 (b) in .

[0092] S1800: forming a second conductive film layer 69 on the mesa of the pixel column, the sidewall of the reflective film layer 66 and the surface of the second isolation layer 68, such as Fig.11 (c) in .

[0093] In some embodiments, the second conductive film layer 69 with a thickness of 30 to 120 nm can be deposited by magnetron sputtering and combined with the RTA (rapid annealing) process to improve the transmittance of the second conductive film layer 69 and reduce the material resistance, wherein the second conductive film layer 69 can be an ITO film layer.

[0094] S1900: depositing a third isolation layer 70 on the sidewalls and bottom wall of the second conductive film layer 69, such as Fig.11 (d) in order to achieve electrical insulation between the pixel column mesas.

[0095] S2000: forming a high reflective electrode 71 in the third isolation layer 70, and the high reflective electrode 71 is disposed in contact with the second conductive film layer 69, such as Fig.11 The high reflective electrode 71 can reduce the light crosstalk and light divergence angle between pixels on the one hand, and improve the light extraction efficiency on the other hand.

[0096] In some embodiments, the material of the high reflective electrode 71 may be aluminum or silver.

[0097] According to an embodiment of the present invention, a monolithic integrated RGB Micro LED pixel column is achieved through an epitaxial growth method. On the one hand, monolithic integration can be achieved to realize full colorization. On the other hand, the damage to the side wall of the pixel column caused by etching during the chip preparation process can be reduced to a certain extent, thereby improving the luminescence performance of the chip.

[0098] In another aspect of the present invention, the present invention provides a Micro LED chip. According to an embodiment of the present invention, the Micro LED chip is prepared using the method described above. As a result, the Micro LED chip can better achieve monolithic integration, achieve full color, and further improve the luminous performance of the chip. Those skilled in the art can understand that the Micro LED chip has all the features and advantages of the method for preparing the Micro LED chip described above, and no further elaboration is given here.

[0099] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0100] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0101] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A method for preparing a Micro-LED chip, characterized in that: include: providing a substrate; forming a buffer layer on a surface of the substrate; A plurality of pixel columns are formed at intervals on a side of the buffer layer away from the substrate, the pixel columns comprising a blue pixel column, a green pixel column and a red pixel column, and a method for forming the pixel columns comprises: epitaxially growing a plurality of first n-type doped GaN layers spaced apart on a side of the buffer layer away from the substrate; Growing a first barrier layer on a surface of the first n-type doped GaN layer away from the substrate; growing a quantum well structure layer on a surface of the first barrier layer away from the substrate; On the surface of the quantum well structure layer away from the substrate, a blue light quantum well light emitting layer, a green light quantum well light emitting layer and a red light quantum well light emitting layer are sequentially grown to obtain the red light pixel column; The red light quantum well light emitting layer and the green light quantum well light emitting layer used to form the blue light pixel column are removed by etching to obtain the blue light pixel column; The red light quantum well light-emitting layer used to form the green light pixel column is removed by etching to obtain the green light pixel column.

2. The method according to claim 1, characterized in that Also includes: Depositing a first isolation layer in the gaps between the blue light pixel column, the green light pixel column and the red light pixel column, wherein the first isolation layer covers the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column; The first isolation layer corresponding to the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column is removed by etching to expose the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column; Growing a protective layer, an electron blocking layer and a first portion of a hole injection layer on the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column, so that the first portion of the hole injection layer is flush with the surface of the first isolation layer away from the substrate; growing a second portion of the hole injection layer on the surface of the first portion of the hole injection layer and the first isolation layer away from the substrate; An ohmic contact layer is deposited on a surface of the second portion of the hole injection layer away from the substrate.

3. The method according to claim 1, characterized in that Also includes: S1: growing a first undoped GaN layer on a surface of the buffer layer away from the substrate, wherein the thickness of the first undoped GaN layer is 0.5-1 μm; S2: forming a first inorganic layer on a surface of the first undoped GaN layer away from the substrate, wherein the first inorganic layer has a plurality of openings arranged at intervals, and a thickness of the first inorganic layer is 10 to 30 nm; S3: growing a second undoped GaN layer on the surface of the first undoped GaN layer not covered by the first inorganic layer, and the second undoped GaN layer covers the surface of the first inorganic layer, and the thickness of the second undoped GaN layer is 0.5-1 μm; S4: Repeat steps S2 and S3 until the total thickness of the non-doped GaN layer is 3.5-4 μm, wherein the orthographic projection of the pixel column on the substrate is located within the orthographic projection of the first inorganic layer on the substrate.

4. The method according to claim 3, characterized in that Also includes: Etching a first groove and a second groove on the surface of the non-doped GaN layer, wherein the orthographic projection of the first groove on the substrate overlaps with the orthographic projection of the green pixel column on the substrate, the orthographic projection of the second groove on the substrate overlaps with the orthographic projection of the red pixel column on the substrate, and the depth of the second groove is greater than the depth of the first groove; A second inorganic layer is deposited on a surface of the non-doped GaN layer away from the substrate, and the second inorganic layer has a first through hole, a second through hole, and a third through hole penetrating the second inorganic layer, the first through hole exposes the first groove, the second through hole exposes the second groove, and the third through hole exposes a predetermined area of ​​the non-doped GaN layer, wherein an orthographic projection of the predetermined area on the substrate overlaps with an orthographic projection of the blue light pixel column on the substrate, Wherein, the blue light pixel column is arranged in the third through hole, the green light pixel column is arranged in the first through hole, and the red light pixel column is arranged in the second through hole.

5. The method according to claim 4, characterized in that The depth of the first groove is 28-145 nm, the depth of the second groove is 50-300 nm, Optionally, the thickness of the second inorganic layer is 100-300 nm.

6. The method according to claim 1, characterized in that The step of growing the first n-type doped GaN layer includes sequentially growing an n-type heavily doped GaN layer and an n-type lightly doped GaN layer, wherein the doping concentration of the n-type heavily doped GaN layer is 5×10 18 ~1×10 19 cm -3 The thickness of the n-type heavily doped GaN layer is 1.5 to 2.5 μm, and the doping concentration of the n-type lightly doped GaN layer is 3×10 17 ~6×10 17 cm -3 , the thickness of the n-type lightly doped GaN layer is 0.3 to 0.5 μm; The first barrier layer is non-doped GaN, and the thickness of the first barrier layer is 20-60 nm; The step of growing the quantum well structure layer comprises sequentially growing a first quantum well structure layer and a second quantum well structure layer, wherein the first quantum well structure layer comprises a stacked arrangement of In x Ga 1-x N potential well layer and GaN barrier layer, x is 0.01 to 0.03, the In x Ga 1-x The thickness of the N potential well layer is 2.5 to 3.5 nm, and the thickness of the GaN barrier layer is 5 to 15 nm; The second quantum well structure layer includes a stacked arrangement of In y Ga 1-y N potential well layer and the second n-type doped GaN barrier layer, y is 0.03 to 0.05, the In y Ga 1-y The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 .

7. The method according to claim 1, characterized in that The blue light quantum well light emitting layer includes a first non-doped GaN film layer, an In a Ga 1-a N potential well layer, second non-doped GaN film layer and In b Ga 1-b N barrier layer, wherein a is 0.18 to 0.21, and b is 0.01 to 0.05; The green light quantum well light emitting layer includes a third non-doped GaN film layer, an In c Ga 1-c N potential well layer, a fourth non-doped GaN film layer and a first n-type doped GaN barrier layer, a fifth non-doped GaN film layer, In d Ga 1-d N potential well layer, a sixth non-doped GaN film layer and a second n-type doped GaN barrier layer, wherein c is 0.24 to 0.25, and d is 0.25 to 0.28; The red light quantum well light emitting layer includes a seventh non-doped GaN film layer, an In e Ga 1-e N potential well layer, eighth non-doped GaN film layer, p-type doped GaN barrier layer and Al h Ga 1-h N layer, wherein e is 0.35 to 0.38 and h is 0.10 to 0.

30.

8. The method according to claim 7, characterized in that The blue light quantum well light emitting layer, the green light quantum well light emitting layer and the red light quantum well light emitting layer further satisfy at least one of the following conditions: The thicknesses of the first to eighth undoped GaN film layers are 12 to 8 nm respectively; In a Ga 1-a The thickness of the N potential well layer is 2.5 to 3.5 nm. b Ga 1-b The thickness of the N barrier layer is 5 to 15 nm; In c Ga 1-c The thickness of the N-type doped GaN barrier layer is 2.5 to 3.5 nm, the thickness of the first n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the first n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 , the In d Ga 1-d The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 ; In e Ga 1-e The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the p-type doped GaN barrier layer is 5 to 15 nm, and the thickness of the Al h Ga 1-h The thickness of the N layer is 1 to 2 nm.

9. The method according to claim 2, characterized in that: The total thickness of the protective layer, the electron blocking layer and the first portion of the hole injection layer is 120-180 nm.

10. The method according to claim 3, characterized in that: The substrate is a sapphire substrate, and the buffer layer is an aluminum nitride layer; Alternatively, the substrate is a silicon substrate, the buffer layer is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in a direction away from the substrate; Alternatively, the substrate is an n-type doped silicon carbide substrate, the buffer layer is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in a direction away from the substrate.

11. The method according to claim 1, characterized in that: The substrate is an n-type doped silicon carbide substrate, the buffer layer is an n-type doped aluminum gallium nitride layer, and the pixel column is directly formed on the surface of the buffer layer away from the substrate; Alternatively, the substrate is an n-type doped gallium nitride substrate, the buffer layer is an aluminum nitride layer, and the pixel column is directly formed on a surface of the buffer layer away from the substrate.

12. The method according to claim 2, characterized in that: Also includes: Depositing a first conductive film layer, a reflector, and a binding metal layer in sequence on a surface of the ohmic contact layer away from the substrate; Binding a pixel driving circuit on a surface of the binding metal layer away from the substrate; peeling off the substrate; Etching the layer structure between the pixel column and the substrate and part of the n-type heavily doped GaN layer in the pixel column by an etching method until the surface of the blue light pixel column away from the first conductive film layer, the surface of the green light pixel column away from the first conductive film layer, and the surface of the red light pixel column away from the first conductive film layer are located in the same plane; removing the first isolation layer between the blue light pixel column, the green light pixel column and the red light pixel column; Sequentially forming a sidewall passivation layer and a reflective film layer on the surface of the pixel column; Etching and removing the sidewall passivation layer, the reflective film layer, the second hole injection layer, the ohmic contact layer and the first conductive film layer between different pixel columns to form an isolation groove; Depositing a second isolation layer in the isolation trench; removing at least a portion of the sidewall passivation layer and the reflective film layer on the mesa of the pixel column to expose the surface of the n-type heavily doped GaN layer; forming a second conductive film layer on the mesa of the pixel column, the sidewall of the reflective film layer, and the surface of the second isolation layer; Depositing a third isolation layer on the sidewalls and bottom wall of the second conductive film layer; A high-reflection electrode is formed in the third isolation layer, and the high-reflection electrode is disposed in contact with the second conductive film layer.

13. A Micro LED chip, characterized in that: The invention is prepared by the method according to any one of claims 1 to 12.

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