Semiconductor element

Abstract

The invention discloses a semiconductor element which comprises an epitaxial structure, a first contact electrode and a second contact electrode. The epitaxial structure includes a first semiconductor structure, a second semiconductor structure and an active region. The first semiconductor structure includes a first semiconductor contact layer. The second semiconductor structure includes a second semiconductor contact layer. The active region is between the first semiconductor structure and the second semiconductor structure. The first contact electrode is located on the second semiconductor contact layer and directly contacts the first semiconductor contact layer. The second contact electrode is located on the second semiconductor contact layer and directly contacts the second semiconductor contact layer. The conductive type of the first semiconductor contact layer is n-type, and the first semiconductor contact layer comprises a first III-V semiconductor material. The conductive type of the second semiconductor contact layer is p-type, and the second semiconductor contact layer comprises a second III-V group semiconductor material, and the second III-V group semiconductor material is an indium-containing phosphide.

Description

Technical Field

[0001] The present invention relates to a semiconductor element, in particular to a semiconductor photoelectric element. Background Art

[0002] Nowadays, semiconductor components have been widely used in various fields, and research on semiconductor materials and related products is also ongoing. For example, III-V semiconductor materials (such as) including group III and group V elements can be applied to various semiconductor optoelectronic components, such as semiconductor light-emitting components such as light-emitting diodes, laser diodes (LD), photodetectors or solar cells, etc., or in power components such as switching components or rectifiers. These semiconductor optoelectronic components can be used in lighting, medical treatment, display, communication, sensing, power supply systems and other fields. As one of the semiconductor light-emitting components, the p-type semiconductor structure in the light-emitting diode can provide holes and the n-type semiconductor structure can provide electrons under the action of an external electric field, and the holes and electrons can recombine to emit light. Because light-emitting diodes have the advantages of low power consumption, fast response speed, small size, and long working life, they are widely used. Summary of the invention

[0003] The present invention provides a semiconductor element, including an epitaxial structure, a first contact electrode and a second contact electrode. The epitaxial structure includes a first semiconductor structure, a second semiconductor structure and an active region. The first semiconductor structure includes a first semiconductor contact layer. The second semiconductor structure includes a second semiconductor contact layer. The active region is between the first semiconductor structure and the second semiconductor structure. The first contact electrode is located on the second semiconductor contact layer and directly contacts the first semiconductor contact layer. The second contact electrode is located on the second semiconductor contact layer and directly contacts the second semiconductor contact layer. The conductivity type of the first semiconductor contact layer is n-type and includes a first III-V semiconductor material. The conductivity type of the second semiconductor contact layer is p-type and includes a second III-V semiconductor material, and the second III-V semiconductor material is an indium-containing phosphide.

[0004] According to an embodiment of the present disclosure, the indium content percentage in the second III-V semiconductor material is in a range of 1% to 30%.

[0005] According to an embodiment of the present disclosure, the first III-V semiconductor material is different from the second III-V semiconductor material.

[0006] According to an embodiment of the present disclosure, the first III-V semiconductor material is a binary III-V compound semiconductor, and the second III-V semiconductor material is a ternary III-V compound semiconductor.

[0007] According to an embodiment of the present invention, the second III-V semiconductor material is In x Ga 1-x P, and 0 <x<1。

[0008] The present invention further provides a semiconductor element, including an epitaxial structure, a first contact electrode and a second contact electrode. The epitaxial structure includes a first semiconductor structure, a second semiconductor structure and an active region. The first semiconductor structure includes a first semiconductor contact layer. The second semiconductor structure includes a second semiconductor contact layer. The active region is between the first semiconductor structure and the second semiconductor structure. The first contact electrode is located on the first semiconductor contact layer and directly contacts the first semiconductor contact layer. The second contact electrode is located on the first semiconductor contact layer and directly contacts the second semiconductor contact layer. The conductivity type of the first semiconductor contact layer is n-type and includes a first III-V semiconductor material. The conductivity type of the second semiconductor contact layer is p-type and includes a second III-V semiconductor material. The first III-V semiconductor material is an indium-containing phosphide and is a ternary III-V compound semiconductor.

[0009] According to one embodiment of the present invention, the first semiconductor contact layer has multiple pairs of alternately stacked first sublayers and second sublayers, the first sublayers comprising a first III-V semiconductor material, and the second sublayers comprising a third III-V semiconductor material different from the first III-V semiconductor material.

[0010] According to an embodiment of the present invention, the first semiconductor contact layer has 2 to 500 pairs of alternately stacked first sub-layers and second sub-layers.

[0011] According to an embodiment of the present invention, the first III-V semiconductor material is Al y In 1-y P, and 0 <y<1。

[0012] According to an embodiment of the present disclosure, the second III-V semiconductor material is a binary III-V compound semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A A schematic diagram of the cross-sectional structure of an epitaxial structure and a substrate according to an embodiment of the present invention;

[0014] Figure 1B A schematic cross-sectional structure diagram of a first semiconductor contact layer according to an embodiment of the present invention;

[0015] Figure 2A A schematic cross-sectional structure diagram of a semiconductor element according to an embodiment of the present invention;

[0016] Figure 2BA schematic cross-sectional structure diagram of a semiconductor element according to an embodiment of the present invention;

[0017] Figure 2C A schematic cross-sectional structure diagram of a semiconductor element according to an embodiment of the present invention;

[0018] Figure 3A A schematic top view of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 3B for Figure 3A A schematic diagram of the cross-sectional structure of a semiconductor element along line AA';

[0020] 4A to 4F A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0021] Figure 4G A schematic top view of a semiconductor device according to an embodiment of the present invention;

[0022] FIG. 5A to FIG. 5F A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0023] Figure 6 FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

[0024] Explanation of symbols

[0025] 10: Epitaxial structure

[0026] 10C: concave part

[0027] 10D: Groove

[0028] 10s1: First surface

[0029] 10s2: Second surface

[0030] 10s3, 110s2, 120s, 130s: side surface

[0031] 20A, 20B, 20C, 30: Semiconductor components

[0032] 80: Carrier board

[0033] 82: Pixel unit

[0034] 84: First semiconductor element

[0035] 86: Second semiconductor element

[0036] 88: The third semiconductor element

[0037] 100, 200: base

[0038] 110: First semiconductor structure

[0039] 110a: First covering layer

[0040] 110b: first semiconductor contact layer

[0041] 110b1: First sublayer

[0042] 110b2: Second sublayer

[0043] 110bs: Coarsened structure

[0044] 110c: Etch stop layer

[0045] 110s1, 120s1: Surface

[0046] 120: Second semiconductor structure

[0047] 120a: Second covering layer

[0048] 120b: second semiconductor contact layer

[0049] 130: Active area

[0050] 130a: Luminous area

[0051] 130b: First local layer

[0052] 130c: Second limit layer

[0053] 201: First contact electrode

[0054] 201a, 202a: upper surface

[0055] 202: Second contact electrode

[0056] 230: Joint structure

[0057] 301: Conductive oxide layer

[0058] 302: Insulation structure

[0059] 302s1: First opening

[0060] 302s2: Second opening

[0061] 302S3: The third opening

[0062] 303a: first electrode pad

[0063] 303b: Second electrode pad

[0064] 400, 401: Semiconductor components

[0065] 403: Adhesive layer

[0066] 410: Unit

[0067] 500: Temporary substrate

[0068] 600: Connection layer

[0069] 700: Target substrate

[0070] A0: Arrow

[0071] C1: first arc

[0072] C2: Second arc

[0073] d: interval

[0074] M1: The first platform structure

[0075] M2: Second platform structure

[0076] t1: thickness

[0077] R: Isolation area

[0078] W1: First width

[0079] W2: Second width

[0080] W3: Third width

[0081] W4: fourth width

[0082] X, Y, Z: direction

[0083] A-A', B-B': line DETAILED DESCRIPTION

[0084] In order to make the description of the content of the present invention more detailed and complete, the following will be described in detail with the accompanying drawings. It should be noted that the embodiments of semiconductor elements shown below for illustrating the content of the present invention do not limit the content of the present invention to the following embodiments. In the drawings or descriptions, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or sizes of the components in the drawings are only for illustration and are not actually limited thereto. It should be noted that the components not described in the drawings may be in a form known to those familiar with the art.

[0085] The semiconductor device of the present invention is, for example, a semiconductor optoelectronic device, such as a semiconductor light-emitting device (e.g., a light-emitting diode, a laser diode), a light-absorbing device (e.g., a photodiode), or other non-luminescent devices. The composition and dopant of each layer of the semiconductor device of the present invention can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM).

[0086] A person with ordinary knowledge in the art should understand that other components can be added on the basis of the embodiments described below. For example, if not specifically stated, a similar description of "a first layer (structure) is located on a second layer (structure)" may include an embodiment in which the first layer (structure) is in direct contact with the second layer (structure), and may also include an embodiment in which there is another structure between the first layer (structure) and the second layer (structure) and they are not in direct contact with each other. In addition, it should be understood that the upper and lower positional relationship of each layer (structure) may change due to observation from different directions.

[0087] Figure 1A FIG. 1 is a schematic cross-sectional view of an epitaxial structure 10 and a substrate 100 according to an embodiment of the present invention. Figure 1A As shown, the epitaxial structure 10 includes a first semiconductor structure 110, a second semiconductor structure 120 and an active region 130. The active region 130 is located between the first semiconductor structure 110 and the second semiconductor structure 120. The first semiconductor structure 110 and the second semiconductor structure 120 are respectively located on both sides of the active region 130 and are adjacent to the active region 130. The epitaxial structure 10 can be formed on a substrate 100. Figure 1A As shown, the substrate 100 is located below the first semiconductor structure 110, the second semiconductor structure 120 and the active region 130. In this embodiment, the substrate 100 is a growth substrate for epitaxial growth, such as a gallium arsenide (GaAs) substrate.

[0088] The first semiconductor structure 110, the second semiconductor structure 120 and the active region 130 may respectively include III-V semiconductor materials. The III-V semiconductor materials may include Al, Ga, As, P, N or In. In one embodiment, the first semiconductor structure 110, the active region 130 and the second semiconductor structure 120 may not include N. Specifically, the III-V semiconductor materials may be binary compound semiconductors (such as GaAs, GaP or GaN), ternary compound semiconductors (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN or AlGaN) or quaternary compound semiconductors (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaNAs or AlGaAsP). According to one embodiment, the total thickness of the epitaxial structure 10 may be in the range of 1 μm to 5 μm to further reduce the thickness of the device, which is conducive to the miniaturization of the device.

[0089] The first semiconductor structure 110 and the second semiconductor structure 120 may have different conductivity types to provide electrons and holes respectively. For example, the first semiconductor structure 110 is n-type and the second semiconductor structure 120 is p-type. Electrons and holes may combine in the active region 130 to emit light of a specific wavelength. The light may include visible light or invisible light. The conductivity type of the first semiconductor structure 110 and the second semiconductor structure 120 may be adjusted by adding different dopants. The dopants may include elements of Group II, Group IV or Group VI in the periodic table, such as magnesium (Mg), zinc (Zn), carbon (C), silicon (Si) or tellurium (Te).

[0090] The first semiconductor structure 110 and the second semiconductor structure 120 can be single-layer or multi-layer structures. In this embodiment, the first semiconductor structure 110 may include a first capping layer 110a and a first semiconductor contact layer 110b. In this embodiment, the first semiconductor contact layer 110b has an n-type conductivity type and includes a first III-V semiconductor material. The second semiconductor structure 120 may include a second capping layer 120a and a second semiconductor contact layer 120b. In this embodiment, the second semiconductor contact layer 120b has a p-type conductivity type and includes a second III-V semiconductor material. The first III-V semiconductor material is different from the second III-V semiconductor material. According to an embodiment, one of the first III-V semiconductor material and the second III-V semiconductor material may be a ternary III-V compound semiconductor, and the other may be a binary III-V compound semiconductor. According to an embodiment, one of the first III-V semiconductor material and the second III-V semiconductor material may be an indium-containing phosphide, and the other is not an indium-containing phosphide. By including different first III-V semiconductor materials and second III-V semiconductor materials in the first semiconductor contact layer 110b and the second semiconductor contact layer 120b, the first semiconductor contact layer 110b and the second semiconductor contact layer 120b in the epitaxial structure 10 can respectively provide appropriate contact characteristics.

[0091] In one embodiment, the side of the first semiconductor contact layer 110b or the second semiconductor contact layer 120b away from the active region 130 has a higher dopant concentration than the side closer to the active region 130 to provide better contact characteristics. The change in the above dopant concentration can gradually increase from the side closer to the active region 130 to the side away from the active region 130. In one embodiment, the dopant concentration on the side away from the active region 130 can be more than 10 times, such as 10 to 100 times, the dopant concentration on the side closer to the active region 130. According to an embodiment, the dopants in the second semiconductor contact layer 120b may include magnesium (Mg), zinc (Zn), or carbon (C), and the dopants in the first semiconductor contact layer 110b may include silicon (Si) or tellurium (Te).

[0092] According to an embodiment, the first III-V semiconductor material is a binary III-V compound semiconductor, such as gallium arsenide (GaAs); the second III-V semiconductor material may be a ternary III-V compound semiconductor. The second III-V semiconductor material may be an indium-containing phosphide, such as In x Ga 1-x P, and 0 < x < 1. According to another embodiment, the first III-V semiconductor material is a ternary III-V compound semiconductor; the first III-V semiconductor material may be an indium-containing phosphide, such as Al y In 1-yP, and 0 < y < 1. The second III-V semiconductor material can be a binary III-V compound semiconductor, such as gallium phosphide (GaP). By making the first semiconductor contact layer 110b with an n-type conductivity type and the second semiconductor contact layer 120b with a p-type conductivity type respectively contain the above materials, it helps to further reduce the resistance value of the semiconductor contact layer at the metal-semiconductor interface formed with the metal.

[0093] According to an embodiment, when the second III-V semiconductor material contains indium, the percentage of indium content in the second III-V semiconductor material can be in the range of 1% to 30%, thereby obtaining better resistance performance. The above indium content percentage can be defined as the content percentage of indium in the first III-V semiconductor material among all three group elements. The indium content percentage can be obtained, for example, in the following way: Measure the second semiconductor contact layer 120b using an Energy Dispersive Spectrometer (EDX), and calculate the indium content percentage (In%) of the second III-V semiconductor material in the second semiconductor contact layer 120b from the measurement results. For example, when the second III-V semiconductor material is In x Ga 1-x P, the atomic percentages (atomic percentage, at%) of In, Ga, and P can be obtained by EDX measurement, and thus x can be calculated. Specifically, x can be obtained by dividing the atomic percentage (at%) of indium (In) in the second semiconductor contact layer 120b by the atomic percentage (at%) of group V elements (i.e., phosphorus (P)). Here, the indium content percentage (In%) can be defined as x × 100%. According to some embodiments, when the second III-V semiconductor material is In x Ga 1-x P, and x is in the range of 0.05 - 0.3 (i.e., the indium content percentage in the second III-V semiconductor material is in the range of 5% to 30%), the second III-V semiconductor material can have a lower bandgap than gallium phosphide (GaP), so it helps to further reduce the resistance value.

[0094] The first semiconductor contact layer 110b can be the layer with the minimum or maximum thickness in the first semiconductor structure 110, and the second semiconductor contact layer 120b can be the layer with the minimum or maximum thickness in the second semiconductor structure 120. As Figure 1AAs shown, the thickness of the first semiconductor contact layer 110b may be less than the thickness of the second semiconductor contact layer 120b. In another embodiment, the thickness of the first semiconductor contact layer 110b may be greater than or equal to the thickness of the second semiconductor contact layer 120b. According to some embodiments, the thickness of the first semiconductor contact layer 110b and the thickness of the second semiconductor contact layer 120b may be respectively within the range.

[0095] The first semiconductor structure 110 may further selectively include an etch stop layer 110c, located between the first semiconductor contact layer 110b and the substrate 100. The first semiconductor structure 110 may further selectively include a transition layer (not shown), located between the substrate 100 and the etch stop layer 110c. The materials of the transition layer and the etch stop layer 110c may be binary or ternary III-V compound semiconductors, such as gallium arsenide (GaAs) or indium gallium phosphide (InGaP).

[0096] Specifically, the active region 130 may include a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantumwells (MQW) structure. According to one embodiment, when a semiconductor device includes the epitaxial structure 10 and is a light emitting device, the active region 130 may emit a light when the semiconductor device is in operation. The light includes visible light or invisible light. The light emitted by the semiconductor device is determined by the material composition in the active region 130. For example, when the material of the active region 130 includes InGaP or AlGaInP, yellow light, orange light, or red light with a peak wavelength of 530nm to 700nm may be emitted; when the material of the active region 130 includes InGaAs, InGaAsP, AlGaAs, or AlGaInAs, infrared light with a peak wavelength of 700nm to 1700nm may be emitted.

[0097] The active region 130 may include a light emitting region 130a, a first confining layer 130b, and a second confining layer 130c, which are located on both sides of the light emitting region 130a. The light emitting region 130a includes a plurality of pairs of well layers and barrier layers (not shown) stacked alternately. The materials of the well layers and barrier layers may include aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). According to some embodiments, the materials of the well layers and barrier layers may include quaternary III-V semiconductor compounds, such as AlGaInP, InGaAsP, or AlGaInAs.

[0098] Based on the above, in the epitaxial structure 10 of the embodiment of the present invention, by including the combination of the above-mentioned first III-V semiconductor material and the second III-V semiconductor material in the first semiconductor contact layer 110b and the second semiconductor contact layer 120b, the first semiconductor contact layer 110b and the second semiconductor contact layer 120b can respectively provide appropriate contact characteristics.

[0099] Figure 1B FIG. is a schematic cross-sectional structure diagram of the first semiconductor contact layer 110b according to an embodiment of the present invention. In this embodiment, the first semiconductor contact layer 110b has multiple pairs of alternately stacked first sub-layers 110b1 and second sub-layers 110b2. According to an embodiment, the first semiconductor contact layer 110b may have 2 to 500 pairs of alternately stacked first sub-layers 110b1 and second sub-layers 110b2. The thicknesses of each first sub-layer 110b1 and each second sub-layer 110b2 may be the same or different. The first sub-layer 110b1 may include a first III-V semiconductor material, and the second sub-layer 110b2 may include a third III-V semiconductor material different from the first III-V semiconductor material. The third III-V semiconductor material may be a ternary III-V compound semiconductor. In one embodiment, the first III-V semiconductor material may be an indium-containing phosphide, such as Al y In 1-y P, where 0 < y < 1; the third III-V semiconductor material may be an indium-containing phosphide, such as In z Ga 1-z P, where 0 < z < 1. In one embodiment, the thickness of each first sub-layer 110b1 is greater than the thickness of the second sub-layer 110b2 adjacent thereto. The ratio of the thickness of each first sub-layer 110b1 to the thickness of each second sub-layer 110b2 may be in the range of 0.5 to 15 times, for example, in the range of 1.5 to 5 times. According to an embodiment, the thickness of the first sub-layer 110b1 is, for example, in the range, and the thickness of the second sub-layer 110b2 is, for example, in the range. In this embodiment, by making the first semiconductor contact layer 110b have multiple pairs of alternately stacked first sub-layers 110b1 and second sub-layers 110b2, the resistance value of the first semiconductor contact layer 110b can be further reduced.

[0100] Figure 2AThe cross-sectional structure diagram of a semiconductor device 20A according to an embodiment of the present invention. The semiconductor device 20A includes an epitaxial structure 10, a first contact electrode 201 and a second contact electrode 202. The epitaxial structure 10 includes a first semiconductor structure 110, a second semiconductor structure 120 and an active region 130. The first semiconductor structure 110 includes a first semiconductor contact layer 110b and may optionally include an etching stop layer 110c. The second semiconductor structure 120 includes a second capping layer 120a and a second semiconductor contact layer 120b. The active region 130 is between the first semiconductor structure 110 and the second semiconductor structure 120. The first contact electrode 201 is located on the first semiconductor contact layer 110b and directly contacts the first semiconductor contact layer 110b. The second contact electrode 202 is located on the first semiconductor contact layer 110b and directly contacts the second semiconductor contact layer 120b. The semiconductor device 20A may optionally include a substrate 100. The substrate 100 is located below the epitaxial structure 10.

[0101] like Figure 2A As shown, the epitaxial structure 10 may have a first surface 10s1, a second surface 10s2 and a side surface 10s3, and there is a horizontal height difference between the first surface 10s1 and the second surface 10s2, and the side surface 10s3 connects the first surface 10s1 and the second surface 10s2. In this embodiment, one side of the epitaxial structure 10 has a recess 10C. The recess 10C may be defined by the first surface 10s1 and the side surface 10s3. The first contact electrode 201 is formed in the recess 10C (or on the first surface 10s1) and is in direct contact with the first semiconductor contact layer 110b to form an electrical connection. In some embodiments, the top view shape of the recess 10C may be circular, elliptical, rectangular or other polygonal. In this embodiment, the first semiconductor structure 110 does not include Figure 1A The first capping layer 110 a and the first semiconductor contact layer 110 b shown in the figure are the thickest layers in the first semiconductor structure 110 and can provide the required carriers (such as electrons), structural support, current diffusion and contact characteristics.

[0102] According to some embodiments, the materials of the first contact electrode 201 and the second contact electrode 202 may include metals or alloys. Examples of metals include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), nickel (Ni), or copper (Cu). The alloy may include at least two selected from the group consisting of the above metals, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), etc. The material of the first contact electrode 201 and the material of the second contact electrode 202 may be different or the same. According to one embodiment, the first contact electrode 201 includes germanium gold (GeAu), and the second contact electrode 202 includes beryllium gold (BeAu).

[0103] Specifically, the manufacturing method of the semiconductor device 20A may include the following steps: performing epitaxial growth on a substrate 100 to form an epitaxial structure 10, the substrate 100 being a growth substrate for epitaxial growth (such as a gallium arsenide substrate); removing a portion of the epitaxial structure 10 (including a portion of the first semiconductor structure 110, a portion of the second semiconductor structure 120, and a portion of the active region 130) to form a recess 10C to expose the first semiconductor structure 110; forming a first contact electrode 201 in direct contact with the first semiconductor contact layer 110b in the recess 10C, and forming a second contact electrode 202 on the second semiconductor contact layer 120b to directly contact with the second semiconductor contact layer 120b. In one embodiment, the manufacturing method of the semiconductor device 20A may further selectively include removing the substrate 100 after forming the first contact electrode 201 and the second contact electrode 202.

[0104] In this embodiment, the first semiconductor contact layer 110b has the functions of providing carriers and forming an ohmic contact with the first contact electrode 201, which can further simplify the device structure and manufacturing process, and is conducive to reducing production costs. The positions, relative relationships, material compositions, etc. of each layer or structure in this embodiment and the structural variation examples have been fully described in the previous embodiments and will not be repeated here.

[0105] Figure 2B FIG. 2 is a cross-sectional view of a semiconductor device 20B according to an embodiment of the present invention. The difference between the semiconductor device 20B and the semiconductor device 20A is that the first semiconductor contact layer 110b of the semiconductor device 20B has a plurality of pairs of alternately stacked first sub-layers 110b1 and second sub-layers 110b2. For information on the structure and materials of the first sub-layers 110b1 and the second sub-layers 110b2, please refer to the aforementioned Figure 1B In this embodiment, the first contact electrode 201 directly contacts one of the plurality of first sub-layers 110b1 to form an electrical connection. In another embodiment, the first contact electrode 201 may directly contact one of the plurality of second sub-layers 110b2 to form an electrical connection.

[0106] Specifically, the manufacturing method of the semiconductor device 20B may include the following steps: performing epitaxial growth on a substrate 100 to form an epitaxial structure 10, the substrate 100 being a growth substrate for epitaxial growth (such as a gallium arsenide substrate); removing a portion of the epitaxial structure 10 (including a portion of the first semiconductor structure 110, a portion of the second semiconductor structure 120, and a portion of the active region 130) to form a recess 10C to expose one of the plurality of first sub-layers 110b1 (or one of the plurality of second sub-layers 110b2); forming a first contact electrode 201 in direct contact with the first sub-layer 110b1 (or the second sub-layer 110b2) in the first semiconductor contact layer 110b in the recess 10C, and forming a second contact electrode 202 in direct contact with the second semiconductor contact layer 120b on the second semiconductor contact layer 120b. In one embodiment, the manufacturing method of the semiconductor device 20B may further selectively include removing the substrate 100 after forming the first contact electrode 201 and the second contact electrode 202.

[0107] In this embodiment, by making the first semiconductor contact layer 110b have multiple pairs of alternately stacked first sub-layers 110b1 and second sub-layers 110b2, the resistance of the first semiconductor contact layer 110b can be further reduced, which is beneficial to improving the electrical properties of the device. The positions, relative relationships, material compositions, etc. of each layer or structure in this embodiment and the structural variation examples have been fully described in the previous embodiments and will not be repeated here.

[0108] Figure 2C The cross-sectional structure diagram of a semiconductor element 20C of an embodiment of the present invention. The difference between the semiconductor element 20C and the semiconductor element 20A mainly lies in that the semiconductor element 20C includes a bonding structure 230, which is located between the substrate 200 and the epitaxial structure 10, and the first semiconductor structure 110 does not include an etching stop layer 110c. In this embodiment, the substrate 200 is a bonding substrate. The bonding substrate may be conductive or electrically insulating, such as a silicon (Si) substrate or a sapphire substrate. Specifically, the material of the substrate 200 may absorb less light emitted by the active region 130 than the growth substrate, so as to improve the light emitting efficiency of the element. The bonding structure 230 may be electrically insulating. In one embodiment, the material of the bonding structure 230 includes a polymer material such as benzocyclobutene (BCB), epoxy, polyimide, or silicone, aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 )wait.

[0109] Specifically, the manufacturing method of the semiconductor element 20C may include the following steps: performing epitaxial growth on a growth substrate (not shown) used for epitaxial growth to form an epitaxial structure 10; connecting the substrate 200 and the epitaxial structure 10 through a bonding structure 230, and the bonding structure 230 directly contacts the second semiconductor structure 120 and the substrate 200; removing the growth substrate used for epitaxial growth; removing a portion of the epitaxial structure 10 (including a portion of the first semiconductor structure 110, a portion of the second semiconductor structure 120, and a portion of the active area 130) to form a recess 10C to expose the surface 120s1 of the second semiconductor contact layer 120b; forming a first contact electrode 201 on the first semiconductor contact layer 110b that is in direct contact with the first semiconductor contact layer 110b, and forming a second contact electrode 202 in the recess 10C that is in direct contact with the second semiconductor contact layer 120b. According to one embodiment, before the substrate 200 and the epitaxial structure 10 are connected via the bonding structure 230 , a step of roughening the surface of the epitaxial structure 10 for bonding can be selectively included to more easily form a stable bonding structure.

[0110] According to some embodiments, when the wavelength range of light absorbed by the material of the growth substrate overlaps with the wavelength range of light emitted by the active region 130, the brightness of the semiconductor device can be improved by transferring the epitaxial structure 10 from the growth substrate used for epitaxial growth to the bonding substrate and removing the growth substrate. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0111] Figure 3A FIG. 1 is a schematic top view of a semiconductor device 30 according to an embodiment of the present invention. Figure 3B for Figure 3A A schematic cross-sectional structure diagram of a semiconductor element 30 along line AA'.

[0112] The semiconductor device 30 includes a substrate 100 and an epitaxial structure 10 located on the substrate 100. The epitaxial structure 10 includes a first semiconductor structure 110, a second semiconductor structure 120, and an active region 130. The first semiconductor structure 110 includes a first semiconductor contact layer 110b. The second semiconductor structure 120 includes a second capping layer 120a and a second semiconductor contact layer 120b. The active region 130 is between the first semiconductor structure 110 and the second semiconductor structure 120. The first semiconductor structure 110 may further optionally include an etching stop layer 110c located between the substrate 100 and the first semiconductor contact layer 110b. Figure 3A and Figure 3B As shown, the epitaxial structure 10 has a recess 10C. In this embodiment, the recess 10C is located in the epitaxial structure 10. Figure 3AAs shown, from a top view, the outline of the recess 10C is a closed figure, such as a circle. The semiconductor element 30 further includes a first contact electrode 201. The first contact electrode 201 is formed in the recess 10C and directly contacts the first semiconductor contact layer 110b to form an electrical connection. The second contact electrode 202 is located on the first semiconductor contact layer 110b and forms an electrical connection with the second semiconductor contact layer 120b. From a top view, the first contact electrode 201 and the second contact electrode 202 can be circular, elliptical, rectangular or other polygonal shapes.

[0113] The semiconductor device 30 further includes an insulating structure 302, which is located on the epitaxial structure 10. The insulating structure 302 has a first opening 302s1 and a second opening 302s2 corresponding to the first contact electrode 201 and the second contact electrode 202, respectively. In one embodiment, the insulating structure 302 may cover a portion of the upper surface 201a of the first contact electrode 201 and a portion of the upper surface 202a of the second contact electrode 202. The insulating structure 302 may provide insulation and / or reflection functions, and may isolate external moisture or pollution, etc., to prevent the active area 130 in the epitaxial structure 10 from being damaged. The insulating structure 302 may have a single-layer or multi-layer structure, and may include a dielectric material, such as an oxide, a nitride or a polymer (polymer) or a combination thereof. The oxide may include aluminum oxide (AlO x ), silicon oxide (SiO x ), titanium oxide (TiO x ), niobium pentoxide (Nb 2 O 5 ) or tantalum pentoxide (Ta 2 O 5 The nitride may include aluminum nitride (AlN) or silicon nitride (SiN x ). The polymer may include polyimide or benzocyclobutane (BCB).

[0114] In one embodiment, the insulating structure 302 may further have a reflective function, for example, including a distributed Bragg reflector (DBR). The distributed Bragg reflector may include a plurality of first dielectric layers and a plurality of second dielectric layers (not shown) overlapping each other, and the first dielectric layers and the second dielectric layers have different refractive indices. The first dielectric layers and the second dielectric layers may include silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ) or niobium pentoxide (Nb 2 O 5 ), for example, the combination of the first dielectric layer and the second dielectric layer is, for example, SiO 2 / TiO2 or SiO 2 / Nb 2 O 5 . By virtue of the reflective function of the insulating structure 180, the light emitted by the active region 130 can be mainly emitted from the side of the first semiconductor structure 110. In one embodiment, the insulating structure 302 can include a distributed Bragg reflector (DBR). The insulating structure 302 can cover the side surface 120s of the second semiconductor structure 120 and the side surface 130s of the active region 130. In this embodiment, the insulating structure 302 covers a portion of the surface 110s1 of the first semiconductor structure 110, but does not cover the side surface 110s2 of the first semiconductor structure 110.

[0115] The semiconductor device 30 may further optionally include a conductive oxide layer 301. The conductive oxide layer 301 may be located on the epitaxial structure 10 and between the epitaxial structure 10 and the insulating structure 302. Figure 3B As shown, the conductive oxide layer 301 located between the epitaxial structure 10 and the second contact electrode 202 can form an ohmic contact with the second semiconductor contact layer 120b to provide a better electrical connection. In some embodiments, the conductive oxide layer 301 can also assist in lateral diffusion of current and improve current spreading in the device. The material of the conductive oxide layer 301 can include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO) or a combination thereof.

[0116] The semiconductor element 30 also includes a first electrode pad 303a and a second electrode pad 303b. The first electrode pad 303a fills the recess 10C and the first opening 302s1 and directly contacts the upper surface 201a of the first contact electrode 201 to form an electrical connection. The second electrode pad 303b fills the second opening 302s2 and directly contacts the upper surface 202a of the second contact electrode 202 to form an electrical connection. The first electrode pad 303a and the second electrode pad 303b may include metal materials, such as nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), silver (Ag), gold (Au), aluminum (Al), tin (Sn), copper (Cu), bismuth (Bi), indium (In) or a combination thereof. In one embodiment, the upper surface of the first electrode pad 303a and the upper surface of the second electrode pad 303b may have substantially the same height. Figure 3A As shown in FIG. 1 , the first electrode pad 303a and the second electrode pad 303b may each be a rectangle with rounded corners when viewed from above. Figure 3AAs shown, from a top view, the diagonal length of the first semiconductor contact layer 110b can be within a range of greater than 1 μm and less than 50 μm to meet the requirements of component miniaturization. The top view area of ​​the first electrode pad 303a can be greater than, less than or equal to the top view area of ​​the second electrode pad 303b. Figure 3A As shown, the top-view area of ​​the first electrode pad 303 a may be larger than the top-view area of ​​the concave portion 10C, so as to ensure that the first electrode pad 303 a can fill the concave portion 10C.

[0117] In this embodiment, the first semiconductor structure 110 does not include Figure 1A The first covering layer 110a shown in the figure, the first semiconductor contact layer 110b is the thickest layer in the first semiconductor structure 110, and can provide the required carriers (such as electrons), structural support, current diffusion and contact characteristics. Because the first semiconductor contact layer 110b can provide carriers and form an ohmic contact with the first contact electrode 201, the device structure can be further simplified. On the other hand, in the manufacturing process of the semiconductor device 30 of this embodiment (see below), FIG. 4A to FIG. 4G In the embodiment of the present invention, there is no need to transfer the substrate (for example, bonding the epitaxial structure 10 to a bonding substrate and removing the growth substrate) before forming the first electrode pad 303a and the second electrode pad 303b, which can further simplify the device manufacturing process and help reduce production costs. The positions, relative relationships, material compositions, etc. of each layer or structure in this embodiment and the structural variation examples have been fully described in the previous embodiments and will not be repeated here.

[0118] FIG. 4A to FIG. 4G FIG. 4 is a schematic diagram of a method for manufacturing a semiconductor component 400 according to an embodiment of the present invention. The semiconductor component 400 may include a plurality of semiconductor elements (such as semiconductor elements 20A, 20B, 20C, 30) as described in any embodiment of the present invention. In this embodiment, the method for manufacturing a semiconductor component 400 including a plurality of semiconductor elements 30 is taken as an example for description.

[0119] First, please refer to Figure 4A , a substrate 100 is provided, and epitaxial growth is performed on the substrate 100 to form an epitaxial structure 10. The substrate 100 is a growth substrate for epitaxial growth (such as a gallium arsenide substrate). Then, a conductive oxide layer 301 can be selectively formed on the epitaxial structure 10. Figure 4A As shown, the conductive oxide layer 301 may cover the entire upper surface of the epitaxial structure 10 .

[0120] Please refer to Figure 4BNext, a first etching process is performed to remove a portion of the epitaxial structure 10 to form a plurality of recesses 10C and a plurality of trenches 10D in the epitaxial structure 10. Here, removing a portion of the epitaxial structure 10 includes removing a portion of the first semiconductor structure 110, a portion of the second semiconductor structure 120, and a portion of the active region 130. When performing the first etching process, a portion of the conductive oxide layer 301 may be removed at the same time. Figure 4B As shown, each recess 10C may have a first width W1, and each groove 10D may have a second width W2 greater than the first width W1. In one embodiment, the thickness t1 of the epitaxial structure 10 removed may account for between 20% and 40% of the total thickness of the epitaxial structure 10, so that a portion of the first semiconductor contact layer 110b in the first semiconductor structure 110 is exposed. Through the first etching process, a plurality of first mesa structures M1 and a plurality of second mesa structures M2 arranged alternately are defined in the epitaxial structure 10. The thickness of the first mesa structure M1 and the second mesa structure M2 is the aforementioned thickness t1. Adjacent first mesa structures M1 and second mesa structures M2 are separated by a recess 10C or a groove 10D. Each first mesa structure M1 may have a third width W3, and each second mesa structure M2 may have a fourth width W4 less than the third width W3. The first etching process may include dry etching or wet etching. The dry etching process is, for example, Electron Cyclotron Resonance (ECR), Inductively Coupled Plasma (ICP) or Reactive Ion Etch (RIE).

[0121] Then, if Figure 4C As shown, a first contact electrode 201 directly contacting the first semiconductor contact layer 110b is formed in each recess 10C, and a second contact electrode 202 directly contacting the conductive oxide layer 301 is formed on each first platform structure M1. In the case where there is no conductive oxide layer 301 on the epitaxial structure 10, the second contact electrode 202 can be in direct contact with the second semiconductor contact layer 120b. In detail, the first contact electrode 201 and the second contact electrode 202 can be formed by sputtering or evaporation. After the first contact electrode 201 and / or the second contact electrode 202 are formed, a heat treatment can be performed to form a good electrical contact (e.g., ohmic contact) between the first contact electrode 201 and the first semiconductor contact layer 110b, and between the second contact electrode 202 and the conductive oxide layer 301 (or the second semiconductor contact layer 120b). The above-mentioned heat treatment is performed in a furnace, for example.

[0122] Afterwards, if Figure 4D As shown, a second etching process may be performed to remove a portion of the first semiconductor structure 110 located in the trench 10D, thereby defining a plurality of semiconductor elements 30 ( Figure 4D In one embodiment, the second etching process may remove the first semiconductor contact layer 110b in the first semiconductor structure 110, and further form an isolation region R in the trench 10D. According to one embodiment, the etching stop layer 110c outside the defined semiconductor element 30 (i.e., the isolation region R) may be completely or partially removed after the second etching process. The second etching process may include dry etching or wet etching.

[0123] Please refer to Figure 4E , an insulating structure 302 may be formed on the epitaxial structure 10. The method of forming the insulating structure 302 is, for example, chemical vapor deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD). In this embodiment, the insulating structure 302 covers the conductive oxide layer 301 and the second semiconductor contact layer 120b, and may cover the side surface of each layer in the second semiconductor structure 120 and the side surface of each layer in the active region 130. According to one embodiment, the insulating structure 302 may further cover the surface of the first semiconductor contact layer 110b that constitutes a portion of the recess 10C (e.g., Figure 4E The insulating structure 302 may have a plurality of first openings 302s1 and a plurality of second openings 302s2. Figure 4E As shown, the first opening 302s1 overlaps with the first contact electrode 201 in the vertical direction (such as the Z direction), and the second opening 302s2 overlaps with the second contact electrode 202 in the vertical direction (such as the Z direction). The width of the first opening 302s1 may be less than or equal to the width of the corresponding first contact electrode 201, and the width of the second opening 302s2 may be less than or equal to the width of the corresponding second contact electrode 202, so as to ensure that the electrode pad and the epitaxial structure 10 are electrically connected via the first contact electrode 201 and the second contact electrode 202 when the device is operated.

[0124] like Figure 4EAs shown, the insulating structure 302 may also have a plurality of third openings 302S3. The third openings 302S3 overlap with the trench 10D (or the isolation region R) in the vertical direction (e.g., the Z direction). The first opening 302s1, the second opening 302s2, and the third opening 302S3 may be formed by performing an etching process (selectivity) after depositing the material of the insulating structure 302, or the insulating structure 302 having the first opening 302s1, the second opening 302s2, and the third opening 302S3 may be directly formed by photomask design. The etching process may include dry etching or wet etching.

[0125] Next, please refer to Figure 4F and Figure 4G , a first electrode pad 303a and a second electrode pad 303b are formed on the first contact electrode 201 and the second contact electrode 202, respectively, to form a semiconductor device 400. The first electrode pad 303a is filled into the first opening 302s1 and is in direct contact with the upper surface 201a of the first contact electrode 201 to form an electrical connection. The second electrode pad 303b is filled into the second opening 302s2 and is in direct contact with the upper surface 202a of the second contact electrode 202 to form an electrical connection. The first electrode pad 303a and the second electrode pad 303b can be formed by sputtering or evaporation. Figure 4G As shown, after forming the first electrode pad 303a and the second electrode pad 303b, the semiconductor device 400 includes a plurality of semiconductor elements 30 from a top view. The plurality of semiconductor elements 30 are arranged in a two-dimensional array along a first direction (X direction) and a second direction (Y direction). Specifically, Figure 4F The cross-sectional structure shown in is, for example, Figure 4G Schematic diagram of the cross section along line BB'.

[0126] FIG. 5A to FIG. 5D FIG. 4 is a schematic diagram of a method for manufacturing a semiconductor device 401 according to an embodiment of the present invention. The method for manufacturing the semiconductor device 401 may selectively include: FIG. 5A to FIG. 5D Specifically, Figure 4F and Figure 4G As shown, after forming the first electrode pad 303a and the second electrode pad 303b, the plurality of semiconductor elements 30 ( Figure 5A The system draws three as an example) and is bonded to the temporary substrate 500, and is turned upside down to form a Figure 5AThe temporary substrate 500 can provide structural support, such as a silicon (Si) substrate or a sapphire substrate. A plurality of semiconductor elements 30 can be embedded in the adhesive layer 403. The adhesive layer 403 can surround each semiconductor element 30 and be distributed between adjacent semiconductor elements 30 and between the first electrode pad 303a and the second electrode pad 303b in each semiconductor element 30. Figure 5A As shown, except for the surface facing the substrate 100, all other surfaces of each semiconductor element 30 are in direct contact with the adhesive layer 403. The adhesive layer 403 may include thermal removal adhesive, photolysis adhesive, chemical removal adhesive, heat-resistant adhesive, blue film, or tape with a dynamic release layer. The material of the adhesive layer 403 is, for example, an insulating adhesive, which may include polyimide, benzocyclobutene (BCB), epoxy resin, silicone resin, acrylic resin, polyester, or a combination thereof. Figure 5A As shown, the first electrode pad 303a and the second electrode pad 303b in the semiconductor element 30 can be fixed in the adhesive layer 403 in a downward direction (i.e., toward the temporary substrate 500). By temporarily fixing the plurality of semiconductor elements 30 in the adhesive layer 403 by burying them in the adhesive layer 403, the relative positions between the plurality of semiconductor elements 30 can be maintained.

[0127] The first electrode pad 303a and the second electrode pad 303b may have a distance from the temporary substrate 500, or directly contact the temporary substrate 500 (not shown). According to one embodiment, if there is a distance between the first electrode pad 303a and the second electrode pad 303b and the temporary substrate 500, the first electrode pad 303a and the second electrode pad 303b can be prevented from being squeezed and damaged. In this embodiment, the first electrode pad 303a and the second electrode pad 303b protrude from the side close to the epitaxial structure 10 toward the temporary substrate 500, and the cross-sectional profile of the second electrode pad 303b may have a first arc-shaped portion C1, and the cross-sectional profile of the first electrode pad 303a may have a second arc-shaped portion C2. This design can increase the surface area of ​​the electrode pad, which is helpful for the stability of bonding, and also helps to further improve the reliability of physical and electrical connections when the semiconductor element 30 is subsequently fixed to a carrier (such as a circuit substrate).

[0128] Then, if Figure 5B As shown, the substrate 100 may be removed to expose the first semiconductor structure 110. In this embodiment, the etching stop layer 110c in the first semiconductor structure 110 may also be completely removed to expose the first semiconductor contact layer 110b.

[0129] Next, if Figure 5CAs shown, optionally, the exposed surface of the first semiconductor structure 110 may be further subjected to a roughening process, and a roughening structure 110bs may be formed on the surface of the first semiconductor structure 110 (here, the surface of the first semiconductor contact layer 110b). By having the roughening structure 110bs on the surface of the first semiconductor structure 110, it is helpful to improve the light extraction efficiency of the semiconductor element 30. The above-mentioned method of removing the substrate 100 and / or the etching stop layer 110c and the roughening process are, for example, dry etching or wet etching.

[0130] Next, if Figure 5D As shown, a portion of the adhesive layer 403 (for example, the portion distributed between adjacent semiconductor elements 30) can be further removed so that each semiconductor element 30 and the remaining portion of the adhesive layer 403 surrounding it form a spatially independent unit 410. Specifically, the portion of the adhesive layer 403 that does not overlap with the semiconductor element 30 in the vertical direction (Z direction) can be removed by dry etching or wet etching to form the above-mentioned multiple units 410. In some embodiments, the adhesive layer 403 can be used as a dissociation layer. For example, the temporary substrate 500 and the structure above can be separated by further etching, laser stripping, heating, or UV light treatment of the adhesive layer 403. Figure 5D In each unit 410 shown, the first electrode pad 303a and the second electrode pad 303b of the semiconductor element 30 face downward, that is, the first electrode pad 303a (or the second electrode pad 303b) is located between the epitaxial structure 10 and the temporary substrate 500. Since the multiple units 410 are spatially independent, the subsequent steps such as transfer can be performed according to actual needs, thereby improving the process operability.

[0131] The method for manufacturing the semiconductor device 401 may also optionally include the following steps: FIG. 5E to FIG. 5F Specifically, Figure 5E As shown, the multiple units 410 on the temporary substrate 500 can be further fixed to the target substrate 700 through the connection layer 600. The connection layer 600 can include a transparent adhesive material. According to some embodiments, the target substrate 700 can be a circuit board, a TFT substrate, or a sub-mount of a package body applied to a display, or can be a temporary carrier similar to the temporary substrate 500. Then, the temporary substrate 500 can be turned upside down and removed, and the target substrate 700 can be obtained as shown in FIG. Fig. 5F The temporary substrate 500 can be removed by wet etching or dry etching.

[0132] exist Fig. 5FIn each unit 410 shown, the first electrode pad 303a and the second electrode pad 303b of the semiconductor element 30 face upward, and the epitaxial structure 10 is located between the first electrode pad 303a (or the second electrode pad 303b) and the target substrate 700. According to one embodiment, the adhesive layer 403 in each unit 410 can be further removed selectively. For example, the adhesive layer 403 covering each semiconductor element 30 can be completely or partially removed by wet etching or dry etching. According to one embodiment, when the target substrate 700 is used as a temporary carrier, the connecting layer 600 can be used as a dissociation layer, for example, by further etching, laser stripping, heating or UV light treatment of the connecting layer 600, each unit 410 and the target substrate 700 can be separated.

[0133] According to another embodiment, the adhesive layer 403 distributed near the first electrode pad 303a and the second electrode pad 303b in each unit 410 can be selectively removed to expose the surface of the first electrode pad 303a and the second electrode pad 303b, and a redistribution layer (RDL) can be further formed on the plurality of semiconductor elements 30 to form a desired electrical connection structure.

[0134] According to another embodiment, the plurality of units 410 may be selectively fixed to the target substrate 700 in a manner such that the first electrode pad 303a and the second electrode pad 303b in each unit 410 face downward, that is, the first electrode pad 303a (or the second electrode pad 303b) is located between the epitaxial structure 10 and the target substrate 700. Specifically, after obtaining the Figure 5D After the structure shown, the multiple semiconductor elements 30 on the temporary substrate 500 can be further bonded to another temporary substrate (not shown, its material can refer to the material of the adhesive layer 403) through another adhesive layer (not shown, its material can refer to the material of the temporary substrate 500), and after turning the temporary substrate 500 upside down and removing it, the multiple units 410 are fixed to the target substrate 700 and the other temporary substrate is removed, thereby forming a plurality of units 410 in which the first electrode pad 303a and the second electrode pad 303b are located between the epitaxial structure 10 and the target substrate 700.

[0135] Depend on FIG. 4A to FIG. 5FAs can be seen from the illustrated embodiment, the semiconductor component 400 including a plurality of semiconductor elements 30 can have different structural patterns, which can actually be selected according to the needs. Specifically, in the manufacturing process of the semiconductor component 400, there is no need to perform substrate transfer (for example, bonding the epitaxial structure 10 to the bonding substrate and removing the growth substrate) before forming the first electrode pad 303a and the second electrode pad 303b, and there is no need to consider the tolerance of the material of the bonding structure 230 to the temperature and other conditions of the aforementioned heating treatment, thereby improving the manufacturing process yield, further simplifying the component manufacturing process, and helping to reduce production costs. The positions, relative relationships, material compositions, and other contents of each layer or structure in this embodiment and the structural variation examples have been fully described in the previous embodiments and will not be repeated here.

[0136] Figure 6 FIG. 8 is a schematic top view of a semiconductor device 800 according to an embodiment of the present invention. The semiconductor device 800 of this embodiment is, for example, a display device. Figure 6 As shown, the semiconductor component 800 includes a carrier 80 and a plurality of pixel units 82 located on the carrier 80. The plurality of pixel units 82 are arranged in an array along directions parallel to the x-axis and the y-axis, and are arranged at an interval d in a direction parallel to the x-axis. The number of pixel units 82 can be adjusted as required. For example, in one embodiment, the plurality of pixel units 82 included in the semiconductor component 800 can provide a resolution of 1920x1080 pixels. In one embodiment, the interval d is less than 1.4 mm. For example, the interval d is between 0.2 mm and 1.3 mm, such as 0.75 mm, 0.8 mm, 1 mm, or 1.25 mm. Figure 6As shown, each pixel unit 82 includes a first semiconductor element 84, a second semiconductor element 86 and a third semiconductor element 88 arranged in a direction parallel to the y-axis. One or more of the first semiconductor element 84, the second semiconductor element 86 and the third semiconductor element 88 can be the semiconductor element described in any embodiment of the present invention (such as semiconductor elements 20A, 20B, 20C, 30). In one embodiment, the first semiconductor element 84, the second semiconductor element 86 and the third semiconductor element 88 are all light-emitting elements and can emit red light, green light and blue light respectively. In one embodiment, the arrangement order of these light-emitting elements can also be adjusted according to demand, for example, the first semiconductor element 84, the second semiconductor element 86 and the third semiconductor element 88 respectively emit red light, blue light and green light. Each pixel unit 82 can be electrically connected to the circuit (not shown) on the surface of the carrier 80, so that the light-emitting element therein can receive external signals and emit light according to the external signals. The carrier 80 can be a single-layer or multi-layer structure. The material of the carrier 80 may include polyester, polyimide (PI), BT resin (Bismaleimide Triazine), PTFE resin (Polytetrafluoroethylene), phenolic resin (Phenol resins, PF) or glass fiber epoxy resin (FR4). In one embodiment, the carrier 80 can be bent, and for example, can withstand a state where the radius of curvature is less than 50 mm, such as 25 mm or 32 mm. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0137] In summary, according to the embodiments of the present invention, an epitaxial structure, a semiconductor element and a method for manufacturing the same, a semiconductor component and a method for manufacturing the semiconductor component, etc. can be provided, which have the advantages of, for example, improving contact characteristics, simplifying the element manufacturing process, reducing production costs, having better manufacturing process stability or production yield, etc., and are also suitable for elements that require miniaturization, and can be widely used in various fields. Specifically, the epitaxial structure, semiconductor element and semiconductor component of the present invention can be applied to products in the fields of lighting, display, communication, power supply system, etc., such as lamps, monitors, car dashboards, televisions, computers, traffic signs, outdoor displays, etc.

[0138] Although the present invention has been disclosed as above by way of embodiments, some modifications or changes may be made without departing from the spirit and scope of the present invention, and therefore the protection scope of the present invention shall be subject to the definition of the appended claims. The contents of the above embodiments may be combined or replaced with each other where appropriate, and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component disclosed in one embodiment or the connection relationship between a specific component and other components may also be applied to other embodiments, and all fall within the scope of protection of the present invention.

Claims

1. A semiconductor element, comprising: Epitaxial structure, including: A first semiconductor structure comprising a first semiconductor contact layer; A second semiconductor structure comprising a second semiconductor contact layer; and an active region between the first semiconductor structure and the second semiconductor structure; A first contact electrode is located on the second semiconductor contact layer and directly contacts the first semiconductor contact layer; and The second contact electrode is located on the second semiconductor contact layer and directly contacts the second semiconductor contact layer; wherein the conductivity type of the first semiconductor contact layer is n-type and comprises a first III-V semiconductor material, the conductivity type of the second semiconductor contact layer is p-type and comprises a second III-V semiconductor material, and the second III-V semiconductor material is an indium-containing phosphide. 2 . The semiconductor device as claimed in claim 1 , wherein a content percentage of indium in the second III-V semiconductor material is in a range of 1% to 30%. 3 . The semiconductor device of claim 1 , wherein the first III-V semiconductor material is different from the second III-V semiconductor material. 4 . The semiconductor device of claim 3 , wherein the first III-V semiconductor material is a binary III-V compound semiconductor, and the second III-V semiconductor material is a ternary III-V compound semiconductor.

5. The semiconductor device as claimed in claim 4, wherein the second III-V semiconductor material is In x Ga 1-x P, and 0 <x<1。 6. A semiconductor element, comprising: Epitaxial structure, including: A first semiconductor structure comprising a first semiconductor contact layer; A second semiconductor structure comprising a second semiconductor contact layer; and an active region between the first semiconductor structure and the second semiconductor structure; A first contact electrode, located on the first semiconductor contact layer and directly contacting the first semiconductor contact layer; and A second contact electrode is located on the first semiconductor contact layer and directly contacts the second semiconductor contact layer; The first semiconductor contact layer has an n-type conductivity and comprises a first III-V semiconductor material, the second semiconductor contact layer has a p-type conductivity and comprises a second III-V semiconductor material, and the first III-V semiconductor material is an indium-containing phosphide and is a ternary III-V compound semiconductor.

7. The semiconductor device as claimed in claim 6, wherein the first semiconductor contact layer has a plurality of pairs of first sub-layers and second sub-layers stacked alternately, the first sub-layer comprises the first III-V semiconductor material, and the second sub-layer comprises a third III-V semiconductor material different from the first III-V semiconductor material. 8 . The semiconductor device as claimed in claim 7 , wherein the first semiconductor contact layer has 2 to 500 pairs of the first sub-layers and the second sub-layers that are alternately stacked.

9. The semiconductor device as claimed in claim 6, wherein the first III-V semiconductor material is Al y In 1-y P, and 0 <y<1。 10 . The semiconductor device of claim 9 , wherein the second III-V semiconductor material is a binary III-V compound semiconductor.

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