Large-capacitance impact current suppression circuit and method

Abstract

The invention provides a large-capacitance impact current suppression circuit, which belongs to the technical field of power electronics and comprises a suppression area circuit, a voltage control area circuit and a current control area circuit, the suppression area circuit comprises a first field effect transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, a third diode and a fourth diode, and the voltage control area circuit comprises a first triode, a fifth resistor, a sixth resistor, a seventh resistor and a first diode. The current control area circuit comprises a second triode, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a second diode. The circuit provided by the invention overcomes the inherent defect that the existing impact current suppression circuit can only suppress the startup impact current, so that the suppression circuit can generate a suppression effect on the impact current caused by short-time repeated startup or voltage transient, power failure restart and other power supply compatibility tests.

Description

Technical Field

[0001] The present application belongs to the field of power electronics technology, and in particular relates to a large capacitor surge current suppression circuit and method. Background Art

[0002] In order to meet the requirements of power supply stability and electromagnetic compatibility testing, power supply equipment usually has a large-capacity capacitor in parallel at the input end for energy storage and filtering to smooth out disturbances on the input side. At the moment of power on or input overvoltage, the large-capacity capacitor will cause a large surge current in the circuit. If the surge current is too large, it will blow the fuse or even trigger the overcurrent protection of the input power supply, thereby affecting the normal operation of other electrical equipment. Therefore, relevant standards have made clear provisions for surge current, requiring that the peak surge current should not exceed five times the rated current.

[0003] The common methods for suppressing inrush current are to connect a power resistor in series on the power bus or in series on the capacitor branch. Directly using a series power resistor to suppress inrush current will cause excessive loss in the circuit and is not suitable for high-power applications. Connecting a power resistor in series on the capacitor branch will seriously deteriorate the capacitor filtering effect.

[0004] Therefore, the existing inrush current suppression technology has limitations in reliability and other aspects when solving the problem of large capacitor input inrush current suppression. Summary of the invention

[0005] The purpose of the present application is to provide a large capacitor surge current suppression circuit and method to solve or alleviate at least one problem in the background technology.

[0006] On the one hand, the technical solution of the present application is: a large capacitor surge current suppression circuit, including a suppression zone circuit, a voltage control zone circuit and a current control zone circuit, wherein:

[0007] The suppression zone circuit includes a first field effect transistor Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a third diode D3 and a fourth diode D4. One end of the first resistor R1 and the first capacitor C1 is connected to the input positive terminal V in+ and the positive output terminal V out+ connected, one end of the second resistor R2, the anode of the fourth diode D4, one end of the second capacitor C2, one end of the third capacitor C3, the source of the first field effect transistor Q1 and one end of the third resistor R3 are connected to the negative output terminal V out- The other end of the second resistor R2, the cathode of the fourth diode D4 and the other end of the second capacitor C2 are connected to the other end of the resistor R1, both ends of the fourth resistor R4 are connected to both ends of the third capacitor C3, and the other end of the third resistor R3 is connected to the other end of the first capacitor C1;

[0008] The voltage control area circuit includes a first transistor V1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a first diode D1, wherein the anode of the first diode D1 is connected to the other end of the second capacitor C2 in the suppression area circuit, one end of the fifth resistor R5 is connected to the drain of the first field effect transistor Q1 in the suppression area circuit, the cathode of the first diode D1 is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is connected to the collector of the first transistor V1, the other end of the fifth resistor R5 is connected to the base of the first transistor V1 and one end of the sixth resistor R6, and the other end of the sixth resistor R6 and the emitter of the first transistor V1 are connected to the output negative terminal V out- ;

[0009] The current control area circuit includes a second transistor V2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 11th resistor R 11 The second diode D2 has an anode connected to the other end of the second capacitor C2 in the suppression zone circuit, and a cathode connected to the eleventh resistor R 11 One end is connected to the eleventh resistor R 11 The other end is connected to the collector of the second transistor V2, and the tenth resistor R 10 The eighth resistor R8 is connected across the negative input terminal V in- With the negative output terminal V out- One end of the ninth resistor R9 is connected to the collector of the second transistor V2, and the other end is connected to the negative output terminal V out- connect.

[0010] In a preferred embodiment of the present application, both the first transistor V1 and the second transistor V2 are NPN transistors.

[0011] In a preferred embodiment of the present application, the first field effect transistor Q1 is an N-channel MOS transistor.

[0012] On the other hand, the technical solution provided by the present application is: a method for implementing current suppression using any of the large-capacitance surge current suppression circuits as described above, the method comprising:

[0013] Step S10: When the power supply is turned on, the voltage of the first capacitor C1 is zero, and the voltage across the third resistor R3 is higher than a predetermined value. After voltage division by the fifth resistor R5 and the sixth resistor R6, the first transistor V1 is turned on, thereby lowering the gate voltage of the first field effect transistor Q1, so that the first field effect transistor Q1 remains in the off state. At this time, the input power charges the first capacitor C1 through the third resistor R3, thereby suppressing the power-on impact current;

[0014] Step S20: As the voltage of the first capacitor C1 increases, the voltage across the third resistor R3 gradually decreases. When the divided voltage of the third resistor R3 is lower than the conduction threshold voltage of the first transistor V1, the first transistor V1 will be cut off, and the power supply charges the second capacitor C2 through the first resistor R1. The gate voltage of the first field effect transistor Q1 increases, and the delayed conduction of the first field effect transistor Q1 is realized, and the power supply power-on process is completed. After the power-on startup is completed, the first capacitor C1 and the turned-on first field effect transistor Q1 are connected in series to the power supply circuit;

[0015] Step S30: When a power input failure occurs, the drain-source voltage of the first field effect transistor Q1 is greater than a predetermined value, and the first triode V1 is turned on after voltage division by the fifth resistor R5 and the sixth resistor R6, and the second capacitor C2 is quickly discharged through the first diode D1, and the gate voltage of the first field effect transistor Q1 is pulled down, so that the first field effect transistor Q1 is quickly restored to the off state; at the same time, the charge on the parasitic capacitor of the first field effect transistor Q1 is quickly discharged through the third diode D3, ensuring that the first field effect transistor Q1 remains in the off state, and the input voltage difference charges the first capacitor C1 through the third resistor R3, so as to suppress transient impact current, and then return to the state of step S20;

[0016] Step S40: When there is an inrush current in the power supply circuit, the voltage difference between the eighth resistor R8 increases. If it exceeds the set threshold value, the voltage difference passes through the ninth resistor R9 and the tenth resistor R 10 After voltage division, the second transistor V2 is turned on, and the second capacitor C2 is quickly discharged through the second diode D2, so as to lower the gate voltage of the first field effect transistor Q1, so that the first field effect transistor Q1 is quickly restored to the off state. At the same time, the charge on the parasitic capacitor of the first field effect transistor Q1 is quickly discharged through the third diode D3 to ensure that the first field effect transistor Q1 remains in the off state. The input voltage difference charges the first capacitor C1 through the third resistor R3, so as to suppress transient impact current, and then return to the state of step S20.

[0017] In an optional implementation manner of the present application, the fault includes power supply overvoltage, power failure and restart, or repeated startup.

[0018] The large-capacitor impact current suppression circuit and method provided by the present application overcome the inherent defect of the existing impact current suppression circuit that can only suppress the startup impact current, so that the suppression circuit can suppress the impact current caused by short-term repeated startup or voltage transients, power failure restart and other power supply compatibility tests. At the same time, the large-capacitor impact current suppression circuit of the present application monitors the input voltage and current to ensure that when a quantity suddenly changes, the field effect tube is turned off in a timely and effective manner, and the power resistor is cut in to suppress the impact current. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solution provided by the present application, the following is a brief introduction to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present application.

[0020] Figure 1 Schematic diagram of the method of this application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the implementation of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below in conjunction with the drawings in the embodiments of this application.

[0022] In the accompanying drawings, the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The described embodiments are part of the embodiments of the present application, rather than all of the embodiments. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0023] It should be understood that, in the description of the present application, the terms "up", "down", "left", "right", "front", "back", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as limiting the scope of protection of the present application.

[0024] In order to solve the technical problems that the existing high-power circuit impulse current suppression technology is not suitable for places with repeated impulses or relatively high reliability requirements, and the technical problem that it is not suitable for places with limited volume or relatively high cost requirements due to complex structure, the present application proposes a low-cost, high-reliability large-capacitor impulse current suppression circuit and suppression method.

[0025] like Figure 1 As shown, the large capacitor impact current suppression circuit provided by the present application includes: a suppression zone circuit, a voltage control zone circuit and a current control zone circuit. The voltage control zone circuit and the current control zone circuit are used to detect the voltage and current of the suppression zone circuit to ensure that when the impact current reaches the set threshold, the suppression zone circuit is restored to the power resistor current limiting state, thereby achieving the suppression of the impact current generated by the large capacitor (C1) in any state.

[0026] The suppression zone circuit in the present application includes a first field effect transistor Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a third diode D3 and a fourth diode D4.

[0027] Specifically, the upper end of the first resistor R1 and the first capacitor C1 are connected to the positive input terminal V in+ and the positive output terminal V out+ The lower end of the second resistor R2, the anode of the fourth diode D4, the lower end of the second capacitor C2, the lower end of the third capacitor C3, the source of the first field effect transistor Q1 and the lower end of the third resistor R3 are connected to the output negative terminal V out- The upper end of the second resistor R2, the cathode of the fourth diode D4 and the upper end of the second capacitor C2 are connected to the lower end of the resistor R1, the two ends of the fourth resistor R4 are connected to the two ends of the third capacitor C3, and the upper end of the third resistor R3 is connected to the lower end of the first capacitor C1.

[0028] The voltage control region circuit in the present application includes a first transistor V1 , a fifth resistor R5 , a sixth resistor R6 , a seventh resistor R7 and a first diode D1 .

[0029] Specifically, the anode of the first diode D1 is connected to the upper end of the second capacitor C2 in the suppression zone circuit, the upper end of the fifth resistor R5 is connected to the drain of the first field effect transistor Q1 in the suppression zone circuit, the cathode of the first diode D1 is connected to the upper end of the seventh resistor R7, the lower end of the seventh resistor R7 is connected to the collector of the first transistor V1, the lower end of the fifth resistor R5 is connected to the base of the first transistor V1 and the upper end of the sixth resistor R6, and the lower end of the sixth resistor R6 and the emitter of the first transistor V1 are connected to the output negative terminal V out- .

[0030] The current control region circuit of the present application includes a second transistor V2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 11th resistor R 11 and a second diode D2.

[0031] Specifically, the anode of the second diode D2 is connected to the upper end of the second capacitor C2 in the suppression zone circuit, and the cathode of the second diode D2 is connected to the eleventh resistor R 11 The right end is connected to the eleventh resistor R 11 The left end is connected to the collector of the second transistor V2, and the tenth resistor R 10 The eighth resistor R8 is connected across the negative input terminal V in- With the negative output terminal V out- The upper end of the ninth resistor R9 is connected to the collector of the second transistor V2, and the lower end is connected to the output negative terminal V out- connect.

[0032] In the preferred embodiment of the present application, the first transistor V1 and the second transistor V2 are both NPN transistors. Further, the first field effect transistor Q1 is an N-channel MOS transistor.

[0033] In addition, the present application also provides a method for current suppression using the above-mentioned large-capacitance surge current suppression circuit, which includes the following process:

[0034] Step S10: When the power supply is turned on, the voltage of the first capacitor C1 is 0, and the voltage across the third resistor R3 is relatively high. After voltage division by the fifth resistor R5 and the sixth resistor R6, the first transistor V1 is turned on, thereby lowering the gate voltage of the first field effect transistor Q1, so that the first field effect transistor Q1 remains in the off state; at this time, the input power charges the first capacitor C1 through the third resistor R3, achieving the effect of suppressing the power-on impact current;

[0035] Step S20: As the voltage of the first capacitor C1 increases, the voltage across the third resistor R3 gradually decreases. When the voltage divided by the third resistor R3 is lower than the conduction threshold voltage of the first transistor V1, the first transistor V1 is cut off, and the input power charges the second capacitor C2 through the first resistor R1, that is, the gate voltage of the first field effect transistor Q1 increases to achieve delayed conduction of the first field effect transistor Q1, completing the power supply power-on process; after the power-on startup is completed, the first capacitor C1 and the turned-on first field effect transistor Q1 are connected in series to the power supply circuit;

[0036] Step S30: When the power input is over-voltage, power-off and restarted, or repeatedly turned on, the voltage between the drain and source of the first field effect tube Q1 is relatively large, and the first triode V1 is turned on after the voltage is divided by the fifth resistor R5 and the sixth resistor R6, and the second capacitor C2 is quickly discharged through the first diode D1, and the gate voltage of the first field effect tube Q1 is pulled down, so that the first field effect tube Q1 is quickly restored to the off state; at the same time, the charge on the parasitic capacitor of the first field effect tube Q1 is quickly discharged through the third diode D3, ensuring that the first field effect tube Q1 remains in the off state; the input voltage difference charges the first capacitor C1 through the third resistor R3, so as to achieve the effect of suppressing transient impact current, and then returns to the state of step S20;

[0037] Step S40: When the power supply circuit flows through the surge current, the voltage difference between the two ends of the detection resistor, that is, the eighth resistor R8, rises. If it exceeds the set threshold value, the voltage difference passes through the ninth resistor R9 and the tenth resistor R 10After voltage division, the second transistor V2 is turned on, and the second capacitor C2 is quickly discharged through the second diode D2, thereby lowering the gate voltage of the first field effect transistor Q1, so that the first field effect transistor Q1 is quickly restored to the off state; at the same time, the charge on the parasitic capacitor of the first field effect transistor Q1 is quickly discharged through the third diode D3, ensuring that the first field effect transistor Q1 remains in the off state; the input voltage difference charges the first capacitor C1 through the third resistor R3, thereby achieving the effect of suppressing transient impact current, and then returns to the state of step S20.

[0038] The large-capacitor impact current suppression circuit and method provided by the present application overcome the inherent defect of the existing impact current suppression circuit that can only suppress the startup impact current, so that the suppression circuit can suppress the impact current caused by short-term repeated startup or voltage transients, power failure restart and other power supply compatibility tests. At the same time, the large-capacitor impact current suppression circuit of the present application monitors the input voltage and current to ensure that when a quantity suddenly changes, the field effect tube is turned off in a timely and effective manner, and the power resistor is cut in to suppress the impact current.

[0039] In addition, the large-capacitor surge current suppression circuit of the present application has strong compatibility with the capacitance of the energy storage capacitor and whether it is started with load. The entire surge current suppression circuit has strong compatibility and can be generally suitable for various occasions requiring current suppression. Due to the simplified structure, the large-capacitor surge current suppression circuit of the present application has fewer power components and complex components, thereby reducing the complexity of the surge current suppression circuit, reducing the circuit volume and cost, and improving the reliability of the circuit and system.

[0040] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A large capacitor surge current suppression circuit, characterized in that: It includes an inhibition zone circuit, a voltage control zone circuit and a current control zone circuit, wherein: The suppression zone circuit includes a first field effect transistor Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a third diode D3 and a fourth diode D4. One end of the first resistor R1 and the first capacitor C1 is connected to the input positive terminal V in+ and the positive output terminal V out+ connected, one end of the second resistor R2, the anode of the fourth diode D4, one end of the second capacitor C2, one end of the third capacitor C3, the source of the first field effect transistor Q1 and one end of the third resistor R3 are connected to the negative output terminal V out- The other end of the second resistor R2, the cathode of the fourth diode D4 and the other end of the second capacitor C2 are connected to the other end of the resistor R1, both ends of the fourth resistor R4 are connected to both ends of the third capacitor C3, and the other end of the third resistor R3 is connected to the other end of the first capacitor C1; The voltage control area circuit includes a first transistor V1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a first diode D1, wherein the anode of the first diode D1 is connected to the other end of the second capacitor C2 in the suppression area circuit, one end of the fifth resistor R5 is connected to the drain of the first field effect transistor Q1 in the suppression area circuit, the cathode of the first diode D1 is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is connected to the collector of the first transistor V1, the other end of the fifth resistor R5 is connected to the base of the first transistor V1 and one end of the sixth resistor R6, and the other end of the sixth resistor R6 and the emitter of the first transistor V1 are connected to the output negative terminal V out- ; The current control area circuit includes a second transistor V2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 11th resistor R 11 The second diode D2 has an anode connected to the other end of the second capacitor C2 in the suppression zone circuit, and a cathode connected to the eleventh resistor R 11 One end is connected to the eleventh resistor R 11 The other end is connected to the collector of the second transistor V2, and the tenth resistor R 10 The eighth resistor R8 is connected across the negative input terminal V in- With the negative output terminal V out- One end of the ninth resistor R9 is connected to the collector of the second transistor V2, and the other end is connected to the negative output terminal V out- connect.

2. The large capacitor surge current suppression circuit according to claim 1, characterized in that: The first transistor V1 and the second transistor V2 are both NPN transistors.

3. The large capacitor surge current suppression circuit according to claim 1 or 2, characterized in that: The first field effect transistor Q1 is an N-channel MOS transistor.

4. A method for current suppression using the large capacitor surge current suppression circuit as claimed in any one of claims 1 to 3, characterized in that: The method comprises: Step S10: When the power supply is turned on, the voltage of the first capacitor C1 is zero, and the voltage across the third resistor R3 is higher than a predetermined value. After voltage division by the fifth resistor R5 and the sixth resistor R6, the first transistor V1 is turned on, thereby lowering the gate voltage of the first field effect transistor Q1, so that the first field effect transistor Q1 remains in the off state. At this time, the input power charges the first capacitor C1 through the third resistor R3, thereby suppressing the power-on impact current; Step S20: As the voltage of the first capacitor C1 increases, the voltage across the third resistor R3 gradually decreases. When the divided voltage of the third resistor R3 is lower than the conduction threshold voltage of the first transistor V1, the first transistor V1 will be cut off, and the power supply charges the second capacitor C2 through the first resistor R1. The gate voltage of the first field effect transistor Q1 increases, and the delayed conduction of the first field effect transistor Q1 is realized, and the power supply power-on process is completed. After the power-on startup is completed, the first capacitor C1 and the turned-on first field effect transistor Q1 are connected in series to the power supply circuit; Step S30: When a power input failure occurs, the drain-source voltage of the first field effect transistor Q1 is greater than a predetermined value, and the first triode V1 is turned on after voltage division by the fifth resistor R5 and the sixth resistor R6, and the second capacitor C2 is quickly discharged through the first diode D1, and the gate voltage of the first field effect transistor Q1 is pulled down, so that the first field effect transistor Q1 is quickly restored to the off state; at the same time, the charge on the parasitic capacitor of the first field effect transistor Q1 is quickly discharged through the third diode D3, ensuring that the first field effect transistor Q1 remains in the off state, and the input voltage difference charges the first capacitor C1 through the third resistor R3, so as to suppress transient impact current, and then return to the state of step S20; Step S40: When there is an inrush current in the power supply circuit, the voltage difference between the eighth resistor R8 increases. If it exceeds the set threshold value, the voltage difference passes through the ninth resistor R9 and the tenth resistor R 10 After voltage division, the second transistor V2 is turned on, and the second capacitor C2 is quickly discharged through the second diode D2, so as to lower the gate voltage of the first field effect transistor Q1, so that the first field effect transistor Q1 is quickly restored to the off state. At the same time, the charge on the parasitic capacitor of the first field effect transistor Q1 is quickly discharged through the third diode D3 to ensure that the first field effect transistor Q1 remains in the off state. The input voltage difference charges the first capacitor C1 through the third resistor R3, so as to suppress transient impact current, and then return to the state of step S20.

5. The method according to claim 4, characterized in that The faults include power overvoltage, power failure and restart, or repeated startup.

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