Synchronous control module and related control circuit and method

Abstract

The invention provides a synchronous control module applied to a switching converter and a related control circuit and method. The synchronous control module comprises a phase-locked loop, a voltage and current conversion circuit and a first feedback loop. When the switching converter works in a synchronous mode, the phase-locked loop receives an external clock signal and a control signal, compares the phases of the external clock signal and the control signal and provides a voltage signal at the output end of the phase-locked loop, and at the moment, the voltage at the output end of the phase-locked loop represents the phase difference between the external clock signal and the control signal. The voltage and current conversion circuit converts the voltage of the output end of the phase-locked loop into a difference current signal. When the switching converter works in an asynchronous mode, the first feedback loop adjusts the voltage of the output end of the phase-locked loop to a first voltage value according to the difference current signal and the reference signal. The control circuit is high in dynamic response speed during mode switching, large frequency change is avoided, and stable transient response can be achieved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a synchronous control module applied to a switching converter and a related control circuit and method. Background Art

[0002] In some chip designs, external clocks can be introduced for synchronization control according to different application scenarios, or internal clocks or other parameters can be used to complete periodic control without external clocks. For example, in some applications of constant on / off time control (COT), such as Figure 1 The COT-controlled BUCK switch converter shown in the figure. If synchronous control is not required, the control circuit only needs to complete periodic control through the fixed on or off time set inside the COT control circuit; if an external clock signal CLK needs to be introduced for synchronous control, a phase-locked loop needs to be introduced to lock the clock signal CLK and the control signal PWM for frequency and phase synchronization. Specifically, the phase-locked loop compares the phases of the clock signal CLK and the control signal PWM and generates a voltage difference signal Vco. The voltage difference signal Vco is sent to the COT control circuit to adjust the phase of the control signal PWM, and finally makes the control signal PWM and the clock signal CLK have the same frequency and phase.

[0003] When the external clock CLK is introduced for synchronization, it takes some time to establish the phase-locked loop and switch the control circuit. During this period, the phase error signal Vco changes greatly, causing the inductor current to fluctuate greatly. Conversely, when exiting the clock synchronization, if no control is performed, the large fluctuation of the phase error signal Vco will also cause a large change in the inductor current. This situation should be avoided in circuit design. Summary of the invention

[0004] The purpose of the present disclosure is to provide a synchronous control module applied to a switching converter and a related control circuit and method to solve the problems in the related art.

[0005] In order to achieve the above-mentioned purpose, according to the first aspect of the embodiment of the present disclosure, a synchronous control module is provided. The synchronous control module is applied to a switching converter, the switching converter includes at least one power switch, and the switching converter has a first working mode and a second working mode. The synchronous control module includes a phase-locked loop, a voltage-current conversion circuit and a first feedback loop. When the switching converter operates in the first working mode, the phase-locked loop is not enabled. When the switching converter operates in the second working mode, the phase-locked loop receives an external clock signal and a control signal, compares the phase of the external clock signal and the control signal, and provides a voltage signal at the output end of the phase-locked loop. At this time, the voltage at the output end of the phase-locked loop represents the phase difference between the external clock signal and the control signal, wherein the control signal is used to control the conduction and shutdown of the at least one power switch. The voltage-current conversion circuit is coupled to the output end of the phase-locked loop to receive the voltage at the output end of the phase-locked loop, and converts the voltage at the output end of the phase-locked loop into a differential current signal and outputs it at its output end, wherein the differential current signal is proportional to the voltage at the output end of the phase-locked loop. The input end of the first feedback loop is coupled to the output end of the voltage conversion circuit to receive the differential current signal, and the output end of the first feedback loop is coupled to the output end of the phase-locked loop. When the switching converter operates in the first operating mode, the first feedback loop generates a first adjustment signal based on the differential current signal and the reference signal, wherein the first adjustment signal is used to adjust the voltage at the output end of the phase-locked loop to a first voltage value.

[0006] According to the second aspect of the embodiment of the present disclosure, a control circuit is provided, the control circuit includes the above-mentioned synchronous control module, a constant on or off time generating circuit, a comparison module and a logic circuit. When the switching converter operates in the second working mode, the constant on or off time generating circuit generates a constant on or off time signal according to the difference current signal, the input voltage and the output voltage of the switching converter. The comparison module receives a feedback signal representing the output voltage of the switching converter, and generates a comparison signal according to the feedback signal and the reference voltage signal. The logic circuit receives the constant on or off time signal and the comparison signal, and performs a logic operation on the constant on or off time signal and the comparison signal to generate a control signal, wherein the control signal controls the on and off of at least one power switch, and the input voltage is converted into an output voltage.

[0007] According to the third aspect of the embodiment of the present disclosure, a synchronous control method is provided. The synchronous control method includes: when the switching converter operates in the first working mode, the phase-locked loop is not enabled; when the switching converter operates in the second working mode, the phase-locked loop is enabled to receive an external clock signal and a control signal, and the phase of the external clock signal and the control signal are compared, and a voltage signal is provided at the output end of the phase-locked loop, at which time the voltage at the output end of the phase-locked loop represents the phase difference between the external clock signal and the control signal, and the control signal is used to control the on and off of the at least one power switch; the voltage at the output end of the phase-locked loop is converted into a differential current signal, wherein the differential current signal is proportional to the voltage at the output end of the phase-locked loop; when the switching converter operates in the first working mode, the phase-locked loop does not receive an external clock signal, adopts a first feedback loop to receive the differential current signal, and generates a first adjustment signal according to the differential current signal and a reference signal, wherein the first adjustment signal is used to adjust the voltage at the output end of the phase-locked loop to a first voltage value.

[0008] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0010] Figure 1 It is a circuit diagram of a switching converter with a clock synchronization function in the prior art;

[0011] Figure 2 is a circuit diagram of a switching converter with a clock synchronization function according to an exemplary embodiment;

[0012] Figure 3 is a circuit schematic diagram of a voltage-current conversion circuit according to an exemplary embodiment;

[0013] Figure 4 is a circuit schematic diagram of a first feedback loop according to an exemplary embodiment;

[0014] Figure 5 is a circuit schematic diagram of a first feedback loop according to yet another exemplary embodiment;

[0015] Figure 6 is a schematic diagram of an enable signal generating circuit according to an exemplary embodiment;

[0016] Figure 7 According to an exemplary embodiment Figure 6 Waveform diagram of the parameters in ;

[0017] Figure 8 is a schematic diagram of a synchronization control module according to yet another exemplary embodiment;

[0018] Fig. 9 is a circuit schematic diagram of a second feedback loop according to an exemplary embodiment;

[0019] Fig.10 is a circuit schematic diagram of a loop control module according to an exemplary embodiment;

[0020] Fig.11 The present invention is a flow chart of a synchronous control method according to an exemplary embodiment. DETAILED DESCRIPTION

[0021] Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described here are only used for illustration and are not intended to limit the present invention. In the following detailed description of the present invention, a large number of details are described in order to better understand the present invention. However, it will be appreciated by those skilled in the art that the present invention can be implemented without these specific details. In order to clearly describe the present invention, the detailed description of some specific structures and functions is simplified herein. In addition, similar structures and functions that have been described in detail in some embodiments will not be repeated in other embodiments. Although the various terms of the present invention are described one by one in conjunction with specific exemplary embodiments, these terms should not be construed as being limited to the exemplary implementations described herein.

[0022] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" that appear in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, particular features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. It should be understood that when an "element" is said to be "connected to" or "coupled" to another element, it may be directly connected or coupled to another element or there may be an intermediate element. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The same reference numerals indicate the same element. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0023] Figure 2FIG. 1 is a circuit diagram of a switching converter 100 with a clock synchronization function according to an exemplary embodiment. Figure 2 As shown, the switching converter 100 includes a switching circuit 10 and a control circuit.

[0024] exist Figure 2 In the illustrated embodiment, the switch circuit 10 is illustrated as a buck BUCK topology structure formed by connecting a main switch tube HS, a freewheeling switch tube LS, an inductor, and a capacitor. Among them, the main switch tube HS and the freewheeling switch tube LS are illustrated as N-type metal semiconductor field effect transistors (NMOS). It can be understood that this does not limit the types of the main switch tube HS and the freewheeling switch tube LS, which may also include any suitable controllable semiconductor switch devices such as PMOS, JFET, IGBT, etc. Similarly, the switch circuit may not be limited to the BUCK topology, but may also be other suitable switch circuit topologies.

[0025] The switching converter 100 has a first operating mode and a second operating mode. Generally, the first operating mode refers to an operating mode when there is no external clock signal CLK input; the second operating mode refers to an operating mode of the switching converter after the external clock signal CLK is input. In one embodiment, the control circuit detects whether there is an external clock signal CLK input, and generates a synchronization enable signal Sync_en accordingly. Generally, the synchronization enable signal Sync_en is a logic high-low level signal. When there is an external clock signal CLK input, the synchronization enable signal Sync_en is valid (for example, a logic high level); when there is no external clock signal CLK input, the synchronization enable signal Sync_en is invalid (for example, a logic low level).

[0026] The control circuit includes a loop control module 20 and a synchronization control module 30 .

[0027] The loop control module 20 is used to generate a control signal PWM, wherein the control signal PWM is used to control the on and off of the main switch tube HS and the freewheeling switch tube LS. In one embodiment, the "on and off" of the control switch refers to the switching frequency and on time of the control switch, wherein the switching frequency is also the operating frequency, which refers to the number of times the switch is turned on and off in a unit time.

[0028] After the switching converter switches from the first working mode to the second working mode, the synchronous control module 30 receives the control signal PWM and the external clock signal CLK, and generates a difference current signal Ico according to the control signal PWM and the external clock signal CLK, wherein the difference current signal Ico represents the phase difference between the control signal PWM and the external clock signal CLK.

[0029] When the switching converter operates in the first operating mode, the loop control module 20 will generate a control signal PWM according to the feedback signal VFB. The feedback signal VFB represents the output voltage VOUT of the switching converter 100. When the switching converter operates in the second operating mode, the loop control module 20 will generate a control signal PWM according to the feedback signal VFB and the difference current signal Ico. The loop control module can select different circuit structures according to different control methods adopted. For example, the control method of the loop control module may include constant on or off time control, valley current control, etc.

[0030] exist Figure 2 In the illustrated embodiment, the synchronous control module 30 includes a phase-locked loop 11 , a voltage-current conversion circuit 12 , and a first feedback loop 13 .

[0031] A phase-locked loop, when the switching converter operates in a first operating mode, the phase-locked loop is not enabled, and when the switching converter operates in a second operating mode, the phase-locked loop receives an external clock signal and a control signal, compares the phases of the external clock signal and the control signal, and provides a voltage signal at the output end of the phase-locked loop, at which time the voltage at the output end of the phase-locked loop represents the phase difference between the external clock signal and the control signal, wherein the control signal is used to control the on and off of at least one power switch.

[0032] When the switching converter 100 operates in the first operating mode, there is no clock signal CLK input, and the phase-locked loop 11 is not enabled. When the switching converter 100 operates in the second operating mode, the phase-locked loop 11 receives the external clock signal CLK and the control signal PWM, and compares the phases of the external clock signal CLK and the control signal PWM. During this period, the voltage Vco at the output end of the phase-locked loop represents the phase difference between the external clock signal CLK and the control signal PWM.

[0033] The voltage-current conversion circuit 12 has an input terminal and an output terminal. The input terminal of the voltage-current conversion circuit 12 receives the voltage Vco of the output terminal of the phase-locked loop. The voltage-current conversion circuit 12 converts the voltage Vco of the output terminal of the phase-locked loop into a differential current signal Ico and outputs it at its output terminal. The differential current signal Ico is proportional to the voltage Vco of the output terminal of the phase-locked loop.

[0034] The first feedback loop 13 has an input terminal and an output terminal. The input terminal of the first feedback loop 13 is coupled to the output terminal of the voltage-current conversion circuit 12 to receive the differential current signal Ico. The output terminal of the first feedback loop 13 is coupled to the output terminal of the phase-locked loop 11, that is, the input terminal of the voltage-current conversion circuit 12. When the switching converter 100 operates in the first operating mode, the first feedback loop 13 generates a first adjustment signal Reg1 according to the differential current signal Ico and the reference signal, wherein the first adjustment signal Reg1 is used to adjust the voltage Vco at the output terminal of the phase-locked loop to a first voltage value. It can be understood that if there is no adjustment of the first feedback loop 13, because the phase-locked loop 11 is not enabled, the voltage Vco at the output terminal of the phase-locked loop is originally zero, and after adjustment by the first feedback loop 13, the voltage Vco at the output terminal of the phase-locked loop is pulled up to the first voltage value. In this embodiment, when the switching converter 100 switches to the second operating mode, that is, the phase-locked loop 11 receives the clock signal CLK, at this time, the output end of the first feedback loop 13 is disconnected from the input end of the voltage-current conversion circuit 12. At this time, the value of the voltage Vco at the output end of the phase-locked loop is determined by the phase difference between the external clock signal CLK and the control signal PWM, and the value of the voltage Vco at the output end of the phase-locked loop will rise from the first voltage value to the second voltage value, wherein the second voltage value changes with the change of the phase difference between the clock signal CLK and the control signal PWM.

[0035] Figure 3 1 is a circuit schematic diagram of a voltage-current conversion circuit 12 according to an exemplary embodiment. As shown in the figure, the voltage-current conversion circuit 12 includes a first resistor R1, a first transistor M1 and a first current mirror circuit 121.

[0036] The first transistor M1 has a first terminal, a second terminal and a control terminal. The first terminal is connected to the reference ground through the first resistor R1 , and the control terminal serves as an input terminal of the voltage-current conversion circuit 12 to receive the voltage Vco of the phase-locked loop output terminal.

[0037] The first current mirror circuit 121 has a power supply end, a first end, and a second end. The power supply end of the first current mirror circuit 121 receives a power supply voltage signal VCC, and the first end of the first current mirror circuit 121 is coupled to the second end of the first switch M1 to generate a first current I1. The first current mirror circuit 121 mirrors the first current I1 and generates a difference current signal Ico at the second end of the first current mirror circuit 121. The difference current signal Ico is proportional to the first current I1, Ico=K0×I1, K0 is a proportionality coefficient, and its value is related to the on-resistance value of each of the transistors M11 and M12 in the first current mirror circuit 121. In one embodiment, K0 is equal to 1.

[0038] It should be noted that in some embodiments, according to design requirements, the difference current signal Ico may include several currents that are proportional to each other. Figure 3 The first current mirror circuit 121 shown further includes transistors M13, M14 and M15, the drain of transistor M13 is used to provide a first mirror current Ico1, the drain of transistor M14 is used to provide a second mirror current Ico2, and the drain of transistor M15 is used to provide a third mirror current Ico3. Wherein, Ico1 = K1 × I1, Ico2 = K2 × I1, Ico3 = K3 × I1, K1, K2 and K3 are proportional coefficients, and their values ​​are related to the on-resistance values ​​of the corresponding transistors. In this embodiment, the first mirror current Ico1, the second mirror current Ico2 and the third mirror current Ico3 are all mirror images of the first current I1, and can be used to characterize the voltage Vco at the output end of the phase-locked loop, so they can all be regarded as differential current signals Ico. In one embodiment, K1, K2 and K3 can all be equal to 1, or can be set to unequal values ​​according to actual application scenarios.

[0039] Figure 4 1 is a circuit diagram of the first feedback loop 13 according to an exemplary embodiment. As shown in the figure, the first feedback loop includes a first reference current source, a second current mirror circuit 131 and a second transistor M2.

[0040] The first reference current source is used to provide a reference signal, and the reference current source has a first terminal and a second terminal, wherein the first terminal receives the difference current signal Ico, and the second terminal is connected to the reference ground. In this embodiment, the reference signal is shown as a reference current IREF1.

[0041] The second current mirror circuit 131 has a power supply terminal, a first terminal, and a second terminal. The power supply terminal of the second current mirror circuit 131 receives a power supply voltage signal VCC, the first terminal of the second current mirror circuit 131 is coupled to the first terminal of the first reference current source, the second terminal of the second current mirror circuit 131 is coupled to the first terminal of the second transistor M2, and the second current mirror circuit 131 mirrors the current Id1 on the first terminal to generate a first regulation signal Reg1 at the second terminal.

[0042] The second transistor M2 has a first end, a second end and a control end, the first end of the second transistor M2 is coupled to the second end of the second current mirror circuit 131, the second end of the second transistor M2 is coupled to the control end of the first transistor M1, and the control end of the second transistor M2 receives the synchronization enable signal Syn_en, wherein, when the synchronization enable signal Syn_en controls the switching converter 100 to work in the first working mode, the synchronization enable signal Syn_en controls the second transistor M2 to be turned on, and the first adjustment signal Reg1 will be sent to the control end of the first transistor M1 to pull the value of the voltage Vco at the output end of the phase-locked loop from zero to the first voltage value. It can be understood that when the synchronization enable signal Syn_en controls the switching converter 100 to work in the second working mode, the synchronization enable signal Syn_en controls the second transistor M2 to be turned off, and the first adjustment signal Reg1 is no longer sent to the control end of the first transistor M1.

[0043] exist Figure 4 In the illustrated embodiment, when the switching converter 100 operates in the first operating mode, that is, there is no external clock signal CLK input, the phase-locked loop is not enabled, and if there is no first adjustment signal Reg1, the value of the voltage Vco at its output end is zero; after the first adjustment signal Reg1 is sent to the gate of the first transistor M1, the voltage Vco at the output end of the phase-locked loop is pulled up to the first voltage value. When the switching converter 100 switches from the first operating mode to the second operating mode, that is, the external clock signal CLK is input, the voltage Vco at the output end of the phase-locked loop output by the phase-locked loop 11 will be pulled up to the second value. Since the voltage Vco at the output end of the phase-locked loop has been pulled up to the first voltage value in the first operating mode, after entering the second operating mode, the voltage Vco at the output end of the phase-locked loop only needs to be increased from the first voltage value to the second voltage value, and the dynamic response speed is fast. At the same time, the frequency of the switching converter will transition from the frequency corresponding to the first voltage value to the frequency of the clock signal CLK required for synchronization, thereby avoiding a large change in frequency and achieving a relatively smooth transient response. By properly setting different reference currents IREF1, different first voltage values ​​can be set.

[0044] Figure 5 FIG. 1 is a circuit schematic diagram of the first feedback loop 13 according to another exemplary embodiment. As shown in the figure, the first feedback loop 13 includes a current error amplifier 132 and a second transistor M2.

[0045] The current error amplifier 132 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the current error amplifier 132 receives a reference signal, and the second input terminal of the current error amplifier 132 receives a difference current signal Ico. The current error amplifier 132 amplifies the difference between the two to generate a first regulation signal Reg1 at its output terminal. In this embodiment, the reference signal is illustrated as a reference current IREF2.

[0046] The second transistor M2 has a first end, a second end and a control end, the first end of the second transistor M2 is coupled to the output end of the current error amplifier 132, the second end of the current error amplifier 132 is coupled to the control end of the first transistor M1, and the control end of the second transistor M2 receives the synchronization enable signal Syn_en, wherein, when the synchronization enable signal Syn_en controls the switching converter 100 to work in the first working mode, the synchronization enable signal Syn_en controls the second transistor M2 to turn on, and the first regulation signal Reg1 will be sent to the control end of the first transistor M1. It can be understood that when the synchronization enable signal Syn_en controls the switching converter 100 to work in the second working mode, the synchronization enable signal Syn_en controls the second transistor M2 to turn off, and the first regulation signal Reg1 is no longer sent to the control end of the first transistor M1.

[0047] and Figure 4 The working principle of the embodiment shown is similar. When the switching converter 100 works in the first working mode, the first regulation signal Reg1 pulls the voltage Vco at the output end of the phase-locked loop to a first voltage value. When the switching converter 100 switches from the first working mode to the second working mode, the voltage Vco at the output end of the phase-locked loop will be pulled up from the first voltage value to the second voltage value. Therefore, the dynamic response speed is fast, and a relatively smooth transient response can be achieved. By reasonably setting different reference currents IREF2, different first voltage values ​​can be set.

[0048] In the embodiment disclosed in the present invention, the synchronization control module further includes an enable signal generating circuit. Figure 6 is a schematic diagram of an enable signal generating circuit according to an exemplary embodiment. Figure 7 It is the waveform diagram of the external clock signal CLK and the synchronization enable signal Syn_en. Figure 6 In the illustrated embodiment, the input end of the enable signal generating circuit is coupled to the input port of the external clock signal CLK, so as to detect whether the external clock signal CLK is input and generate the synchronization enable signal Syn_en.

[0049] In some applications, when the rising edge of the clock signal CLK arrives, the synchronization enable signal Syn_en synchronously changes to a logic high level. At the same time, at the first falling edge of the clock signal CLK (t0), the enable signal generating circuit simultaneously starts a preset detection time. In the detection time period P1 from t0 to t1, if the enable signal generating circuit continues to detect continuous high pulse falling edges, the synchronization enable signal Syn_en remains in a logic high level state; if the enable signal generating circuit does not continue to detect a high pulse falling edge, the synchronization enable signal Syn_en changes to a logic low level state. This can avoid misjudgment caused by other interference signals. Figure 7 As shown, in the detection time period P1 during t0-t1, the enable signal generating circuit continuously detects high pulses, so the synchronization enable signal Syn_en is at a high level. At t2, the external clock signal CLK disappears, but in the detection time period P2 equal to P1, the synchronization enable signal Syn_en still maintains a high level, until the detection time period P2 ends (t3) and the falling edge of the next high pulse is still not detected, the synchronization enable signal Syn_en becomes low, and the switching converter 100 enters the first working mode. In the detection time period P2 during t2-t3, since the switching converter 100 is in the second working mode, the output end of the first feedback loop 13 is still disconnected from the output end of the phase-locked loop 11, and the first regulation signal Reg1 cannot adjust the voltage Vco at the output end of the phase-locked loop to the first voltage value. During this period, the external clock signal CLK has disappeared, so the voltage Vco at the output of the phase-locked loop will drop to zero. After the synchronization enable signal Syn_en becomes low, the switching converter 100 switches to the first working mode, the first feedback loop 13 is connected, and the voltage Vco at the output of the phase-locked loop recovers from zero to the first voltage value. In other words, during the period when the switching converter 100 switches from the second working mode to the first working mode, the voltage Vco at the output of the phase-locked loop needs to decrease from the second voltage value to zero, and then recover from zero to the first voltage value, and a smooth transient response cannot be achieved.

[0050] To this end, the present invention further provides another embodiment, such as Figure 8 As shown. Figure 8 In the illustrated embodiment, the synchronous control module 30 further includes a second feedback loop 14. The second feedback loop 14 has an input end and an output end. The input end of the second feedback loop 14 is coupled to the output end of the voltage-current conversion circuit 12 to receive the differential current signal Ico. The output end of the second feedback loop 14 is coupled to the input end of the voltage-current conversion circuit 12. During the period from when the external clock signal CLK disappears to when the switching converter 100 switches to the first working mode, the second feedback loop 14 generates a second adjustment signal Reg2 according to the differential current signal Ico. The second adjustment signal Reg2 adjusts the voltage Vco at the output end of the phase-locked loop from the second voltage value to the third voltage value. It can be understood that when the switching converter 100 switches to the first working mode, the output end of the second feedback loop 14 is disconnected from the input end of the voltage-current conversion circuit 12.

[0051] exist Figure 8 In the embodiment shown, the third voltage value may be equal to or less than the second voltage value. In one embodiment, the second feedback loop 14 is used to generate a voltage between the time when the external clock signal CLK disappears and the time when the switching converter 100 switches to the first working mode (for example, Figure 7The detection time period P2 in the phase-locked loop maintains the voltage Vco at the output end of the phase-locked loop at the second voltage value, at which time, the third voltage value may be equal to or slightly less than the second voltage value. In another embodiment, the second feedback loop 14 is used to control the voltage Vco at the output end of the phase-locked loop to slowly decrease from the second voltage value to the third voltage value during the time when the external clock signal CLK disappears to the time when the switching converter 100 switches to the first working mode, so as to achieve a smooth transient response. The third voltage value is related to the duration of the detection time period P2, the second voltage value of the voltage Vco at the output end of the phase-locked loop, and the parameter setting in the second feedback loop 14, and the third voltage value may be greater than the first voltage value or less than the first voltage value. When the detection time period P2 ends, the voltage Vco at the output end of the phase-locked loop will be directly adjusted from the third voltage value to the first voltage value, without having to decrease from the second voltage value to zero during the mode switching period, and then recover from zero to the first voltage value.

[0052] Fig. 9 FIG. 1 is a circuit diagram of the second feedback loop 14 according to an exemplary embodiment. In one embodiment, the difference current signal is shown as including Figure 3 In the illustrated embodiment, the first mirror current signal Ico1 and the second mirror current signal Ico2 are shown in FIG.

[0053] The third current mirror circuit 141 has a ground terminal, a first terminal, and a second terminal. The ground terminal of the third current mirror circuit 141 is connected to the reference ground. The first terminal of the third current mirror circuit 141 receives the first mirror current Ico1. The third current mirror circuit 141 mirrors the first mirror current Ico1 at its first terminal to generate a second current I2 at its second terminal. During the period from when the external clock signal CLK disappears to when the switching converter switches to the first working mode (for example, Figure 7 During the detection time period P2), the third current mirror circuit 141 controls the second current I2 to remain unchanged or decrease slowly.

[0054] exist Fig. 9 In the further embodiment shown, the third current mirror circuit 141 is illustrated as including an NMOS tube M31, an NMOS tube M32 and a capacitor C1. The drain of the NMOS tube M31 is coupled to the first current mirror circuit 121 to receive the first mirror current Ico1, the source of the NMOS tube M31 is connected to the reference ground, and the control end of the NMOS tube M31 is connected to its drain. The drain of the NMOS tube M32 provides a second current I2 as the second end of the third current mirror, the source of the NMOS tube M32 is connected to the reference ground, and the control end of the NMOS tube M32 is connected to the control end of the NMOS tube M31. The capacitor C1 is coupled between the control end of the NMOS tube M32 and the reference ground.

[0055] In one embodiment, when the first mirror current Ico1 suddenly decreases, due to the presence of capacitor C1, the gate-source voltage of the NMOS tube M32 can be maintained for a certain period of time, so the second current I2 can remain unchanged for a certain period of time. Considering the presence of parasitic resistance on the line, the voltage on the capacitor C1 will decrease over time, and the second current I2 will also decrease. In another embodiment, the third current mirror circuit 141 also includes a second resistor R2, and the second resistor R2 is coupled between the control end of the NMOS tube M31 and the control end of the NMOS tube M32. When the first mirror current Ico1 suddenly decreases, due to the presence of capacitor C1 and the second resistor R2, the gate-source voltage of the NMOS tube M32 slowly decreases, and the second current I2 will slowly decrease.

[0056] The fourth current mirror circuit 142 has a power supply terminal, a first terminal, and a second terminal. The power supply terminal of the fourth current mirror circuit 142 receives the power supply voltage signal VCC, the first terminal of the fourth current mirror circuit 142 is coupled to the second terminal of the third current mirror 141, and the common node A of the first terminal of the fourth current mirror circuit 142 and the second terminal of the third current mirror 141 also receives the second mirror current Ico2. During the period from when the external clock signal disappears to when the switching converter switches to the first working mode, the fourth current mirror circuit 142 mirrors the current Id2 on its first terminal to generate the second regulation signal Reg2 at its second terminal.

[0057] exist Fig. 9 In the figure, the fourth current mirror circuit 142 is shown to include a PMOS tube M41 and a PMOS tube M42. The drain of the PMOS tube M41 is coupled to the first current mirror circuit 121 to receive the second mirror current Ico2, the source of the PMOS tube M41 is connected to the power supply voltage signal VCC, and the control end of the PMOS tube M41 is connected to the drain. The drain of the PMOS tube M42 generates a second regulation signal Reg2, the source of the PMOS tube M42 is connected to the power supply voltage signal VCC, and the control end of the PMOS tube M42 is connected to the control end of the PMOS tube M41.

[0058] When the switching converter operates in the second operating mode, the second current I2 is set to be smaller than the second mirror current Ico2. In one embodiment, the first mirror current signal Ico1 can be set to be smaller than the second mirror current signal Ico2, and the third current mirror circuit 141 performs a 1:1 mirroring on the first mirror current signal Ico1 to generate the second current I2 so that the second current I2 is smaller than the second mirror current Ico2. During this period, the current Id2 is used to raise the gate voltage of the PMOS tube M41 and the PMOS tube M42, so that the PMOS tube M41 and the PMOS tube M42 are turned off, so that the drain of the PMOS tube M42 is disconnected from the control end of the first transistor M1.

[0059] When the external clock signal CLK disappears, and the switching converter 100 is still operating in the second working mode, the voltage Vco at the output of the phase-locked loop will drop rapidly from the second voltage value, and the first mirror current Ico1 will also decrease rapidly, while the second current I2 will remain unchanged or slowly decrease within a certain period of time due to the holding effect of the third current mirror circuit 141. Therefore, the current Id2 is reversed and used to pull down the gate voltage of the PMOS tube M41 and the PMOS tube M42 to control the conduction of the PMOS tube M41 and the PMOS tube M42, thereby generating a second adjustment signal Reg2 at the drain of the PMOS tube M42. The second adjustment signal Reg2 maintains the voltage Vco at the output of the phase-locked loop at the second voltage value, or adjusts the voltage Vco at the output of the phase-locked loop to slowly decrease from the second voltage value to the third voltage value.

[0060] When the synchronization enable signal Sync_en becomes low and the switching converter 100 enters the first operation mode, the first feedback loop 13 starts to operate, and the voltage Vco at the output terminal of the phase-locked loop is adjusted from the third voltage value to the first voltage value.

[0061] therefore, Figure 8 and Fig. 9 The illustrated embodiment can make the transient response of the switching converter 100 relatively smooth and the dynamic response speed fast during the switching from the second working mode to the first working mode.

[0062] Fig.10 is a circuit schematic diagram of a loop control module according to an exemplary embodiment. Fig.10 The circuit 20 of the loop control module of the sampling COT control is shown in FIG. The loop control module circuit 20 includes a comparison circuit 51 , a constant on or off time generating circuit 52 and a logic circuit 53 .

[0063] The comparison circuit 51 receives the feedback signal VFB, and generates a comparison signal COM according to the feedback signal VFB and a reference voltage signal.

[0064] The constant on-time or off-time generating circuit 52 generates a constant on-time or off-time signal Ton according to the input voltage VIN, the output voltage VOUT and the difference current signal Ico.

[0065] The logic circuit 53 receives the comparison signal COM and the constant on or off time signal Ton, and performs a logic operation on the comparison signal COM and the constant on or off time signal Ton to generate a control signal PWM.

[0066] Fig.11 FIG. 1 is a flow chart of a synchronous control method according to an exemplary embodiment. As shown in the figure, the synchronous control method includes steps S1-S3.

[0067] In step S1, when the switching converter operates in the second operating mode, a phase-locked loop is used to receive an external clock signal CLK and a control signal PWM, and the phases of the external clock signal CLK and the control signal PWM are compared, and a voltage signal is provided at the output end of the phase-locked loop. At this time, the voltage Vco at the output end of the phase-locked loop represents the phase difference between the external clock signal CLK and the control signal PWM, wherein the control signal PWM is used to control the on and off of the at least one power switch; when the switching converter operates in the first operating mode, the phase-locked loop is not enabled.

[0068] In step S2, the voltage Vco at the output end of the phase-locked loop is converted into a difference current signal Ico, wherein the difference current signal Ico is proportional to the voltage Vco at the output end of the phase-locked loop.

[0069] In step S3, when the switching converter operates in the first operating mode, a first feedback loop is used to receive the difference current signal Ico, and a first adjustment signal Reg1 is generated according to the difference current signal Ico and a reference signal REF1, wherein the first adjustment signal Reg1 is used to adjust the voltage Vco at the output end of the phase-locked loop to a first voltage value.

[0070] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, the technical solution of the present disclosure can be subjected to a variety of simple modifications, and these simple modifications all belong to the protection scope of the present disclosure. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations. In addition, the various different embodiments of the present disclosure can also be arbitrarily combined, as long as they do not violate the ideas of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A synchronous control module applied to a switching converter, characterized in that: The switching converter includes at least one power switch, the switching converter has a first working mode and a second working mode, and the synchronization control module includes: A phase-locked loop, when the switching converter operates in the first operating mode, the phase-locked loop is not enabled; when the switching converter operates in the second operating mode, the phase-locked loop receives an external clock signal and a control signal, compares the phases of the external clock signal and the control signal, and provides a voltage signal at an output terminal of the phase-locked loop, at which time the voltage at the output terminal of the phase-locked loop represents the phase difference between the external clock signal and the control signal, wherein the control signal is used to control the on and off of the at least one power switch; A voltage-to-current conversion circuit is coupled to the output terminal of the phase-locked loop to receive the voltage of the output terminal of the phase-locked loop, and converts the voltage of the output terminal of the phase-locked loop into a differential current signal and outputs it at its output terminal, wherein the differential current signal is proportional to the voltage of the output terminal of the phase-locked loop; The first feedback loop has an input end and an output end, the input end of the first feedback loop is coupled to the output end of the voltage conversion circuit to receive the differential current signal, the output end of the first feedback loop is coupled to the output end of the phase-locked loop, when the switching converter operates in the first operating mode, the first feedback loop generates a first adjustment signal according to the differential current signal and the reference signal, wherein the first adjustment signal is used to adjust the output voltage of the phase-locked loop to a first voltage value.

2. The synchronous control module according to claim 1, characterized in that: The voltage-current conversion circuit comprises: a first resistor; A first transistor having a first end, a second end and a control end, wherein the first end of the first transistor is connected to a reference ground via a first resistor, and the control end of the first transistor serves as an input end of a voltage-current conversion circuit to receive a voltage at an output end of a phase-locked loop; The first current mirror circuit has a power supply end, a first end, and a second end. The power supply end of the first current mirror circuit receives a power supply voltage signal. The first end of the first current mirror circuit is coupled to the second end of the first transistor to generate a first current. The first current mirror circuit mirrors the first current and generates a difference current signal at the second end of the first current mirror circuit.

3. The synchronous control module according to claim 2, characterized in that: The first feedback loop comprises: A first reference current source, used for providing the reference signal, the first reference current source having a first end and a second end, the first end of the first reference current source receiving the difference current signal, and the second end of the first reference current source connected to a reference ground; A second current mirror circuit has a power supply end, a first end and a second end, the power supply end of the second current mirror circuit receives a power supply voltage signal, the first end of the second current mirror circuit is coupled to the first end of the first reference current source, and the second current mirror circuit mirrors the current on the first end to generate a first adjustment signal at the second end; The second transistor has a first end, a second end and a control end, the first end of the second transistor is coupled to the second end of the second current mirror circuit, the second end of the second transistor is coupled to the control end of the first transistor, and the control end of the second transistor receives a synchronous enable signal, wherein when the switching converter operates in the second operating mode, the synchronous enable signal controls the second transistor to be disconnected.

4. The synchronous control module according to claim 2, characterized in that: The first feedback loop comprises: A current error amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the current error amplifier receives a reference signal, the second input terminal of the current error amplifier receives a difference current signal, and the current error amplifier amplifies the difference between the two to generate a first adjustment signal at its output terminal; The second transistor has a first end, a second end and a control end, the first end of the second transistor is coupled to the output end of the current error amplifier, the second end of the current error amplifier is coupled to the control end of the first transistor, and the control end of the second transistor receives a synchronous enable signal, wherein when the switching converter operates in the second operating mode, the synchronous enable signal controls the second transistor to be disconnected.

5. The synchronous control module according to claim 1, characterized in that: The voltage-to-current conversion circuit further comprises: The second feedback loop has an input end and an output end. The input end of the second feedback loop is coupled to the output end of the voltage-current conversion circuit to receive the differential current signal. The output end of the second feedback loop is coupled to the input end of the voltage-current conversion circuit. During the period from when the external clock signal disappears to when the switching converter switches to the first working mode, the second feedback loop generates a second adjustment signal according to the differential current signal. The second adjustment signal adjusts the voltage at the output end of the phase-locked loop from the second voltage value to the third voltage value.

6. The synchronous control module according to claim 5, characterized in that: The second voltage value is greater than the first voltage value, and the third voltage value is equal to or less than the second voltage value.

7. The synchronous control module according to claim 5, characterized in that: The difference current signal includes a first mirror current signal and a second mirror current signal, the first mirror current signal and the second mirror current signal are both in a mirror relationship with the first current, and the second feedback loop includes: A third current mirror circuit has a ground terminal, a first terminal, and a second terminal. The ground terminal of the third current mirror circuit is connected to a reference ground. The first terminal of the third current mirror circuit receives a first mirror current. The third current mirror circuit mirrors the first mirror current at its first terminal to generate a second current at its second terminal. During a period from when the external clock signal disappears to when the switching converter switches to the first working mode, the third current mirror circuit controls the second current to remain unchanged or decrease slowly. A fourth current mirror circuit has a power supply end, a first end and a second end. The power supply end of the fourth current mirror circuit receives a power supply voltage signal. The first end of the fourth current mirror circuit is coupled to the second end of the third current mirror. A common node between the first end of the fourth current mirror circuit and the second end of the third current mirror also receives a second mirror current. The fourth current mirror circuit mirrors the current on its first end to generate a second adjustment signal at its second end.

8. The synchronous control module according to claim 7, characterized in that: The third current mirror circuit comprises: A first NMOS tube has a drain, a source and a gate, the drain of the first NMOS tube receives a first mirror current, the source of the first NMOS tube is connected to a reference ground, and the control end of the first NMOS tube is connected to its drain; A second resistor; a second NMOS tube having a drain, a source and a gate, the drain of the second NMOS tube serving as a second end of the third current mirror to provide a second current, the source of the second NMOS tube being connected to a reference ground, and the control end of the second NMOS tube being connected to the control end of the second NMOS tube through a second resistor; The capacitor is coupled between the control terminal of the second NMOS tube and the reference ground.

9. A control circuit for a switching converter, the switching converter comprising at least one power switch, characterized in that: include: A synchronous control module as claimed in any one of claims 1 to 8; a constant on-time or off-time generating circuit, wherein when the switching converter operates in the second operating mode, the constant on-time or off-time generating circuit generates a constant on-time or off-time signal according to the difference current signal, the input voltage and the output voltage of the switching converter; A comparison module receives a feedback signal representing an output voltage of the switching converter and generates a comparison signal based on the feedback signal and a reference voltage signal; A logic circuit receives a constant on-time or off-time signal and a comparison signal, performs a logic operation on the constant on-time or off-time signal and the comparison signal, and generates a control signal, wherein the control signal is used to control the on and off of at least one power switch to convert the input voltage into the output voltage.

10. A synchronous control method applied to a switching converter, characterized in that: The switching converter includes at least one power switch, the switching converter has a first working mode and a second working mode, and the synchronous control method includes: When the switching converter operates in the second operating mode, the phase-locked loop is enabled to receive an external clock signal and a control signal, and the phases of the external clock signal and the control signal are compared, and a voltage signal is provided at an output terminal of the phase-locked loop, wherein the voltage at the output terminal of the phase-locked loop represents a phase difference between the external clock signal and the control signal, wherein the control signal is used to control the on and off of the at least one power switch; when the switching converter operates in the first operating mode, the phase-locked loop is not enabled; Converting the voltage at the output end of the phase-locked loop into a differential current signal, wherein the differential current signal is proportional to the voltage at the output end of the phase-locked loop; When the switching converter operates in the first operating mode, a first feedback loop is used to receive a differential current signal, and a first adjustment signal is generated according to the differential current signal and a reference signal, wherein the first adjustment signal is used to adjust the voltage at the output end of the phase-locked loop to a first voltage value.

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