Correction circuit of differential amplifier

Abstract

The invention discloses a correction circuit for a differential amplifier. The correction circuit comprises a trimming circuit, a bias generator and a compensation output circuit, the trimming circuit is used for outputting a trimming code. The bias generator is coupled to the trimming circuit and is used for generating a bias current or voltage according to the trimming code. The compensation output circuit is coupled to the bias generator for receiving a data code and outputting the bias current or voltage corresponding to the data code to the differential amplifier.

Description

Technical Field

[0001] The present invention relates to a correction circuit of a differential difference amplifier (DDA), and in particular to a correction circuit for correcting the output voltage of the differential difference amplifier. Background Art

[0002] As modern display screens develop towards a wide color gamut, the demand for output grayscale of display driver integrated circuits (DDIC) has also increased. The increase in grayscale leads to a significant increase in the area of ​​the digital-to-analog converter (DAC) to be implemented in the source driver of the display driver integrated circuit, thereby increasing the cost of the display driver integrated circuit. The differential difference amplifier (DDA) is a solution to save the use of digital-to-analog converters. However, linearity issues limit the output voltage range of the differential differential amplifier. Although the grayscale value continues to increase, the output efficiency of the differential differential amplifier cannot keep up with the increased grayscale value. In this case, the area of ​​the display driver integrated circuit will still increase with the increase in grayscale value. In view of this, the prior art really needs to be improved. Summary of the invention

[0003] Therefore, the main purpose of the present invention is to provide a correction circuit for correcting the output voltage of a differential difference amplifier (DDA), thereby improving the output linearity of the differential difference amplifier, helping to improve the accuracy of the differential difference amplifier output, and at the same time increasing the output range of the differential difference amplifier.

[0004] An embodiment of the present invention discloses a correction circuit for a differential amplifier, the correction circuit comprising a trimming circuit, a bias generator and a compensation output circuit. The trimming circuit is used to output a trimming code. The bias generator is coupled to the trimming circuit and is used to generate a bias current or voltage according to the trimming code. The compensation output circuit is coupled to the bias generator and is used to receive a data code and output the bias current or voltage corresponding to the data code to the differential amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A schematic diagram of a source driving device of a display driving circuit.

[0006] Figure 2An exemplary implementation of a source operational amplifier used to implement the operation of a differential difference amplifier is shown.

[0007] Figure 3 The corresponding relationship between the output voltage and the data code in the operation of the differential amplifier is shown.

[0008] Figure 4 An error curve resulting from the operation of the differential difference amplifier is shown.

[0009] Figure 5 FIG. 1 is a schematic diagram of a correction circuit according to an embodiment of the present invention.

[0010] Figure 6 The compensation value corresponding to the differential amplifier error within a voltage range of a portion of the data code is shown.

[0011] Figure 7 It is a schematic diagram of a source operational amplifier controlled by a correction circuit to compensate for the error of a differential amplifier according to an embodiment of the present invention.

[0012] Figure 8 An embodiment of bias control for a current source array included in the input stage of a source operational amplifier is shown.

[0013] Fig. 9 It is a schematic diagram of a source operational amplifier controlled by another correction circuit to compensate for the error of a differential amplifier according to an embodiment of the present invention.

[0014] Fig.10 An exemplary implementation of an auxiliary input pair is shown.

[0015] The reference numerals are described as follows:

[0016] 10 Source driver

[0017] 102 Latch Circuit

[0018] 104 Digital to Analog Converter

[0019] 106, 70, 90 Source Operational Amplifier

[0020] VH High Voltage

[0021] VL Low Voltage

[0022] VOUT, VX, VX' Output voltage

[0023] DC, DC_X, D0~D3 data code

[0024] Comp1, Comp2 compensation value

[0025] 50 Correction circuit

[0026] 502, 730, 930 trimming circuit

[0027] 504 Bias Generator

[0028] 506 Compensation Output Circuit

[0029] TC Trim Code

[0030] IREF Bias Current

[0031] VREF bias voltage

[0032] D[2:0] Data bits

[0033] 702, 704 input pair

[0034] 712, 714, CS1~CS8, 912 voltage-controlled current source

[0035] 720, 920 decoder

[0036] 740, 940 bias circuit

[0037] I1~I4 Current

[0038] S1~S8、S1'~S8'、AUX1~AUX4 switch

[0039] ANCOM1, ANCOM2 common nodes

[0040] IN_1~IN_N basic input pair

[0041] 902 Auxiliary input pair

[0042] M1, M2 input transistors

[0043] I_AUX current value DETAILED DESCRIPTION

[0044] Figure 1The source driving device 10 of a display driving circuit is a schematic diagram. The display driving circuit can be implemented by a display driver integrated circuit (DDIC). The source driving device 10 includes a latch circuit 102, a digital-to-analog converter (DAC) 104 and a source operational amplifier (SOP) 106. The source operational amplifier 106 is a differential difference amplifier (DDA) that can perform interpolation on the input voltage (including a high voltage VH and a low voltage VL) received by it to generate an output voltage VOUT.

[0045] In the source driving device 10, the latch circuit 102 can output a data code DC to the digital-to-analog converter 104. Based on the operation of the differential amplifier, the digital-to-analog converter 104 can output a high voltage VH and a low voltage VL, which correspond to a portion of the bits of the data code DC from the latch circuit 102. The source operational amplifier 106 generates an output voltage VOUT according to the high voltage VH and the low voltage VL, wherein the output voltage VOUT can be a voltage between the high voltage VH and the low voltage VL generated by interpolation, and the interpolation is performed according to other bits of the data code DC.

[0046] Figure 2 An exemplary implementation of a source operational amplifier 106 for implementing the operation of a differential difference amplifier is shown. Figure 2 As shown, the source operational amplifier 106 can generally be divided into an input stage, a gain stage and an output stage. In this example, the operation of the differential amplifier can be implemented in the input stage, wherein the transconductance Gm1, Gm2, ... can be modified according to the data code to generate an interpolated voltage as the output voltage VOUT. In general, by receiving the N-bit data code DC, the source operational amplifier 106 can perform N-bit interpolation to generate the output voltage VOUT, wherein N can be any and suitable integer. For example, if the operation of a 4-bit differential amplifier is adopted, the source operational amplifier 106 can generate 16 different output voltages VOUT between the high voltage VH and the low voltage VL, and the voltage step is approximately 1 / 16 of the voltage difference between VH and VL. The transconductance Gm1, Gm2, ... can be pre-set to a suitable value to generate the desired value of the output voltage VOUT. In one embodiment, the values ​​of the transconductances Gm1, Gm2, . . . can be modified by controlling a current source used to supply bias current to the input pair in the input stage.

[0047] However, when the number of bits used for interpolation increases, the linearity of the output voltage VOUT will decrease, that is, in the operation of a 4-bit differential amplifier, the voltage step between two adjacent values ​​of the output voltage VOUT may deviate from 1 / 16 of the voltage difference between VH and VL. For example, Figure 3 As shown, the source operational amplifier 106 can receive a high voltage VH and a low voltage VL to perform interpolation in response to the data code DC, wherein the high voltage VH corresponds to a maximum data code (Max) and the low voltage VL corresponds to a minimum data code (Min). In the range between the high voltage VH and the low voltage VL, the corresponding relationship between the output voltage VOUT and the data code DC should ideally be a straight line. However, in the actual circuit of the source operational amplifier 106, the corresponding relationship between the output voltage VOUT and the data code DC is nonlinear, resulting in the following Figure 3 For example, for a data code DC_X, the output voltage VOUT of the source operational amplifier 106 should ideally be equal to VX, but due to the nonlinear relationship, the output voltage VOUT is equal to VX'.

[0048] This nonlinear relationship comes from the transconductance of the source operational amplifier 106, which can be generated by the input transistors in the input stage, where the input transistors have nonlinear voltage-to-current conversion behavior. More specifically, the purpose of the input stage is to generate a differential current for supplying to the gain stage, where the value of the differential current is determined by the input voltage (i.e., VH and VL) and the transconductance of the source operational amplifier 106. The conversion of the input voltage to the differential current follows the square law of the input transistor, which is nonlinear. In this case, the interpolation voltage generated based on the change in the transconductance value also has nonlinear characteristics, thereby generating a differential differential amplifier error on the output voltage VOUT.

[0049] The differential amplifier error can also be represented by an error curve in the range between the high voltage VH and the low voltage VL. If a 4-bit differential amplifier is used, the error curve can be obtained in the 4 data codes D0 to D3, such as Figure 4 If there is no differential amplifier error, the curve between VL and VH should be completely at the 0V level. Figure 4The error curve shown indicates that the lower half range has a negative error and the upper half range has a positive error. The pattern of the error curve can be derived from the current-to-voltage curve of the input transistor in the input stage of the source operational amplifier 106 according to the interpolation mechanism of the differential differential amplifier. It should be noted that different differential differential amplifier interpolation methods performed in the source operational amplifier 106 may produce different error curves. In order to improve the linearity of the output voltage VOUT, a compensation value (such as Comp1 or Comp2) must be used to compensate for the error term and correct the output voltage VOUT. After correction, the error curve for each voltage step between VH and VL will be closer to 0, indicating that the error of the differential differential amplifier has decreased.

[0050] The present invention proposes a correction circuit for a differential amplifier to improve the linearity of an output voltage VOUT output by a source operational amplifier 106 . Figure 5 FIG. 1 is a schematic diagram of a correction circuit 50 according to an embodiment of the present invention, wherein the source operational amplifier 106, the digital-to-analog converter 104 and the latch circuit 102 in the source driving device 10 are also shown in FIG. Figure 5 For convenience of explanation, the correction circuit 50 can be used to correct the output voltage VOUT of the source operational amplifier 106. In one embodiment, the correction circuit 50 can be implemented in conjunction with the source driving device 10 in the display driver integrated circuit.

[0051] like Figure 5 As shown, the calibration circuit 50 includes a trimming circuit 502, a bias generator 504, and a compensation output circuit 506. The trimming circuit 502 is used to output a trimming code TC, which can be used to determine a bias current IREF and / or a bias voltage VREF for the source operational amplifier 106. The bias generator 504 is coupled to the trimming circuit 502, and can generate a bias current IREF and / or a bias voltage VREF according to the trimming code TC. The compensation output circuit 506 is coupled to the bias generator 504, and can receive a data code DC, and output a bias current IREF and / or a bias voltage VREF corresponding to the data code DC to the source operational amplifier 106. Figure 5 As shown, the compensation output circuit 506 is coupled to the latch circuit 102 to receive the data code DC from the latch circuit 102 .

[0052] Please refer back Figure 4Different data codes DC have different error terms, and therefore require different compensation values ​​(such as Comp1 or Comp2). The trimming circuit 502 can provide a trimming code TC for each data code value, so that the bias generator 504 generates a bias current IREF and / or a bias voltage VREF that each data code value is intended to achieve. The compensation output circuit 506 can obtain the data code DC from the latch circuit 102, and correspondingly output a bias current IREF and / or a bias voltage VREF to compensate for the error term of the data code value.

[0053] In one embodiment, the output voltage VOUT of the source operational amplifier 106 may be measured to determine the corresponding differential amplifier error. For example, when the calibration circuit 50 is not included, the output voltage VOUT may be measured for each data code DC in the voltage range between the high voltage VH and the low voltage VL, and the measurement result may be used to determine the trimming code TC, so that the corresponding bias current IREF and / or bias voltage VREF may be used to compensate the differential amplifier error.

[0054] Figure 6 FIG. 4 shows the compensation value corresponding to the differential amplifier error within a voltage range of a portion of the data code. Figure 6 As shown, the source operational amplifier 106 can receive the data bits D[2:0] to perform a 3-bit differential amplifier operation, and its error curve is also shown in Figure 6 . For the data code value D[2:0]=000, the measured error is quite small, so the correction circuit 50 can determine that no compensation is required. For the data code value D[2:0]=001, the measurement result of the output voltage VOUT indicates that its error term increases to a level that cannot be ignored. Therefore, the trimming circuit 502 can output a first trimming code to control the bias generator 504 to modify the output bias current IREF or bias voltage VREF. In this example, the bias current IREF or bias voltage VREF can generate an appropriate compensation value Comp1 to reduce the error term after calibration.

[0055] In a similar manner, for the data code value D[2:0]=011, the measurement result of the output voltage VOUT indicates that its error term is further increased, so the trimming circuit 502 can output a second trimming code to control the bias generator 504 to further adjust the output bias current IREF or bias voltage VREF. The bias current IREF or bias voltage VREF can generate a larger compensation value Comp2 to further reduce the error term after calibration.

[0056] In this case, after the measurement, the calibration circuit 50 can determine the compensation values ​​for all data code values ​​D[2:0] from 000 to 111 in the differential amplifier operation. In one embodiment, the trimming codes corresponding to the compensation values ​​for different data codes can be stored in a look-up table (LUT) in a memory, which can be included in the trimming circuit 502. Therefore, when the compensation output circuit 506 obtains the data code from the latch circuit 102 for the source operational amplifier 106, it can also obtain the corresponding trimming code TC, or obtain the bias setting corresponding to the trimming code TC, so as to output the corresponding bias current IREF and / or bias voltage VREF.

[0057] Figure 7 FIG. 1 is a schematic diagram of a source operational amplifier 70 controlled by a correction circuit to compensate for the error of a differential amplifier according to an embodiment of the present invention. The source operational amplifier 70 includes an input stage, a gain stage, and an output stage, wherein: Figure 7 Detailed implementation of the input stage is shown. As described above, the operation of the differential difference amplifier can be performed in the input stage of the source operational amplifier 70. The input stage includes at least two input pairs, wherein one input pair 702 receives a high voltage VH and the other input pair 704 receives a low voltage VL. Each input pair 702 and 704 receives a current from a voltage-controlled current source (VCCS) 712 and 714, respectively, wherein the voltage-controlled current sources 712 and 714 are controlled by a bias voltage VREF.

[0058] like Figure 7 As shown, the source operational amplifier 70 is calibrated by a calibration circuit, which includes a decoder 720, a trimming circuit 730 and a bias circuit 740. The decoder 720 can be implemented in the compensation output circuit of the calibration circuit, such as Figure 5 The compensation output circuit 506 in FIG. 7A . The trimming circuit 730 may be Figure 5 An embodiment of the trimming circuit 502 in the embodiment of the present invention may include a lookup table or be coupled to a lookup table for storing the trimming code. The bias circuit 740 may be Figure 5 An implementation of the bias generator 504 and the compensation output circuit 506 in FIG.

[0059] The input pair 702 includes a voltage-controlled current source 712 for supplying current to the input pair 702, and the input pair 704 includes a voltage-controlled current source 714 for supplying current to the input pair 704. It should be noted that this is only a conceptual illustration, and in fact, in the input stage, the voltage-controlled current source 712 of the input pair 702 may represent a combination of one or more voltage-controlled current sources for supplying current to the input transistors in the input pair 702 that receive the high voltage VH, and the voltage-controlled current source 714 of the input pair 704 may represent a combination of one or more voltage-controlled current sources for supplying current to the input transistors in the input pair 704 that receive the low voltage VL. Figure 7 As shown, the decoder 720 can receive the data code DC for the source operational amplifier 70, and decode the data code DC to determine the number of voltage-controlled current sources that should be included in the voltage-controlled current source 712 and the number of voltage-controlled current sources that should be included in the voltage-controlled current source 714. In the voltage range between VH and VL, a lower output voltage VOUT can be generated corresponding to a smaller data code DC, at which time more voltage-controlled current sources in the input stage are switched to the input pair 704 for receiving the low voltage VL to generate an interpolated output voltage VOUT closer to VL; a higher output voltage VOUT can be generated corresponding to a larger data code DC, at which time more voltage-controlled current sources in the input stage are switched to the input pair 702 for receiving the high voltage VH to generate an interpolated output voltage VOUT closer to VH.

[0060] Each voltage-controlled current source 712 and 714 may receive a bias voltage VREF from a bias circuit 740. The trimming circuit 730 may output a trimming code TC to control the bias circuit 740 to provide the bias voltage VREF to each voltage-controlled current source included in 712 and 714.

[0061] Figure 8 FIG. 7 shows an implementation of bias control for a current source array included in the input stage of the source operational amplifier 70. Figure 8 As shown, in order to realize a 3-bit differential amplifier, the input stage may include 8 voltage-controlled current sources CS1-CS8, and each voltage-controlled current source CS1-CS8 may supply the same or different currents. In this example, two voltage-controlled current sources CS1 and CS2 are used to supply a current I1, two voltage-controlled current sources CS3 and CS4 are used to supply a current I2, two voltage-controlled current sources CS5 and CS6 are used to supply a current I3, and two voltage-controlled current sources CS7 and CS8 are used to supply a current I4. Each voltage-controlled current source CS1-CS8 may be controlled by two switches (one of S1-S8 and one of S1'-S8') to selectively couple to a common node ANCOM1 or ANCOM2. Common node ANCOM1 represents the common node of input pair 702, and common node ANCOM2 represents the common node of input pair 704.

[0062] The decoder 720 can allocate the voltage-controlled current sources CS1-CS8 according to the data code DC. More specifically, the decoder 720 can decode the data code DC to output control signals to the corresponding switches S1-S8 and S1'-S8', thereby controlling the voltage-controlled current sources CS1-CS8 to selectively couple to the same node ANCOM1 or ANCOM2. The voltage-controlled current sources coupled to the same common node can be considered to be connected in parallel, and their output currents can be added to each other.

[0063] Therefore, each voltage-controlled current source CS1-CS8 can be switched between the configuration of 712 and the configuration of 714 according to Table 1 to realize the operation of the 3-bit differential amplifier, thereby generating the output voltage VOUT of the source operational amplifier 70 corresponding to different data codes DC. In this example, ideally, each voltage-controlled current source CS1-CS8 can supply the same current, that is, I1=I2=I3=I4. Therefore, the output voltage VOUT can be determined according to the number of voltage-controlled current sources switched to be coupled to the common node ANCOM1 to supply current to the input pair 702 and the number of voltage-controlled current sources switched to be coupled to the common node ANCOM2 to supply current to the input pair 704. For example, for the operation of the 3-bit differential amplifier, the data code DC for interpolation can be represented by a 3-bit code in a differential amplifier cycle, which ranges from 0 (000) to 7 (111). If the coding value is 0, all voltage-controlled current sources CS1-CS8 are switched to input pair 704, and the output voltage VOUT is equal to the low voltage VL. If the coding value is 1, there are 7 voltage-controlled current sources switched to input pair 704 and only 1 voltage-controlled current source switched to input pair 702. At this time, the output voltage VOUT is approximately equal to 7 / 8×VL+1 / 8×VH. The detailed implementation is shown in Table 1.

[0064]

[0065] Table 1

[0066] However, if the values ​​of the currents I1 to I4 are exactly the same, the output voltage VOUT may slightly deviate from its desired value, thereby generating an error term and an error curve, such as Figure 6As shown. In order to compensate for the differential amplifier error, some currents I1~I4 can be fine-tuned to have slightly different values, and the values ​​of currents I1~I4 can be adjusted using trimming codes. As described above, the output voltage VOUT can be measured for each data code DC (for example, from 0 to 7) within the voltage range between the high voltage VH and the low voltage VL. Based on the measurement results, the values ​​of currents I1~I4 can be adjusted to their target values. After trimming and correction operations, the output voltage VOUT corresponding to each data code can be closer to its ideal value. For example, the preset value of currents I1~I4 can be 1 nanoampere (nA). After the trimming operation, the values ​​of currents I1~I4 may be fine-tuned to 0.9nA, 1.1nA, 1.05nA and 1nA, respectively.

[0067] The current values ​​of I1-I4 can be adjusted according to the trimming code by controlling the bias voltage VREF output to the voltage-controlled current sources CS1-CS8. The trimming codes used to generate these current values ​​can be stored in the lookup table of the trimming circuit 730. According to the data code DC obtained from the decoder 720, the trimming circuit 730 can select a suitable trimming code from the trimming codes stored in the lookup table for the corresponding voltage-controlled current sources CS1-CS8. The bias circuit 740 can output the bias voltage VREF to the voltage-controlled current sources CS1-CS8 according to the trimming code to control the voltage-controlled current sources CS1-CS8 to generate the target values ​​of the currents I1-I4. By receiving the same or different bias voltages VREF, the voltage-controlled current sources CS1-CS8 can output the same or different current values.

[0068] Therefore, when the input data code DC changes, the decoder 720 can control the voltage-controlled current sources CS1-CS8 to switch accordingly. Through the adjustment of the current values ​​of I1-I4 and the appropriate configuration of the voltage-controlled current sources CS1-CS8, the output voltage VOUT generated by the corresponding data code DC will be closer to its target value. In this way, the output voltage VOUT in the important range will be more linear, and the differential amplifier error can be minimized.

[0069] It is worth noting that the output voltage used to generate the same desired brightness may be different on different display screens, which can be obtained through the gamma tuning process before the display screen product leaves the factory. Similarly, the performance of the differential amplifier error on different display screens may also be different. Therefore, the trimming operation including measuring the data voltage corresponding to each data code and calculating the trimming code can be completed before the display screen product leaves the factory. In this way, the current value of the voltage-controlled current source can be adjusted to the desired value before the display screen product begins to be used, wherein the display driver integrated circuit used for different display screens may be applicable to different trimming codes.

[0070] It should also be noted that the above Figure 7 and Figure 8 The implementation of the correction circuit shown is only one of many embodiments of the present invention. In another embodiment, the correction circuit can also use the trimming code to control the bias voltage / current in other ways.

[0071] Fig. 9 Schematic diagram of a source operational amplifier 90 controlled by another correction circuit to compensate for the error of a differential amplifier according to an embodiment of the present invention. The source operational amplifier 90 can use a plurality of basic input pairs IN_1 to IN_N with different transconductance weights at its input stage to implement the operation of a differential amplifier. Based on the received data code DC, each basic input pair IN_1 to IN_N can be configured to receive a high voltage VH or a low voltage VL, thereby generating a desired output voltage VOUT through interpolation.

[0072] In addition to the basic input pairs IN_1 to IN_N, the input stage of the source operational amplifier 90 may also include one or more auxiliary input pairs 902, wherein the basic input pairs IN_1 to IN_N and the auxiliary input pair 902 jointly supply a differential current to the gain stage. The auxiliary input pair 902 can selectively receive a high voltage VH or a low voltage VL to generate an increment value or a decrement value for the output voltage VOUT. The auxiliary input pair 902 may include one or more current sources, such as a voltage-controlled current source 912, which may receive a bias voltage VREF to generate a desired output current value. The output current of the voltage-controlled current source 912 may become a part of the differential current to be transmitted to the gain stage, thereby adjusting the output voltage VOUT of the source operational amplifier 90.

[0073] like Fig. 9 As shown, the source operational amplifier 90 is calibrated by a calibration circuit, which includes a decoder 920, a trimming circuit 930 and a bias circuit 940. Similarly, the decoder 920 can be implemented in the compensation output circuit of the calibration circuit, such as Figure 5 The compensation output circuit 506 in FIG. 9A . The trimming circuit 930 may be Figure 5 An embodiment of the trimming circuit 502 in the embodiment may include a lookup table or be coupled to a lookup table for storing the trimming code. The bias circuit 940 may be Figure 5 An implementation of the bias generator 504 and the compensation output circuit 506 in FIG.

[0074] In a similar manner, the current value of the voltage-controlled current source 912 in the auxiliary input pair 902 can be modified using a trimming code, which can be obtained by measurement and stored in a lookup table in the trimming circuit 930. The operation of the voltage-controlled current source 912 can be controlled by a decoder 920, which can receive a data code DC (e.g., from a latch circuit) and decode the data code DC to generate a control signal for controlling the voltage-controlled current source 912 in the auxiliary input pair 902. In addition, the bias circuit 940 can output a bias voltage VREF to the voltage-controlled current source 912 to control the voltage-controlled current source 912 to supply a desired current.

[0075] From another perspective, the voltage-controlled current source 912 can be considered to be implemented by the bias circuit 940 in the compensation output circuit of the calibration circuit. Therefore, the compensation output circuit can be used to output a bias current (i.e., the output current of the voltage-controlled current source 912) to the auxiliary input pair 902, wherein the value of the bias current can be adjusted according to the trimming code.

[0076] Fig.10 An exemplary embodiment of the auxiliary input pair 902 is shown, which includes two input transistors M1 and M2 for receiving supply current from four voltage-controlled current sources CS1-CS4. The input transistor M1 can be used to receive a high voltage VH or a low voltage VL, and the input transistor M2 is coupled to the output terminal of the source operational amplifier 90. The voltage-controlled current sources CS1-CS4 can be Fig. 9 The voltage-controlled current source 912 in FIG. 1 is respectively coupled to the input transistors M1 and M2 through four switches AUX1 to AUX4. The voltage-controlled current sources CS1 to CS4 are respectively used to supply currents I1 to I4 to the auxiliary input pair 902, wherein the values ​​of the currents I1 to I4 can be controlled by the bias circuit 940 according to the trimming code. Each switch AUX1 to AUX4 can be turned on or off to generate a current value I_AUX to be supplied to the auxiliary input pair 902.

[0077] In one embodiment, the auxiliary input pair 902 can receive a high voltage VH or a low voltage VL according to the received data code DC, and the switches AUX1-AUX4 can be controlled according to the data code DC. An exemplary implementation is shown in Table 2. In this example, the calibration is performed using the operation of a 4-bit differential amplifier to control the differential amplifier cycle corresponding to the range of 0 (0000) to 15 (1111) by the data code DC, wherein the error curve has the same as Figure 4Similar patterns. Specifically, there is no differential amplifier error in the minimum code (DC=0), the maximum code (DC=15), and the middle code (DC=8), so for these data codes, all switches AUX1-AUX4 are closed (represented by 0), and the auxiliary input pair 902 can be disabled. In the range of the lower half code (DC=1-7), there is a negative differential amplifier error, so the auxiliary input pair 902 can receive a high voltage VH (i.e., VIN=VH), and a selection switch is turned on (represented by 1) to supply a current value I_AUX, thereby slightly increasing the output voltage VOUT of the source operational amplifier 90 to eliminate the negative differential amplifier error. There is a positive differential amplifier error within the range of the upper half code (DC=9~15), so the auxiliary input pair 902 can receive a low voltage VL (i.e., VIN=VL), and a selection switch is turned on (indicated by 1) to supply a current value I_AUX, thereby slightly reducing the output voltage VOUT of the source operational amplifier 90 to eliminate the positive differential amplifier error.

[0078] DC VIN I_AUX AUX1 AUX2 AUX3 AUX4 0 VH 0 0 0 0 0 1 VH I1 1 0 0 0 2 VH I2 0 1 0 0 3 VH I3 0 0 1 0 4 VH I4 0 0 0 1 5 VH I3 0 0 1 0 6 VH I2 0 1 0 0 7 VH I1 1 0 0 0 8 V L 0 0 0 0 0 9 V L I1 1 0 0 0 10 V L I2 0 1 0 0 11 V L I3 0 0 1 0 12 V L I4 0 0 0 1 13 V L I3 0 0 1 0 14 V L I2 0 1 0 0 15 V L I1 1 0 0 0

[0079] Table 2

[0080] In this example, the voltage-controlled current source CS4 can supply a maximum current I4, which is greater than the currents I3, I2, and I1 in sequence, i.e., I4>I3>I2>I1. The values ​​of the currents I1-I4 can be fine-tuned to a specific level through a trimming operation, and an example of a trimming result is shown in Table 3. In another embodiment, multiple switches can also be turned on simultaneously to provide more possible current values, thereby producing a more flexible and more powerful calibration effect.

[0081] I1 I2 I3 I4 4nA 8nA 10nA 12nA

[0082] Table 3

[0083] It is worth noting that the purpose of the present invention is to provide a correction circuit for a differential amplifier, which is used to correct the linearity of the output voltage of the source operational amplifier. Those skilled in the art can make modifications or changes accordingly, but are not limited to this. For example, in some embodiments, the error term of each input data code can be measured to obtain a suitable trimming code. However, in other embodiments, in order to simplify the calculation cost, a measurement can be made for several adjacent data code values, so that the same trimming results can be used for these data code values. For example, in Figure 4In the embodiment, two adjacent data code values ​​use the compensation value Comp1, and two adjacent data code values ​​use the compensation value Comp2. In addition, in the above embodiment, a compensation value (bias voltage or current) corresponding to a trimming code can be obtained for a data code after measurement. In another embodiment, the trimming operation can also be adjusted in response to changes in process, voltage, and temperature (PVT). In other words, for the same data code value, different trimming codes and different compensation values ​​can be obtained under different environmental parameters, which may be affected by process, temperature, and / or data voltage level, thereby achieving a more accurate calibration result.

[0084] In addition, in the input stages of different source operational amplifiers, the number of voltage-controlled current sources used to implement the differential differential amplifier operation may be different, and these voltage-controlled current sources may have the same or different current values. The above current values ​​are only an implementation of the output results generated by an example of a trimming code, and these current values ​​can be modified or adjusted under different trimming codes, and the related implementations should not be limited to the scope of this specification.

[0085] In summary, the present invention proposes a correction circuit for a differential differential amplifier. The differential differential amplifier operation is a technology used for the source operational amplifier of a display driver integrated circuit, wherein the source operational amplifier can receive a high voltage and a low voltage from a digital-to-analog converter to generate an output voltage by interpolation. Part of the bits of the data code can be used to implement the interpolation of the source operational amplifier, thereby reducing the number of bits that the digital-to-analog converter needs to process, thereby saving the area of ​​the digital-to-analog converter. Since the output voltage generated by the differential differential amplifier operation has a differential differential amplifier error and causes its nonlinearity, a correction scheme is required to compensate for the differential differential amplifier error. The correction circuit proposed by the present invention can be used to achieve this purpose.

[0086] In one embodiment of the present invention, a correction circuit may be provided to adjust the current source for the input pair of the source operational amplifier. Each current source may be a voltage-controlled current source controlled by a bias voltage, and the bias voltage may be fine-tuned using a trimming operation. The voltage-controlled current source may be adjusted using a trimming code to output a suitable current value, so that the output voltage of the source operational amplifier becomes more accurate (i.e., closer to the desired voltage value), thereby reducing the error of the differential differential amplifier. In another embodiment, in addition to the basic input pair of the input stage of the source operational amplifier, the input stage may also include one or more auxiliary input pairs, and the auxiliary input pairs may selectively receive a high voltage or a low voltage to generate an incremental value or a decrement value for the output voltage, thereby making the output voltage closer to the desired voltage value. The current supplied to the auxiliary input pair may be adjusted to a suitable value using a trimming code to control the output voltage to accurately reach the desired voltage value. In this case, the output linearity of the source operational amplifier may be improved, and the possible number of bits of the differential differential amplifier operation may be increased without affecting the output linearity. In this way, the application voltage range of the differential amplifier can be expanded, thereby reducing the area of ​​the digital-to-analog converter and saving the circuit cost of the display driver integrated circuit.

[0087] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A correction circuit for a differential amplifier, characterized in that: include: a trimming circuit, used for outputting a trimming code; a bias generator, coupled to the trimming circuit, for generating a bias current or voltage according to the trimming code; as well as A compensation output circuit is coupled to the bias generator, and is used for receiving a data code and outputting the bias current or voltage corresponding to the data code to the differential amplifier.

2. The correction circuit according to claim 1, characterized in that The trimming circuit includes a lookup table for storing a plurality of trimming codes corresponding to a plurality of data codes.

3. The correction circuit according to claim 2, characterized in that The compensation output circuit includes a decoder for decoding the data code for the differential amplifier, and the compensation output circuit selects the trimming code from the plurality of trimming codes according to the data code.

4. The correction circuit according to claim 1, characterized in that: The compensation output circuit is also coupled to a latch circuit to receive the data code from the latch circuit.

5. The correction circuit according to claim 1, characterized in that: An input stage of the differential amplifier includes a plurality of current sources respectively coupled to a plurality of input pairs, and the compensation output circuit outputs a first bias voltage to at least one current source among the plurality of current sources to adjust an output current of the at least one current source.

6. The correction circuit according to claim 1, characterized in that: An input stage of the differential amplifier includes a plurality of basic input pairs and an auxiliary input pair.

7. The correction circuit according to claim 6, characterized in that: The compensation output circuit is coupled to the auxiliary input pair and is used for supplying the bias current or voltage to the auxiliary input pair.

8. The correction circuit according to claim 6, characterized in that: The compensation output circuit outputs a first bias voltage to a current source of the auxiliary input pair.

9. The correction circuit according to claim 6, characterized in that: The compensation output circuit outputs a first bias current to the auxiliary input pair.

10. The correction circuit according to claim 1, characterized in that: The trimming code is determined by measuring an output voltage of the differential amplifier.

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